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Migrate to Vitis2023.2 version

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This commit is contained in:
Jeremy Shen
2026-05-26 17:02:52 +08:00
parent 2dca3709ef
commit 3b268f6583
5060 changed files with 1117688 additions and 288060 deletions
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2.FW/CPLD1/tb_RelayConTop.sv
+16 -10
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@@ -369,11 +369,11 @@ module tb_RelayConTop;
tb_assert(o_wready === 1'b1,
"o_wready is HIGH after reset (SPI ready)", "");
// IDENT register: bug on Reg_file.v:38 uses || instead of |
// IDENT register: CPLD1=bit21, version=1.1.0 = 24'h200010
spi_read(mk_read(7'd0), r_ident);
r_ident = r_ident[23:0];
tb_assert(r_ident === 24'h000001,
"IDENT register returns 24'h000001 (known || bug)", "");
tb_assert(r_ident === 24'h200010,
"IDENT register returns 24'h200010 (CPLD1, v1.1.0)", "");
tb_assert(o_DMM_EN === 19'b0,
"o_DMM_EN is all zeros after reset", "");
@@ -528,8 +528,9 @@ module tb_RelayConTop;
#(`SPI_CLK_PERIOD);
// Slot1 Ch50 (range 9-72): DMM_EN[1]=1
// = (0<<10) | (50<<1) | 1 = 24'h000065
$display(" Slot1 Ch50 (range 9-72): DMM_EN[1]=1");
spi_write(mk_write(7'd2, 24'h002805));
spi_write(mk_write(7'd2, 24'h000065));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -540,8 +541,9 @@ module tb_RelayConTop;
#(`SPI_CLK_PERIOD);
// Slot1 Ch100 (range 73-136): OC_x17=1, DMM_EN[2]=1
// = (0<<10) | (100<<1) | 1 = 24'h0000C9
$display(" Slot1 Ch100 (range 73-136): OC_x17=1, DMM_EN[2]=1");
spi_write(mk_write(7'd2, 24'h006405));
spi_write(mk_write(7'd2, 24'h0000C9));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -552,8 +554,9 @@ module tb_RelayConTop;
#(`SPI_CLK_PERIOD);
// Slot1 Ch150 (range 137-200): DMM_EN[3]=1
// = (0<<10) | (150<<1) | 1 = 24'h00012D
$display(" Slot1 Ch150 (range 137-200): DMM_EN[3]=1");
spi_write(mk_write(7'd2, 24'h009605));
spi_write(mk_write(7'd2, 24'h00012D));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -563,6 +566,7 @@ module tb_RelayConTop;
#(`SPI_CLK_PERIOD);
// Slot2 Ch5 (range 1-8): OC_x01=2, DMM_EN[4]=1
// = (0<<10) | (5<<1) | 1 = 24'h000006
$display(" Slot2 Ch5 (range 1-8): OC_x01=2, DMM_EN[4]=1");
spi_write(mk_write(7'd3, 24'h000006));
@(negedge i_sclk);
@@ -575,8 +579,9 @@ module tb_RelayConTop;
#(`SPI_CLK_PERIOD);
// Slot3 Ch100 (range 73-136): OC_x17=4, DMM_EN[10]=1
// = (0<<10) | (100<<1) | 1 = 24'h0000C9
$display(" Slot3 Ch100 (range 73-136): OC_x17=4, DMM_EN[10]=1");
spi_write(mk_write(7'd4, 24'h006407));
spi_write(mk_write(7'd4, 24'h0000C9));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -587,8 +592,9 @@ module tb_RelayConTop;
#(`SPI_CLK_PERIOD);
// Slot4 Ch50 (range 9-72): DMM_EN[5]=1
// = (0<<10) | (50<<1) | 1 = 24'h000065
$display(" Slot4 Ch50 (range 9-72): DMM_EN[5]=1");
spi_write(mk_write(7'd5, 24'h003208));
spi_write(mk_write(7'd5, 24'h000065));
@(negedge i_sclk);
spi_write(mk_write(7'd1, 24'h000001));
@(negedge i_sclk);
@@ -699,8 +705,8 @@ module tb_RelayConTop;
$display(" Group 6: RC_Tx relay output (slot 4)");
$display("-------------------------------------------------------------");
// 6a. RC_Tx pattern: bits 17:12 = 6'b101010
// = (42<<10) | (5<<1) | 1 = 24'h02A00B
// 6a. RC_Tx pattern: bits 17:12 = 6'b101010 (42)
// = (42<<12) | (5<<1) | 1 = 24'h02A00B
$display(" Slot4: RC_Tx = 6'b101010");
spi_write(mk_write(7'd5, 24'h02A00B));
@(negedge i_sclk);