CPLD bug fixes

2.FW/CPLD2/BUS_Con.v

@@ -9,14 +9,14 @@ module BUS_Con (
     output o_miso,          // <-- MISO Logic added here
     
     // Local Interface
-    output o_rvaild,        // (Typo in original: o_rvalid)
-    input i_rvaild,         // Valid signal from Backend (Data is ready)
-    input i_wvaild,
+    output o_rvalid,        // (Typo in original: o_rvalid)
+    input i_rvalid,         // Valid signal from Backend (Data is ready)
+    input i_wvalid,
     output o_wready,
     input i_reg_busy,
     input [23:0] i_rdata,   // Data from Backend to send to Master
     output o_wr,
-    output o_cmd_vaild,
+    output o_cmd_valid,
     output [23:0] o_data,
     output [6:0] o_addr,
     output o_err
@@ -61,19 +61,19 @@ module BUS_Con (
     reg        err_flag;
 	reg [1:0] state;
 	//
-	reg [31:0] tx_buffer;  // Holds data waiting for the next CS Low
-    reg [31:0] miso_shift; // The actual shifter
-    // Output Registers
-    reg [6:0]  addr_out;
-    reg [23:0] data_out;
-    reg        wr_out;
+	reg [31:0] tx_buffer;  // Holds data waiting for the next CS Low
+    reg [31:0] miso_shift; // The actual shifter
+    // Output Registers
+    reg [6:0]  addr_out;
+    reg [23:0] data_out;
+    reg        wr_out;
     reg        cmd_valid_out;
 	
 	//
-	localparam IDLE      = 2'b00;
-    localparam CMD_SENT  = 2'b01;
-    localparam WAIT_BUSY = 2'b10;
-    localparam DONE      = 2'b11;
+	localparam IDLE      = 2'b00;
+    localparam CMD_SENT  = 2'b01;
+    localparam WAIT_BUSY = 2'b10;
+    localparam DONE      = 2'b11;
     
 
     always @(posedge i_sys_clk) begin
@@ -122,7 +122,7 @@ module BUS_Con (
         end else begin
             // If backend provides valid read data, store it.
             // We pad the top 8 bits with Zeros (or you can put status flags here)
-            if (i_rvaild) begin
+            if (i_rvalid) begin
                 tx_buffer <= {8'h00, i_rdata}; 
             end
         end
@@ -205,11 +205,11 @@ module BUS_Con (
     assign o_addr      = addr_out;
     assign o_data      = data_out;
     assign o_wr        = wr_out;
-    assign o_cmd_vaild = cmd_valid_out;
+    assign o_cmd_valid = cmd_valid_out;
     assign o_err       = err_flag;
     assign o_wready    = (state == IDLE); 
     
     // Pass through unused signal or hook it up if needed
-    assign o_rvaild    = 1'b0; 
+    assign o_rvalid    = i_rvalid; 
 
 endmodule