diff --git a/2.FW/CPLD1/BUS_Con.v b/2.FW/CPLD1/BUS_Con.v
index f7e4935..c28774e 100644
--- a/2.FW/CPLD1/BUS_Con.v
+++ b/2.FW/CPLD1/BUS_Con.v
@@ -208,6 +208,6 @@ module BUS_Con (
     assign o_wready    = (state == IDLE); 
     
     // Pass through unused signal or hook it up if needed
-    assign o_rvalid    = 1'b0; 
+    assign o_rvalid    = i_rvalid; 
 
 endmodule
\ No newline at end of file
diff --git a/2.FW/CPLD1/RelayConTop.v b/2.FW/CPLD1/RelayConTop.v
index 6095b4c..1fe1182 100644
--- a/2.FW/CPLD1/RelayConTop.v
+++ b/2.FW/CPLD1/RelayConTop.v
@@ -93,7 +93,7 @@ module RelayConTop (
 		.i_wvalid(i_wvalid),
 		.i_reg_busy(reg_busy),
 		.i_rdata(r_data),
-		.o_cmd_valid(cmd_vaild),
+		.o_cmd_valid(cmd_valid),
 		.o_wr(wr_flag),
  		.o_miso(o_miso),
 		.o_rvalid(o_rvalid),
@@ -106,7 +106,7 @@ module RelayConTop (
 	Reg_file CPLD_Reg_1(
 		.i_sys_clk(i_sys_clk),
 		.i_rst_n(i_rst_n),
-		.i_wr_req(cmd_vaild),
+		.i_wr_req(cmd_valid),
 		.i_wr(wr_flag),
 		.i_addr(reg_addr),
 		.i_wdata(w_data),
diff --git a/2.FW/CPLD2/BUS_Con.v b/2.FW/CPLD2/BUS_Con.v
index 8fe11fe..82c450f 100644
--- a/2.FW/CPLD2/BUS_Con.v
+++ b/2.FW/CPLD2/BUS_Con.v
@@ -9,14 +9,14 @@ module BUS_Con (
     output o_miso,          // <-- MISO Logic added here
     
     // Local Interface
-    output o_rvaild,        // (Typo in original: o_rvalid)
-    input i_rvaild,         // Valid signal from Backend (Data is ready)
-    input i_wvaild,
+    output o_rvalid,        // (Typo in original: o_rvalid)
+    input i_rvalid,         // Valid signal from Backend (Data is ready)
+    input i_wvalid,
     output o_wready,
     input i_reg_busy,
     input [23:0] i_rdata,   // Data from Backend to send to Master
     output o_wr,
-    output o_cmd_vaild,
+    output o_cmd_valid,
     output [23:0] o_data,
     output [6:0] o_addr,
     output o_err
@@ -61,19 +61,19 @@ module BUS_Con (
     reg        err_flag;
 	reg [1:0] state;
 	//
-	reg [31:0] tx_buffer;  // Holds data waiting for the next CS Low
-    reg [31:0] miso_shift; // The actual shifter
-    // Output Registers
-    reg [6:0]  addr_out;
-    reg [23:0] data_out;
-    reg        wr_out;
+	reg [31:0] tx_buffer;  // Holds data waiting for the next CS Low
+    reg [31:0] miso_shift; // The actual shifter
+    // Output Registers
+    reg [6:0]  addr_out;
+    reg [23:0] data_out;
+    reg        wr_out;
     reg        cmd_valid_out;
 	
 	//
-	localparam IDLE      = 2'b00;
-    localparam CMD_SENT  = 2'b01;
-    localparam WAIT_BUSY = 2'b10;
-    localparam DONE      = 2'b11;
+	localparam IDLE      = 2'b00;
+    localparam CMD_SENT  = 2'b01;
+    localparam WAIT_BUSY = 2'b10;
+    localparam DONE      = 2'b11;
     
 
     always @(posedge i_sys_clk) begin
@@ -122,7 +122,7 @@ module BUS_Con (
         end else begin
             // If backend provides valid read data, store it.
             // We pad the top 8 bits with Zeros (or you can put status flags here)
-            if (i_rvaild) begin
+            if (i_rvalid) begin
                 tx_buffer <= {8'h00, i_rdata}; 
             end
         end
@@ -205,11 +205,11 @@ module BUS_Con (
     assign o_addr      = addr_out;
     assign o_data      = data_out;
     assign o_wr        = wr_out;
-    assign o_cmd_vaild = cmd_valid_out;
+    assign o_cmd_valid = cmd_valid_out;
     assign o_err       = err_flag;
     assign o_wready    = (state == IDLE); 
     
     // Pass through unused signal or hook it up if needed
-    assign o_rvaild    = 1'b0; 
+    assign o_rvalid    = i_rvalid; 
 
 endmodule
\ No newline at end of file
diff --git a/2.FW/CPLD2/CPLD_Con.v b/2.FW/CPLD2/CPLD_Con.v
index ac34a8b..1ff77a2 100644
--- a/2.FW/CPLD2/CPLD_Con.v
+++ b/2.FW/CPLD2/CPLD_Con.v
@@ -104,6 +104,10 @@ module CPLD_Con (
             exec_flag <= 1'b0;
             exec_done_flag <= 1'b1;
 			freq_slot_flag <= 'd0;
+            PMU_OC_1 <= 'd0;
+            PMU_OC_2 <= 'd0;
+            PMU_OC_3 <= 'd0;
+            PMU_OC_4 <= 'd0;
             dc_slot_flag<='d0;
 			err_flag <= 'd0;
         end
diff --git a/2.FW/CPLD2/NewExtIns_CPLD2.ldf b/2.FW/CPLD2/NewExtIns_CPLD2.ldf
index 311daa7..f5d011c 100644
--- a/2.FW/CPLD2/NewExtIns_CPLD2.ldf
+++ b/2.FW/CPLD2/NewExtIns_CPLD2.ldf
@@ -2,7 +2,7 @@
 <BaliProject version="3.2" title="NewExtIns_CPLD2" device="LCMXO2-7000HC-4FG484C" default_implementation="impl1">
     <Options/>
     <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="CPLD_Con" top="RelayConTop"/>
+        <Options def_top="RelayConTop" top="RelayConTop"/>
         <Source name="RelayConTop.v" type="Verilog" type_short="Verilog">
             <Options top_module="RelayConTop"/>
         </Source>
diff --git a/2.FW/CPLD2/NewExtIns_CPLD2.lpf b/2.FW/CPLD2/NewExtIns_CPLD2.lpf
index 524b088..134bbe9 100644
--- a/2.FW/CPLD2/NewExtIns_CPLD2.lpf
+++ b/2.FW/CPLD2/NewExtIns_CPLD2.lpf
@@ -1,3 +1,4 @@
+rvl_alias "i_sys_clk" "i_sys_clk";
 RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
 RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
 RVL_ALIAS "i_sys_clk" "i_sys_clk"; 
diff --git a/2.FW/CPLD2/RelayConTop.v b/2.FW/CPLD2/RelayConTop.v
index 51785b1..a20acac 100644
--- a/2.FW/CPLD2/RelayConTop.v
+++ b/2.FW/CPLD2/RelayConTop.v
@@ -8,7 +8,7 @@ module RelayConTop (
 	output o_miso,
 	output o_rvalid,
 	input i_rready,
-	input i_wvaild,
+	input i_wvalid,
 	output o_wready,
 	output o_err,
 	output [7:0]o_RC_F,           //Ref: Schematic
@@ -61,20 +61,20 @@ module RelayConTop (
 
 	wire con_done;
 
-	BUS_Con BUS_Con_2(
+BUS_Con BUS_Con_2(
 		.i_sys_clk(i_sys_clk),
 		.i_rst_n(i_rst_n),
 		.i_sclk(i_sclk),
 		.i_mosi(i_mosi),
 		.i_cs(i_cs),
-		.i_rvaild(con_rvaild),
-		.i_wvaild(i_wvaild),
+		.i_rvalid(con_rvalid),
+		.i_wvalid(i_wvalid),
 		.i_reg_busy(reg_busy),
 		.i_rdata(r_data),
-		.o_cmd_vaild(cmd_valid),
+		.o_cmd_valid(cmd_valid),
 		.o_wr(wr_flag),
- 		.o_miso(o_miso),
-		.o_rvaild(o_rvalid),
+  		.o_miso(o_miso),
+		.o_rvalid(o_rvalid),
 		.o_wready(o_wready),
 		.o_data(w_data),
 		.o_addr(reg_addr),
@@ -161,7 +161,7 @@ module RelayConTop (
 	assign o_PMU_OC_4[31:25] = PMU_OC_4[31:25];
 
 
-	assign o_err = bus_err_flag || reg_err_flag;
+	assign o_err = bus_err_flag || reg_err_flag ||  cpld_err_flag;
 	
 	
 endmodule
diff --git a/2.FW/CPLD3/CPLD_Con.v b/2.FW/CPLD3/CPLD_Con.v
index 270abb0..2a6bb73 100644
--- a/2.FW/CPLD3/CPLD_Con.v
+++ b/2.FW/CPLD3/CPLD_Con.v
@@ -109,6 +109,9 @@ module CPLD_Con (
                         4'b1000: begin
                             PMU_RC <= 4'b0110;
                         end
+                        default:begin
+                            PMU_RC <= 4'b0000;
+                        end
                     endcase
                 end
                 else if (dc_t == 1'b1)  begin
@@ -125,6 +128,9 @@ module CPLD_Con (
                         4'b1000: begin
                             PMU_RC <= 4'b1000;
                         end
+                        default:begin
+                            PMU_RC <= 4'b0000;
+                        end
                     endcase
                 end
                 done_flag <= 1'b1;
diff --git a/2.FW/CPLD3/Reg_file.v b/2.FW/CPLD3/Reg_file.v
index 78576c2..8f00652 100644
--- a/2.FW/CPLD3/Reg_file.v
+++ b/2.FW/CPLD3/Reg_file.v
@@ -131,7 +131,9 @@ module Reg_file (
                 // Wait for Controller to register the command and pull 'done' LOW (Busy)
                 EXEC_ACK: begin
                     busy_flag <= 1'b1;
-                    state <= EXEC_WAIT;
+                    if (i_con_done == 1'b0) begin
+                        state <= EXEC_WAIT;
+                    end
                     // Optional: Timeout counter here to prevent hanging if Controller is dead
                 end
 
diff --git a/2.FW/CPLD3/RelayConTop.v b/2.FW/CPLD3/RelayConTop.v
index 2337ec4..9c7aeb6 100644
--- a/2.FW/CPLD3/RelayConTop.v
+++ b/2.FW/CPLD3/RelayConTop.v
@@ -6,7 +6,7 @@ module RelayConTop (
 	input i_mosi,
 	input i_cs,
 	output o_miso,
-	output o_rvaild,
+	output o_rvalid,
 	input i_rready,
 	input i_wvaild,
 
@@ -23,7 +23,7 @@ module RelayConTop (
 	wire [23:0]w_data ;
 	wire [6:0]reg_addr ;
 
-	wire cmd_vaild;
+	wire cmd_valid;
 	wire reg_busy;
 	wire wr_flag;						//1=write,0=read
 	wire bus_err_flag;
@@ -55,7 +55,7 @@ module RelayConTop (
 		.i_wvalid(i_wvalid),
 		.i_reg_busy(reg_busy),
 		.i_rdata(r_data),
-		.o_cmd_valid(cmd_vaild),
+		.o_cmd_valid(cmd_valid),
 		.o_wr(wr_flag),
  		.o_miso(o_miso),
 		.o_rvalid(o_rvalid),
@@ -68,7 +68,7 @@ module RelayConTop (
 	Reg_file CPLD_Reg_3(
 		.i_sys_clk(i_sys_clk),
 		.i_rst_n(i_rst_n),
-		.i_wr_req(cmd_vaild),
+		.i_wr_req(cmd_valid),
 		.i_wr(wr_flag),
 		.i_addr(reg_addr),
 		.i_wdata(w_data),