61 lines
1.5 KiB
Plaintext
61 lines
1.5 KiB
Plaintext
# =============================================================================
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# .gitignore — Xilinx Vitis Embedded Project (Zynq-7000)
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# Workspace: Cal_Net/
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#
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# Strategy:
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# IGNORE: build outputs, IDE workspace state, BSP (regenerated).
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# TRACK: source (.c/.h/.ld), project config, hardware outputs
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# (.xsa/.bit/.elf/.bin), wizard files (.spr/.sprj), Tcl scripts.
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# =============================================================================
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# ----- BSP (ignore generated, keep project config for regeneration) -----
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NewExtInst_bsp/*
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!NewExtInst_bsp/.project
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!NewExtInst_bsp/.cproject
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!NewExtInst_bsp/platform.spr
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!NewExtInst_bsp/platform.tcl
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# ----- Build Output Directories (contents only) -----
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# Using "/*" instead of "/" so negation rules can un-ignore deliverables.
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*/Debug/*
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*/Release/*
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# ----- Object & Dependency Files -----
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*.o
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*.d
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# ----- Logs -----
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*.log
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*.jou
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IDE.log
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# ----- IDE / Eclipse Workspace State -----
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.metadata/
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.analytics
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RemoteSystemsTempFiles/
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# ----- Xilinx Tool Caches -----
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.Xil/
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*/_ide/*
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!*/_ide/bitstream/
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# ----- OS / Editor Files -----
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.DS_Store
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Thumbs.db
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*.swp
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*~
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*.bak
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*.swo
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# ----- Python Cache -----
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__pycache__/
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*.pyc
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# =============================================================================
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# Deliverables — explicitly tracked
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# (negation rules override the ignore patterns above)
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# =============================================================================
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!*/Debug/*.elf
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!*/Debug/sd_card/
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!*/_ide/bitstream/*.bit
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