yuysh
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  • Joined on 2025-08-22
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yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-06-09 03:39:24 +00:00
e19adb09f9 Fix bugs and Unify the PMU_OC logic
092cad794c Remove unecessary code in CPLD1
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yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-06-08 07:44:31 +00:00
1d92e2c53e Add DC Relay Control Logic
yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-06-08 02:14:38 +00:00
61076299a0 Add SPI testbench
yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-06-08 02:13:17 +00:00
4fd22c4919 Add Channel Naming for CPLD2
0c9843f9c8 Fix CPLD1 Rx_T
c828a3b019 Make the CPLD_Con more readable
36e6eb5768 Unify the OC_Con logic
607b43837d Fix RC_RLSel Shifting logic(2/?)
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yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-06-02 09:22:00 +00:00
ff4d6a10cc Fix RC_RLSel Shifting logic
yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-06-02 03:23:47 +00:00
ed3fbd7cf5 Fix the SPI MISO logic
yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-06-01 10:03:40 +00:00
070ad1c768 Merge branch 'master' of http://mkb.local:3000/yuysh/NewInstrCalBoard_CPLD
34b8bdbdd8 Add SPI_Reg testbench
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yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-06-01 08:18:29 +00:00
263eb9f16d TODO: Fix MISO logic (1/?)
8f65c6908d Change RC_RLSel logic
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yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-06-01 06:45:20 +00:00
e60d56dd26 Change MISO logic
yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-06-01 04:37:09 +00:00
5b949c6b63 Fix MISO Logic
yuysh pushed to master at yuysh/NewInstrCalBoard_Zynq 2026-06-01 02:51:52 +00:00
6991600083 Add CPLD_Con.c/h: Move CPLD Control Code to seperate file.
yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-05-29 10:29:10 +00:00
54a64ec222 Bug fixes for all CPLDs
yuysh pushed to master at yuysh/NewInstrCalBoard_Zynq 2026-05-29 10:16:39 +00:00
a4abf50594 Fix u_rLoad shifting bug
yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-05-29 09:42:15 +00:00
b3eef70c28 CPLD1 fix DMM & OC shifting logic
yuysh pushed to master at yuysh/NewInstrCalBoard_CPLD 2026-05-29 08:49:39 +00:00
3e722a7f15 Modify simulation files
yuysh pushed to master at yuysh/NewInstrCalBoard_Zynq 2026-05-29 06:09:16 +00:00
893467bdfe Add CPLD DC Processing
yuysh pushed to master at yuysh/NewInstrCalBoard_Zynq 2026-05-28 10:37:04 +00:00
6f02f47407 Moved echo.c -> echo.c.bak
54777d3fd9 Add Command Parser
67faaf25d2 Remove unnecessary tracked files
f4150f12fe Update gitignore
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yuysh pushed to master at yuysh/NewInstrCalBoard_Zynq 2026-05-28 09:26:25 +00:00
0424f932a1 Remove unnecessary tracked files
yuysh pushed to master at yuysh/NewInstrCalBoard_Zynq 2026-05-28 09:01:52 +00:00
50d16ab13d Merge branch 'master' of http://mkb.local:3000/yuysh/NewInstrCalBoard_Zynq
480f680726 Add UART Debugging code
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yuysh pushed to master at yuysh/NewInstrCalBoard_Zynq 2026-05-28 08:56:00 +00:00
41aeab4240 Update .gitignore: add universal .metadata/, export/, tempdsa/, RemoteSystemsTempFiles/ patterns
fd6f7b6332 Add general .gitignore for Xilinx Vivado/Vitis/SDK projects
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