Jeremy Shen
e3e3763dc4
Fix 1 — SubStepFrame readability:
- FONT_BODY (12pt) instead of FONT_SMALL dots/labels
- Number-circle colored dots (CIRCLE_PENDING/RUNNING/COMPLETE/ERROR)
- Accent-colored labels matching StepHeader (ACCENT_*)
- Percentage label next to running phase name
Fix 2 — erase_all full-chip erase:
- Creates temp zero-filled file of flash capacity (from flash_model)
- Uses -erase_only with dummy file instead of failing -erase_all flag
- Supports s25fl256s1 (32MB) which lacks density info for -erase_all
- _flash_capacity() maps model name→bytes
Fix 3 — Error state:
- set_phase('error') shows ✗ red on all sub-steps
- Only shows 'done' (green ●) on actual success
Fix 4 — Style consistency:
- Sub-step colors match StepHeader: CIRCLE_*/ACCENT_*/SUCCESS/DANGER
26 lines
869 B
YAML
26 lines
869 B
YAML
bootloader_bin_path: /home/ly0kos/work/Verify/FW/tftp_app/bootloader/bootloader_z100_800M.bin
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bootloader_bit_path: /home/ly0kos/work/Verify/FW/tftp_app/bootloader/pl_arm_wrapper_hw_platform_0/pl_arm_wrapper.bit
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bootloader_elf_path: /home/ly0kos/work/Verify/FW/tftp_app/bootloader/app.elf
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erase_all: true
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firmware_bin_path: /home/ly0kos/work/Verify/FW/V1.3.1.3.3_06_01_pmu_cpld_check/V1.3.1.3.3_06_01_pmu_cpld_check.bin
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flash_model: s25fl256s1
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flash_type: qspi-x4-single
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fsbl_elf_path: /home/ly0kos/work/Verify/FPGA/Xilinx/Z100/fsbl_qspi_bypass.elf
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inter_step_delay: 2
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ping_count: 3
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ping_timeout: 5
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reboot_timeout: 30
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serial_baudrate: 115200
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serial_port: /dev/ttyUSB0
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step_timeouts:
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bitstream: 60
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check_env: 30
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elf_download: 60
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flash_erase: 120
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flash_program: 600
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tftp_reboot: 120
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tftp_upload_name: z7bin
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uart_delay: 3
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vitis_path: ''
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zynq_ip: 192.168.100.11
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