BREAKING: Replaces obsolete impact (ISE-era) and misused bootgen with the correct Xilinx 2018.3–2023.2 toolchain. Toolchain changes: - vitis_checker: impact → xsct + program_flash + bootgen detection - flash_programmer: bootgen/impact → program_flash (erase + program + verify) - bitstream_programmer: impact → xsct fpga/dow (primary), vivado (fallback) - Removed duplicated _get_impact_path() — now shared from vitis_checker Config additions: - fsbl_elf_path: FSBL ELF required by program_flash for QSPI init - flash_type: QSPI mode (default: qspi-x4-single) GUI additions: - FSBL ELF file selector in Configuration panel - Step 2 validates FSBL ELF is selected - Step 1 now shows xsct/program_flash/bootgen in tool check
38 lines
1023 B
YAML
38 lines
1023 B
YAML
# Default configuration for Zynq XC7Z100 Flasher
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# Paths are relative to this config file's directory.
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# Vitis/Vivado installation path (where bootgen, impact, etc. reside)
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vitis_path: ""
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# Zynq device network settings
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zynq_ip: "192.168.100.11"
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tftp_upload_name: "z7bin"
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# Serial port settings
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serial_port: ""
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serial_baudrate: 115200
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# File paths (relative to config file directory)
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# Bootloader files (Step 3: Load Bootloader)
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bootloader_bit_path: ""
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bootloader_elf_path: ""
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# Flash programming (Step 2: Program & Verify Flash)
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# bootloader_bin_path is the bootloader image to program into QSPI flash
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# fsbl_elf_path is the FSBL (First Stage Boot Loader) required by program_flash
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# flash_type sets the QSPI interface mode (qspi-x4-single, qspi-x8-dual_parallel, etc.)
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bootloader_bin_path: ""
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fsbl_elf_path: ""
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flash_type: "qspi-x4-single"
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# Firmware upload (Step 4: Load Main Program via TFTP)
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firmware_bin_path: ""
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# Reboot settings
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reboot_timeout: 30
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# Ping verification settings
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ping_timeout: 5
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ping_count: 3
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