# Default configuration for Zynq XC7Z100 Flasher
# Paths are relative to this config file's directory.

# Vitis/Vivado installation path (where bootgen, impact, etc. reside)
vitis_path: ""

# Zynq device network settings
zynq_ip: "192.168.100.11"
tftp_upload_name: "z7bin"

# Serial port settings
serial_port: ""
serial_baudrate: 115200

# File paths (relative to config file directory)

# Bootloader files (Step 3: Load Bootloader)
bootloader_bit_path: ""
bootloader_elf_path: ""

# Flash programming (Step 2: Program & Verify Flash)
# bootloader_bin_path is the bootloader image to program into QSPI flash
# fsbl_elf_path is the FSBL (First Stage Boot Loader) required by program_flash
# flash_type sets the QSPI interface mode (qspi-x4-single, qspi-x8-dual_parallel, etc.)
# flash_model determines chip capacity: s25fl256s1=32MiB, s25fl128s=16MiB, etc.
# erase_before_program: if true, erase flash sectors before programming
bootloader_bin_path: ""
fsbl_elf_path: ""
flash_type: "qspi-x4-single"
flash_model: "s25fl256s1"
erase_before_program: true

# Firmware upload (Step 4: Load Main Program via TFTP)
firmware_bin_path: ""

# Reboot settings
reboot_timeout: 30

# Ping verification settings
ping_timeout: 5
ping_count: 3

# Step timing (seconds) — used for progress bar max and timeout (experience × 2)
step_timeouts:
  check_env: 30      # Step 1: tool detection + JTAG scan (~5s actual)
  flash_erase: 120   # Step 2a: QSPI chip erase (~40s actual for 17MB)
  flash_program: 600 # Step 2b: QSPI program+verify (~300s actual for 17MB at x4)
  bitstream: 60      # Step 3a: FPGA configuration via JTAG (~16s actual)
  elf_download: 60   # Step 3b: ELF download to PS via JTAG (~9s actual)
  tftp_reboot: 120   # Step 4: TFTP upload + reboot + boot verify (~30s network)

# Delays (seconds)
inter_step_delay: 2
uart_delay: 3