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97a116b36f
fix: cancel SD timer on new log output; change popup prompt to QSPI
yuysh
2026-06-12 18:29:36 +08:00
fce940926f
feat: SD boot mode detection — kill hw_server + popup after 30s if Boot mode is SD
yuysh
2026-06-12 18:16:35 +08:00
c0f7219d30
fix: replace Popen readline loop with subprocess.run for Windows pipe reliability; add close_hw before quit in TCL; revert console=True
yuysh
2026-06-12 17:46:11 +08:00
4da03e97d8
fix: open_hw_manager→open_hw for 2018.3 batch mode compat; revert console=True
yuysh
2026-06-12 17:37:54 +08:00
c9eae220f0
Fix naming
yuysh
2026-06-12 17:24:01 +08:00
e09f16a3aa
fix: Xilinx 2018.3 tool discovery — add SDK dir, .bat PATH search, older versions
yuysh
2026-06-12 17:20:49 +08:00
47ea614ba2
fix: switch to console=False (GUI only, no terminal window)
yuysh
2026-06-12 16:56:56 +08:00
13ed0d89f8
fix: resolve config.yaml path to exe directory when frozen (PyInstaller)
yuysh
2026-06-12 16:55:35 +08:00
0d66f65ef2
feat: add PyInstaller spec + Windows build script (console=True)
yuysh
2026-06-12 16:51:26 +08:00
4c01acdf69
fix: print log messages to terminal in addition to GUI
yuysh
2026-06-12 16:38:51 +08:00
c0cac5b2c5
fix: ping_ip bool unpack, skip sub-step visibility, IP 192.168.100.11 after Step 3
yuysh
2026-06-12 16:35:32 +08:00
5ed195e2d6
fix: skip marking, fixed panel ratio, dialog hints, 30s boot, ping+UDP fallback
yuysh
2026-06-12 16:10:28 +08:00
639f2e3ce6
feat: 5 improvements — file info, download verify, UART warning, status display, COM port reuse
yuysh
2026-06-12 15:47:40 +08:00
9502bba636
fix: config save broken (relative_to→relpath), startup validation, auto-create, untrack config.yaml
yuysh
2026-06-12 15:02:09 +08:00
9238cbc63e
fix: correct indentation errors in widgets.py (TftpSubStepFrame, UartMonitorWindow)
yuysh
2026-06-12 14:14:17 +08:00
f330f8c276
fix: remove 'uboot'/'u-boot' from fail keywords — too broad
yuysh
2026-06-11 18:13:30 +08:00
04ad61e694
fix: convert all TCL-embedded paths to forward slashes (cross-platform)
yuysh
2026-06-11 18:11:44 +08:00
4ca15c1190
fix: detect flash failure from output even when returncode is 0
yuysh
2026-06-11 18:00:49 +08:00
4453fc8e12
feat: validate JTAG Zynq part matches config.zynq_part (default XC7Z100)
yuysh
2026-06-11 17:38:27 +08:00
799da5b2f3
fix: Windows common paths try .bat before .exe (Xilinx tools are .bat)
yuysh
2026-06-11 17:34:36 +08:00
7e8427d522
fix: redirect Vivado .jou/.log to temp dir with -tempDir
yuysh
2026-06-11 17:26:41 +08:00
66c04da5e0
fix: stream Vivado output live, remove broken normalize_port
yuysh
2026-06-11 17:24:31 +08:00
954aed7c0d
chore: expand .gitignore for all Vivado/Xilinx temp files
yuysh
2026-06-11 17:03:18 +08:00
474e3f122b
fix: use Vivado TCL for JTAG check — xsct 'targets' has broken TCL list parsing
yuysh
2026-06-11 17:02:23 +08:00
dd35ab0846
fix: use xsct 'jtag targets' for raw JTAG chain with IDCODE
yuysh
2026-06-11 16:45:37 +08:00
86d65641cc
chore: gitignore Vivado/JTAG temp files, delete existing ones
yuysh
2026-06-11 16:37:21 +08:00
7716171aeb
fix: use xsct (not Vivado) for JTAG check + normalize COM>=10 ports on Windows
yuysh
2026-06-11 16:29:32 +08:00
91417f609e
fix: start hw_server explicitly before Vivado JTAG scan
yuysh
2026-06-11 15:57:53 +08:00
72d0eceb8d
fix: don't restart Boot Verify pulse after step 4 already completed it
yuysh
2026-06-11 15:49:10 +08:00
1619dc194f
fix: two-phase boot wait — don't stop on version when IP still pending
yuysh
2026-06-11 15:41:21 +08:00
267cae93b6
fix: use tempfile.gettempdir() instead of hardcoded /tmp/ for JTAG TCL file
yuysh
2026-06-11 15:36:04 +08:00
17c8f2d68b
refactor: replace all config.vitis_path with config.xilinx_path across codebase
yuysh
2026-06-11 15:33:54 +08:00
61f0e6cd2b
🐛 fix: Step 1 JTAG check uses shared vivado path finder + build_tool_command
yuysh
2026-06-11 15:30:43 +08:00
6d686964e2
🐛 fix: Step 4 boot wait uses UART window monitor data, not just main monitor
yuysh
2026-06-11 15:21:36 +08:00
da94cc6cdc
🐛 fix: lambda closure crash + .bat version noise on Windows
yuysh
2026-06-11 15:18:08 +08:00
70c88815cc
✨ feat: auto-discover Zynq IP after reboot (UART or UDP scan)
yuysh
2026-06-11 15:11:59 +08:00
32b201cf8e
✨ feat: Windows .bat support + settings64 env setup for Xilinx tools
yuysh
2026-06-11 15:08:25 +08:00
21acc16c8c
✨ feat: smart Xilinx version scanning — pick newest, log all versions
yuysh
2026-06-11 14:56:40 +08:00
475042c85c
🐛 fix: JTAG reboot 'Already running' error after rst -system
yuysh
2026-06-11 14:48:45 +08:00
f6cf5de96f
✨ feat: UART boot wait, serial validation, xsct logging, layout fix
yuysh
2026-06-11 14:44:58 +08:00
9b07a4d5ca
✨ feat: add scrollbar via CTkScrollableFrame for window resize
yuysh
2026-06-11 14:29:17 +08:00
84142bb229
🎨 style: compact 2-col Utility panel, both reboot buttons red
yuysh
2026-06-11 14:27:48 +08:00
f04fbe2130
✨ feat: add TFTP download verify, Step 4 sub-steps, and fix UI layout
yuysh
2026-06-11 11:47:35 +08:00
5ce544cd3c
🐛 fix: recover JTAG DAP after flash programming with system reset
Jeremy Shen
2026-06-10 18:29:26 +08:00
73b8225a27
feat: DAP error detection and recovery in Step 3 TCL
Jeremy Shen
2026-06-10 17:52:14 +08:00
0568315b83
fix: re-read config.yaml before each workflow run
Jeremy Shen
2026-06-10 17:04:32 +08:00
7067ce273f
feat: user TCL flow + parser dedup + Python TFTP
Jeremy Shen
2026-06-10 16:57:54 +08:00
9a7a625c46
feat: boot mode parsing, FSBL-first flow, UI reorder
Jeremy Shen
2026-06-10 16:20:12 +08:00
47569a0e43
refactor: ELF step uses FSBL instead of ps7_init
Jeremy Shen
2026-06-10 16:09:05 +08:00
8b2fac931c
fix: FirmWare version parsing + prevent boot-from-Flash in ELF step
Jeremy Shen
2026-06-10 15:50:31 +08:00
09be20791f
feat: forward UART parsed boot info to main log window
Jeremy Shen
2026-06-10 15:40:09 +08:00
b294dfe58a
fix: ELF step no longer re-runs ps7_init unnecessarily
Jeremy Shen
2026-06-10 15:30:11 +08:00
a47e3b78ae
fix: avoid serial port conflict between workflow and UART window
Jeremy Shen
2026-06-10 15:23:28 +08:00
2695180c8f
fix: auto-start UART monitoring on port open success
Jeremy Shen
2026-06-10 15:21:12 +08:00
8130578f70
fix: remove grab_set() to allow main window interaction
Jeremy Shen
2026-06-10 15:04:39 +08:00
778bee5d19
fix: import DARK_CARD + use hasattr for vitis_path
Jeremy Shen
2026-06-10 15:00:15 +08:00
b4126a14ac
fix: add missing DARK_CARD import in widgets.py
Jeremy Shen
2026-06-10 14:58:48 +08:00
7afc9051ab
fix: defer grab_set() to avoid 'window not viewable' error
Jeremy Shen
2026-06-10 14:53:22 +08:00
d5fd816ff9
✨ feat: UART Monitor standalone window
Jeremy Shen
2026-06-10 14:51:13 +08:00
93ab224d6d
✨ feat: Xilinx Kit directory selector + multi-version scan
Jeremy Shen
2026-06-10 14:27:47 +08:00
699ad82834
🐛 fix: sub-step default expanded, real-time checkbox, startup freeze, color sync
Jeremy Shen
2026-06-10 14:11:59 +08:00
35bd6e600c
Revert sub-step custom colors — use default CTkLabel white text
Jeremy Shen
2026-06-10 13:54:06 +08:00
e3e3763dc4
🐛 fix: sub-step readability, erase_all workaround, error state
Jeremy Shen
2026-06-10 13:51:41 +08:00
95c04d94ae
✨ feat: collapsible flash sub-steps UI + erase_all checkbox
Jeremy Shen
2026-06-10 13:45:57 +08:00
ea3e3b8ac7
✨ feat: flash phase tracking, erase checkbox, flash_model config
Jeremy Shen
2026-06-10 13:39:11 +08:00
2c48224aea
✨ feat: UART monitor, step timeouts, and non-blocking subprocess output
Jeremy Shen
2026-06-10 13:21:32 +08:00
ab7264d5c7
🐛 fix(xsct): PS init before FPGA config keeps JTAG DAP alive
Jeremy Shen
2026-06-10 12:53:02 +08:00
80fb704221
🐛 fix(xsct): TCL file instead of -eval, add ps7_init, remove broken Vivado ELF path
Jeremy Shen
2026-06-10 12:47:59 +08:00
cddacc5d9f
♻️ refactor(toolchain): replace impact/bootgen with xsct/program_flash + add fsbl
Jeremy Shen
2026-06-10 12:13:02 +08:00
1ad2dcdeb9
fix(config): correct path to project root config.yaml
Jeremy Shen
2026-06-10 11:50:14 +08:00
8f83fa9eae
fix(config): save user config to project root config.yaml
Jeremy Shen
2026-06-10 11:47:43 +08:00
1bbce6e72a
🐛 fix(config): save to config.yaml instead of default_config.yaml
Jeremy Shen
2026-06-10 11:21:34 +08:00
9de0153854
🐛 fix(gui): fix config save and UI freeze on startup
Jeremy Shen
2026-06-10 10:58:29 +08:00
7ac04a6bea
✨ feat(serial): add version test via 'ver()' command
Jeremy Shen
2026-06-10 10:20:05 +08:00
fddcc3689a
🐛 fix(gui): make UART unavailable notification persistent
Jeremy Shen
2026-06-10 10:06:50 +08:00
b222bd4586
🐛 fix(gui): allow all steps to be runnable independently
Jeremy Shen
2026-06-10 10:00:28 +08:00
f7cf179aa4
🐛 fix(gui): single-step execution now runs only selected step
Jeremy Shen
2026-06-10 09:53:42 +08:00
0af388a8f6
🐛 fix(gui): add time import and fix left panel layout scaling
Jeremy Shen
2026-06-10 09:46:28 +08:00
62609b6e80
✨ feat(jtag): enhance Zynq JTAG detection with PS/PL status
Jeremy Shen
2026-06-10 09:43:02 +08:00
2bde6d869e
✨ feat(jtag): add Zynq JTAG presence detection via hw_server
Jeremy Shen
2026-06-09 18:33:50 +08:00
90c3dca8b8
fix(vitis): add xsct fallback for impact detection in Xilinx 2023.2
Jeremy Shen
2026-06-09 18:07:39 +08:00
3a9bc5d9ed
✨ feat(uart): add UART availability check, inter-step delays, and post-download Zynq status verification
Jeremy Shen
2026-06-09 17:53:48 +08:00
91a7843dbe
🐛 fix(gui): resolve step header layout overlaps and improve scaling
Jeremy Shen
2026-06-09 17:30:36 +08:00
bda64d5f46
♻️ refactor(gui): improve left panel readability with better fonts, colors, and layout
Jeremy Shen
2026-06-09 17:12:41 +08:00
5277c88e3d
refactor(gui,config): rename file path fields and split BIN selector
Jeremy Shen
2026-06-09 16:58:45 +08:00
bd39023ba7
feat: initial Zynq XC7Z100 Flasher GUI project
Jeremy Shen
2026-06-08 11:33:50 +08:00
yuysh
Jeremy Shen