feat: flash phase tracking, erase checkbox, flash_model config

Step 2 UI now shows real-time flash operation phases parsed from program_flash output:
- Erase: "Performing Erase Operation..." → sf erase → Erased: OK
- Program: "Performing Program Operation..." → write blocks 0%→100%
- Verify: "Performing Verify Operation..." → read+cmp 0%→100%

Configuration additions:
- erase_before_program checkbox: controls whether to pre-erase before programming
- flash_model: chip type for capacity reference (s25fl256s1 = 32 MiB)

subprocess_utils.py now emits 'phase' callbacks (erase/program/verify/done)
detected from program_flash output transitions.
This commit is contained in:
Jeremy Shen
2026-06-10 13:39:11 +08:00
parent 2c48224aea
commit ea3e3b8ac7
6 changed files with 101 additions and 17 deletions
+7 -6
View File
@@ -3,6 +3,8 @@ bootloader_bit_path: /home/ly0kos/work/Verify/FW/tftp_app/bootloader/pl_arm_wrap
bootloader_elf_path: /home/ly0kos/work/Verify/FW/tftp_app/bootloader/app.elf
firmware_bin_path: /home/ly0kos/work/Verify/FW/V1.3.1.3.3_06_01_pmu_cpld_check/V1.3.1.3.3_06_01_pmu_cpld_check.bin
flash_type: qspi-x4-single
flash_model: s25fl256s1
erase_before_program: true
fsbl_elf_path: /home/ly0kos/work/Verify/FPGA/Xilinx/Z100/fsbl_qspi_bypass.elf
inter_step_delay: 2
ping_count: 3
@@ -10,15 +12,14 @@ ping_timeout: 5
reboot_timeout: 30
serial_baudrate: 115200
serial_port: /dev/ttyUSB0
tftp_upload_name: z7bin
uart_delay: 3
inter_step_delay: 2
step_timeouts:
bitstream: 60
check_env: 30
elf_download: 60
flash_erase: 120
flash_program: 600
bitstream: 60
elf_download: 60
tftp_reboot: 120
vitis_path: ""
tftp_upload_name: z7bin
uart_delay: 3
vitis_path: ''
zynq_ip: 192.168.100.11