✨ feat: UART monitor, step timeouts, and non-blocking subprocess output

Based on real hardware timing data from XC7Z100 testing:

UART Monitoring:
- New UartMonitor class in serial_monitor.py: background thread reads
  serial output continuously, parses for IP/version/boot messages
- GUI starts monitor when workflow runs, stops on completion/close
- Serial lines flow into log display in real time

Step Timing:
- New step_timeouts config (experience × 2):
  check_env:30s flash_erase:120s flash_program:600s
  bitstream:60s elf_download:60s tftp_reboot:120s
- GUI shows estimated timeout before each step
- Shows actual elapsed time after each step completes
- All subprocess calls now use config-driven timeouts

Non-blocking Output:
- New subprocess_utils.py: run_streaming() uses Popen + threaded
  stdout/stderr readers, parses WARNING/ERROR/progress% in real time
- flash_programmer and bitstream_programmer use it
- Callbacks receive categorized events (out/err/warn/error/progress/done)

config.yaml

@@ -0,0 +1,24 @@
+bootloader_bin_path: /home/ly0kos/work/Verify/FW/tftp_app/bootloader/bootloader_z100_800M.bin
+bootloader_bit_path: /home/ly0kos/work/Verify/FW/tftp_app/bootloader/pl_arm_wrapper_hw_platform_0/pl_arm_wrapper.bit
+bootloader_elf_path: /home/ly0kos/work/Verify/FW/tftp_app/bootloader/app.elf
+firmware_bin_path: /home/ly0kos/work/Verify/FW/V1.3.1.3.3_06_01_pmu_cpld_check/V1.3.1.3.3_06_01_pmu_cpld_check.bin
+flash_type: qspi-x4-single
+fsbl_elf_path: /home/ly0kos/work/Verify/FPGA/Xilinx/Z100/fsbl_qspi_bypass.elf
+inter_step_delay: 2
+ping_count: 3
+ping_timeout: 5
+reboot_timeout: 30
+serial_baudrate: 115200
+serial_port: /dev/ttyUSB0
+tftp_upload_name: z7bin
+uart_delay: 3
+inter_step_delay: 2
+step_timeouts:
+  check_env: 30
+  flash_erase: 120
+  flash_program: 600
+  bitstream: 60
+  elf_download: 60
+  tftp_reboot: 120
+vitis_path: ""
+zynq_ip: 192.168.100.11