✨ feat: UART monitor, step timeouts, and non-blocking subprocess output

Based on real hardware timing data from XC7Z100 testing:

UART Monitoring:
- New UartMonitor class in serial_monitor.py: background thread reads
  serial output continuously, parses for IP/version/boot messages
- GUI starts monitor when workflow runs, stops on completion/close
- Serial lines flow into log display in real time

Step Timing:
- New step_timeouts config (experience × 2):
  check_env:30s flash_erase:120s flash_program:600s
  bitstream:60s elf_download:60s tftp_reboot:120s
- GUI shows estimated timeout before each step
- Shows actual elapsed time after each step completes
- All subprocess calls now use config-driven timeouts

Non-blocking Output:
- New subprocess_utils.py: run_streaming() uses Popen + threaded
  stdout/stderr readers, parses WARNING/ERROR/progress% in real time
- flash_programmer and bitstream_programmer use it
- Callbacks receive categorized events (out/err/warn/error/progress/done)

config/default_config.yaml

@@ -35,3 +35,16 @@ reboot_timeout: 30
 # Ping verification settings
 ping_timeout: 5
 ping_count: 3
+
+# Step timing (seconds) — used for progress bar max and timeout (experience × 2)
+step_timeouts:
+  check_env: 30      # Step 1: tool detection + JTAG scan (~5s actual)
+  flash_erase: 120   # Step 2a: QSPI chip erase (~40s actual for 17MB)
+  flash_program: 600 # Step 2b: QSPI program+verify (~300s actual for 17MB at x4)
+  bitstream: 60      # Step 3a: FPGA configuration via JTAG (~16s actual)
+  elf_download: 60   # Step 3b: ELF download to PS via JTAG (~9s actual)
+  tftp_reboot: 120   # Step 4: TFTP upload + reboot + boot verify (~30s network)
+
+# Delays (seconds)
+inter_step_delay: 2
+uart_delay: 3