58 lines
2.9 KiB
XML
58 lines
2.9 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<Description>Composite Fileset</Description>
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<Generation Name="SIMULATION" State="GENERATED" Timestamp="1779695252"/>
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<Generation Name="IMPLEMENTATION" State="GENERATED" Timestamp="1779695252"/>
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<Generation Name="HW_HANDOFF" State="GENERATED" Timestamp="1779695252"/>
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<FileCollection Name="SOURCES" Type="SOURCES">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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<File Name="sim/system.v" Type="Verilog">
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<Properties IsEditable="false" IsVisible="true" IsNetlistSimulation="false" Timestamp="0" IsTrackable="false" IsStatusTracked="false"/>
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<Library Name="xil_defaultlib"/>
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</File>
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<Library Name="xil_defaultlib"/>
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