1506 lines
43 KiB
Plaintext
1506 lines
43 KiB
Plaintext
{
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"design": {
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"design_info": {
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"boundary_crc": "0xF05D3B15999F7489",
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"device": "xc7z035ffg676-2",
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"gen_directory": "../../../../Debug_FW.gen/sources_1/bd/system",
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"name": "system",
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"rev_ctrl_bd_flag": "RevCtrlBdOff",
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"synth_flow_mode": "None",
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"tool_version": "2023.2",
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"validated": "true"
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},
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"design_tree": {
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"processing_system7_0": "",
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"dna_port_read_0": "",
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"mydna_read_v1_0_0": "",
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"ps7_0_axi_periph": {
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"s00_couplers": {
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"auto_pc": ""
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}
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},
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"rst_ps7_0_100M": ""
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},
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"interface_ports": {
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"DDR": {
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"mode": "Master",
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"vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0",
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"vlnv": "xilinx.com:interface:ddrx_rtl:1.0",
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"parameters": {
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"AXI_ARBITRATION_SCHEME": {
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"value": "TDM",
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"value_src": "default"
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},
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"BURST_LENGTH": {
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"value": "8",
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"value_src": "default"
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},
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"CAN_DEBUG": {
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"value": "false",
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"value_src": "default"
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},
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"CAS_LATENCY": {
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"value": "11",
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"value_src": "default"
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},
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"CAS_WRITE_LATENCY": {
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"value": "11",
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"value_src": "default"
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},
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"CS_ENABLED": {
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"value": "true",
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"value_src": "default"
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},
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"DATA_MASK_ENABLED": {
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"value": "true",
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"value_src": "default"
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},
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"DATA_WIDTH": {
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"value": "8",
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"value_src": "default"
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},
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"MEMORY_TYPE": {
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"value": "COMPONENTS",
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"value_src": "default"
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},
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"MEM_ADDR_MAP": {
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"value": "ROW_COLUMN_BANK",
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"value_src": "default"
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},
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"SLOT": {
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"value": "Single",
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"value_src": "default"
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},
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"TIMEPERIOD_PS": {
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"value": "1250",
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"value_src": "default"
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}
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},
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"port_maps": {
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"CAS_N": {
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"physical_name": "DDR_cas_n",
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"direction": "IO"
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},
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"CKE": {
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"physical_name": "DDR_cke",
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"direction": "IO"
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},
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"CK_N": {
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"physical_name": "DDR_ck_n",
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"direction": "IO"
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},
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"CK_P": {
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"physical_name": "DDR_ck_p",
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"direction": "IO"
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},
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"CS_N": {
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"physical_name": "DDR_cs_n",
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"direction": "IO"
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},
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"RESET_N": {
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"physical_name": "DDR_reset_n",
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"direction": "IO"
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},
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"ODT": {
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"physical_name": "DDR_odt",
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"direction": "IO"
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},
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"RAS_N": {
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"physical_name": "DDR_ras_n",
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"direction": "IO"
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},
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"WE_N": {
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"physical_name": "DDR_we_n",
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"direction": "IO"
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},
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"BA": {
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"physical_name": "DDR_ba",
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"direction": "IO",
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"left": "2",
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"right": "0"
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},
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"ADDR": {
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"physical_name": "DDR_addr",
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"direction": "IO",
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"left": "14",
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"right": "0"
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},
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"DM": {
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"physical_name": "DDR_dm",
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"direction": "IO",
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"left": "3",
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"right": "0"
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},
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"DQ": {
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"physical_name": "DDR_dq",
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"direction": "IO",
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"left": "31",
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"right": "0"
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},
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"DQS_N": {
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"physical_name": "DDR_dqs_n",
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"direction": "IO",
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"left": "3",
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"right": "0"
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},
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"DQS_P": {
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"physical_name": "DDR_dqs_p",
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"direction": "IO",
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"left": "3",
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"right": "0"
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}
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}
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},
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"FIXED_IO": {
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"mode": "Master",
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"vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0",
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"vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0",
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"parameters": {
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"CAN_DEBUG": {
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"value": "false",
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"value_src": "default"
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}
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},
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"port_maps": {
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"MIO": {
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"physical_name": "FIXED_IO_mio",
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"direction": "IO",
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"left": "53",
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"right": "0"
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},
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"DDR_VRN": {
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"physical_name": "FIXED_IO_ddr_vrn",
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"direction": "IO"
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},
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"DDR_VRP": {
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"physical_name": "FIXED_IO_ddr_vrp",
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"direction": "IO"
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},
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"PS_SRSTB": {
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"physical_name": "FIXED_IO_ps_srstb",
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"direction": "IO"
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},
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"PS_CLK": {
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"physical_name": "FIXED_IO_ps_clk",
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"direction": "IO"
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},
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"PS_PORB": {
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"physical_name": "FIXED_IO_ps_porb",
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"direction": "IO"
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}
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}
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},
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"EMIO_0": {
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"mode": "Master",
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"vlnv_bus_definition": "xilinx.com:interface:gpio:1.0",
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"vlnv": "xilinx.com:interface:gpio_rtl:1.0",
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"port_maps": {
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"TRI_I": {
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"physical_name": "EMIO_0_tri_i",
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"direction": "I",
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"left": "32",
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"right": "0"
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},
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"TRI_O": {
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"physical_name": "EMIO_0_tri_o",
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"direction": "O",
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"left": "32",
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"right": "0"
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},
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"TRI_T": {
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"physical_name": "EMIO_0_tri_t",
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"direction": "O",
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"left": "32",
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"right": "0"
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}
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}
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}
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},
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"components": {
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"processing_system7_0": {
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"vlnv": "xilinx.com:ip:processing_system7:5.5",
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"ip_revision": "6",
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"xci_name": "system_processing_system7_0_0",
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"xci_path": "ip/system_processing_system7_0_0/system_processing_system7_0_0.xci",
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"inst_hier_path": "processing_system7_0",
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"parameters": {
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"PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
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"value": "666.666687"
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},
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"PCW_ACT_CAN_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_DCI_PERIPHERAL_FREQMHZ": {
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"value": "10.158730"
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},
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"PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": {
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"value": "125.000000"
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},
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"PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": {
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"value": "100.000000"
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},
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"PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": {
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"value": "200.000000"
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},
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"PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": {
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"value": "142.857132"
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},
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"PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": {
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"value": "50.000000"
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},
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"PCW_ACT_SMC_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
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"value": "10.000000"
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},
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"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
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"value": "200.000000"
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},
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"PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_ACT_UART_PERIPHERAL_FREQMHZ": {
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"value": "100.000000"
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},
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"PCW_ACT_WDT_PERIPHERAL_FREQMHZ": {
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"value": "111.111115"
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},
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"PCW_CLK0_FREQ": {
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"value": "100000000"
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},
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"PCW_CLK1_FREQ": {
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"value": "10000000"
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},
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"PCW_CLK2_FREQ": {
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"value": "10000000"
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},
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"PCW_CLK3_FREQ": {
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"value": "10000000"
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},
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"PCW_DDR_RAM_HIGHADDR": {
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"value": "0x3FFFFFFF"
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},
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"PCW_ENET0_ENET0_IO": {
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"value": "MIO 16 .. 27"
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},
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"PCW_ENET0_GRP_MDIO_ENABLE": {
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"value": "1"
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},
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"PCW_ENET0_GRP_MDIO_IO": {
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"value": "MIO 52 .. 53"
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},
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"PCW_ENET0_PERIPHERAL_CLKSRC": {
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"value": "IO PLL"
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},
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"PCW_ENET0_PERIPHERAL_ENABLE": {
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"value": "1"
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},
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"PCW_ENET0_PERIPHERAL_FREQMHZ": {
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"value": "1000 Mbps"
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},
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"PCW_EN_EMIO_CD_SDIO0": {
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"value": "0"
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},
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"PCW_EN_EMIO_ENET0": {
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"value": "0"
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},
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"PCW_EN_EMIO_GPIO": {
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"value": "1"
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},
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"PCW_EN_EMIO_WP_SDIO0": {
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"value": "0"
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},
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"PCW_EN_ENET0": {
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"value": "1"
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},
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"PCW_EN_QSPI": {
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"value": "1"
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},
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"PCW_EN_SDIO0": {
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"value": "1"
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},
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"PCW_EN_UART1": {
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"value": "1"
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},
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"PCW_FPGA0_PERIPHERAL_FREQMHZ": {
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"value": "100"
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},
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"PCW_FPGA_FCLK0_ENABLE": {
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"value": "1"
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},
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"PCW_GPIO_EMIO_GPIO_ENABLE": {
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"value": "1"
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},
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"PCW_GPIO_EMIO_GPIO_IO": {
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"value": "33"
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},
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"PCW_GPIO_EMIO_GPIO_WIDTH": {
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"value": "33"
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},
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"PCW_MIO_16_IOTYPE": {
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"value": "LVCMOS 1.8V"
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},
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"PCW_MIO_16_PULLUP": {
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"value": "enabled"
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},
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"PCW_MIO_16_SLEW": {
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"value": "slow"
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},
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"PCW_MIO_17_IOTYPE": {
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"value": "LVCMOS 1.8V"
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},
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"PCW_MIO_17_PULLUP": {
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"value": "enabled"
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},
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"PCW_MIO_17_SLEW": {
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"value": "slow"
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},
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"PCW_MIO_18_IOTYPE": {
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"value": "LVCMOS 1.8V"
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},
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"PCW_MIO_18_PULLUP": {
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"value": "enabled"
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},
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"PCW_MIO_18_SLEW": {
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"value": "slow"
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},
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"PCW_MIO_19_IOTYPE": {
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"value": "LVCMOS 1.8V"
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},
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"PCW_MIO_19_PULLUP": {
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"value": "enabled"
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},
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"PCW_MIO_19_SLEW": {
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"value": "slow"
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},
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"PCW_MIO_1_IOTYPE": {
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"value": "LVCMOS 3.3V"
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},
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"PCW_MIO_1_PULLUP": {
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"value": "enabled"
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},
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"PCW_MIO_1_SLEW": {
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"value": "slow"
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},
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"PCW_MIO_20_IOTYPE": {
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"value": "LVCMOS 1.8V"
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},
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"PCW_MIO_20_PULLUP": {
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"value": "enabled"
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},
|
|
"PCW_MIO_20_SLEW": {
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"value": "slow"
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|
},
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|
"PCW_MIO_21_IOTYPE": {
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"value": "LVCMOS 1.8V"
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|
},
|
|
"PCW_MIO_21_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_21_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_22_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
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|
},
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|
"PCW_MIO_22_PULLUP": {
|
|
"value": "enabled"
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|
},
|
|
"PCW_MIO_22_SLEW": {
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"value": "slow"
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|
},
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|
"PCW_MIO_23_IOTYPE": {
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"value": "LVCMOS 1.8V"
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|
},
|
|
"PCW_MIO_23_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_23_SLEW": {
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|
"value": "slow"
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|
},
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|
"PCW_MIO_24_IOTYPE": {
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|
"value": "LVCMOS 1.8V"
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|
},
|
|
"PCW_MIO_24_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_24_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_25_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_25_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_25_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_26_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_26_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_26_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_27_IOTYPE": {
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|
"value": "LVCMOS 1.8V"
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|
},
|
|
"PCW_MIO_27_PULLUP": {
|
|
"value": "enabled"
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|
},
|
|
"PCW_MIO_27_SLEW": {
|
|
"value": "slow"
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|
},
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|
"PCW_MIO_2_IOTYPE": {
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|
"value": "LVCMOS 3.3V"
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|
},
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|
"PCW_MIO_2_SLEW": {
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|
"value": "slow"
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|
},
|
|
"PCW_MIO_3_IOTYPE": {
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|
"value": "LVCMOS 3.3V"
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|
},
|
|
"PCW_MIO_3_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_40_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_40_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_40_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_41_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_41_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_41_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_42_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_42_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_42_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_43_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_43_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_43_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_44_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_44_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_44_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_45_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_45_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_45_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_46_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_46_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_46_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_47_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_47_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_47_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_48_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_48_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_48_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_49_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_49_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_49_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_4_IOTYPE": {
|
|
"value": "LVCMOS 3.3V"
|
|
},
|
|
"PCW_MIO_4_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_52_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_52_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_52_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_53_IOTYPE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_MIO_53_PULLUP": {
|
|
"value": "enabled"
|
|
},
|
|
"PCW_MIO_53_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_5_IOTYPE": {
|
|
"value": "LVCMOS 3.3V"
|
|
},
|
|
"PCW_MIO_5_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_6_IOTYPE": {
|
|
"value": "LVCMOS 3.3V"
|
|
},
|
|
"PCW_MIO_6_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_8_IOTYPE": {
|
|
"value": "LVCMOS 3.3V"
|
|
},
|
|
"PCW_MIO_8_SLEW": {
|
|
"value": "slow"
|
|
},
|
|
"PCW_MIO_TREE_PERIPHERALS": {
|
|
"value": [
|
|
"unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#Quad SPI",
|
|
"Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet",
|
|
"0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#UART 1#UART",
|
|
"1#unassigned#unassigned#Enet 0#Enet 0"
|
|
]
|
|
},
|
|
"PCW_MIO_TREE_SIGNALS": {
|
|
"value": "unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#qspi_fbclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#clk#cmd#data[0]#data[1]#data[2]#data[3]#wp#cd#tx#rx#unassigned#unassigned#mdc#mdio"
|
|
},
|
|
"PCW_PRESET_BANK1_VOLTAGE": {
|
|
"value": "LVCMOS 1.8V"
|
|
},
|
|
"PCW_QSPI_GRP_FBCLK_ENABLE": {
|
|
"value": "1"
|
|
},
|
|
"PCW_QSPI_GRP_FBCLK_IO": {
|
|
"value": "MIO 8"
|
|
},
|
|
"PCW_QSPI_GRP_IO1_ENABLE": {
|
|
"value": "0"
|
|
},
|
|
"PCW_QSPI_GRP_SINGLE_SS_ENABLE": {
|
|
"value": "1"
|
|
},
|
|
"PCW_QSPI_GRP_SINGLE_SS_IO": {
|
|
"value": "MIO 1 .. 6"
|
|
},
|
|
"PCW_QSPI_GRP_SS1_ENABLE": {
|
|
"value": "0"
|
|
},
|
|
"PCW_QSPI_INTERNAL_HIGHADDRESS": {
|
|
"value": "0xFCFFFFFF"
|
|
},
|
|
"PCW_QSPI_PERIPHERAL_ENABLE": {
|
|
"value": "1"
|
|
},
|
|
"PCW_QSPI_PERIPHERAL_FREQMHZ": {
|
|
"value": "150"
|
|
},
|
|
"PCW_QSPI_QSPI_IO": {
|
|
"value": "MIO 1 .. 6"
|
|
},
|
|
"PCW_SD0_GRP_CD_ENABLE": {
|
|
"value": "1"
|
|
},
|
|
"PCW_SD0_GRP_CD_IO": {
|
|
"value": "MIO 47"
|
|
},
|
|
"PCW_SD0_GRP_POW_ENABLE": {
|
|
"value": "0"
|
|
},
|
|
"PCW_SD0_GRP_WP_ENABLE": {
|
|
"value": "1"
|
|
},
|
|
"PCW_SD0_GRP_WP_IO": {
|
|
"value": "MIO 46"
|
|
},
|
|
"PCW_SD0_PERIPHERAL_ENABLE": {
|
|
"value": "1"
|
|
},
|
|
"PCW_SD0_SD0_IO": {
|
|
"value": "MIO 40 .. 45"
|
|
},
|
|
"PCW_SDIO_PERIPHERAL_FREQMHZ": {
|
|
"value": "50"
|
|
},
|
|
"PCW_SDIO_PERIPHERAL_VALID": {
|
|
"value": "1"
|
|
},
|
|
"PCW_SINGLE_QSPI_DATA_MODE": {
|
|
"value": "x4"
|
|
},
|
|
"PCW_UART1_GRP_FULL_ENABLE": {
|
|
"value": "0"
|
|
},
|
|
"PCW_UART1_PERIPHERAL_ENABLE": {
|
|
"value": "1"
|
|
},
|
|
"PCW_UART1_UART1_IO": {
|
|
"value": "MIO 48 .. 49"
|
|
},
|
|
"PCW_UART_PERIPHERAL_FREQMHZ": {
|
|
"value": "100"
|
|
},
|
|
"PCW_UART_PERIPHERAL_VALID": {
|
|
"value": "1"
|
|
},
|
|
"PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
|
|
"value": "533.333374"
|
|
},
|
|
"PCW_UIPARAM_DDR_PARTNO": {
|
|
"value": "MT41K256M16 RE-125"
|
|
}
|
|
},
|
|
"interface_ports": {
|
|
"M_AXI_GP0": {
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
|
"mode": "Master",
|
|
"address_space_ref": "Data",
|
|
"base_address": {
|
|
"minimum": "0x40000000",
|
|
"maximum": "0x7FFFFFFF",
|
|
"width": "32"
|
|
}
|
|
}
|
|
},
|
|
"addressing": {
|
|
"address_spaces": {
|
|
"Data": {
|
|
"range": "4G",
|
|
"width": "32",
|
|
"local_memory_map": {
|
|
"name": "Data",
|
|
"description": "Address Space Segments",
|
|
"address_blocks": {
|
|
"segment1": {
|
|
"name": "segment1",
|
|
"display_name": "segment1",
|
|
"base_address": "0x00000000",
|
|
"range": "256K",
|
|
"width": "18",
|
|
"usage": "register"
|
|
},
|
|
"segment2": {
|
|
"name": "segment2",
|
|
"display_name": "segment2",
|
|
"base_address": "0x00040000",
|
|
"range": "256K",
|
|
"width": "19",
|
|
"usage": "register"
|
|
},
|
|
"segment3": {
|
|
"name": "segment3",
|
|
"display_name": "segment3",
|
|
"base_address": "0x00080000",
|
|
"range": "512K",
|
|
"width": "20",
|
|
"usage": "register"
|
|
},
|
|
"segment4": {
|
|
"name": "segment4",
|
|
"display_name": "segment4",
|
|
"base_address": "0x00100000",
|
|
"range": "1023M",
|
|
"width": "30",
|
|
"usage": "register"
|
|
},
|
|
"M_AXI_GP0": {
|
|
"name": "M_AXI_GP0",
|
|
"display_name": "M_AXI_GP0",
|
|
"base_address": "0x40000000",
|
|
"range": "1G",
|
|
"width": "31",
|
|
"usage": "register"
|
|
},
|
|
"M_AXI_GP1": {
|
|
"name": "M_AXI_GP1",
|
|
"display_name": "M_AXI_GP1",
|
|
"base_address": "0x80000000",
|
|
"range": "1G",
|
|
"width": "32",
|
|
"usage": "register"
|
|
},
|
|
"IO_Peripheral_Registers": {
|
|
"name": "IO_Peripheral_Registers",
|
|
"display_name": "IO Peripheral Registers",
|
|
"base_address": "0xE0000000",
|
|
"range": "3M",
|
|
"width": "32",
|
|
"usage": "register"
|
|
},
|
|
"SMC_Memories": {
|
|
"name": "SMC_Memories",
|
|
"display_name": "SMC Memories",
|
|
"base_address": "0xE1000000",
|
|
"range": "80M",
|
|
"width": "32",
|
|
"usage": "register"
|
|
},
|
|
"SLCR_Registers": {
|
|
"name": "SLCR_Registers",
|
|
"display_name": "SLCR Registers",
|
|
"base_address": "0xF8000000",
|
|
"range": "3K",
|
|
"width": "32",
|
|
"usage": "register"
|
|
},
|
|
"PS_System_Registers": {
|
|
"name": "PS_System_Registers",
|
|
"display_name": "PS System Registers",
|
|
"base_address": "0xF8001000",
|
|
"range": "8252K",
|
|
"width": "32",
|
|
"usage": "register"
|
|
},
|
|
"CPU_Private_Registers": {
|
|
"name": "CPU_Private_Registers",
|
|
"display_name": "CPU Private Registers",
|
|
"base_address": "0xF8900000",
|
|
"range": "6156K",
|
|
"width": "32",
|
|
"usage": "register"
|
|
},
|
|
"segment5": {
|
|
"name": "segment5",
|
|
"display_name": "segment5",
|
|
"base_address": "0xFC000000",
|
|
"range": "32M",
|
|
"width": "32",
|
|
"usage": "register"
|
|
},
|
|
"segment6": {
|
|
"name": "segment6",
|
|
"display_name": "segment6",
|
|
"base_address": "0xFFFC0000",
|
|
"range": "256K",
|
|
"width": "32",
|
|
"usage": "register"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"dna_port_read_0": {
|
|
"vlnv": "xilinx.com:module_ref:dna_port_read:1.0",
|
|
"ip_revision": "1",
|
|
"xci_name": "system_dna_port_read_0_0",
|
|
"xci_path": "ip/system_dna_port_read_0_0/system_dna_port_read_0_0.xci",
|
|
"inst_hier_path": "dna_port_read_0",
|
|
"reference_info": {
|
|
"ref_type": "hdl",
|
|
"ref_name": "dna_port_read",
|
|
"boundary_crc": "0x0"
|
|
},
|
|
"ports": {
|
|
"clk": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"FREQ_HZ": {
|
|
"value": "100000000",
|
|
"value_src": "user_prop"
|
|
},
|
|
"CLK_DOMAIN": {
|
|
"value": "system_processing_system7_0_0_FCLK_CLK0",
|
|
"value_src": "default_prop"
|
|
}
|
|
}
|
|
},
|
|
"rst_n": {
|
|
"type": "rst",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"POLARITY": {
|
|
"value": "ACTIVE_LOW",
|
|
"value_src": "constant"
|
|
}
|
|
}
|
|
},
|
|
"start_vld": {
|
|
"direction": "I"
|
|
},
|
|
"read_vld": {
|
|
"direction": "O"
|
|
},
|
|
"dna_port": {
|
|
"direction": "O",
|
|
"left": "56",
|
|
"right": "0"
|
|
}
|
|
}
|
|
},
|
|
"mydna_read_v1_0_0": {
|
|
"vlnv": "xilinx.com:module_ref:mydna_read_v1_0:1.0",
|
|
"ip_revision": "1",
|
|
"xci_name": "system_mydna_read_v1_0_0_0",
|
|
"xci_path": "ip/system_mydna_read_v1_0_0_0/system_mydna_read_v1_0_0_0.xci",
|
|
"inst_hier_path": "mydna_read_v1_0_0",
|
|
"reference_info": {
|
|
"ref_type": "hdl",
|
|
"ref_name": "mydna_read_v1_0",
|
|
"boundary_crc": "0x0"
|
|
},
|
|
"interface_ports": {
|
|
"s00_axi": {
|
|
"mode": "Slave",
|
|
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
|
"parameters": {
|
|
"DATA_WIDTH": {
|
|
"value": "32",
|
|
"value_src": "auto"
|
|
},
|
|
"PROTOCOL": {
|
|
"value": "AXI4LITE",
|
|
"value_src": "constant"
|
|
},
|
|
"FREQ_HZ": {
|
|
"value": "100000000",
|
|
"value_src": "user_prop"
|
|
},
|
|
"ID_WIDTH": {
|
|
"value": "0",
|
|
"value_src": "constant"
|
|
},
|
|
"ADDR_WIDTH": {
|
|
"value": "4",
|
|
"value_src": "auto"
|
|
},
|
|
"AWUSER_WIDTH": {
|
|
"value": "0",
|
|
"value_src": "constant"
|
|
},
|
|
"ARUSER_WIDTH": {
|
|
"value": "0",
|
|
"value_src": "constant"
|
|
},
|
|
"WUSER_WIDTH": {
|
|
"value": "0",
|
|
"value_src": "constant"
|
|
},
|
|
"RUSER_WIDTH": {
|
|
"value": "0",
|
|
"value_src": "constant"
|
|
},
|
|
"BUSER_WIDTH": {
|
|
"value": "0",
|
|
"value_src": "constant"
|
|
},
|
|
"READ_WRITE_MODE": {
|
|
"value": "READ_WRITE",
|
|
"value_src": "constant"
|
|
},
|
|
"HAS_BURST": {
|
|
"value": "0",
|
|
"value_src": "constant"
|
|
},
|
|
"HAS_LOCK": {
|
|
"value": "0",
|
|
"value_src": "constant"
|
|
},
|
|
"HAS_PROT": {
|
|
"value": "1",
|
|
"value_src": "constant"
|
|
},
|
|
"HAS_CACHE": {
|
|
"value": "0",
|
|
"value_src": "constant"
|
|
},
|
|
"HAS_QOS": {
|
|
"value": "0",
|
|
"value_src": "constant"
|
|
},
|
|
"HAS_REGION": {
|
|
"value": "0",
|
|
"value_src": "constant"
|
|
},
|
|
"HAS_WSTRB": {
|
|
"value": "1",
|
|
"value_src": "constant"
|
|
},
|
|
"HAS_BRESP": {
|
|
"value": "1",
|
|
"value_src": "constant"
|
|
},
|
|
"HAS_RRESP": {
|
|
"value": "1",
|
|
"value_src": "constant"
|
|
},
|
|
"SUPPORTS_NARROW_BURST": {
|
|
"value": "0",
|
|
"value_src": "auto"
|
|
},
|
|
"NUM_READ_OUTSTANDING": {
|
|
"value": "1",
|
|
"value_src": "auto"
|
|
},
|
|
"NUM_WRITE_OUTSTANDING": {
|
|
"value": "1",
|
|
"value_src": "auto"
|
|
},
|
|
"MAX_BURST_LENGTH": {
|
|
"value": "1",
|
|
"value_src": "auto"
|
|
},
|
|
"PHASE": {
|
|
"value": "0.000",
|
|
"value_src": "default_prop"
|
|
},
|
|
"CLK_DOMAIN": {
|
|
"value": "system_processing_system7_0_0_FCLK_CLK0",
|
|
"value_src": "default_prop"
|
|
},
|
|
"NUM_READ_THREADS": {
|
|
"value": "4",
|
|
"value_src": "const_prop"
|
|
},
|
|
"NUM_WRITE_THREADS": {
|
|
"value": "4",
|
|
"value_src": "const_prop"
|
|
}
|
|
},
|
|
"port_maps": {
|
|
"AWADDR": {
|
|
"physical_name": "s00_axi_awaddr",
|
|
"direction": "I",
|
|
"left": "3",
|
|
"right": "0"
|
|
},
|
|
"AWPROT": {
|
|
"physical_name": "s00_axi_awprot",
|
|
"direction": "I",
|
|
"left": "2",
|
|
"right": "0"
|
|
},
|
|
"AWVALID": {
|
|
"physical_name": "s00_axi_awvalid",
|
|
"direction": "I"
|
|
},
|
|
"AWREADY": {
|
|
"physical_name": "s00_axi_awready",
|
|
"direction": "O"
|
|
},
|
|
"WDATA": {
|
|
"physical_name": "s00_axi_wdata",
|
|
"direction": "I",
|
|
"left": "31",
|
|
"right": "0"
|
|
},
|
|
"WSTRB": {
|
|
"physical_name": "s00_axi_wstrb",
|
|
"direction": "I",
|
|
"left": "3",
|
|
"right": "0"
|
|
},
|
|
"WVALID": {
|
|
"physical_name": "s00_axi_wvalid",
|
|
"direction": "I"
|
|
},
|
|
"WREADY": {
|
|
"physical_name": "s00_axi_wready",
|
|
"direction": "O"
|
|
},
|
|
"BRESP": {
|
|
"physical_name": "s00_axi_bresp",
|
|
"direction": "O",
|
|
"left": "1",
|
|
"right": "0"
|
|
},
|
|
"BVALID": {
|
|
"physical_name": "s00_axi_bvalid",
|
|
"direction": "O"
|
|
},
|
|
"BREADY": {
|
|
"physical_name": "s00_axi_bready",
|
|
"direction": "I"
|
|
},
|
|
"ARADDR": {
|
|
"physical_name": "s00_axi_araddr",
|
|
"direction": "I",
|
|
"left": "3",
|
|
"right": "0"
|
|
},
|
|
"ARPROT": {
|
|
"physical_name": "s00_axi_arprot",
|
|
"direction": "I",
|
|
"left": "2",
|
|
"right": "0"
|
|
},
|
|
"ARVALID": {
|
|
"physical_name": "s00_axi_arvalid",
|
|
"direction": "I"
|
|
},
|
|
"ARREADY": {
|
|
"physical_name": "s00_axi_arready",
|
|
"direction": "O"
|
|
},
|
|
"RDATA": {
|
|
"physical_name": "s00_axi_rdata",
|
|
"direction": "O",
|
|
"left": "31",
|
|
"right": "0"
|
|
},
|
|
"RRESP": {
|
|
"physical_name": "s00_axi_rresp",
|
|
"direction": "O",
|
|
"left": "1",
|
|
"right": "0"
|
|
},
|
|
"RVALID": {
|
|
"physical_name": "s00_axi_rvalid",
|
|
"direction": "O"
|
|
},
|
|
"RREADY": {
|
|
"physical_name": "s00_axi_rready",
|
|
"direction": "I"
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"ports": {
|
|
"start_vld": {
|
|
"direction": "O"
|
|
},
|
|
"read_vld": {
|
|
"direction": "I"
|
|
},
|
|
"dna_port": {
|
|
"direction": "I",
|
|
"left": "56",
|
|
"right": "0"
|
|
},
|
|
"s00_axi_aclk": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "s00_axi",
|
|
"value_src": "constant"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "s00_axi_aresetn",
|
|
"value_src": "constant"
|
|
},
|
|
"FREQ_HZ": {
|
|
"value": "100000000",
|
|
"value_src": "user_prop"
|
|
},
|
|
"PHASE": {
|
|
"value": "0.000",
|
|
"value_src": "default_prop"
|
|
},
|
|
"CLK_DOMAIN": {
|
|
"value": "system_processing_system7_0_0_FCLK_CLK0",
|
|
"value_src": "default_prop"
|
|
}
|
|
}
|
|
},
|
|
"s00_axi_aresetn": {
|
|
"type": "rst",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"POLARITY": {
|
|
"value": "ACTIVE_LOW",
|
|
"value_src": "constant"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"ps7_0_axi_periph": {
|
|
"vlnv": "xilinx.com:ip:axi_interconnect:2.1",
|
|
"xci_path": "ip/system_ps7_0_axi_periph_1/system_ps7_0_axi_periph_1.xci",
|
|
"inst_hier_path": "ps7_0_axi_periph",
|
|
"xci_name": "system_ps7_0_axi_periph_1",
|
|
"parameters": {
|
|
"NUM_MI": {
|
|
"value": "1"
|
|
}
|
|
},
|
|
"interface_ports": {
|
|
"S00_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"M00_AXI": {
|
|
"mode": "Master",
|
|
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_RESET": {
|
|
"value": "ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S00_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S00_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S00_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S00_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"M00_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M00_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M00_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M00_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"components": {
|
|
"s00_couplers": {
|
|
"interface_ports": {
|
|
"M_AXI": {
|
|
"mode": "Master",
|
|
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
},
|
|
"S_AXI": {
|
|
"mode": "Slave",
|
|
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
|
}
|
|
},
|
|
"ports": {
|
|
"M_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "M_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "M_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"M_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
},
|
|
"S_ACLK": {
|
|
"type": "clk",
|
|
"direction": "I",
|
|
"parameters": {
|
|
"ASSOCIATED_BUSIF": {
|
|
"value": "S_AXI"
|
|
},
|
|
"ASSOCIATED_RESET": {
|
|
"value": "S_ARESETN"
|
|
}
|
|
}
|
|
},
|
|
"S_ARESETN": {
|
|
"type": "rst",
|
|
"direction": "I"
|
|
}
|
|
},
|
|
"components": {
|
|
"auto_pc": {
|
|
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
|
|
"ip_revision": "29",
|
|
"xci_name": "system_auto_pc_0",
|
|
"xci_path": "ip/system_auto_pc_0/system_auto_pc_0.xci",
|
|
"inst_hier_path": "ps7_0_axi_periph/s00_couplers/auto_pc",
|
|
"parameters": {
|
|
"MI_PROTOCOL": {
|
|
"value": "AXI4LITE"
|
|
},
|
|
"SI_PROTOCOL": {
|
|
"value": "AXI3"
|
|
}
|
|
},
|
|
"interface_ports": {
|
|
"S_AXI": {
|
|
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
|
"mode": "Slave",
|
|
"bridges": [
|
|
"M_AXI"
|
|
]
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"auto_pc_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"M_AXI",
|
|
"auto_pc/M_AXI"
|
|
]
|
|
},
|
|
"s00_couplers_to_auto_pc": {
|
|
"interface_ports": [
|
|
"S_AXI",
|
|
"auto_pc/S_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"S_ACLK_1": {
|
|
"ports": [
|
|
"S_ACLK",
|
|
"auto_pc/aclk"
|
|
]
|
|
},
|
|
"S_ARESETN_1": {
|
|
"ports": [
|
|
"S_ARESETN",
|
|
"auto_pc/aresetn"
|
|
]
|
|
}
|
|
}
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"ps7_0_axi_periph_to_s00_couplers": {
|
|
"interface_ports": [
|
|
"S00_AXI",
|
|
"s00_couplers/S_AXI"
|
|
]
|
|
},
|
|
"s00_couplers_to_ps7_0_axi_periph": {
|
|
"interface_ports": [
|
|
"s00_couplers/M_AXI",
|
|
"M00_AXI"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"S00_ACLK_1": {
|
|
"ports": [
|
|
"S00_ACLK",
|
|
"s00_couplers/S_ACLK"
|
|
]
|
|
},
|
|
"S00_ARESETN_1": {
|
|
"ports": [
|
|
"S00_ARESETN",
|
|
"s00_couplers/S_ARESETN"
|
|
]
|
|
},
|
|
"ps7_0_axi_periph_ACLK_net": {
|
|
"ports": [
|
|
"M00_ACLK",
|
|
"s00_couplers/M_ACLK"
|
|
]
|
|
},
|
|
"ps7_0_axi_periph_ARESETN_net": {
|
|
"ports": [
|
|
"M00_ARESETN",
|
|
"s00_couplers/M_ARESETN"
|
|
]
|
|
}
|
|
}
|
|
},
|
|
"rst_ps7_0_100M": {
|
|
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
|
|
"ip_revision": "14",
|
|
"xci_name": "system_rst_ps7_0_100M_1",
|
|
"xci_path": "ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xci",
|
|
"inst_hier_path": "rst_ps7_0_100M"
|
|
}
|
|
},
|
|
"interface_nets": {
|
|
"processing_system7_0_DDR": {
|
|
"interface_ports": [
|
|
"DDR",
|
|
"processing_system7_0/DDR"
|
|
]
|
|
},
|
|
"processing_system7_0_FIXED_IO": {
|
|
"interface_ports": [
|
|
"FIXED_IO",
|
|
"processing_system7_0/FIXED_IO"
|
|
]
|
|
},
|
|
"processing_system7_0_GPIO_0": {
|
|
"interface_ports": [
|
|
"EMIO_0",
|
|
"processing_system7_0/GPIO_0"
|
|
]
|
|
},
|
|
"processing_system7_0_M_AXI_GP0": {
|
|
"interface_ports": [
|
|
"processing_system7_0/M_AXI_GP0",
|
|
"ps7_0_axi_periph/S00_AXI"
|
|
]
|
|
},
|
|
"ps7_0_axi_periph_M00_AXI": {
|
|
"interface_ports": [
|
|
"ps7_0_axi_periph/M00_AXI",
|
|
"mydna_read_v1_0_0/s00_axi"
|
|
]
|
|
}
|
|
},
|
|
"nets": {
|
|
"dna_port_read_0_dna_port": {
|
|
"ports": [
|
|
"dna_port_read_0/dna_port",
|
|
"mydna_read_v1_0_0/dna_port"
|
|
]
|
|
},
|
|
"dna_port_read_0_read_vld": {
|
|
"ports": [
|
|
"dna_port_read_0/read_vld",
|
|
"mydna_read_v1_0_0/read_vld"
|
|
]
|
|
},
|
|
"mydna_read_v1_0_0_start_vld": {
|
|
"ports": [
|
|
"mydna_read_v1_0_0/start_vld",
|
|
"dna_port_read_0/start_vld"
|
|
]
|
|
},
|
|
"processing_system7_0_FCLK_CLK0": {
|
|
"ports": [
|
|
"processing_system7_0/FCLK_CLK0",
|
|
"dna_port_read_0/clk",
|
|
"processing_system7_0/M_AXI_GP0_ACLK",
|
|
"ps7_0_axi_periph/ACLK",
|
|
"ps7_0_axi_periph/S00_ACLK",
|
|
"ps7_0_axi_periph/M00_ACLK",
|
|
"rst_ps7_0_100M/slowest_sync_clk",
|
|
"mydna_read_v1_0_0/s00_axi_aclk"
|
|
]
|
|
},
|
|
"processing_system7_0_FCLK_RESET0_N": {
|
|
"ports": [
|
|
"processing_system7_0/FCLK_RESET0_N",
|
|
"rst_ps7_0_100M/ext_reset_in"
|
|
]
|
|
},
|
|
"rst_ps7_0_100M_interconnect_aresetn": {
|
|
"ports": [
|
|
"rst_ps7_0_100M/interconnect_aresetn",
|
|
"ps7_0_axi_periph/ARESETN"
|
|
]
|
|
},
|
|
"rst_ps7_0_100M_peripheral_aresetn": {
|
|
"ports": [
|
|
"rst_ps7_0_100M/peripheral_aresetn",
|
|
"dna_port_read_0/rst_n",
|
|
"ps7_0_axi_periph/S00_ARESETN",
|
|
"ps7_0_axi_periph/M00_ARESETN",
|
|
"mydna_read_v1_0_0/s00_axi_aresetn"
|
|
]
|
|
}
|
|
},
|
|
"addressing": {
|
|
"/processing_system7_0": {
|
|
"address_spaces": {
|
|
"Data": {
|
|
"segments": {
|
|
"SEG_mydna_read_v1_0_0_reg0": {
|
|
"address_block": "/mydna_read_v1_0_0/s00_axi/reg0",
|
|
"offset": "0x43C00000",
|
|
"range": "64K"
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
} |