*** Running vivado with args -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source system_wrapper.tcl -notrace INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'. Command: synth_design -top system_wrapper -part xc7z035ffg676-2 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035' INFO: [Device 21-403] Loading part xc7z035ffg676-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 958941 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2149.453 ; gain = 411.629 ; free physical = 845 ; free virtual = 70077 --------------------------------------------------------------------------------- WARNING: [Synth 8-11121] redeclaration of ANSI port 'read_vld' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:33] WARNING: [Synth 8-11121] redeclaration of ANSI port 'dna_port' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:34] INFO: [Synth 8-6157] synthesizing module 'system_wrapper' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13] INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197] INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197] INFO: [Synth 8-6157] synthesizing module 'system' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318] INFO: [Synth 8-6157] synthesizing module 'system_dna_port_read_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53] INFO: [Synth 8-6157] synthesizing module 'dna_port_read' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23] INFO: [Synth 8-6157] synthesizing module 'DNA_PORT' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264] Parameter SIM_DNA_VALUE bound to: 57'b000000000000000000000000000000000000000000000000000000000 INFO: [Synth 8-6155] done synthesizing module 'DNA_PORT' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264] INFO: [Synth 8-6155] done synthesizing module 'dna_port_read' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23] INFO: [Synth 8-6155] done synthesizing module 'system_dna_port_read_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53] INFO: [Synth 8-6157] synthesizing module 'system_mydna_read_v1_0_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53] INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4] Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4] Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:235] INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:379] INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4] INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4] INFO: [Synth 8-6155] done synthesizing module 'system_mydna_read_v1_0_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53] INFO: [Synth 8-6157] synthesizing module 'system_processing_system7_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53] INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152] INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951] INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951] INFO: [Synth 8-6157] synthesizing module 'BIBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598] INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598] INFO: [Synth 8-6157] synthesizing module 'PS7' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859] INFO: [Synth 8-6155] done synthesizing module 'PS7' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859] INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152] WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] INFO: [Synth 8-6155] done synthesizing module 'system_processing_system7_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53] INFO: [Synth 8-6157] synthesizing module 'system_ps7_0_axi_periph_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632] INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_11SE3QO' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13] INFO: [Synth 8-6157] synthesizing module 'system_auto_pc_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392] INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3446] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546] INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3608] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'SI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871] WARNING: [Synth 8-7023] instance 'SI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'MI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126] WARNING: [Synth 8-7023] instance 'MI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704] INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285] INFO: [Synth 8-6155] done synthesizing module 'system_auto_pc_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53] INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_11SE3QO' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13] INFO: [Synth 8-6155] done synthesizing module 'system_ps7_0_axi_periph_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632] INFO: [Synth 8-638] synthesizing module 'system_rst_ps7_0_100M_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74] Parameter C_FAMILY bound to: zynq - type: string Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer Parameter C_EXT_RESET_HIGH bound to: 1'b0 Parameter C_AUX_RESET_HIGH bound to: 1'b0 Parameter C_NUM_BUS_RST bound to: 1 - type: integer Parameter C_NUM_PERP_RST bound to: 1 - type: integer Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:129] INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441] Parameter INIT bound to: 1'b1 INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488] INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821] INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873] INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721] INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721] INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574] Parameter INIT bound to: 1'b0 INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584] INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821] INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304] INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126] INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126] INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304] INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330] INFO: [Synth 8-256] done synthesizing module 'system_rst_ps7_0_100M_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74] WARNING: [Synth 8-7071] port 'mb_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622] WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622] WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622] WARNING: [Synth 8-7023] instance 'rst_ps7_0_100M' of module 'system_rst_ps7_0_100M_1' has 10 connections declared, but only 7 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622] INFO: [Synth 8-6155] done synthesizing module 'system' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318] INFO: [Synth 8-6155] done synthesizing module 'system_wrapper' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13] WARNING: [Synth 8-6014] Unused sequential element slv_reg1_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:228] WARNING: [Synth 8-6014] Unused sequential element slv_reg2_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:229] WARNING: [Synth 8-6014] Unused sequential element state_r1_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3596] WARNING: [Synth 8-6014] Unused sequential element s_arlen_r_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3597] WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load WARNING: [Synth 8-7129] Port m_axi_bid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port m_axi_rid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port m_axi_rlast in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_wid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_wlast in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice is either unconnected or has no load WARNING: [Synth 8-7129] Port s_arlen[7] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load WARNING: [Synth 8-7129] Port s_arlen[6] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load WARNING: [Synth 8-7129] Port s_arlen[5] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load WARNING: [Synth 8-7129] Port s_arlen[4] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load WARNING: [Synth 8-7129] Port s_arlen[3] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load WARNING: [Synth 8-7129] Port s_arlen[2] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 767 ; free virtual = 69885 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2359.391 ; gain = 0.000 ; free physical = 749 ; free virtual = 69874 INFO: [Netlist 29-17] Analyzing 46 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst' Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0' Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0' Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0' Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0' INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc] Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc] Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2518.867 ; gain = 0.000 ; free physical = 714 ; free virtual = 69858 INFO: [Project 1-111] Unisim Transformation Summary: A total of 46 instances were transformed. FDR => FDRE: 12 instances IOBUF => IOBUF (IBUF, OBUFT): 33 instances SRL16 => SRL16E: 1 instance Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 872 ; free virtual = 69870 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 946 ; free virtual = 69833 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z035ffg676-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 945 ; free virtual = 69833 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 1). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_1. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 2). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_2. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 3). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_3. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 4). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_4. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 5). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_5. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 6). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_6. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 7). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_7. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 8). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_8. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 9). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_9. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 10). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_10. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 11). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_11. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 12). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_12. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 13). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_13. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 14). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_14. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 15). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_15. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 16). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_16. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 17). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_17. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 18). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_18. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 19). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_19. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 20). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_20. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 21). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_21. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 22). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_22. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 23). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_23. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 24). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_24. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 25). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_25. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 26). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_28. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 27). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_29. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 28). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_30. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 29). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_26. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 30). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_27. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 31). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_31. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 32). Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_32. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 33). Applied set_property MARK_DEBUG = true for EMIO_0_tri_o_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 34). Applied set_property MARK_DEBUG = true for EMIO_0_tri_t_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 67). Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0/inst. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 30). Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M/U0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 35). Applied set_property KEEP_HIERARCHY = SOFT for system_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for system_i/dna_port_read_0. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for system_i/mydna_read_v1_0_0. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph/s00_couplers/auto_pc. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M. (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 940 ; free virtual = 69830 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_0'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:213] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_1'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:218] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_2'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:273] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_3'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:328] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_4'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:348] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_5'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:353] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_6'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:358] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_7'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:363] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_8'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:368] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_9'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:373] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_10'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:223] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_11'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:228] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_12'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:233] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_13'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:238] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_14'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:243] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_15'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:248] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_16'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:253] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_17'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:258] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_18'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:263] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_19'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:268] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_20'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:278] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_21'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:283] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_22'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:288] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_23'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:293] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_24'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:298] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_25'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:303] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_28'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:318] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_29'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:323] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_30'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:333] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_26'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:308] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_27'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:313] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_31'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:338] INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_32'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:343] WARNING: [Synth 8-327] inferring latch for variable 'dna_port_reg_reg' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:413] --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- SM_IDLE | 01 | 00 SM_CMD_EN | 11 | 01 SM_CMD_ACCEPTED | 10 | 10 SM_DONE_WAIT | 00 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- SM_IDLE | 01 | 00 SM_CMD_EN | 11 | 01 SM_CMD_ACCEPTED | 10 | 10 SM_DONE | 00 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 929 ; free virtual = 69825 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 8 2 Input 9 Bit Adders := 2 2 Input 8 Bit Adders := 2 2 Input 6 Bit Adders := 1 2 Input 5 Bit Adders := 4 2 Input 4 Bit Adders := 4 2 Input 2 Bit Adders := 2 +---Registers : 66 Bit Registers := 4 57 Bit Registers := 1 47 Bit Registers := 2 32 Bit Registers := 3 14 Bit Registers := 2 12 Bit Registers := 9 9 Bit Registers := 2 8 Bit Registers := 3 6 Bit Registers := 1 5 Bit Registers := 4 4 Bit Registers := 8 3 Bit Registers := 3 2 Bit Registers := 9 1 Bit Registers := 43 +---Muxes : 2 Input 66 Bit Muxes := 4 2 Input 47 Bit Muxes := 2 4 Input 32 Bit Muxes := 3 2 Input 32 Bit Muxes := 9 2 Input 14 Bit Muxes := 2 2 Input 12 Bit Muxes := 6 2 Input 9 Bit Muxes := 4 2 Input 8 Bit Muxes := 1 2 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 4 2 Input 4 Bit Muxes := 18 2 Input 2 Bit Muxes := 17 4 Input 2 Bit Muxes := 4 2 Input 1 Bit Muxes := 37 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 900 (col length:140) BRAMs: 1000 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset. WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset. WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module proc_sys_reset. WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2) is unused and will be removed from module proc_sys_reset. WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3) is unused and will be removed from module proc_sys_reset. WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4) is unused and will be removed from module proc_sys_reset. WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset. WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset. WARNING: [Synth 8-3332] Sequential element (FDRE_inst) is unused and will be removed from module proc_sys_reset. WARNING: [Synth 8-3332] Sequential element (BSR_OUT_DFF[0].FDRE_BSR) is unused and will be removed from module proc_sys_reset. WARNING: [Synth 8-3332] Sequential element (ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N) is unused and will be removed from module proc_sys_reset. WARNING: [Synth 8-3332] Sequential element (PR_OUT_DFF[0].FDRE_PER) is unused and will be removed from module proc_sys_reset. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1838 ; free virtual = 70743 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1815 ; free virtual = 70747 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1781 ; free virtual = 70713 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1765 ; free virtual = 70711 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Dynamic Shift Register Report: +------------+----------------+--------+------------+--------+---------+--------+--------+--------+ |Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | +------------+----------------+--------+------------+--------+---------+--------+--------+--------+ |dsrl | memory_reg[3] | 20 | 20 | 20 | 0 | 0 | 0 | 0 | |dsrl__1 | memory_reg[3] | 2 | 2 | 2 | 0 | 0 | 0 | 0 | |dsrl__2 | memory_reg[31] | 34 | 34 | 0 | 34 | 0 | 0 | 0 | |dsrl__3 | memory_reg[31] | 13 | 13 | 0 | 13 | 0 | 0 | 0 | +------------+----------------+--------+------------+--------+---------+--------+--------+--------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |BIBUF | 130| |2 |BUFG | 1| |3 |CARRY4 | 6| |4 |DNA_PORT | 1| |5 |LUT1 | 69| |6 |LUT2 | 24| |7 |LUT3 | 169| |8 |LUT4 | 52| |9 |LUT5 | 71| |10 |LUT6 | 118| |11 |PS7 | 1| |12 |SRL16 | 1| |13 |SRL16E | 16| |14 |SRLC32E | 45| |15 |FDCE | 66| |16 |FDR | 4| |17 |FDRE | 501| |18 |FDSE | 20| |19 |LD | 57| |20 |IOBUF | 33| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 136 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 618.598 ; free physical = 1531 ; free virtual = 70510 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1531 ; free virtual = 70509 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 1748 ; free virtual = 70732 INFO: [Netlist 29-17] Analyzing 101 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2563.766 ; gain = 0.000 ; free physical = 1757 ; free virtual = 70743 INFO: [Project 1-111] Unisim Transformation Summary: A total of 95 instances were transformed. FDR => FDRE: 4 instances IOBUF => IOBUF (IBUF, OBUFT): 33 instances LD => LDCE: 57 instances SRL16 => SRL16E: 1 instance Synth Design complete | Checksum: 8993d7c INFO: [Common 17-83] Releasing license: Synthesis 187 Infos, 142 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2563.801 ; gain = 1259.379 ; free physical = 1759 ; free virtual = 70746 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1991.605; main = 1727.861; forked = 379.983 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3465.613; main = 2563.770; forked = 1042.766 Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2611.777 ; gain = 0.000 ; free physical = 1758 ; free virtual = 70746 INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:36:31 2026...