Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date             : Wed May 27 16:42:41 2026
| Host             : mkb running 64-bit unknown
| Command          : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
| Design           : system_wrapper
| Device           : xc7z035ffg676-2
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 1.909        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 1.688        |
| Device Static (W)        | 0.221        |
| Effective TJA (C/W)      | 1.9          |
| Max Ambient (C)          | 81.4         |
| Junction Temperature (C) | 28.6         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     0.097 |        4 |       --- |             --- |
| Slice Logic              |     0.012 |    67930 |       --- |             --- |
|   LUT as Logic           |     0.011 |    13657 |    171900 |            7.94 |
|   Register               |    <0.001 |    29180 |    343800 |            8.49 |
|   LUT as Shift Register  |    <0.001 |     6873 |     70400 |            9.76 |
|   LUT as Distributed RAM |    <0.001 |      152 |     70400 |            0.22 |
|   CARRY4                 |    <0.001 |     1979 |     54650 |            3.62 |
|   BUFG                   |    <0.001 |        1 |        32 |            3.13 |
|   F7/F8 Muxes            |    <0.001 |     1059 |    218600 |            0.48 |
|   Others                 |     0.000 |     6317 |       --- |             --- |
| Signals                  |     0.025 |    38363 |       --- |             --- |
| Block RAM                |     0.002 |      2.5 |       500 |            0.50 |
| I/O                      |     0.024 |       33 |       250 |           13.20 |
| PS7                      |     1.528 |        1 |       --- |             --- |
| Static Power             |     0.221 |          |           |                 |
| Total                    |     1.909 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint    |       1.000 |     0.194 |       0.136 |      0.059 |       NA    | Unspecified | NA         |
| Vccaux    |       1.800 |     0.041 |       0.001 |      0.040 |       NA    | Unspecified | NA         |
| Vcco33    |       3.300 |     0.008 |       0.007 |      0.001 |       NA    | Unspecified | NA         |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccbram   |       1.000 |     0.002 |       0.000 |      0.002 |       NA    | Unspecified | NA         |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccpint   |       1.000 |     0.736 |       0.718 |      0.018 |       NA    | Unspecified | NA         |
| Vccpaux   |       1.800 |     0.061 |       0.051 |      0.010 |       NA    | Unspecified | NA         |
| Vccpll    |       1.800 |     0.017 |       0.014 |      0.003 |       NA    | Unspecified | NA         |
| Vcco_ddr  |       1.500 |     0.459 |       0.457 |      0.002 |       NA    | Unspecified | NA         |
| Vcco_mio0 |       1.800 |     0.003 |       0.002 |      0.001 |       NA    | Unspecified | NA         |
| Vcco_mio1 |       1.800 |     0.003 |       0.002 |      0.001 |       NA    | Unspecified | NA         |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 1.9                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 3.4                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------+-----------------+
| Clock                                                                                      | Domain                                                            | Constraint (ns) |
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------+-----------------+
| clk_fpga_0                                                                                 | system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]         |            10.0 |
| dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TCK |            33.0 |
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+--------------------------+-----------+
| Name                     | Power (W) |
+--------------------------+-----------+
| system_wrapper           |     1.688 |
|   dbg_hub                |     0.003 |
|     inst                 |     0.003 |
|       BSCANID.u_xsdbm_id |     0.003 |
|   system_i               |     1.535 |
|     processing_system7_0 |     1.530 |
|       inst               |     1.530 |
|     ps7_0_axi_periph     |     0.003 |
|       s00_couplers       |     0.003 |
|   u_ila_0                |     0.125 |
|     inst                 |     0.125 |
|       ila_core_inst      |     0.125 |
+--------------------------+-----------+