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This commit is contained in:
Jeremy Shen
2026-05-27 09:56:09 +00:00
commit ee3ede1152
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Vitis_Classic/NewInstCal_bsp/zynq_fsbl/CMakeLists.txt
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# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
# SPDX-License-Identifier: MIT
cmake_minimum_required(VERSION 3.15)
set(APP_NAME zynq_fsbl)
project(${APP_NAME})
include_directories(${CMAKE_BINARY_DIR}/include)
include(${CMAKE_CURRENT_SOURCE_DIR}/UserConfig.cmake)
find_package(common)
enable_language(C ASM)
collect(PROJECT_LIB_DEPS xiltimer)
collect(PROJECT_LIB_DEPS xilffs)
collect(PROJECT_LIB_DEPS xilrsa)
collect(PROJECT_LIB_DEPS xil)
collect(PROJECT_LIB_DEPS xilstandalone)
collect(PROJECT_LIB_DEPS gcc)
collect(PROJECT_LIB_DEPS c)
list (APPEND _deps ${USER_LINK_LIBRARIES})
collector_list (_deps PROJECT_LIB_DEPS)
if(CMAKE_EXPORT_COMPILE_COMMANDS)
set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_CXX_IMPLICIT_INCLUDE_DIRECTORIES})
set(CMAKE_C_STANDARD_INCLUDE_DIRECTORIES ${CMAKE_C_IMPLICIT_INCLUDE_DIRECTORIES})
endif()
collector_create (PROJECT_LIB_HEADERS "${CMAKE_CURRENT_SOURCE_DIR}")
collector_create (PROJECT_LIB_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}")
collect (PROJECT_LIB_HEADERS fsbl_debug.h)
collect (PROJECT_LIB_HEADERS fsbl.h)
collect (PROJECT_LIB_HEADERS fsbl_hooks.h)
collect (PROJECT_LIB_HEADERS image_mover.h)
collect (PROJECT_LIB_HEADERS md5.h)
collect (PROJECT_LIB_HEADERS nand.h)
collect (PROJECT_LIB_HEADERS nor.h)
collect (PROJECT_LIB_HEADERS pcap.h)
collect (PROJECT_LIB_HEADERS qspi.h)
collect (PROJECT_LIB_HEADERS rsa.h)
collect (PROJECT_LIB_HEADERS sd.h)
collect (PROJECT_LIB_HEADERS ps7_init.h)
collect (PROJECT_LIB_SOURCES fsbl_hooks.c)
collect (PROJECT_LIB_SOURCES image_mover.c)
collect (PROJECT_LIB_SOURCES main.c)
collect (PROJECT_LIB_SOURCES md5.c)
collect (PROJECT_LIB_SOURCES nand.c)
collect (PROJECT_LIB_SOURCES nor.c)
collect (PROJECT_LIB_SOURCES pcap.c)
collect (PROJECT_LIB_SOURCES qspi.c)
collect (PROJECT_LIB_SOURCES rsa.c)
collect (PROJECT_LIB_SOURCES sd.c)
collect (PROJECT_LIB_SOURCES ps7_init.c)
collector_list (_sources PROJECT_LIB_SOURCES)
collector_list (_headers PROJECT_LIB_HEADERS)
string(APPEND CMAKE_C_FLAGS ${USER_COMPILE_OPTIONS})
string(APPEND CMAKE_CXX_FLAGS ${USER_COMPILE_OPTIONS})
string(APPEND CMAKE_C_LINK_FLAGS ${USER_LINK_OPTIONS})
string(APPEND CMAKE_CXX_LINK_FLAGS ${USER_LINK_OPTIONS})
set_source_files_properties(${_sources} OBJECT_DEPENDS "${CMAKE_LIBRARY_PATH}/*.a")
add_executable(${APP_NAME}.elf fsbl_handoff.S ${_sources})
set_target_properties(${APP_NAME}.elf PROPERTIES LINK_DEPENDS ${CMAKE_SOURCE_DIR}/lscript.ld)
target_link_libraries(${APP_NAME}.elf -Os -Wl,--gc-sections -n -T\"${CMAKE_SOURCE_DIR}/lscript.ld\" -L\"${CMAKE_LIBRARY_PATH}/\" -L\"${USER_LINK_DIRECTORIES}/\" -Wl,--start-group ${_deps} -Wl,--end-group)
target_compile_definitions(${APP_NAME}.elf PUBLIC ${USER_COMPILE_DEFINITIONS})
target_include_directories(${APP_NAME}.elf PUBLIC ${USER_INCLUDE_DIRECTORIES})
print_elf_size(CMAKE_SIZE ${APP_NAME})
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/Makefile
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# Auto Generated by Xilinx generate_app. Modify at your own risk
CC := arm-none-eabi-gcc
CC_FLAGS := -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard
CFLAGS :=
BSP_FLAGS := -O2 -c
LN_FLAGS := -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group -Wl,--gc-sections
c_SOURCES := $(wildcard *.c)
S_SOURCES := $(wildcard *.S)
s_SOURCES := $(wildcard *.s)
INCLUDES := $(wildcard *.h)
OBJS := $(patsubst %.c, %.o, $(c_SOURCES))
OBJS += $(patsubst %.S, %.o, $(S_SOURCES))
OBJS += $(patsubst %.s, %.o, $(s_SOURCES))
LSCRIPT := -Tlscript.ld
CURRENT_DIR = $(shell pwd)
DEPFILES := $(patsubst %.o, %.d, $(OBJS))
LIBS := zynq_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a
EXEC := fsbl.elf
INCLUDEPATH := -Izynq_fsbl_bsp/ps7_cortexa9_0/include -I.
LIBPATH := -Lzynq_fsbl_bsp/ps7_cortexa9_0/lib -L./
all: $(EXEC)
$(EXEC): $(LIBS) $(OBJS) $(INCLUDES)
$(CC) -o $@ $(sort $(OBJS)) $(CC_FLAGS) $(CFLAGS) $(LN_FLAGS) $(LIBPATH) $(LSCRIPT)
$(LIBS):
$(MAKE) -C zynq_fsbl_bsp
%.o:%.c
$(CC) $(CFLAGS) $(BSP_FLAGS) $(CC_FLAGS) -c $< -o $@ $(INCLUDEPATH)
%.o:%.S
$(CC) $(CFLAGS) $(BSP_FLAGS) $(CC_FLAGS) -c $< -o $@ $(INCLUDEPATH)
%.o:%.s
$(CC) $(CFLAGS) $(BSP_FLAGS) $(CC_FLAGS) -c $< -o $@ $(INCLUDEPATH)
clean:
rm -rf $(OBJS) $(LIBS) $(EXEC) *.o
-include $(DEPFILES)
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/Xilinx.spec
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*startfile:
crti%O%s crtbegin%O%s
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/fsbl.elf
Executable
BIN
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Binary file not shown.
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/fsbl.h
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/******************************************************************************
* Copyright (c) 2012 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file fsbl.h
*
* Contains the function prototypes, defines and macros for the
* First Stage Boot Loader (FSBL) functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 03/04/11 Initial release
* 2.00a mb 06/06/12 Removed the qspi define, will be picked from
* xparameters.h file
* 3.00a np/mb 08/08/12 Added the error codes for the FSBL hook errors.
* Added the debug levels
* 4.00a sgd 02/28/13 Removed DDR initialization check
* Removed DDR ECC initialization code
* Modified hand off address check to 1MB
* Added RSA authentication support
* Removed LPBK_DLY_ADJ register setting code as we use
* divisor 8
* Removed check for Fabric is already initialized
*
* CR's fixed and description
* 689026: FSBL doesn't hold PL resets active during
* bit download
* Resolution: PL resets are released just before
* handoff
*
* 689077: FSBL hangs at Handoff clearing the
* TX UART buffer
* Resolution: STDOUT_BASEADDRESS macro value changes
* based UART select, hence used STDOUT_BASEADDRESS
* as UART base address
*
* 695578: FSBL failed to load standalone application
* in secure bootmode
* Resolution: Application will be placed at load address
* instead of DDR temporary address
*
* 699475: FSBL functionality is broken and its
* not able to boot in QSPI/NAND bootmode
* Resolution: New flags are added DevCfg driver
* for handling loopback
* XDCFG_CONCURRENT_NONSEC_READ_WRITE
* XDCFG_CONCURRENT_SECURE_READ_WRITE
*
* 683145: Define stack area for FIQ, UNDEF modes
* in linker file
* Resolution: FSBL linker modified to create stack area
* for FIQ, UNDEF
*
* 705664: FSBL fails to decrypt the bitstream when
* the image is AES encrypted using non-zero key value
* Resolution: Fabric cleaning will not be done
* for AES-E-Fuse encryption
*
* Watchdog disabled for AES E-Fuse encryption
*
* 5.00a sgd 05/17/13 Fallback support for E-Fuse encryption
* Added QSPI Flash Size > 128Mbit support
* QSPI Dual Stack support
* Added Md5 checksum support
*
* CR's fixed and description
* 692045 FSBL: Linker script of FSBL has PHDR workaround,
* this needs to be fixed
* Resolution: Removed PHDR from Linker file
*
* 704287 FSBL: fsbl.h file has a few error codes that
* are not used by FSBL, that needs to be removed
* Resolution: Removed unused error codes
*
* 704379 FSBL: Check if DDR is in proper state before
* handoff
* Resolution: Added DDR initialization check
*
* 709077 If FSBL_DEBUG and FSBL_DEBUG_INFO are defined,
* the debug level is FSBL_DEBUG only.
*
* 710128 FSBL: Linux boot failing without load attribute
* set for Linux partitions in BIF
* Resolution: FSBL will load partitions with valid load
* address and stop loading if any invalid load address
*
* 708728 Issues seen while making HP interconnect
* 32 bit wide
* Resolution: ps7_post_config function generated by PCW
* will be called after Bit stream download
* Added MMC support
* 6.00a kc 07/31/2013 CR's fixed and description
* 724166 FSBL doesn’t use PPK authenticated by Boot ROM
* for authenticating the Partition images
* Resolution: FSBL now uses the PPK left by Boot ROM in
* OCM for authencating the SPK
*
* 724165 Partition Header used by FSBL is not
* authenticated
* Resolution: FSBL now authenticates the partition header
*
* 691150 ps7_init does not check for peripheral
* initialization failures or timeout on polls
* Resolution: Return value of ps7_init() is now checked
* by FSBL and prints the error string
*
* 708316 PS7_init.tcl file should have Error mechanism
* for all mask_poll
* Resolution: Return value of ps7_init() is now checked
* by FSBL and prints the error string
*
* 732062 FSBL fails to build if UART not available
* Resolution: Added define to call xil_printf only
* if uart is defined
*
* 722979 Provide customer-friendly changelogs in FSBL
* Resolution: Added CR description for all the files
*
* 732865 Backward compatibility for ps7_init function
* Resolution: Added a new define for ps7_init success
* and value is defined based on ps7_init define
*
* Fix for CR#739711 - FSBL not able to read Large
* QSPI (512M) in IO Mode
* Resolution: Modified the address calculation
* algorithm in dual parallel mode for QSPI
*
* 7.00a kc 10/18/13 Integrated SD/MMC driver
* 10/23/13 Support for armcc compiler added
* 741003 FSBL has to check the HMAC error status after
* decryption
* Resolution: Added code for checking the error status
* after PCAP completion
* 739968 FSBL should do the QSPI config settings for
* Dual parallel configuration in IO mode
* Resolution: Added QSPI config settings in qspi.c
* 724620 FSBL: How to handle PCAP_MODE after bitstream
* configuration.
* Resolution: PCAP_MODE and PCAP_PR bits are now cleared
* after PCAP transfer completion
* 726178 In the 14.6 FSBL function FabricInit() PROG_B
* is kept active for 5mS.
* Resolution: PROG_B is now kept active for 5ms only in case
* if efuse is the aes key source.
* 755245 FSBL does not load partition if eMMC has only
* one partition
* Resolution: Changed the if condition for MMC
* 12/04/13 764382 FSBL: How to handle PCAP_MODE after bitstream
* configuration
* Resolution: Reverted back the changes of 724620. PCAP_MODE
* and PCAP_PR bits are not changed
* 8.00a kc 01/16/13 767798 Fsbl MD5 Checksum failiure for encrypted images
* Resolution: For checksum enabled partitions, total
* total partition image length is copied now.
* 761895 FSBL should authenticate image only if
* partition owner was not set to u-boot
* Resolution: Partition owner check added in
* image_mover.c
* 02/20/14 775631 - FSBL: FsblGetGlobalTimer() is not proper
* Resolution: Function argument is updated from value
* to pointer to reflect updated value
* 9.00a kc 04/16/14 773866 - SetPpk() will fail on secure fallback
* unless FSBL* and FSBL are identical in length
* Resolution: PPK is set only once now.
* 785778 - FSBL takes 8 seconds to
* authenticate (RSA) a bitstream on zc706
* Resolution: Data Caches are enabled only for
* authentication.
* 791245 - Use of xilrsa in fsbl
* Resolution: Rsa library is removed from fsbl source
* and xilrsa is used from BSP
* 10.00a kc 07/15/14 804595 Zynq FSBL - Issues with
* fallback image offset handling using MD5
* Resolution: Updated the checksum offset to add with
* image base address
* 782309 Fallback support for AES
* encryption with E-Fuse - Enhancement
* Resolution: Same as 773866
* 809336 Minor code cleanup
* Resolution Minor code changes
* kc 08/27/14 820356 - FSBL compilation fails with IAR compiler
* Resolution: Change of __asm__ to __asm
* 11.00a kv 10/08/14 826030 - FSBL:LinearBootDeviceFlag is not initialized
* in IO mode case.Due to which the variable is
* remaining in unknown state.
* Resolution: LinearBootDeviceFlag is initialized 0
* in main.c
* 12.00a ssc 12/11/14 839182 - FSBL -In the file sd.c, f_mount is called with
* two arguments but f_mount is expecting the 3 arguments
* from build 2015.1_1210_1, causing compilation error.
* Resolution: Arguments for f_mount in InitSD() are
* changed as per new signature.
* 13.00a ssc 04/10/15 846899 - FSBL -In the file pcap.c, to clear DMA done
* count, devcfg.INT_STS register is written to, which is
* not correct.
* Resolution: Corresponding fields in the devcfg.STATUS
* register are written to, for clearing DMA done count.
* 14.00a gan 01/13/16 869081 -(2016.1)FSBL -In qspi.c, FSBL picks the qspi
* read command from LQSPI_CFG register instead of hard
* coded read command (0x6B).
* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
* Fabric Initialization sequence is modified to check
* the PL power before sequence starts and checking INIT_B
* reset status twice in case of failure.
* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
* In pcap.c, check pl power through MCTRL register
* for 3.0 and later versions of silicon.
* 17.00a bsv 27/03/18 Fix for CR# 996973 Add code under JTAG_ENABLE_LEVEL_SHIFTERS macro
* to enable level shifters in jtag boot mode.
* 18.00a ka 10/29/18 Fix for CR# 1006294 Added macro for FORCE_USE_AES_EXCLUDE
* 19.0 vns 03/18/22 Fixed CR#1125470, added FsblPrintArray() prototype
* 20.0 ng 12/08/22 Updated SDK release version
* 21.0 skd 02/10/22 SDK release version updated
* 21.1 ng 07/13/23 Add SDT support
* 21.2 ng 07/25/23 Fixed DDR address support in SDT
*
* </pre>
*
* </pre>
*
* @note
*
* Flags in FSBL
*
* FSBL_PERF
*
* This Flag can be set at compilation time. This flag is set for
* measuring the performance of FSBL.That is the time taken to execute is
* measured.when this flag is set.Execution time with reference to
* global timer is taken here
*
* Total Execution time is the time taken for executing FSBL till handoff
* to any application .
* If there is a bitstream in the partition header then the
* execution time includes the copying of the bitstream to DDR
* (in case of SD/NAND bootmode)
* and programming the devcfg dma is accounted.
*
* FSBL provides two debug levels
* DEBUG GENERAL - fsbl_printf under this category will appear only when the
* FSBL_DEBUG flag is set during compilation
* DEBUG_INFO - fsbl_printf under this category will appear when the
* FSBL_DEBUG_INFO flag is set during compilation
* For a more detailed output log can be used.
* FSBL_DEBUG_RSA - Define this macro to print more detailed values used in
* RSA functions
* These macros are input to the fsbl_printf function
*
* DEBUG LEVELS
* FSBL_DEBUG level is level 1, when this flag is set all the fsbl_prints
* that are with the DEBUG_GENERAL argument are shown
* FSBL_DEBUG_INFO is level 2, when this flag is set during the
* compilation , the fsbl_printf with DEBUG_INFO will appear on the com port
*
* DEFAULT LEVEL
* By default no print messages will appear.
*
* NON_PS_INSTANTIATED_BITSTREAM
*
* FSBL will not enable the level shifters for a NON PS instantiated
* Bitstream.This flag can be set during compilation for a NON PS instantiated
* bitstream
*
* ECC_ENABLE
* This flag will be defined in the ps7_init.h file when ECC is enabled
* in the DDR configuration (XPS GUI)
*
* RSA_SUPPORT
* This flag is used to enable authentication feature
* Default this macro disabled, reason to avoid increase in code size
*
* MMC_SUPPORT
* This flag is used to enable MMC support feature
*
* JTAG_ENABLE_LEVEL_SHIFTERS
* FSBL will not enable the level shifters for jtag boot mode. This flag can be
* set during compilation for jtag boot mode to enable level shifters.
*
* FORCE_USE_AES_EXCLUDE
* Defining this flag will exclude the feature, forcing every partition to be
* encrypted when EFUSE_SEC_EN bit is set.
* This flag can be set/unset during compilation.
* By default this flag is unset/undefined which enables the above feature
* Note : Changing the default behaviour is not recommended from
* Security perspective.
*
*******************************************************************************/
#ifndef XIL_FSBL_H
#define XIL_FSBL_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_io.h"
#include "xparameters.h"
#include "xpseudo_asm.h"
#include "xil_printf.h"
#include "pcap.h"
#include "fsbl_debug.h"
#include "ps7_init.h"
#ifdef FSBL_PERF
#ifndef SDT
#include "xtime_l.h"
#else
#include "xiltimer.h"
#endif
#include <stdio.h>
#endif
/************************** Constant Definitions *****************************/
/*
* SDK release version
*/
#define SDK_RELEASE_YEAR 2023
#define SDK_RELEASE_QUARTER 2
#define WORD_LENGTH_SHIFT 2
/*
* On a Successful handoff to an application FSBL sets this SUCCESS code
*/
#define SUCCESSFUL_HANDOFF 0x1 /* Successful Handoff */
/*
* Backward compatibility for ps7_init
*/
#ifdef NEW_PS7_ERR_CODE
#define FSBL_PS7_INIT_SUCCESS PS7_INIT_SUCCESS
#else
#define FSBL_PS7_INIT_SUCCESS (1)
#endif
/*
* ERROR CODES
* The following are the Error codes that FSBL uses
* If the Debug prints are enabled only then the error codes will be
* seen on the com port.Without the debug prints enabled no error codes will
* be visible.There are not saved in any register
* Boot Mode States used for error and status output
* Error codes are defined below
*/
#define ILLEGAL_BOOT_MODE 0xA000 /**< Illegal boot mode */
#define ILLEGAL_RETURN 0xA001 /**< Illegal return */
#define PCAP_INIT_FAIL 0xA002 /**< Pcap driver Init Failed */
#define DECRYPTION_FAIL 0xA003 /**< Decryption Failed */
#define BITSTREAM_DOWNLOAD_FAIL 0xA004 /**< Bitstream download fail */
#define DMA_TRANSFER_FAIL 0xA005 /**< DMA Transfer Fail */
#define INVALID_FLASH_ADDRESS 0xA006 /**< Invalid Flash Address */
#define DDR_INIT_FAIL 0xA007 /**< DDR Init Fail */
#define NO_DDR 0xA008 /**< DDR missing */
#define SD_INIT_FAIL 0xA009 /**< SD Init fail */
#define NAND_INIT_FAIL 0xA00A /**< Nand Init Fail */
#define PARTITION_MOVE_FAIL 0xA00B /**< Partition move fail */
#define AUTHENTICATION_FAIL 0xA00C /**< Authentication fail */
#define INVALID_HEADER_FAIL 0xA00D /**< Invalid header fail */
#define GET_HEADER_INFO_FAIL 0xA00E /**< Get header fail */
#define INVALID_LOAD_ADDRESS_FAIL 0xA00F /**< Invalid load address fail */
#define PARTITION_CHECKSUM_FAIL 0xA010 /**< Partition checksum fail */
#define RSA_SUPPORT_NOT_ENABLED_FAIL 0xA011 /**< RSA not enabled fail */
#define PS7_INIT_FAIL 0xA012 /**< ps7 Init Fail */
#define PARTITION_LOAD_FAIL 0xA013 /**< Partition load fail*/
/*
* FSBL Exception error codes
*/
#define EXCEPTION_ID_UNDEFINED_INT 0xA301 /**< Undefined INT Exception */
#define EXCEPTION_ID_SWI_INT 0xA302 /**< SWI INT Exception */
#define EXCEPTION_ID_PREFETCH_ABORT_INT 0xA303 /**< Prefetch Abort xception */
#define EXCEPTION_ID_DATA_ABORT_INT 0xA304 /**< Data Abort Exception */
#define EXCEPTION_ID_IRQ_INT 0xA305 /**< IRQ Exception Occurred */
#define EXCEPTION_ID_FIQ_INT 0xA306 /**< FIQ Exception Occurred */
/*
* FSBL hook routine failures
*/
#define FSBL_HANDOFF_HOOK_FAIL 0xA401 /**< FSBL handoff hook failed */
#define FSBL_BEFORE_BSTREAM_HOOK_FAIL 0xA402 /**< FSBL before bit stream
download hook failed */
#define FSBL_AFTER_BSTREAM_HOOK_FAIL 0xA403 /**< FSBL after bitstream
download hook failed */
/*
* Watchdog related Error codes
*/
#define WDT_RESET_OCCURED 0xA501 /**< WDT Reset happened in FSBL */
#define WDT_INIT_FAIL 0xA502 /**< WDT driver INIT failed */
/*
* SLCR Registers
*/
#define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200)
#define FPGA_RESET_REG (XPS_SYS_CTRL_BASEADDR + 0x240)
#define RESET_REASON_REG (XPS_SYS_CTRL_BASEADDR + 0x250)
#define RESET_REASON_CLR (XPS_SYS_CTRL_BASEADDR + 0x254)
#define REBOOT_STATUS_REG (XPS_SYS_CTRL_BASEADDR + 0x258)
#define BOOT_MODE_REG (XPS_SYS_CTRL_BASEADDR + 0x25C)
#define PS_LVL_SHFTR_EN (XPS_SYS_CTRL_BASEADDR + 0x900)
/*
* Efuse Status Register
*/
#define EFUSE_STATUS_REG (0xF800D010) /**< Efuse Status Register */
#define EFUSE_STATUS_RSA_ENABLE_MASK (0x400) /**< Status of RSA enable */
/*
* PS reset control register define
*/
#define PS_RST_MASK 0x1 /**< PS software reset */
/*
* SLCR BOOT Mode Register defines
*/
#define BOOT_MODES_MASK 0x00000007 /**< FLASH types */
/*
* Boot Modes
*/
#define JTAG_MODE 0x00000000 /**< JTAG Boot Mode */
#define QSPI_MODE 0x00000001 /**< QSPI Boot Mode */
#define NOR_FLASH_MODE 0x00000002 /**< NOR Boot Mode */
#define NAND_FLASH_MODE 0x00000004 /**< NAND Boot Mode */
#define SD_MODE 0x00000005 /**< SD Boot Mode */
#define MMC_MODE 0x00000006 /**< MMC Boot Device */
#define RESET_REASON_SRST 0x00000020 /**< Reason for reset is SRST */
#define RESET_REASON_SWDT 0x00000001 /**< Reason for reset is SWDT */
/*
* Golden image offset
*/
#define GOLDEN_IMAGE_OFFSET 0x8000
/*
* Silicon Version
*/
#define SILICON_VERSION_1 0
#define SILICON_VERSION_2 1
#define SILICON_VERSION_3 2
#define SILICON_VERSION_3_1 3
/*
* In case of PL DDR, this macros defined based PL DDR address
*/
#if !defined(XPAR_PS7_DDR_0_S_AXI_BASEADDR) && !defined(XPAR_PS7_DDR_0_BASEADDRESS)
#define DDR_START_ADDR 0x00
#define DDR_END_ADDR 0x00
#else
/*
* DDR start address for storing the data temporarily(1M)
* Need to finalize correct logic
*/
#ifndef SDT
#if defined(XPAR_PS7_DDR_0_S_AXI_BASEADDR)
#define DDR_START_ADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR
#define DDR_END_ADDR XPAR_PS7_DDR_0_S_AXI_HIGHADDR
#endif
#else
#if defined(XPAR_PS7_DDR_0_BASEADDRESS)
#define DDR_START_ADDR XPAR_PS7_DDR_0_BASEADDRESS
#define DDR_END_ADDR XPAR_PS7_DDR_0_HIGHADDRESS
#endif
#endif
#endif
#define DDR_TEMP_START_ADDR DDR_START_ADDR
/*
* DDR test pattern
*/
#define DDR_TEST_PATTERN 0xAA55AA55
#define DDR_TEST_OFFSET 0x100000
/*
*
*/
#define QSPI_DUAL_FLASH_SIZE 0x2000000; /*32MB*/
#define QSPI_SINGLE_FLASH_SIZE 0x1000000; /*16MB*/
#define NAND_FLASH_SIZE 0x8000000; /*128MB*/
#define NOR_FLASH_SIZE 0x2000000; /*32MB*/
#define LQSPI_CFG_OFFSET 0xA0
#define LQSPI_CFG_DUAL_FLASH_MASK 0x40000000
/*
* These are the SLCR lock and unlock macros
*/
#define SlcrUnlock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x08, 0xDF0DDF0D)
#define SlcrLock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x04, 0x767B767B)
#define IMAGE_HEADER_CHECKSUM_COUNT 10
/* Boot ROM Image defines */
#define IMAGE_WIDTH_CHECK_OFFSET (0x020) /**< 0xaa995566 Width Detection word */
#define IMAGE_IDENT_OFFSET (0x024) /**< 0x584C4E58 "XLNX" */
#define IMAGE_ENC_FLAG_OFFSET (0x028) /**< 0xA5C3C5A3 */
#define IMAGE_USR_DEF_OFFSET (0x02C) /**< undefined could be used as */
#define IMAGE_SOURCE_ADDR_OFFSET (0x030) /**< start address of image */
#define IMAGE_BYTE_LEN_OFFSET (0x034) /**< length of image> in bytes */
#define IMAGE_DEST_ADDR_OFFSET (0x038) /**< destination address in OCM */
#define IMAGE_EXECUTE_ADDR_OFFSET (0x03c) /**< address to start executing at */
#define IMAGE_TOT_BYTE_LEN_OFFSET (0x040) /**< total length of image in bytes */
#define IMAGE_QSPI_CFG_WORD_OFFSET (0x044) /**< QSPI configuration data */
#define IMAGE_CHECKSUM_OFFSET (0x048) /**< Header Checksum offset */
#define IMAGE_IDENT (0x584C4E58) /**< XLNX pattern */
/* Reboot status register defines:
* 0xF0000000 for FSBL fallback mask to notify Boot Rom
* 0x60000000 for FSBL to mark that FSBL has not handoff yet
* 0x00FFFFFF for user application to use across soft reset
*/
#define FSBL_FAIL_MASK 0xF0000000
#define FSBL_IN_MASK 0x60000000
/* The address that holds the base address for the image Boot ROM found */
#define BASEADDR_HOLDER 0xFFFFFFF8
/**************************** Type Definitions *******************************/
/************************** Function Prototypes ******************************/
void OutputStatus(u32 State);
void FsblFallback(void);
int FsblSetNextPartition(int Num);
void *(memcpy_rom)(void * s1, const void * s2, u32 n);
char *strcpy_rom(char *Dest, const char *Src);
void ClearFSBLIn(void);
void MarkFSBLIn(void);
void FsblHandoff(u32 FsblStartAddr);
u32 GetResetReason(void);
#ifdef FSBL_PERF
void FsblGetGlobalTime (XTime * tCur);
void FsblMeasurePerfTime (XTime tCur, XTime tEnd);
#endif
void GetSiliconVersion(void);
void FsblHandoffExit(u32 FsblStartAddr);
void FsblHandoffJtagExit();
void FsblPrintArray (u8 *Buf, u32 Len, char *Str);
/************************** Variable Definitions *****************************/
extern int SkipPartition;
/***************** Macros (Inline Functions) Definitions *********************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/fsbl_debug.h
+56
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@@ -0,0 +1,56 @@
/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file fsbl_debug.h
*
* This file contains the debug verbose information for FSBL print functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 3.00a mb 01/09/12 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef _FSBL_DEBUG_H
#define _FSBL_DEBUG_H
#ifdef __cplusplus
extern "C" {
#endif
#define DEBUG_GENERAL 0x00000001 /* general debug messages */
#define DEBUG_INFO 0x00000002 /* More debug information */
#if defined (FSBL_DEBUG_INFO)
#define fsbl_dbg_current_types ((DEBUG_INFO) | (DEBUG_GENERAL))
#elif defined (FSBL_DEBUG)
#define fsbl_dbg_current_types (DEBUG_GENERAL)
#else
#define fsbl_dbg_current_types 0
#endif
#ifdef STDOUT_BASEADDRESS
#define fsbl_printf(type,...) \
if (((type) & fsbl_dbg_current_types)) {xil_printf (__VA_ARGS__); }
#else
#define fsbl_printf(type, ...)
#endif
#ifdef __cplusplus
}
#endif
#endif /* _FSBL_DEBUG_H */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/fsbl_handoff.S
+194
View File
@@ -0,0 +1,194 @@
/******************************************************************************
*
* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file handoff.S
*
* Contains the code that does the handoff to the loaded application. This
* code lives high in the ROM.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date.word Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 03/01/10 Initial release
* 7.00a kc 10/23/13 Added support for armcc compiler
* </pre>
*
* @note
* Assumes that the starting address of the FSBL is provided by the calling routine
* in R0.
*
******************************************************************************/
#ifdef __GNUC__
.globl FsblHandoffJtagExit
.globl FsblHandoffExit
.section .handoff,"axS"
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
FsblHandoffJtagExit:
mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
dsb
isb /* make sure it completes */
ldr r4, =0
mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
isb /* make sure it completes */
Loop:
wfe
b Loop
FsblHandoffExit:
mov lr, r0 /* move the destination address into link register */
mcr 15,0,r0,cr7,cr5,0 /* Invalidate Instruction cache */
mcr 15,0,r0,cr7,cr5,6 /* Invalidate branch predictor array */
dsb
isb /* make sure it completes */
ldr r4, =0
mcr 15,0,r4,cr1,cr0,0 /* disable the ICache and MMU */
isb /* make sure it completes */
bx lr /* force the switch, destination should have been in r0 */
.Ldone: b .Ldone /* Paranoia: we should never get here */
.end
#elif defined (__IASMARM__)
PUBLIC FsblHandoffJtagExit
PUBLIC FsblHandoffExit
SECTION .handoff:CODE:NOROOT(2)
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
FsblHandoffJtagExit
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
dsb
isb ;/* make sure it completes */
ldr r4, =0
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
isb ;/* make sure it completes */
Loop
wfe
b Loop
FsblHandoffExit
mov lr, r0 ;/* move the destination address into link register */
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
dsb
isb ;/* make sure it completes */
ldr r4, =0
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
isb ;/* make sure it completes */
bx lr ;/* force the switch, destination should have been in r0 */
.Ldone
b .Ldone ;/* Paranoia: we should never get here */
END
#else
EXPORT FsblHandoffJtagExit
EXPORT FsblHandoffExit
AREA |.handoff|,CODE
;/***************************** Include Files *********************************/
;/************************** Constant Definitions *****************************/
;/**************************** Type Definitions *******************************/
;/***************** Macros (Inline Functions) Definitions *********************/
;/************************** Function Prototypes ******************************/
;/************************** Variable Definitions *****************************/
FsblHandoffJtagExit
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
dsb
isb ;/* make sure it completes */
ldr r4, =0
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
isb ;/* make sure it completes */
Loop
wfe
b Loop
FsblHandoffExit
mov lr, r0 ;/* move the destination address into link register */
mcr p15,0,r0,c7,c5,0 ;/* Invalidate Instruction cache */
mcr p15,0,r0,c7,c5,6 ;/* Invalidate branch predictor array */
dsb
isb ;/* make sure it completes */
ldr r4, =0
mcr p15,0,r4,c1,c0,0 ;/* disable the ICache and MMU */
isb ;/* make sure it completes */
bx lr ;/* force the switch, destination should have been in r0 */
Ldone b Ldone ;/* Paranoia: we should never get here */
END
#endif
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/fsbl_hooks.c
+138
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@@ -0,0 +1,138 @@
/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************
*
* @file fsbl_hooks.c
*
* This file provides functions that serve as user hooks. The user can add the
* additional functionality required into these routines. This would help retain
* the normal FSBL flow unchanged.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 3.00a np 08/03/12 Initial release
* </pre>
*
* @note
*
******************************************************************************/
#include "fsbl.h"
#include "xstatus.h"
#include "fsbl_hooks.h"
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
/******************************************************************************
* This function is the hook which will be called before the bitstream download.
* The user can add all the customized code required to be executed before the
* bitstream download to this routine.
*
* @param None
*
* @return
* - XST_SUCCESS to indicate success
* - XST_FAILURE.to indicate failure
*
****************************************************************************/
u32 FsblHookBeforeBitstreamDload(void)
{
u32 Status;
Status = XST_SUCCESS;
/*
* User logic to be added here. Errors to be stored in the status variable
* and returned
*/
fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n");
return (Status);
}
/******************************************************************************
* This function is the hook which will be called after the bitstream download.
* The user can add all the customized code required to be executed after the
* bitstream download to this routine.
*
* @param None
*
* @return
* - XST_SUCCESS to indicate success
* - XST_FAILURE.to indicate failure
*
****************************************************************************/
u32 FsblHookAfterBitstreamDload(void)
{
u32 Status;
Status = XST_SUCCESS;
/*
* User logic to be added here.
* Errors to be stored in the status variable and returned
*/
fsbl_printf(DEBUG_INFO, "In FsblHookAfterBitstreamDload function \r\n");
return (Status);
}
/******************************************************************************
* This function is the hook which will be called before the FSBL does a handoff
* to the application. The user can add all the customized code required to be
* executed before the handoff to this routine.
*
* @param None
*
* @return
* - XST_SUCCESS to indicate success
* - XST_FAILURE.to indicate failure
*
****************************************************************************/
u32 FsblHookBeforeHandoff(void)
{
u32 Status;
Status = XST_SUCCESS;
/*
* User logic to be added here.
* Errors to be stored in the status variable and returned
*/
fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n");
return (Status);
}
/******************************************************************************
* This function is the hook which will be called in case FSBL fall back
*
* @param None
*
* @return None
*
****************************************************************************/
void FsblHookFallback(void)
{
/*
* User logic to be added here.
* Errors to be stored in the status variable and returned
*/
fsbl_printf(DEBUG_INFO,"In FsblHookFallback function \r\n");
while(1);
}
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/fsbl_hooks.h
+55
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@@ -0,0 +1,55 @@
/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file fsbl_hooks.h
*
* Contains the function prototypes, defines and macros required by fsbl_hooks.c
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 3.00a np/mb 10/08/12 Initial release
* Corrected the prototype
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef FSBL_HOOKS_H_
#define FSBL_HOOKS_H_
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "fsbl.h"
/************************** Function Prototypes ******************************/
/* FSBL hook function which is called before bitstream download */
u32 FsblHookBeforeBitstreamDload(void);
/* FSBL hook function which is called after bitstream download */
u32 FsblHookAfterBitstreamDload(void);
/* FSBL hook function which is called before handoff to the application */
u32 FsblHookBeforeHandoff(void);
/* FSBL hook function which is called in FSBL fallback */
void FsblHookFallback(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/image_mover.c
+1372
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File diff suppressed because it is too large Load Diff
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/image_mover.h
+137
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@@ -0,0 +1,137 @@
/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file image_mover.h
*
* This file contains the interface for moving the image from FLASH to OCM
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 03/04/11 Initial release
* 2.00a jz 06/04/11 partition header expands to 12 words
* 5.00a kc 07/30/13 Added defines for image header information
* 8.00a kc 01/16/13 Added defines for partition owner attribute
* 9.0 vns 03/21/22 Deleted GetImageHeaderAndSignature() and added
* GetNAuthImageHeader()
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___IMAGE_MOVER_H___
#define ___IMAGE_MOVER_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "fsbl.h"
/************************** Constant Definitions *****************************/
#define PARTITION_NUMBER_SHIFT 24
#define MAX_PARTITION_NUMBER (0xE)
/* Boot Image Header defines */
#define IMAGE_HDR_OFFSET 0x098 /* Start of image header table */
#define IMAGE_PHDR_OFFSET 0x09C /* Start of partition headers */
#define IMAGE_HEADER_SIZE (64)
#define IMAGE_HEADER_TABLE_SIZE (64)
#define TOTAL_PARTITION_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
#define TOTAL_IMAGE_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE)
#define TOTAL_HEADER_SIZE (IMAGE_HEADER_TABLE_SIZE + \
TOTAL_IMAGE_HEADER_SIZE + \
TOTAL_PARTITION_HEADER_SIZE + 64)
/* Partition Header defines */
#define PARTITION_IMAGE_WORD_LEN_OFFSET 0x00 /* Word length of image */
#define PARTITION_DATA_WORD_LEN_OFFSET 0x04 /* Word length of data */
#define PARTITION_WORD_LEN_OFFSET 0x08 /* Word length of partition */
#define PARTITION_LOAD_ADDRESS_OFFSET 0x0C /* Load addr in DDR */
#define PARTITION_EXEC_ADDRESS_OFFSET 0x10 /* Addr to start executing */
#define PARTITION_ADDR_OFFSET 0x14 /* Partition word offset */
#define PARTITION_ATTRIBUTE_OFFSET 0x18 /* Partition type */
#define PARTITION_HDR_CHECKSUM_OFFSET 0x3C /* Header Checksum offset */
#define PARTITION_HDR_CHECKSUM_WORD_COUNT 0xF /* Checksum word count */
#define PARTITION_HDR_WORD_COUNT 0x10 /* Header word len */
#define PARTITION_HDR_TOTAL_LEN 0x40 /* One partition hdr length*/
/* Attribute word defines */
#define ATTRIBUTE_IMAGE_TYPE_MASK 0xF0 /* Destination Device type */
#define ATTRIBUTE_PS_IMAGE_MASK 0x10 /* Code partition */
#define ATTRIBUTE_PL_IMAGE_MASK 0x20 /* Bit stream partition */
#define ATTRIBUTE_CHECKSUM_TYPE_MASK 0x7000 /* Checksum Type */
#define ATTRIBUTE_RSA_PRESENT_MASK 0x8000 /* RSA Signature Present */
#define ATTRIBUTE_PARTITION_OWNER_MASK 0x30000 /* Partition Owner */
#define ATTRIBUTE_PARTITION_OWNER_FSBL 0x00000 /* FSBL Partition Owner */
/**************************** Type Definitions *******************************/
typedef u32 (*ImageMoverType)( u32 SourceAddress,
u32 DestinationAddress,
u32 LengthBytes);
typedef struct StructPartHeader {
u32 ImageWordLen; /* 0x0 */
u32 DataWordLen; /* 0x4 */
u32 PartitionWordLen; /* 0x8 */
u32 LoadAddr; /* 0xC */
u32 ExecAddr; /* 0x10 */
u32 PartitionStart; /* 0x14 */
u32 PartitionAttr; /* 0x18 */
u32 SectionCount; /* 0x1C */
u32 CheckSumOffset; /* 0x20 */
u32 Pads1[1];
u32 ACOffset; /* 0x28 */
u32 Pads2[4];
u32 CheckSum; /* 0x3C */
}PartHeader;
struct HeaderArray {
u32 Fields[16];
};
/***************** Macros (Inline Functions) Definitions *********************/
#define MoverIn32 Xil_In32
#define MoverOut32 Xil_Out32
/************************** Function Prototypes ******************************/
u32 LoadBootImage(void);
u32 GetPartitionHeaderInfo(u32 ImageBaseAddress);
u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header);
u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H);
u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset);
u32 GetNAuthImageHeader(u32 ImageAddress);
u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength);
u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header);
u32 IsEmptyHeader(struct HeaderArray *H);
u32 IsLastPartition(struct HeaderArray *H);
void HeaderDump(PartHeader *Header);
u32 GetPartitionCount(PartHeader *Header);
u32 ValidateHeader(PartHeader *Header);
u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___IMAGE_MOVER_H___ */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/lscript.ld
+299
View File
@@ -0,0 +1,299 @@
/******************************************************************************
* Copyright (C) 2012 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x6000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000;
_RSA_AC_SIZE = DEFINED(_RSA_AC_SIZE) ? _RSA_AC_SIZE : 0x1000;
_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024;
_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048;
_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024;
_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
ps7_ram_0_S_AXI_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x00030000
ps7_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x0000FE00
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
SECTIONS
{
.text : {
*(.vectors)
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.vfp11_veneer)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > ps7_ram_0_S_AXI_BASEADDR
.note.gnu.build-id : {
KEEP (*(.note.gnu.build-id))
} > ps7_ram_0_S_AXI_BASEADDR
.init : {
KEEP (*(.init))
} > ps7_ram_0_S_AXI_BASEADDR
.fini : {
KEEP (*(.fini))
} > ps7_ram_0_S_AXI_BASEADDR
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.rodata1 : {
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.sdata2 : {
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.data : {
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.data1 : {
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.got : {
*(.got)
} > ps7_ram_0_S_AXI_BASEADDR
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > ps7_ram_0_S_AXI_BASEADDR
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > ps7_ram_0_S_AXI_BASEADDR
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.eh_frame : {
*(.eh_frame)
} > ps7_ram_0_S_AXI_BASEADDR
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.gcc_except_table : {
*(.gcc_except_table)
} > ps7_ram_0_S_AXI_BASEADDR
.mmu_tbl (ALIGN(0x4000)): {
__mmu_tbl_start = .;
*(.mmu_tbl)
__mmu_tbl_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.preinit_array : {
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.init_array : {
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.fini_array : {
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.rsa_ac : {
. = ALIGN(64);
__rsa_ac_start = .;
. += _RSA_AC_SIZE;
__rsa_ac_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.sdata : {
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.sbss (NOLOAD) : {
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
__sbss_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > ps7_ram_0_S_AXI_BASEADDR
.bss (NOLOAD) : {
__bss_start = .;
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
__bss_end = .;
__bss_end__ = .;
} > ps7_ram_0_S_AXI_BASEADDR
.drvcfg_sec : {
. = ALIGN(8);
__drvcfgsecdata_start = .;
KEEP (*(.drvcfg_sec))
__drvcfgsecdata_end = .;
__drvcfgsecdata_size = __drvcfgsecdata_end - __drvcfgsecdata_start;
} > ps7_ram_0_S_AXI_BASEADDR
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(16);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > ps7_ram_0_S_AXI_BASEADDR
.stack (NOLOAD) : {
. = ALIGN(16);
_stack_end = .;
. += _STACK_SIZE;
_stack = .;
__stack = _stack;
. = ALIGN(16);
_irq_stack_end = .;
. += _STACK_SIZE;
__irq_stack = .;
_supervisor_stack_end = .;
. += _SUPERVISOR_STACK_SIZE;
. = ALIGN(16);
__supervisor_stack = .;
_abort_stack_end = .;
. += _ABORT_STACK_SIZE;
. = ALIGN(16);
__abort_stack = .;
_fiq_stack_end = .;
. += _FIQ_STACK_SIZE;
. = ALIGN(16);
__fiq_stack = .;
_undef_stack_end = .;
. += _UNDEF_STACK_SIZE;
. = ALIGN(16);
__undef_stack = .;
} > ps7_ram_1_S_AXI_BASEADDR
_end = .;
}
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/main.c
+1534
View File
File diff suppressed because it is too large Load Diff
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/md5.c
+484
View File
@@ -0,0 +1,484 @@
/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
* All rights reserved.
*
* This package is an SSL implementation written
* by Eric Young (eay@cryptsoft.com).
* The implementation was written so as to conform with Netscapes SSL.
*
* This library is free for commercial and non-commercial use as long as
* the following conditions are adhered to. The following conditions
* apply to all code found in this distribution, be it the RC4, RSA,
* lhash, DES, etc., code; not just the SSL code. The SSL documentation
* included with this distribution is covered by the same copyright terms
* except that the holder is Tim Hudson (tjh@cryptsoft.com).
*
* Copyright remains Eric Young's, and as such any Copyright notices in
* the code are not to be removed.
* If this package is used in a product, Eric Young should be given attribution
* as the author of the parts of the library used.
* This can be in the form of a textual message at program startup or
* in documentation (online or textual) provided with the package.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* "This product includes cryptographic software written by
* Eric Young (eay@cryptsoft.com)"
* The word 'cryptographic' can be left out if the routines from the library
* being used are not cryptographic related :-).
* 4. If you include any Windows specific code (or a derivative thereof) from
* the apps directory (application code) you must include an acknowledgement:
* "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
*
* THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The licence and distribution terms for any publicly available version or
* derivative of this code cannot be changed. i.e. this code cannot simply be
* copied and put under another distribution licence
* [including the GNU Public Licence.]
*/
/*****************************************************************************/
/**
*
* @file md5.c
*
* Contains code to calculate checksum using md5 algorithm
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 5.00a sgd 05/17/13 Initial release
*
*
* </pre>
*
* @note
*
******************************************************************************/
/****************************** Include Files *********************************/
#include "md5.h"
/******************************************************************************/
/**
*
* This function sets the memory
*
* @param dest
*
* @param ch
*
* @param count
*
* @return None
*
* @note None
*
****************************************************************************/
inline void * MD5Memset( void *dest, int ch, u32 count )
{
register char *dst8 = (char*)dest;
while( count-- )
*dst8++ = ch;
return dest;
}
/******************************************************************************/
/**
*
* This function copy the memory
*
* @param dest
*
* @param ch
*
* @param count
*
* @return None
*
* @note None
*
****************************************************************************/
inline void * MD5Memcpy( void *dest, const void *src,
u32 count, boolean doByteSwap )
{
register char * dst8 = (char*)dest;
register char * src8 = (char*)src;
if( doByteSwap == FALSE ) {
while( count-- )
*dst8++ = *src8++;
} else {
count /= sizeof( u32 );
while( count-- ) {
dst8[ 0 ] = src8[ 3 ];
dst8[ 1 ] = src8[ 2 ];
dst8[ 2 ] = src8[ 1 ];
dst8[ 3 ] = src8[ 0 ];
dst8 += 4;
src8 += 4;
}
}
return dest;
}
/******************************************************************************/
/**
*
* This function is the core of the MD5 algorithm,
* this alters an existing MD5 hash to
* reflect the addition of 16 longwords of new data. MD5Update blocks
* the data and converts bytes into longwords for this routine.
*
* Use binary integer part of the sine of integers (Radians) as constants.
* Calculated as:
*
* for( i = 0; i < 63; i++ )
* k[ i ] := floor( abs( sin( i + 1 ) ) × pow( 2, 32 ) )
*
* Following number is the per-round shift amount.
*
* @param dest
*
* @param ch
*
* @param count
*
* @return None
*
* @note None
*
****************************************************************************/
void MD5Transform( u32 *buffer, u32 *intermediate )
{
register u32 a, b, c, d;
a = buffer[ 0 ];
b = buffer[ 1 ];
c = buffer[ 2 ];
d = buffer[ 3 ];
MD5_STEP( F1, a, b, c, d, intermediate[ 0 ] + 0xd76aa478, 7 );
MD5_STEP( F1, d, a, b, c, intermediate[ 1 ] + 0xe8c7b756, 12 );
MD5_STEP( F1, c, d, a, b, intermediate[ 2 ] + 0x242070db, 17 );
MD5_STEP( F1, b, c, d, a, intermediate[ 3 ] + 0xc1bdceee, 22 );
MD5_STEP( F1, a, b, c, d, intermediate[ 4 ] + 0xf57c0faf, 7 );
MD5_STEP( F1, d, a, b, c, intermediate[ 5 ] + 0x4787c62a, 12 );
MD5_STEP( F1, c, d, a, b, intermediate[ 6 ] + 0xa8304613, 17 );
MD5_STEP( F1, b, c, d, a, intermediate[ 7 ] + 0xfd469501, 22 );
MD5_STEP( F1, a, b, c, d, intermediate[ 8 ] + 0x698098d8, 7 );
MD5_STEP( F1, d, a, b, c, intermediate[ 9 ] + 0x8b44f7af, 12 );
MD5_STEP( F1, c, d, a, b, intermediate[ 10 ] + 0xffff5bb1, 17 );
MD5_STEP( F1, b, c, d, a, intermediate[ 11 ] + 0x895cd7be, 22 );
MD5_STEP( F1, a, b, c, d, intermediate[ 12 ] + 0x6b901122, 7 );
MD5_STEP( F1, d, a, b, c, intermediate[ 13 ] + 0xfd987193, 12 );
MD5_STEP( F1, c, d, a, b, intermediate[ 14 ] + 0xa679438e, 17 );
MD5_STEP( F1, b, c, d, a, intermediate[ 15 ] + 0x49b40821, 22 );
MD5_STEP( F2, a, b, c, d, intermediate[ 1 ] + 0xf61e2562, 5 );
MD5_STEP( F2, d, a, b, c, intermediate[ 6 ] + 0xc040b340, 9 );
MD5_STEP( F2, c, d, a, b, intermediate[ 11 ] + 0x265e5a51, 14 );
MD5_STEP( F2, b, c, d, a, intermediate[ 0 ] + 0xe9b6c7aa, 20 );
MD5_STEP( F2, a, b, c, d, intermediate[ 5 ] + 0xd62f105d, 5 );
MD5_STEP( F2, d, a, b, c, intermediate[ 10 ] + 0x02441453, 9 );
MD5_STEP( F2, c, d, a, b, intermediate[ 15 ] + 0xd8a1e681, 14 );
MD5_STEP( F2, b, c, d, a, intermediate[ 4 ] + 0xe7d3fbc8, 20 );
MD5_STEP( F2, a, b, c, d, intermediate[ 9 ] + 0x21e1cde6, 5 );
MD5_STEP( F2, d, a, b, c, intermediate[ 14 ] + 0xc33707d6, 9 );
MD5_STEP( F2, c, d, a, b, intermediate[ 3 ] + 0xf4d50d87, 14 );
MD5_STEP( F2, b, c, d, a, intermediate[ 8 ] + 0x455a14ed, 20 );
MD5_STEP( F2, a, b, c, d, intermediate[ 13 ] + 0xa9e3e905, 5 );
MD5_STEP( F2, d, a, b, c, intermediate[ 2 ] + 0xfcefa3f8, 9 );
MD5_STEP( F2, c, d, a, b, intermediate[ 7 ] + 0x676f02d9, 14 );
MD5_STEP( F2, b, c, d, a, intermediate[ 12 ] + 0x8d2a4c8a, 20 );
MD5_STEP( F3, a, b, c, d, intermediate[ 5 ] + 0xfffa3942, 4 );
MD5_STEP( F3, d, a, b, c, intermediate[ 8 ] + 0x8771f681, 11 );
MD5_STEP( F3, c, d, a, b, intermediate[ 11 ] + 0x6d9d6122, 16 );
MD5_STEP( F3, b, c, d, a, intermediate[ 14 ] + 0xfde5380c, 23 );
MD5_STEP( F3, a, b, c, d, intermediate[ 1 ] + 0xa4beea44, 4 );
MD5_STEP( F3, d, a, b, c, intermediate[ 4 ] + 0x4bdecfa9, 11 );
MD5_STEP( F3, c, d, a, b, intermediate[ 7 ] + 0xf6bb4b60, 16 );
MD5_STEP( F3, b, c, d, a, intermediate[ 10 ] + 0xbebfbc70, 23 );
MD5_STEP( F3, a, b, c, d, intermediate[ 13 ] + 0x289b7ec6, 4 );
MD5_STEP( F3, d, a, b, c, intermediate[ 0 ] + 0xeaa127fa, 11 );
MD5_STEP( F3, c, d, a, b, intermediate[ 3 ] + 0xd4ef3085, 16 );
MD5_STEP( F3, b, c, d, a, intermediate[ 6 ] + 0x04881d05, 23 );
MD5_STEP( F3, a, b, c, d, intermediate[ 9 ] + 0xd9d4d039, 4 );
MD5_STEP( F3, d, a, b, c, intermediate[ 12 ] + 0xe6db99e5, 11 );
MD5_STEP( F3, c, d, a, b, intermediate[ 15 ] + 0x1fa27cf8, 16 );
MD5_STEP( F3, b, c, d, a, intermediate[ 2 ] + 0xc4ac5665, 23 );
MD5_STEP( F4, a, b, c, d, intermediate[ 0 ] + 0xf4292244, 6 );
MD5_STEP( F4, d, a, b, c, intermediate[ 7 ] + 0x432aff97, 10 );
MD5_STEP( F4, c, d, a, b, intermediate[ 14 ] + 0xab9423a7, 15 );
MD5_STEP( F4, b, c, d, a, intermediate[ 5 ] + 0xfc93a039, 21 );
MD5_STEP( F4, a, b, c, d, intermediate[ 12 ] + 0x655b59c3, 6 );
MD5_STEP( F4, d, a, b, c, intermediate[ 3 ] + 0x8f0ccc92, 10 );
MD5_STEP( F4, c, d, a, b, intermediate[ 10 ] + 0xffeff47d, 15 );
MD5_STEP( F4, b, c, d, a, intermediate[ 1 ] + 0x85845dd1, 21 );
MD5_STEP( F4, a, b, c, d, intermediate[ 8 ] + 0x6fa87e4f, 6 );
MD5_STEP( F4, d, a, b, c, intermediate[ 15 ] + 0xfe2ce6e0, 10 );
MD5_STEP( F4, c, d, a, b, intermediate[ 6 ] + 0xa3014314, 15 );
MD5_STEP( F4, b, c, d, a, intermediate[ 13 ] + 0x4e0811a1, 21 );
MD5_STEP( F4, a, b, c, d, intermediate[ 4 ] + 0xf7537e82, 6 );
MD5_STEP( F4, d, a, b, c, intermediate[ 11 ] + 0xbd3af235, 10 );
MD5_STEP( F4, c, d, a, b, intermediate[ 2 ] + 0x2ad7d2bb, 15 );
MD5_STEP( F4, b, c, d, a, intermediate[ 9 ] + 0xeb86d391, 21 );
buffer[ 0 ] += a;
buffer[ 1 ] += b;
buffer[ 2 ] += c;
buffer[ 3 ] += d;
}
/******************************************************************************/
/**
*
* This function Start MD5 accumulation
* Set bit count to 0 and buffer to mysterious initialization constants
*
* @param
*
* @return None
*
* @note None
*
****************************************************************************/
inline void MD5Init( MD5Context *context )
{
context->buffer[ 0 ] = 0x67452301;
context->buffer[ 1 ] = 0xefcdab89;
context->buffer[ 2 ] = 0x98badcfe;
context->buffer[ 3 ] = 0x10325476;
context->bits[ 0 ] = 0;
context->bits[ 1 ] = 0;
}
/******************************************************************************/
/**
*
* This function updates context to reflect the concatenation of another
* buffer full of bytes
*
* @param
*
* @param
*
* @param
*
* @param
*
* @return None
*
* @note None
*
****************************************************************************/
inline void MD5Update( MD5Context *context, u8 *buffer,
u32 len, boolean doByteSwap )
{
register u32 temp;
register u8 * p;
/*
* Update bitcount
*/
temp = context->bits[ 0 ];
if( ( context->bits[ 0 ] = temp + ( (u32)len << 3 ) ) < temp ) {
/*
* Carry from low to high
*/
context->bits[ 1 ]++;
}
context->bits[ 1 ] += len >> 29;
/*
* Bytes already in shsInfo->data
*/
temp = ( temp >> 3 ) & 0x3f;
/*
* Handle any leading odd-sized chunks
*/
if( temp ) {
p = (u8 *)context->intermediate + temp;
temp = MD5_SIGNATURE_BYTE_SIZE - temp;
if( len < temp ) {
MD5Memcpy( p, buffer, len, doByteSwap );
return;
}
MD5Memcpy( p, buffer, temp, doByteSwap );
MD5Transform( context->buffer, (u32 *)context->intermediate );
buffer += temp;
len -= temp;
}
/*
* Process data in 64-byte, 512 bit, chunks
*/
while( len >= MD5_SIGNATURE_BYTE_SIZE ) {
MD5Memcpy( context->intermediate, buffer, MD5_SIGNATURE_BYTE_SIZE,
doByteSwap );
MD5Transform( context->buffer, (u32 *)context->intermediate );
buffer += MD5_SIGNATURE_BYTE_SIZE;
len -= MD5_SIGNATURE_BYTE_SIZE;
}
/*
* Handle any remaining bytes of data
*/
MD5Memcpy( context->intermediate, buffer, len, doByteSwap );
}
/******************************************************************************/
/**
*
* This function final wrap-up - pad to 64-byte boundary with the bit pattern
* 1 0* (64-bit count of bits processed, MSB-first
*
* @param
*
* @param
*
* @param
*
* @param
*
* @return None
*
* @note None
*
****************************************************************************/
inline void MD5Final( MD5Context *context, u8 *digest,
boolean doByteSwap )
{
u32 count;
u8 * p;
/*
* Compute number of bytes mod 64
*/
count = ( context->bits[ 0 ] >> 3 ) & 0x3F;
/*
* Set the first char of padding to 0x80. This is safe since there is
* always at least one byte free
*/
p = context->intermediate + count;
*p++ = 0x80;
/*
* Bytes of padding needed to make 64 bytes
*/
count = MD5_SIGNATURE_BYTE_SIZE - 1 - count;
/*
* Pad out to 56 mod 64
*/
if( count < 8 ) {
/*
* Two lots of padding: Pad the first block to 64 bytes
*/
MD5Memset( p, 0, count );
MD5Transform( context->buffer, (u32 *)context->intermediate );
/*
* Now fill the next block with 56 bytes
*/
MD5Memset( context->intermediate, 0, 56 );
} else {
/*
* Pad block to 56 bytes
*/
MD5Memset( p, 0, count - 8 );
}
/*
* Append length in bits and transform
*/
( (u32 *)context->intermediate )[ 14 ] = context->bits[ 0 ];
( (u32 *)context->intermediate )[ 15 ] = context->bits[ 1 ];
MD5Transform( context->buffer, (u32 *)context->intermediate );
/*
* Now return the digest
*/
MD5Memcpy( digest, context->buffer, 16, doByteSwap );
}
/******************************************************************************/
/**
*
* This function calculate and store in 'digest' the MD5 digest of 'len' bytes at
* 'input'. 'digest' must have enough space to hold 16 bytes
*
* @param
*
* @param
*
* @param
*
* @param
*
* @return None
*
* @note None
*
****************************************************************************/
void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap )
{
MD5Context context;
MD5Init( &context );
MD5Update( &context, input, len, doByteSwap );
MD5Final( &context, digest, doByteSwap );
}
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/md5.h
+94
View File
@@ -0,0 +1,94 @@
/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file md5.h
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 5.00a sgd 05/17/13 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___MD5_H___
#define ___MD5_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#define MD5_SIGNATURE_BYTE_SIZE 64
/**************************** Type Definitions *******************************/
typedef u8 boolean;
typedef u8 signature[ MD5_SIGNATURE_BYTE_SIZE ];
struct MD5Context
{
u32 buffer[ 4 ];
u32 bits[ 2 ];
signature intermediate;
};
typedef struct MD5Context MD5Context;
/***************** Macros (Inline Functions) Definitions *********************/
/*
* The four core functions - F1 is optimized somewhat
*/
#define F1( x, y, z ) ( z ^ ( x & ( y ^ z ) ) )
#define F2( x, y, z ) F1( z, x, y )
#define F3( x, y, z ) ( x ^ y ^ z )
#define F4( x, y, z ) ( y ^ ( x | ~z ) )
/*
* This is the central step in the MD5 algorithm
*/
#define MD5_STEP( f, w, x, y, z, data, s ) \
( w += f( x, y, z ) + data, w = w << s | w >> ( 32 - s ), w += x )
/************************** Function Prototypes ******************************/
void * MD5Memset( void *dest, int ch, u32 count );
void * MD5Memcpy( void *dest, const void *src, u32 count, boolean doByteSwap );
void MD5Transform( u32 *buffer, u32 *intermediate );
void MD5Init( MD5Context *context );
void MD5Update( MD5Context *context, u8 *buffer, u32 len, boolean doByteSwap );
void MD5Final( MD5Context *context, u8 *digest, boolean doByteSwap );
void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap );
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___MD5_H___ */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/nand.c
+274
View File
@@ -0,0 +1,274 @@
/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file nand.c
*
* Contains code for the NAND FLASH functionality. Bad Block management
* is simple: skip the bad blocks and keep going.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 01/10/10 Initial release
* 2.00a mb 25/05/12 fsbl changes for standalone bsp based
* 3.00a sgd 30/01/13 Code cleanup
* 5.00a sgd 17/05/13 Support for Multi Boot
* 21.2 ng 07/25/23 Add SDT support
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "fsbl.h"
#if defined(XPAR_PS7_NAND_0_BASEADDR) || defined(XPAR_XNANDPS_0_FLASHBASE)
#include "nand.h"
#include "xnandps_bbm.h"
/************************** Constant Definitions *****************************/
#ifndef SDT
#define NAND_DEVICE XPAR_XNANDPS_0_DEVICE_ID
#else
#define NAND_DEVICE XPAR_XNANDPS_0_BASEADDR
#endif
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
u64 Offset,
u32 Length);
/************************** Variable Definitions *****************************/
extern u32 FlashReadBaseAddress;
extern u32 FlashOffsetAddress;
XNandPs *NandInstPtr;
XNandPs NandInstance; /* XNand Instance. */
/******************************************************************************/
/**
*
* This function initializes the controller for the NAND FLASH interface.
*
* @param none
*
* @return
* - XST_SUCCESS if the controller initializes correctly
* - XST_FAILURE if the controller fails to initializes correctly
*
* @note none.
*
****************************************************************************/
u32 InitNand(void)
{
u32 Status;
XNandPs_Config *ConfigPtr;
/*
* Set up pointers to instance and the config structure
*/
NandInstPtr = &NandInstance;
/*
* Initialize the flash driver.
*/
ConfigPtr = XNandPs_LookupConfig(NAND_DEVICE);
if (ConfigPtr == NULL) {
fsbl_printf(DEBUG_GENERAL,"Nand Driver failed \n \r");
return XST_FAILURE;
}
Status = XNandPs_CfgInitialize(NandInstPtr, ConfigPtr,
ConfigPtr->SmcBase,ConfigPtr->FlashBase);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_GENERAL,"NAND initialization failed \n \r");
return XST_FAILURE;
}
/*
* Set up base address for access
*/
FlashReadBaseAddress = XPS_NAND_BASEADDR;
fsbl_printf(DEBUG_INFO,"InitNand: Geometry = 0x%x\r\n",
NandInstPtr->Geometry.FlashWidth);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_GENERAL,"InitNand: Status = 0x%.8x\r\n",
Status);
return XST_FAILURE;
}
/*
* set up the FLASH access pointers
*/
fsbl_printf(DEBUG_INFO,"Nand driver initialized \n\r");
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function provides the NAND FLASH interface for the Simplified header
* functionality. This function handles bad blocks.
*
* The source address is the absolute good address, bad blocks are skipped
* without incrementing the source address.
*
* @param SourceAddress is address in FLASH data space, absolute good address
* @param DestinationAddress is address in OCM data space
*
* @return XST_SUCCESS if the transfer completes correctly
* XST_FAILURE if the transfer fails to completes correctly
*
* @note none.
*
****************************************************************************/
u32 NandAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
{
u32 ActLen;
u32 BlockOffset;
u32 Block;
u32 Status;
u32 BytesLeft = LengthBytes;
u32 BlockSize = NandInstPtr->Geometry.BlockSize;
u8 *BufPtr = (u8 *)DestinationAddress;
u32 ReadLen;
u32 BlockReadLen;
u32 Offset;
u32 TmpAddress = 0 ;
u32 BlockCount = 0;
u32 BadBlocks = 0;
/*
* First get bad blocks before the source address
*/
while (TmpAddress < SourceAddress) {
while (XNandPs_IsBlockBad(NandInstPtr, BlockCount) ==
XST_SUCCESS) {
BlockCount ++;
BadBlocks ++;
}
TmpAddress += BlockSize;
BlockCount ++;
}
Offset = SourceAddress + BadBlocks * BlockSize;
/*
* Calculate the actual length including bad blocks
*/
ActLen = XNandPs_CalculateLength(NandInstPtr, Offset, LengthBytes);
/*
* Check if the actual length cross flash size
*/
if (Offset + ActLen > NandInstPtr->Geometry.DeviceSize) {
return XST_FAILURE;
}
while (BytesLeft > 0) {
BlockOffset = Offset & (BlockSize - 1);
Block = (Offset & ~(BlockSize - 1))/BlockSize;
BlockReadLen = BlockSize - BlockOffset;
Status = XNandPs_IsBlockBad(NandInstPtr, Block);
if (Status == XST_SUCCESS) {
/* Move to next block */
Offset += BlockReadLen;
continue;
}
/*
* Check if we cross block boundary
*/
if (BytesLeft < BlockReadLen) {
ReadLen = BytesLeft;
} else {
ReadLen = BlockReadLen;
}
/*
* Read from the NAND flash
*/
Status = XNandPs_Read(NandInstPtr, Offset, ReadLen, BufPtr, NULL);
if (Status != XST_SUCCESS) {
return Status;
}
BytesLeft -= ReadLen;
Offset += ReadLen;
BufPtr += ReadLen;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function returns the length including bad blocks from a given offset and
* length.
*
* @param NandInstPtr is the pointer to the XNandPs instance.
* @param Offset is the flash data address to read from.
* @param Length is number of bytes to read.
*
* @return
* - Return actual length including bad blocks.
*
* @note None.
*
******************************************************************************/
static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr,
u64 Offset,
u32 Length)
{
u32 BlockSize = NandInstPtr->Geometry.BlockSize;
u32 CurBlockLen;
u32 CurBlock;
u32 Status;
u32 TempLen = 0;
u32 ActLen = 0;
while (TempLen < Length) {
CurBlockLen = BlockSize - (Offset & (BlockSize - 1));
CurBlock = (Offset & ~(BlockSize - 1))/BlockSize;
/*
* Check if the block is bad
*/
Status = XNandPs_IsBlockBad(NandInstPtr, CurBlock);
if (Status != XST_SUCCESS) {
/* Good Block */
TempLen += CurBlockLen;
}
ActLen += CurBlockLen;
Offset += CurBlockLen;
if (Offset >= NandInstPtr->Geometry.DeviceSize) {
break;
}
}
return ActLen;
}
#endif
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/nand.h
+67
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/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file nand.h
*
* This file contains the interface for the NAND FLASH functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 01/10/10 Initial release
* 2.00a mb 30/05/12 added the flag XPAR_PS7_NAND_0_BASEADDR
* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
* 21.2 ng 07/25/23 Add SDT support
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___NAND_H___
#define ___NAND_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#if defined(XPAR_PS7_NAND_0_BASEADDR) || defined(XPAR_XNANDPS_0_FLASHBASE)
#include "xnandps.h"
#include "xnandps_bbm.h"
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
u32 InitNand(void);
u32 NandAccess( u32 SourceAddress,
u32 DestinationAddress,
u32 LengthWords);
#endif
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___NAND_H___ */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/nor.c
+118
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@@ -0,0 +1,118 @@
/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file nor.c
*
* Contains code for the NOR FLASH functionality.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 01/10/10 Initial release
* 2.00a mb 25/05/12 mio init removed
* 3.00a sgd 30/01/13 Code cleanup
*
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "fsbl.h"
#include "nor.h"
#include "xstatus.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern u32 FlashReadBaseAddress;
/******************************************************************************/
/******************************************************************************/
/**
*
* This function initializes the controller for the NOR FLASH interface.
*
* @param None
*
* @return None
*
* @note None.
*
****************************************************************************/
void InitNor(void)
{
/*
* Set up the base address for access
*/
FlashReadBaseAddress = XPS_NOR_BASEADDR;
}
/******************************************************************************/
/**
*
* This function provides the NOR FLASH interface for the Simplified header
* functionality.
*
* @param SourceAddress is address in FLASH data space
* @param DestinationAddress is address in OCM data space
* @param LengthBytes is the data length to transfer in bytes
*
* @return
* - XST_SUCCESS if the write completes correctly
* - XST_FAILURE if the write fails to completes correctly
*
* @note None.
*
****************************************************************************/
u32 NorAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
{
u32 Data;
u32 Count;
u32 *SourceAddr;
u32 *DestAddr;
u32 LengthWords;
/*
* check for non-word tail
* add bytes to cover the end
*/
if ((LengthBytes%4) != 0){
LengthBytes += (4 - (LengthBytes & 0x00000003));
}
LengthWords = LengthBytes >> WORD_LENGTH_SHIFT;
SourceAddr = (u32 *)(SourceAddress + FlashReadBaseAddress);
DestAddr = (u32 *)(DestinationAddress);
/*
* Word transfers, endianism isn't an issue
*/
for (Count=0; Count < LengthWords; Count++){
Data = Xil_In32((u32)(SourceAddr++));
Xil_Out32((u32)(DestAddr++), Data);
}
return XST_SUCCESS;
}
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/nor.h
+61
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@@ -0,0 +1,61 @@
/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file nor.h
*
* This file contains the interface for the NOR FLASH functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 01/10/10 Initial release
* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___NOR_H___
#define ___NOR_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#define XPS_NOR_BASEADDR XPS_PARPORT0_BASEADDR
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
void InitNor(void);
u32 NorAccess( u32 SourceAddress,
u32 DestinationAddress,
u32 LengthBytes);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___NOR_H___ */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/pcap.c
+799
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@@ -0,0 +1,799 @@
/*****************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file pcap.c
*
* Contains code for enabling and accessing the PCAP
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 02/10/10 Initial release
* 2.00a jz 05/28/11 Add SD support
* 2.00a mb 25/05/12 using the EDK provided devcfg driver
* Nand/SD encryption and review comments
* 3.00a mb 16/08/12 Added the poll function
* Removed the FPGA_RST_CTRL define
* Added the flag for NON PS instantiated bitstream
* 4.00a sgd 02/28/13 Fix for CR#681014 - ECC init in FSBL should not call
* fabric_init()
* Fix for CR#689026 - FSBL doesn't hold PL resets active
* during bit download
* Fix for CR#699475 - FSBL functionality is broken and
* its not able to boot in QSPI/NAND
* bootmode
* Fix for CR#705664 - FSBL fails to decrypt the
* bitstream when the image is AES
* encrypted using non-zero key value
* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
* changelogs in FSBL
* 7.00a kc 10/25/13 Fix for CR#724620 - How to handle PCAP_MODE after
* bitstream configuration
* Fix for CR#726178 - FabricInit() PROG_B is kept active
* for 5mS.
* Fix for CR#731839 - FSBL has to check the
* HMAC error status after decryption
* 12/04/13 Fix for CR#764382 - How to handle PCAP_MODE after
* bitstream configuration - PCAP_MODE
* and PCAP_PR bits are not modified
* 8.00a kc 2/20/14 Fix for CR#775631 - FSBL: FsblGetGlobalTimer()
* is not proper
* 10.00a kc 07/24/14 Fix for CR#809336 - Minor code cleanup
* 13.00a ssc 04/10/15 Fix for CR#846899 - Corrected logic to clear
* DMA done count
* 15.00a gan 07/21/16 Fix for CR# 953654 -(2016.3)FSBL -
* In pcap.c/pcap.h/main.h,
* Fabric Initialization sequence
* is modified to check the PL power
* before sequence starts and checking
* INIT_B reset status twice in case
* of failure.
* 16.00a gan 08/02/16 Fix for CR# 955897 -(2016.3)FSBL -
* In pcap.c, check pl power
* through MCTRL register for
* 3.0 and later versions of silicon.
* 21.1 ng 07/13/23 Add SDT support
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "pcap.h"
#include "nand.h" /* For NAND geometry information */
#include "fsbl.h"
#include "image_mover.h" /* For MoveImage */
#include "xparameters.h"
#include "xil_exception.h"
#include "xdevcfg.h"
#include "sleep.h"
#ifndef SDT
#include "xtime_l.h"
#else
#include "xiltimer.h"
#endif
#ifdef XPAR_XWDTPS_0_BASEADDR
#include "xwdtps.h"
#endif
/************************** Constant Definitions *****************************/
/*
* The following constants map to the XPAR parameters created in the
* xparameters.h file. They are only defined here such that a user can easily
* change all the needed parameters in one place.
*/
#ifndef SDT
#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID
#else
#define DCFG_DEVICE_ID XPAR_XDEVCFG_0_BASEADDR
#endif
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
extern int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
/************************** Variable Definitions *****************************/
/* Devcfg driver instance */
static XDcfg DcfgInstance;
XDcfg *DcfgInstPtr;
extern u32 Silicon_Version;
#ifdef XPAR_XWDTPS_0_BASEADDR
extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
#endif
/******************************************************************************/
/**
*
* This function transfer data using PCAP
*
* @param SourceDataPtr is a pointer to where the data is read from
* @param DestinationDataPtr is a pointer to where the data is written to
* @param SourceLength is the length of the data to be moved in words
* @param DestinationLength is the length of the data to be moved in words
* @param SecureTransfer indicated the encryption key location, 0 for
* non-encrypted
*
* @return
* - XST_SUCCESS if the transfer is successful
* - XST_FAILURE if the transfer fails
*
* @note None
*
****************************************************************************/
u32 PcapDataTransfer(u32 *SourceDataPtr, u32 *DestinationDataPtr,
u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
{
u32 Status;
u32 IntrStsReg;
u32 PcapTransferType = XDCFG_CONCURRENT_NONSEC_READ_WRITE;
/*
* Check for secure transfer
*/
if (SecureTransfer) {
PcapTransferType = XDCFG_CONCURRENT_SECURE_READ_WRITE;
}
#ifdef FSBL_PERF
XTime tXferCur = 0;
FsblGetGlobalTime(&tXferCur);
#endif
/*
* Clear the PCAP status registers
*/
Status = ClearPcapStatus();
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
return XST_FAILURE;
}
#ifdef XPAR_XWDTPS_0_BASEADDR
/*
* Prevent WDT reset
*/
XWdtPs_RestartWdt(&Watchdog);
#endif
/*
* PCAP single DMA transfer setup
*/
SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
/*
* Transfer using Device Configuration
*/
Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
SourceLength,
(u8 *)DestinationDataPtr,
DestinationLength, PcapTransferType);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
return XST_FAILURE;
}
/*
* Dump the PCAP registers
*/
PcapDumpRegisters();
/*
* Poll for the DMA done
*/
Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
return XST_FAILURE;
}
fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
/*
* Check for errors
*/
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
return XST_FAILURE;
}
/*
* For Performance measurement
*/
#ifdef FSBL_PERF
XTime tXferEnd = 0;
fsbl_printf(DEBUG_GENERAL,"Time taken is ");
FsblMeasurePerfTime(tXferCur,tXferEnd);
#endif
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function loads PL partition using PCAP
*
* @param SourceDataPtr is a pointer to where the data is read from
* @param DestinationDataPtr is a pointer to where the data is written to
* @param SourceLength is the length of the data to be moved in words
* @param DestinationLength is the length of the data to be moved in words
* @param SecureTransfer indicated the encryption key location, 0 for
* non-encrypted
*
* @return
* - XST_SUCCESS if the transfer is successful
* - XST_FAILURE if the transfer fails
*
* @note None
*
****************************************************************************/
u32 PcapLoadPartition(u32 *SourceDataPtr, u32 *DestinationDataPtr,
u32 SourceLength, u32 DestinationLength, u32 SecureTransfer)
{
u32 Status;
u32 IntrStsReg;
u32 PcapTransferType = XDCFG_NON_SECURE_PCAP_WRITE;
/*
* Check for secure transfer
*/
if (SecureTransfer) {
PcapTransferType = XDCFG_SECURE_PCAP_WRITE;
}
#ifdef FSBL_PERF
XTime tXferCur = 0;
FsblGetGlobalTime(&tXferCur);
#endif
/*
* Clear the PCAP status registers
*/
Status = ClearPcapStatus();
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n");
return XST_FAILURE;
}
/*
* For Bitstream case destination address will be 0xFFFFFFFF
*/
DestinationDataPtr = (u32*)XDCFG_DMA_INVALID_ADDRESS;
/*
* New Bitstream download initialization sequence
*/
Status = FabricInit();
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#ifdef XPAR_XWDTPS_0_BASEADDR
/*
* Prevent WDT reset
*/
XWdtPs_RestartWdt(&Watchdog);
#endif
/*
* PCAP single DMA transfer setup
*/
SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER);
DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER);
/*
* Transfer using Device Configuration
*/
Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr,
SourceLength,
(u8 *)DestinationDataPtr,
DestinationLength, PcapTransferType);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status);
return XST_FAILURE;
}
/*
* Dump the PCAP registers
*/
PcapDumpRegisters();
/*
* Poll for the DMA done
*/
Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n");
return XST_FAILURE;
}
fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r");
/*
* Poll for FPGA Done
*/
Status = XDcfgPollDone(XDCFG_IXR_PCFG_DONE_MASK, MAX_COUNT);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO,"PCAP_FPGA_DONE_FAIL\r\n");
return XST_FAILURE;
}
fsbl_printf(DEBUG_INFO,"FPGA Done ! \n\r");
/*
* Check for errors
*/
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n");
return XST_FAILURE;
}
/*
* For Performance measurement
*/
#ifdef FSBL_PERF
XTime tXferEnd = 0;
fsbl_printf(DEBUG_GENERAL,"Time taken is ");
FsblMeasurePerfTime(tXferCur,tXferEnd);
#endif
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function Initializes the PCAP driver.
*
* @param none
*
* @return
* - XST_SUCCESS if the pcap driver initialization is successful
* - XST_FAILURE if the pcap driver initialization fails
*
* @note none
*
****************************************************************************/
int InitPcap(void)
{
XDcfg_Config *ConfigPtr;
int Status = XST_SUCCESS;
DcfgInstPtr = &DcfgInstance;
/*
* Initialize the Device Configuration Interface driver.
*/
ConfigPtr = XDcfg_LookupConfig(DCFG_DEVICE_ID);
Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr,
ConfigPtr->BaseAddr);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO, "XDcfg_CfgInitialize failed \n\r");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function programs the Fabric for use.
*
* @param None
*
* @return
* - XST_SUCCESS if the Fabric initialization is successful
* - XST_FAILURE if the Fabric initialization fails
* @note None
*
****************************************************************************/
u32 FabricInit(void)
{
u32 PcapReg;
u32 PcapCtrlRegVal;
u32 StatusReg;
u32 MctrlReg;
u32 PcfgInit;
u32 TimerExpired=0;
XTime tCur=0;
XTime tEnd=0;
/*
* Set Level Shifters DT618760 - PS to PL enabling
*/
Xil_Out32(PS_LVL_SHFTR_EN, LVL_PS_PL);
fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%lx \r\n",
Xil_In32(PS_LVL_SHFTR_EN));
/*
* Get DEVCFG controller settings
*/
PcapReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr,
XDCFG_CTRL_OFFSET);
/*
* Check the PL power status
*/
if(Silicon_Version >= SILICON_VERSION_3)
{
MctrlReg = XDcfg_GetMiscControlRegister(DcfgInstPtr);
if((MctrlReg & XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK) !=
XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK)
{
fsbl_printf(DEBUG_INFO,"Fabric not powered up\r\n");
return XST_FAILURE;
}
}
/*
* Setting PCFG_PROG_B signal to high
*/
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
/*
* Check for AES source key
*/
PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
/*
* 5msec delay
*/
usleep(5000);
}
/*
* Setting PCFG_PROG_B signal to low
*/
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
/*
* Check for AES source key
*/
if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
/*
* 5msec delay
*/
usleep(5000);
}
/*
* Polling the PCAP_INIT status for Reset or timeout
*/
XTime_GetTime(&tCur);
do
{
PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) &
XDCFG_STATUS_PCFG_INIT_MASK);
if(PcfgInit == 0)
{
break;
}
XTime_GetTime(&tEnd);
if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd)
{
TimerExpired = 1;
}
} while(!TimerExpired);
if(TimerExpired == 1)
{
TimerExpired = 0;
/*
* Came here due to expiration and PCAP_INIT is set.
* Retry PCFG_PROG_B High -> Low again
*/
/*
* Setting PCFG_PROG_B signal to high
*/
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
/*
* Check for AES source key
*/
PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr);
if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
/*
* 5msec delay
*/
usleep(5000);
}
/*
* Setting PCFG_PROG_B signal to low
*/
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK));
/*
* Check for AES source key
*/
if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) {
/*
* 5msec delay
*/
usleep(5000);
}
/*
* Polling the PCAP_INIT status for Reset or timeout (second iteration)
*/
XTime_GetTime(&tCur);
do
{
PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) &
XDCFG_STATUS_PCFG_INIT_MASK);
if(PcfgInit == 0)
{
break;
}
XTime_GetTime(&tEnd);
if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd)
{
TimerExpired = 1;
}
} while(!TimerExpired);
if(TimerExpired == 1)
{
/*
* Came here due to PCAP_INIT is not getting reset
* for PCFG_PROG_B signal High -> Low
*/
fsbl_printf(DEBUG_INFO,"Fabric Init failed\r\n");
return XST_FAILURE;
}
}
/*
* Setting PCFG_PROG_B signal to high
*/
XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET,
(PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK));
/*
* Polling the PCAP_INIT status for Set
*/
while(!(XDcfg_GetStatusRegister(DcfgInstPtr) &
XDCFG_STATUS_PCFG_INIT_MASK));
/*
* Get Device configuration status
*/
StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%lx \r\n",StatusReg);
fsbl_printf(DEBUG_INFO,"PCAP:Fabric is Initialized done\r\n");
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function Clears the PCAP status registers.
*
* @param None
*
* @return
* - XST_SUCCESS if the pcap status registers are cleared
* - XST_FAILURE if errors are there
* - XST_DEVICE_BUSY if Pcap device is busy
* @note None
*
****************************************************************************/
u32 ClearPcapStatus(void)
{
u32 StatusReg;
u32 IntStatusReg;
/*
* Clear it all, so if Boot ROM comes back, it can proceed
*/
XDcfg_IntrClear(DcfgInstPtr, 0xFFFFFFFF);
/*
* Get PCAP Interrupt Status Register
*/
IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
if (IntStatusReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
IntStatusReg);
return XST_FAILURE;
}
/*
* Read the PCAP status register for DMA status
*/
StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr);
fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8lx\r\n", StatusReg);
/*
* If the queue is full, return w/ XST_DEVICE_BUSY
*/
if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) ==
XDCFG_STATUS_DMA_CMD_Q_F_MASK) {
fsbl_printf(DEBUG_INFO,"PCAP_DEVICE_BUSY\r\n");
return XST_DEVICE_BUSY;
}
fsbl_printf(DEBUG_INFO,"PCAP:device ready\r\n");
/*
* There are unacknowledged DMA commands outstanding
*/
if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_E_MASK) !=
XDCFG_STATUS_DMA_CMD_Q_E_MASK) {
IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr);
if ((IntStatusReg & XDCFG_IXR_DMA_DONE_MASK) !=
XDCFG_IXR_DMA_DONE_MASK){
/*
* Error state, transfer cannot occur
*/
fsbl_printf(DEBUG_INFO,"PCAP:IntStatus indicates error\r\n");
return XST_FAILURE;
}
else {
/*
* clear out the status
*/
XDcfg_IntrClear(DcfgInstPtr, XDCFG_IXR_DMA_DONE_MASK);
}
}
if ((StatusReg & XDCFG_STATUS_DMA_DONE_CNT_MASK) != 0) {
XDcfg_SetStatusRegister(DcfgInstPtr, StatusReg |
XDCFG_STATUS_DMA_DONE_CNT_MASK);
}
fsbl_printf(DEBUG_INFO,"PCAP:Clear done\r\n");
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function prints PCAP register status.
*
* @param none
*
* @return none
*
* @note none
*
****************************************************************************/
void PcapDumpRegisters (void) {
fsbl_printf(DEBUG_INFO,"PCAP register dump:\r\n");
fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET));
fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08lx\r\n",
XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET,
Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET));
}
/******************************************************************************/
/**
*
* This function Polls for the DMA done or FPGA done.
*
* @param none
*
* @return
* - XST_SUCCESS if polling for DMA/FPGA done is successful
* - XST_FAILURE if polling for DMA/FPGA done fails
*
* @note none
*
****************************************************************************/
int XDcfgPollDone(u32 MaskValue, u32 MaxCount)
{
int Count = MaxCount;
u32 IntrStsReg = 0;
/*
* poll for the DMA done
*/
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
while ((IntrStsReg & MaskValue) !=
MaskValue) {
IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr);
Count -=1;
if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) {
fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n",
IntrStsReg);
PcapDumpRegisters();
return XST_FAILURE;
}
if(!Count) {
fsbl_printf(DEBUG_GENERAL,"PCAP transfer timed out \r\n");
return XST_FAILURE;
}
if (Count > (MAX_COUNT-100)) {
fsbl_printf(DEBUG_GENERAL,".");
}
}
fsbl_printf(DEBUG_GENERAL,"\n\r");
XDcfg_IntrClear(DcfgInstPtr, IntrStsReg & MaskValue);
return XST_SUCCESS;
}
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/pcap.h
+89
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/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file pcap.h
*
* This file contains the interface for intiializing and accessing the PCAP
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 02/10/10 Initial release
* 2.00a mb 16/08/12 Added the macros and function prototypes
* 15.00a gan 07/21/16 953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
* Fabric Initialization sequence is modified to check
* the PL power before sequence starts and checking INIT_B
* reset status twice in case of failure.
* 21.2 ng 07/13/23 Add SDT support
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___PCAP_H___
#define ___PCAP_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xdevcfg.h"
#ifndef SDT
#include "xtime_l.h"
#else
#include "xiltimer.h"
#endif
/************************** Function Prototypes ******************************/
/* Multiboot register offset mask */
#define PCAP_MBOOT_REG_REBOOT_OFFSET_MASK 0x1FFF
#define PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK 0x1000
/*Miscellaneous Control Register mask*/
#define XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK 0x00000100
#define COUNTS_PER_MILLI_SECOND (COUNTS_PER_SECOND/1000)
#define PCAP_LAST_TRANSFER 1
#define MAX_COUNT 1000000000
#define LVL_PL_PS 0x0000000F
#define LVL_PS_PL 0x0000000A
/* Fix for #672779 */
#define FSBL_XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WERR_MASK | \
XDCFG_IXR_AXI_RTO_MASK | \
XDCFG_IXR_AXI_RERR_MASK | \
XDCFG_IXR_RX_FIFO_OV_MASK | \
XDCFG_IXR_DMA_CMD_ERR_MASK |\
XDCFG_IXR_DMA_Q_OV_MASK | \
XDCFG_IXR_P2D_LEN_ERR_MASK |\
XDCFG_IXR_PCFG_HMAC_ERR_MASK)
int InitPcap(void);
void PcapDumpRegisters(void);
u32 ClearPcapStatus(void);
u32 FabricInit(void);
int XDcfgPollDone(u32 MaskValue, u32 MaxCount);
u32 PcapLoadPartition(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
u32 DestinationLength, u32 Flags);
u32 PcapDataTransfer(u32 *SourceData, u32 *DestinationData, u32 SourceLength,
u32 DestinationLength, u32 Flags);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___PCAP_H___ */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/ps7_init.c
+10066
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Vitis_Classic/NewInstCal_bsp/zynq_fsbl/ps7_init.h
+117
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@@ -0,0 +1,117 @@
/******************************************************************************
*
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/ps7_parameters.xml
+643
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@@ -0,0 +1,643 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
<designInfo version="1.0" >
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
<PARAMETERS >
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="666.666666" />
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="MIO 16 .. 27" />
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="MIO 52 .. 53" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="8" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="" />
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="0" />
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="5" />
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="2" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE" />
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" />
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" />
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="33" />
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="" />
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="" />
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="30" />
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1000.000" />
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="in" />
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled" />
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="" />
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out" />
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="" />
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="" />
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="" />
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="5" />
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
<PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 3.3V" />
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 1.8V" />
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="MIO 8" />
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="MIO 1 .. 6" />
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="7" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="150" />
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="MIO 47" />
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="MIO 46" />
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="MIO 40 .. 45" />
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="20" />
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="x4" />
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="" />
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="" />
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="MIO 48 .. 49" />
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="10" />
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.25" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.25" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.25" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.25" />
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="32 Bit" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="139.2255" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="139.2255" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="139.2255" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="139.2255" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="101.3165" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="120.42" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="121.0875" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="142.1405" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="105.3065" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="126.177" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="129.083" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="148.0365" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" />
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" />
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41K256M16 RE-125" />
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15" />
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.75" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="" />
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="" />
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="" />
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
</PARAMETERS>
<BUSINTERFACES >
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
</BUSINTERFACES>
<CLOCKOUTS >
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="100.000000" />
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="10.000000" />
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" />
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" />
</CLOCKOUTS>
</MODULE>
</designInfo>
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/qspi.c
+870
View File
@@ -0,0 +1,870 @@
/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023, Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file qspi.c
*
* Contains code for the QSPI FLASH functionality.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 01/10/10 Initial release
* 3.00a mb 25/06/12 InitQspi, data is read first and required config bits
* are set
* 4.00a sg 02/28/13 Cleanup
* Removed LPBK_DLY_ADJ register setting code as we use
* divisor 8
* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
* Dual Stack support
* Fix for CR:721674 - FSBL- Failed to boot from Dual
* stacked QSPI
* 6.00a kc 08/30/13 Fix for CR#722979 - Provide customer-friendly
* changelogs in FSBL
* Fix for CR#739711 - FSBL not able to read Large QSPI
* (512M) in IO Mode
* 7.00a kc 10/25/13 Fix for CR#739968 - FSBL should do the QSPI config
* settings for Dual parallel
* configuration in IO mode
* 14.0 gan 01/13/16 Fix for CR#869081 - (2016.1)FSBL picks the qspi read
* command from LQSPI_CFG register
* instead of hard coded read
* command (0x6B).
* 15.0 bsv 09/04/20 Add support for 2Gb flash parts
* 21.1 ng 07/13/23 Add SDT support
* 21.2 ng 07/25/23 Updated QSPI address support in SDT flow
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "qspi.h"
#include "image_mover.h"
#if defined(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR) || defined(XPAR_PS7_QSPI_LINEAR_0_BASEADDR)
#include "xqspips_hw.h"
#include "xqspips.h"
/************************** Constant Definitions *****************************/
/*
* The following constants map to the XPAR parameters created in the
* xparameters.h file. They are defined here such that a user can easily
* change all the needed parameters in one place.
*/
#ifndef SDT
#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_DEVICE_ID
#define QSPI_CONNECTION_MODE (XPAR_XQSPIPS_0_QSPI_MODE)
#define QSPI_BUS_WIDTH (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH)
#else
#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_BASEADDR
#define QSPI_CONNECTION_MODE (XPAR_XQSPIPS_0_CONNECTION_MODE)
#define QSPI_BUS_WIDTH (XPAR_XQSPIPS_0_QSPI_BUS_WIDTH)
#endif
/*
* The following constants define the commands which may be sent to the FLASH
* device.
*/
#define QUAD_READ_CMD 0x6B
#define READ_ID_CMD 0x9F
#define WRITE_ENABLE_CMD 0x06
#define BANK_REG_RD 0x16
#define BANK_REG_WR 0x17
/* Bank register is called Extended Address Reg in Micron */
#define EXTADD_REG_RD 0xC8
#define EXTADD_REG_WR 0xC5
#define COMMAND_OFFSET 0 /* FLASH instruction */
#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */
#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */
#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */
#define DATA_OFFSET 4 /* Start of Data for Read/Write */
#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad
reads */
#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and
quad reads */
#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */
#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank value */
#define WRITE_ENABLE_CMD_SIZE 1 /* WE command */
/*
* The following constants specify the extra bytes which are sent to the
* FLASH on the QSPI interface, that are not data, but control information
* which includes the command and address
*/
#define OVERHEAD_SIZE 4
/*
* The following constants specify the max amount of data and the size of the
* the buffer required to hold the data and overhead to transfer the data to
* and from the FLASH.
*/
#define DATA_SIZE 4096
/*
* The following defines are for dual flash interface.
*/
#define LQSPI_CR_FAST_READ 0x0000000B
#define LQSPI_CR_FAST_DUAL_READ 0x0000003B
#define LQSPI_CR_FAST_QUAD_READ 0x0000006B /* Fast Quad Read output */
#define LQSPI_CR_1_DUMMY_BYTE 0x00000100 /* 1 Dummy Byte between
address and return data */
#define SINGLE_QSPI_CONFIG_FAST_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_READ)
#define SINGLE_QSPI_CONFIG_FAST_DUAL_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_DUAL_READ)
#define SINGLE_QSPI_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_READ)
#define DUAL_QSPI_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \
XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_READ)
#define DUAL_STACK_CONFIG_FAST_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_READ)
#define DUAL_STACK_CONFIG_FAST_DUAL_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_DUAL_READ)
#define DUAL_STACK_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_READ)
#define SINGLE_QSPI_IO_CONFIG_FAST_READ (LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_READ)
#define SINGLE_QSPI_IO_CONFIG_FAST_DUAL_READ (LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_DUAL_READ)
#define SINGLE_QSPI_IO_CONFIG_FAST_QUAD_READ (LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_READ)
#define DUAL_QSPI_IO_CONFIG_FAST_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \
XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \
LQSPI_CR_1_DUMMY_BYTE | \
LQSPI_CR_FAST_QUAD_READ)
#define QSPI_BUSWIDTH_ONE 0U
#define QSPI_BUSWIDTH_TWO 1U
#define QSPI_BUSWIDTH_FOUR 2U
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
XQspiPs QspiInstance;
XQspiPs *QspiInstancePtr;
u32 QspiFlashSize;
u32 QspiFlashMake;
extern u32 FlashReadBaseAddress;
extern u8 LinearBootDeviceFlag;
/*
* The following variables are used to read and write to the eeprom and they
* are global to avoid having large buffers on the stack
*/
u8 ReadBuffer[DATA_SIZE + DATA_OFFSET + DUMMY_SIZE];
u8 WriteBuffer[DATA_OFFSET + DUMMY_SIZE];
/******************************************************************************/
/**
*
* This function initializes the controller for the QSPI interface.
*
* @param None
*
* @return None
*
* @note None
*
****************************************************************************/
u32 InitQspi(void)
{
XQspiPs_Config *QspiConfig;
int Status;
u32 ConfigCmd;
QspiInstancePtr = &QspiInstance;
/*
* Set up the base address for access
*/
FlashReadBaseAddress = XPS_QSPI_LINEAR_BASEADDR;
/*
* Initialize the QSPI driver so that it's ready to use
*/
QspiConfig = XQspiPs_LookupConfig(QSPI_DEVICE_ID);
if (NULL == QspiConfig) {
return XST_FAILURE;
}
Status = XQspiPs_CfgInitialize(QspiInstancePtr, QspiConfig,
QspiConfig->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Set Manual Chip select options and drive HOLD_B pin high.
*/
XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_FORCE_SSELECT_OPTION |
XQSPIPS_HOLD_B_DRIVE_OPTION);
/*
* Set the prescaler for QSPI clock
*/
XQspiPs_SetClkPrescaler(QspiInstancePtr, XQSPIPS_CLK_PRESCALE_8);
/*
* Assert the FLASH chip select.
*/
XQspiPs_SetSlaveSelect(QspiInstancePtr);
/*
* Read Flash ID and extract Manufacture and Size information
*/
Status = FlashReadID();
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
if (QSPI_CONNECTION_MODE == SINGLE_FLASH_CONNECTION) {
fsbl_printf(DEBUG_INFO,"QSPI is in single flash connection\r\n");
/*
* For Flash size <128Mbit controller configured in linear mode
*/
if (QspiFlashSize <= FLASH_SIZE_16MB) {
LinearBootDeviceFlag = 1;
/*
* Enable linear mode
*/
XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
XQSPIPS_HOLD_B_DRIVE_OPTION);
switch (QSPI_BUS_WIDTH) {
case QSPI_BUSWIDTH_ONE:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
ConfigCmd = SINGLE_QSPI_CONFIG_FAST_READ;
}
break;
case QSPI_BUSWIDTH_TWO:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
ConfigCmd = SINGLE_QSPI_CONFIG_FAST_DUAL_READ;
}
break;
case QSPI_BUSWIDTH_FOUR:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
ConfigCmd = SINGLE_QSPI_CONFIG_FAST_QUAD_READ;
}
break;
}
/*
* Single linear read
*/
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
/*
* Enable the controller
*/
XQspiPs_Enable(QspiInstancePtr);
} else {
switch (QSPI_BUS_WIDTH) {
case QSPI_BUSWIDTH_ONE:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_READ;
}
break;
case QSPI_BUSWIDTH_TWO:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_DUAL_READ;
}
break;
case QSPI_BUSWIDTH_FOUR:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
ConfigCmd = SINGLE_QSPI_IO_CONFIG_FAST_QUAD_READ;
}
break;
}
/*
* Single flash IO read
*/
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
/*
* Enable the controller
*/
XQspiPs_Enable(QspiInstancePtr);
}
}
if (QSPI_CONNECTION_MODE == DUAL_PARALLEL_CONNECTION) {
fsbl_printf(DEBUG_INFO,"QSPI is in Dual Parallel connection\r\n");
/*
* For Single Flash size <128Mbit controller configured in linear mode
*/
if (QspiFlashSize <= FLASH_SIZE_16MB) {
/*
* Setting linear access flag
*/
LinearBootDeviceFlag = 1;
/*
* Enable linear mode
*/
XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION |
XQSPIPS_HOLD_B_DRIVE_OPTION);
/*
* Dual linear read
*/
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_CONFIG_FAST_QUAD_READ);
/*
* Enable the controller
*/
XQspiPs_Enable(QspiInstancePtr);
} else {
/*
* Dual flash IO read
*/
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_IO_CONFIG_FAST_QUAD_READ);
/*
* Enable the controller
*/
XQspiPs_Enable(QspiInstancePtr);
}
/*
* Total flash size is two time of single flash size
*/
QspiFlashSize = 2 * QspiFlashSize;
}
/*
* It is expected to same flash size for both chip selection
*/
if (QSPI_CONNECTION_MODE == DUAL_STACK_CONNECTION) {
fsbl_printf(DEBUG_INFO,"QSPI is in Dual Stack connection\r\n");
QspiFlashSize = 2 * QspiFlashSize;
/*
* Enable two flash memories on separate buses
*/
switch (QSPI_BUS_WIDTH) {
case QSPI_BUSWIDTH_ONE:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 1-bit mode\r\n");
ConfigCmd = DUAL_STACK_CONFIG_FAST_READ;
}
break;
case QSPI_BUSWIDTH_TWO:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 2-bit mode\r\n");
ConfigCmd = DUAL_STACK_CONFIG_FAST_DUAL_READ;
}
break;
case QSPI_BUSWIDTH_FOUR:
{
fsbl_printf(DEBUG_INFO,"QSPI is in 4-bit mode\r\n");
ConfigCmd = DUAL_STACK_CONFIG_FAST_QUAD_READ;
}
break;
}
XQspiPs_SetLqspiConfigReg(QspiInstancePtr, ConfigCmd);
}
return XST_SUCCESS;
}
/******************************************************************************
*
* This function reads serial FLASH ID connected to the SPI interface.
* It then deduces the make and size of the flash and obtains the
* connection mode to point to corresponding parameters in the flash
* configuration table. The flash driver will function based on this and
* it presently supports Micron and Spansion - 128, 256 and 512Mbit and
* Winbond 128Mbit
*
* @param none
*
* @return XST_SUCCESS if read id, otherwise XST_FAILURE.
*
* @note None.
*
******************************************************************************/
u32 FlashReadID(void)
{
u32 Status;
/*
* Read ID in Auto mode.
*/
WriteBuffer[COMMAND_OFFSET] = READ_ID_CMD;
WriteBuffer[ADDRESS_1_OFFSET] = 0x00; /* 3 dummy bytes */
WriteBuffer[ADDRESS_2_OFFSET] = 0x00;
WriteBuffer[ADDRESS_3_OFFSET] = 0x00;
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
RD_ID_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
fsbl_printf(DEBUG_INFO,"Single Flash Information\r\n");
fsbl_printf(DEBUG_INFO,"FlashID=0x%x 0x%x 0x%x\r\n", ReadBuffer[1],
ReadBuffer[2],
ReadBuffer[3]);
/*
* Deduce flash make
*/
if (ReadBuffer[1] == MICRON_ID) {
QspiFlashMake = MICRON_ID;
fsbl_printf(DEBUG_INFO, "MICRON ");
} else if(ReadBuffer[1] == SPANSION_ID) {
QspiFlashMake = SPANSION_ID;
fsbl_printf(DEBUG_INFO, "SPANSION ");
} else if(ReadBuffer[1] == WINBOND_ID) {
QspiFlashMake = WINBOND_ID;
fsbl_printf(DEBUG_INFO, "WINBOND ");
} else if(ReadBuffer[1] == MACRONIX_ID) {
QspiFlashMake = MACRONIX_ID;
fsbl_printf(DEBUG_INFO, "MACRONIX ");
} else if(ReadBuffer[1] == ISSI_ID) {
QspiFlashMake = ISSI_ID;
fsbl_printf(DEBUG_INFO, "ISSI ");
}
/*
* Deduce flash Size
*/
if (ReadBuffer[3] == FLASH_SIZE_ID_8M) {
QspiFlashSize = FLASH_SIZE_8M;
fsbl_printf(DEBUG_INFO, "8M Bits\r\n");
} else if (ReadBuffer[3] == FLASH_SIZE_ID_16M) {
QspiFlashSize = FLASH_SIZE_16M;
fsbl_printf(DEBUG_INFO, "16M Bits\r\n");
} else if (ReadBuffer[3] == FLASH_SIZE_ID_32M) {
QspiFlashSize = FLASH_SIZE_32M;
fsbl_printf(DEBUG_INFO, "32M Bits\r\n");
} else if (ReadBuffer[3] == FLASH_SIZE_ID_64M) {
QspiFlashSize = FLASH_SIZE_64M;
fsbl_printf(DEBUG_INFO, "64M Bits\r\n");
} else if (ReadBuffer[3] == FLASH_SIZE_ID_128M) {
QspiFlashSize = FLASH_SIZE_128M;
fsbl_printf(DEBUG_INFO, "128M Bits\r\n");
} else if (ReadBuffer[3] == FLASH_SIZE_ID_256M) {
QspiFlashSize = FLASH_SIZE_256M;
fsbl_printf(DEBUG_INFO, "256M Bits\r\n");
} else if ((ReadBuffer[3] == FLASH_SIZE_ID_512M)
|| (ReadBuffer[3] == MACRONIX_FLASH_1_8_V_MX66_ID_512)
|| (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_512M)) {
QspiFlashSize = FLASH_SIZE_512M;
fsbl_printf(DEBUG_INFO, "512M Bits\r\n");
} else if ((ReadBuffer[3] == FLASH_SIZE_ID_1G)
|| (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_1G)) {
QspiFlashSize = FLASH_SIZE_1G;
fsbl_printf(DEBUG_INFO, "1G Bits\r\n");
} else if ((ReadBuffer[3] == FLASH_SIZE_ID_2G)
|| (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_2G)) {
QspiFlashSize = FLASH_SIZE_2G;
fsbl_printf(DEBUG_INFO, "2G Bits\r\n");
}
return XST_SUCCESS;
}
/******************************************************************************
*
* This function reads from the serial FLASH connected to the
* QSPI interface.
*
* @param Address contains the address to read data from in the FLASH.
* @param ByteCount contains the number of bytes to read.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void FlashRead(u32 Address, u32 ByteCount)
{
/*
* Setup the write command with the specified address and data for the
* FLASH
*/
u32 LqspiCrReg;
u8 ReadCommand;
LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
ReadCommand = (u8) (LqspiCrReg & XQSPIPS_LQSPI_CR_INST_MASK);
WriteBuffer[COMMAND_OFFSET] = ReadCommand;
WriteBuffer[ADDRESS_1_OFFSET] = (u8)((Address & 0xFF0000) >> 16);
WriteBuffer[ADDRESS_2_OFFSET] = (u8)((Address & 0xFF00) >> 8);
WriteBuffer[ADDRESS_3_OFFSET] = (u8)(Address & 0xFF);
ByteCount += DUMMY_SIZE;
/*
* Send the read command to the FLASH to read the specified number
* of bytes from the FLASH, send the read command and address and
* receive the specified number of bytes of data in the data buffer
*/
XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
ByteCount + OVERHEAD_SIZE);
}
/******************************************************************************/
/**
*
* This function provides the QSPI FLASH interface for the Simplified header
* functionality.
*
* @param SourceAddress is address in FLASH data space
* @param DestinationAddress is address in DDR data space
* @param LengthBytes is the length of the data in Bytes
*
* @return
* - XST_SUCCESS if the write completes correctly
* - XST_FAILURE if the write fails to completes correctly
*
* @note none.
*
****************************************************************************/
u32 QspiAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
{
u8 *BufferPtr;
u32 Length = 0;
u32 BankSel = 0;
u32 LqspiCrReg;
u32 Status;
u8 BankSwitchFlag = 1;
/*
* Linear access check
*/
if (LinearBootDeviceFlag == 1) {
/*
* Check for non-word tail, add bytes to cover the end
*/
if ((LengthBytes%4) != 0){
LengthBytes += (4 - (LengthBytes & 0x00000003));
}
memcpy((void*)DestinationAddress,
(const void*)(SourceAddress + FlashReadBaseAddress),
(size_t)LengthBytes);
} else {
/*
* Non Linear access
*/
BufferPtr = (u8*)DestinationAddress;
/*
* Dual parallel connection actual flash is half
*/
if (QSPI_CONNECTION_MODE == DUAL_PARALLEL_CONNECTION) {
SourceAddress = SourceAddress/2;
}
while(LengthBytes > 0) {
/*
* Local of DATA_SIZE size used for read/write buffer
*/
if(LengthBytes > DATA_SIZE) {
Length = DATA_SIZE;
} else {
Length = LengthBytes;
}
/*
* Dual stack connection
*/
if (QSPI_CONNECTION_MODE == DUAL_STACK_CONNECTION) {
/*
* Get the current LQSPI configuration value
*/
LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr);
/*
* Select lower or upper Flash based on sector address
*/
if (SourceAddress >= (QspiFlashSize/2)) {
/*
* Set selection to U_PAGE
*/
XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
LqspiCrReg | XQSPIPS_LQSPI_CR_U_PAGE_MASK);
/*
* Subtract first flash size when accessing second flash
*/
SourceAddress = SourceAddress - (QspiFlashSize/2);
fsbl_printf(DEBUG_INFO, "stacked - upper CS \n\r");
/*
* Assert the FLASH chip select.
*/
XQspiPs_SetSlaveSelect(QspiInstancePtr);
}
}
/*
* Select bank
*/
if ((SourceAddress >= FLASH_SIZE_16MB) && (BankSwitchFlag == 1)) {
BankSel = SourceAddress/FLASH_SIZE_16MB;
fsbl_printf(DEBUG_INFO, "Bank Selection %lu\n\r", BankSel);
Status = SendBankSelect(BankSel);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO, "Bank Selection Failed\n\r");
return XST_FAILURE;
}
BankSwitchFlag = 0;
}
/*
* If data to be read spans beyond the current bank, then
* calculate length in current bank else no change in length
*/
if (QSPI_CONNECTION_MODE == DUAL_PARALLEL_CONNECTION) {
/*
* In dual parallel mode, check should be for half
* the length.
*/
if((SourceAddress & BANKMASK) != ((SourceAddress + (Length/2)) & BANKMASK))
{
Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
/*
* Above length calculated is for single flash
* Length should be doubled since dual parallel
*/
Length = Length * 2;
BankSwitchFlag = 1;
}
} else {
if((SourceAddress & BANKMASK) != ((SourceAddress + Length) & BANKMASK))
{
Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress;
BankSwitchFlag = 1;
}
}
/*
* Copying the image to local buffer
*/
FlashRead(SourceAddress, Length);
/*
* Moving the data from local buffer to DDR destination address
*/
memcpy(BufferPtr, &ReadBuffer[DATA_OFFSET + DUMMY_SIZE], Length);
/*
* Updated the variables
*/
LengthBytes -= Length;
/*
* For Dual parallel connection address increment should be half
*/
if (QSPI_CONNECTION_MODE == DUAL_PARALLEL_CONNECTION) {
SourceAddress += Length/2;
} else {
SourceAddress += Length;
}
BufferPtr = (u8*)((u32)BufferPtr + Length);
}
/*
* Reset Bank selection to zero
*/
Status = SendBankSelect(0);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO, "Bank Selection Reset Failed\n\r");
return XST_FAILURE;
}
if (QSPI_CONNECTION_MODE == DUAL_STACK_CONNECTION) {
/*
* Reset selection to L_PAGE
*/
XQspiPs_SetLqspiConfigReg(QspiInstancePtr,
LqspiCrReg & (~XQSPIPS_LQSPI_CR_U_PAGE_MASK));
fsbl_printf(DEBUG_INFO, "stacked - lower CS \n\r");
/*
* Assert the FLASH chip select.
*/
XQspiPs_SetSlaveSelect(QspiInstancePtr);
}
}
return XST_SUCCESS;
}
/******************************************************************************
*
* This functions selects the current bank
*
* @param BankSel is the bank to be selected in the flash device(s).
*
* @return XST_SUCCESS if bank selected
* XST_FAILURE if selection failed
* @note None.
*
******************************************************************************/
u32 SendBankSelect(u8 BankSel)
{
u32 Status;
/*
* bank select commands for Micron and Spansion are different
* Macronix bank select is same as Micron
*/
if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) {
/*
* For micron command WREN should be sent first
* except for some specific feature set
*/
WriteBuffer[COMMAND_OFFSET] = WRITE_ENABLE_CMD;
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
WRITE_ENABLE_CMD_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Send the Extended address register write command
* written, no receive buffer required
*/
WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_WR;
WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
BANK_SEL_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
if (QspiFlashMake == SPANSION_ID) {
WriteBuffer[COMMAND_OFFSET] = BANK_REG_WR;
WriteBuffer[ADDRESS_1_OFFSET] = BankSel;
/*
* Send the Extended address register write command
* written, no receive buffer required
*/
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL,
BANK_SEL_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
/*
* For testing - Read bank to verify
*/
if (QspiFlashMake == SPANSION_ID) {
WriteBuffer[COMMAND_OFFSET] = BANK_REG_RD;
WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
/*
* Send the Extended address register write command
* written, no receive buffer required
*/
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
BANK_SEL_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) {
WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_RD;
WriteBuffer[ADDRESS_1_OFFSET] = 0x00;
/*
* Send the Extended address register write command
* written, no receive buffer required
*/
Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer,
BANK_SEL_SIZE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
if (ReadBuffer[1] != BankSel) {
fsbl_printf(DEBUG_INFO, "BankSel %d != Register Read %d\n\r", BankSel,
ReadBuffer[1]);
return XST_FAILURE;
}
return XST_SUCCESS;
}
#endif
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/qspi.h
+115
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@@ -0,0 +1,115 @@
/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file qspi.h
*
* This file contains the interface for the QSPI FLASH functionality
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a ecm 01/10/10 Initial release
* 3.00a mb 01/09/12 Added the Delay Values defines for qspi
* 5.00a sgd 05/17/13 Added Flash Size > 128Mbit support
* Dual Stack support
* 6.00a bsv 09/04/20 Added support for 2Gb flash parts
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___QSPI_H___
#define ___QSPI_H___
#include "fsbl.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "fsbl.h"
/************************** Constant Definitions *****************************/
#define SINGLE_FLASH_CONNECTION 0
#define DUAL_STACK_CONNECTION 1
#define DUAL_PARALLEL_CONNECTION 2
#define FLASH_SIZE_16MB 0x1000000
/*
* Bank mask
*/
#define BANKMASK 0xF000000
/*
* Identification of Flash
* Micron:
* Byte 0 is Manufacturer ID;
* Byte 1 is first byte of Device ID - 0xBB or 0xBA
* Byte 2 is second byte of Device ID describes flash size:
* 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
* Spansion:
* Byte 0 is Manufacturer ID;
* Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02
* Byte 2 is second byte of Device ID describes flash size:
* 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20
*/
#define MICRON_ID 0x20
#define SPANSION_ID 0x01
#define WINBOND_ID 0xEF
#define MACRONIX_ID 0xC2
#define ISSI_ID 0x9D
#define FLASH_SIZE_ID_8M 0x14
#define FLASH_SIZE_ID_16M 0x15
#define FLASH_SIZE_ID_32M 0x16
#define FLASH_SIZE_ID_64M 0x17
#define FLASH_SIZE_ID_128M 0x18
#define FLASH_SIZE_ID_256M 0x19
#define FLASH_SIZE_ID_512M 0x20
#define FLASH_SIZE_ID_1G 0x21
#define FLASH_SIZE_ID_2G 0x22
/* Macronix size constants are different for 512M and 1G */
#define MACRONIX_FLASH_SIZE_ID_512M 0x1A
#define MACRONIX_FLASH_SIZE_ID_1G 0x1B
#define MACRONIX_FLASH_SIZE_ID_2G 0x1C
#define MACRONIX_FLASH_1_8_V_MX66_ID_512 (0x3A)
/*
* Size in bytes
*/
#define FLASH_SIZE_8M 0x0100000
#define FLASH_SIZE_16M 0x0200000
#define FLASH_SIZE_32M 0x0400000
#define FLASH_SIZE_64M 0x0800000
#define FLASH_SIZE_128M 0x1000000
#define FLASH_SIZE_256M 0x2000000
#define FLASH_SIZE_512M 0x4000000
#define FLASH_SIZE_1G 0x8000000
#define FLASH_SIZE_2G 0x10000000
/************************** Function Prototypes ******************************/
u32 InitQspi(void);
u32 QspiAccess( u32 SourceAddress,
u32 DestinationAddress,
u32 LengthBytes);
u32 FlashReadID(void);
u32 SendBankSelect(u8 BankSel);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___QSPI_H___ */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/rsa.c
+330
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/******************************************************************************
* Copyright (c) 2012 - 2022 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file rsa.c
*
* Contains code for the RSA authentication
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.00a sgd 02/28/13 Initial release
* 6.00a kc 07/30/13 Added FSBL_DEBUG_RSA to print more RSA buffers
* Fix for CR#724165 - Partition Header used by FSBL is
* not authenticated
* Fix for CR#724166 - FSBL doesn’t use PPK authenticated
* by Boot ROM for authenticating
* the Partition images
* Fix for CR#722979 - Provide customer-friendly
* changelogs in FSBL
* 9.00a kc 04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
* fallback unless FSBL* and FSBL are
* identical in length
* Fix for CR#791245 - Use of xilrsa in FSBL
* 10.0 vns 03/18/22 Fixed CR#1125470 to authenticate the parition header buffer
* which is being used instead of one from DDR. Modified
* prototype of AuthenticatePartition() API
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#ifdef RSA_SUPPORT
#include "fsbl.h"
#include "rsa.h"
#include "xilrsa.h"
#ifdef XPAR_XWDTPS_0_BASEADDR
#include "xwdtps.h"
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
#ifdef XPAR_XWDTPS_0_BASEADDR
extern XWdtPs Watchdog; /* Instance of WatchDog Timer */
#endif
/************************** Variable Definitions *****************************/
static u8 *PpkModular;
static u8 *PpkModularEx;
static u32 PpkExp;
static u32 PpkAlreadySet=0;
extern u32 FsblLength;
void FsblPrintArray (u8 *Buf, u32 Len, char *Str)
{
#ifdef FSBL_DEBUG_RSA
int Index;
fsbl_printf(DEBUG_INFO, "%s START\r\n", Str);
for (Index=0;Index<Len;Index++)
{
fsbl_printf(DEBUG_INFO, "%02x",Buf[Index]);
if ((Index+1)%16 == 0){
fsbl_printf(DEBUG_INFO, "\r\n");
}
}
fsbl_printf(DEBUG_INFO, "\r\n %s END\r\n",Str);
#endif
return;
}
/*****************************************************************************/
/**
*
* This function is used to set ppk pointer to ppk in OCM
*
* @param None
*
* @return
*
* @note None
*
******************************************************************************/
void SetPpk(void )
{
u32 PadSize;
u8 *PpkPtr;
/*
* Set PPK only if is not already set
*/
if(PpkAlreadySet == 0)
{
/*
* Set PpkPtr to PPK in OCM
*/
/*
* Skip FSBL Length
*/
PpkPtr = (u8 *)(FsblLength);
/*
* Skip to 64 byte Boundary
*/
PadSize = ((u32)PpkPtr % 64);
if(PadSize != 0)
{
PpkPtr += (64 - PadSize);
}
/*
* Increment the pointer by authentication Header size
*/
PpkPtr += RSA_HEADER_SIZE;
/*
* Increment the pointer by Magic word size
*/
PpkPtr += RSA_MAGIC_WORD_SIZE;
/*
* Set pointer to PPK
*/
PpkModular = (u8 *)PpkPtr;
PpkPtr += RSA_PPK_MODULAR_SIZE;
PpkModularEx = (u8 *)PpkPtr;
PpkPtr += RSA_PPK_MODULAR_EXT_SIZE;
PpkExp = *((u32 *)PpkPtr);
/*
* Setting variable to avoid resetting PPK pointers
*/
PpkAlreadySet=1;
}
return;
}
/*****************************************************************************/
/**
*
* This function Authenticate Partition Signature
*
* @param AC is the pointer to authentication certificate
* @param Hash is the pointer which holds the SHA2 digest of data
* to be authenticated.
*
* @return
* - XST_SUCCESS if Authentication passed
* - XST_FAILURE if Authentication failed
*
* @note None
*
******************************************************************************/
u32 AuthenticatePartition(u8 *Ac, u8* Hash)
{
u8 DecryptSignature[256];
u8 HashSignature[32];
u8 *SpkModular;
u8 *SpkModularEx;
u32 SpkExp;
u8 *SignaturePtr;
u32 Status;
#ifdef XPAR_XWDTPS_0_BASEADDR
/*
* Prevent WDT reset
*/
XWdtPs_RestartWdt(&Watchdog);
#endif
/*
* Point to Authentication Certificate
*/
SignaturePtr = (u8 *)Ac;
/*
* Increment the pointer by authentication Header size
*/
SignaturePtr += RSA_HEADER_SIZE;
/*
* Increment the pointer by Magic word size
*/
SignaturePtr += RSA_MAGIC_WORD_SIZE;
/*
* Increment the pointer beyond the PPK
*/
SignaturePtr += RSA_PPK_MODULAR_SIZE;
SignaturePtr += RSA_PPK_MODULAR_EXT_SIZE;
SignaturePtr += RSA_PPK_EXPO_SIZE;
/*
* Calculate Hash Signature
*/
sha_256((u8 *)SignaturePtr, (RSA_SPK_MODULAR_EXT_SIZE +
RSA_SPK_EXPO_SIZE + RSA_SPK_MODULAR_SIZE),
HashSignature);
FsblPrintArray(HashSignature, 32, "SPK Hash Calculated");
/*
* Extract SPK signature
*/
SpkModular = (u8 *)SignaturePtr;
SignaturePtr += RSA_SPK_MODULAR_SIZE;
SpkModularEx = (u8 *)SignaturePtr;
SignaturePtr += RSA_SPK_MODULAR_EXT_SIZE;
SpkExp = *((u32 *)SignaturePtr);
SignaturePtr += RSA_SPK_EXPO_SIZE;
/*
* Decrypt SPK Signature
*/
rsa2048_pubexp((RSA_NUMBER)DecryptSignature,
(RSA_NUMBER)SignaturePtr,
(u32)PpkExp,
(RSA_NUMBER)PpkModular,
(RSA_NUMBER)PpkModularEx);
FsblPrintArray(DecryptSignature, RSA_SPK_SIGNATURE_SIZE,
"SPK Decrypted Hash");
Status = RecreatePaddingAndCheck(DecryptSignature, HashSignature);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO, "Partition SPK Signature "
"Authentication failed\r\n");
return XST_FAILURE;
}
SignaturePtr += RSA_SPK_SIGNATURE_SIZE;
/*
* Decrypt Partition Signature
*/
rsa2048_pubexp((RSA_NUMBER)DecryptSignature,
(RSA_NUMBER)SignaturePtr,
(u32)SpkExp,
(RSA_NUMBER)SpkModular,
(RSA_NUMBER)SpkModularEx);
FsblPrintArray(DecryptSignature, RSA_PARTITION_SIGNATURE_SIZE,
"Partition Decrypted Hash");
Status = RecreatePaddingAndCheck(DecryptSignature, Hash);
if (Status != XST_SUCCESS) {
fsbl_printf(DEBUG_INFO, "Partition Signature "
"Authentication failed\r\n");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/*****************************************************************************/
/**
*
* This function recreates the and check signature
*
* @param Partition signature
* @param Partition hash value which includes boot header, partition data
* @return
* - XST_SUCCESS if check passed
* - XST_FAILURE if check failed
*
* @note None
*
******************************************************************************/
u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash)
{
u8 T_padding[] = {0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48,
0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20 };
u8 * pad_ptr = signature + 256;
u32 pad = 256 - 3 - 19 - 32;
u32 ii;
/*
* Re-Create PKCS#1v1.5 Padding
* MSB ----------------------------------------------------LSB
* 0x0 || 0x1 || 0xFF(for 202 bytes) || 0x0 || T_padding || SHA256 Hash
*/
if (*--pad_ptr != 0x00 || *--pad_ptr != 0x01) {
return XST_FAILURE;
}
for (ii = 0; ii < pad; ii++) {
if (*--pad_ptr != 0xFF) {
return XST_FAILURE;
}
}
if (*--pad_ptr != 0x00) {
return XST_FAILURE;
}
for (ii = 0; ii < sizeof(T_padding); ii++) {
if (*--pad_ptr != T_padding[ii]) {
return XST_FAILURE;
}
}
for (ii = 0; ii < 32; ii++) {
if (*--pad_ptr != hash[ii])
return XST_FAILURE;
}
return XST_SUCCESS;
}
#endif
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/rsa.h
+55
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@@ -0,0 +1,55 @@
/******************************************************************************
* Copyright (c) 2012 - 2022 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file rsa.h
*
* This file contains the RSA algorithm functions
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 4.00a sg 02/28/13 Initial release
* 5.0 vns 03/18/22 Modified prototype of AuthenticatePartition() API
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___RSA_H___
#define ___RSA_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#define RSA_PPK_MODULAR_SIZE 256
#define RSA_PPK_MODULAR_EXT_SIZE 256
#define RSA_PPK_EXPO_SIZE 64
#define RSA_SPK_MODULAR_SIZE 256
#define RSA_SPK_MODULAR_EXT_SIZE 256
#define RSA_SPK_EXPO_SIZE 64
#define RSA_SPK_SIGNATURE_SIZE 256
#define RSA_PARTITION_SIGNATURE_SIZE 256
#define RSA_SIGNATURE_SIZE 0x6C0 /* Signature size in bytes */
#define RSA_HEADER_SIZE 4 /* Signature header size in bytes */
#define RSA_MAGIC_WORD_SIZE 60 /* Magic word size in bytes */
void SetPpk(void );
u32 AuthenticatePartition(u8 *Ac, u8 *Hash);
u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash);
#ifdef __cplusplus
}
#endif
#endif /* ___RSA_H___ */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/sd.c
+165
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@@ -0,0 +1,165 @@
/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file sd.c
*
* Contains code for the SD card FLASH functionality.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a jz 04/28/11 Initial release
* 7.00a kc 10/18/13 Integrated SD/MMC driver
* 12.00a ssc 12/11/14 Fix for CR# 839182
*
* </pre>
*
* @note
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "fsbl.h"
#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
#ifndef XPAR_PS7_SD_0_S_AXI_BASEADDR
#define XPAR_PS7_SD_0_S_AXI_BASEADDR XPAR_XSDPS_0_BASEADDR
#endif
#include "xstatus.h"
#include "ff.h"
#include "sd.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Variable Definitions *****************************/
extern u32 FlashReadBaseAddress;
static FIL fil; /* File object */
static FATFS fatfs;
static char buffer[32];
static char *boot_file = buffer;
/******************************************************************************/
/******************************************************************************/
/**
*
* This function initializes the controller for the SD FLASH interface.
*
* @param filename of the file that is to be used
*
* @return
* - XST_SUCCESS if the controller initializes correctly
* - XST_FAILURE if the controller fails to initializes correctly
*
* @note None.
*
****************************************************************************/
u32 InitSD(const char *filename)
{
FRESULT rc;
TCHAR *path = "0:/"; /* Logical drive number is 0 */
/* Register volume work area, initialize device */
rc = f_mount(&fatfs, path, 0);
fsbl_printf(DEBUG_INFO,"SD: rc= %.8x\n\r", rc);
if (rc != FR_OK) {
return XST_FAILURE;
}
strcpy_rom(buffer, filename);
boot_file = (char *)buffer;
FlashReadBaseAddress = XPAR_PS7_SD_0_S_AXI_BASEADDR;
rc = f_open(&fil, boot_file, FA_READ);
if (rc) {
fsbl_printf(DEBUG_GENERAL,"SD: Unable to open file %s: %d\n", boot_file, rc);
return XST_FAILURE;
}
return XST_SUCCESS;
}
/******************************************************************************/
/**
*
* This function provides the SD FLASH interface for the Simplified header
* functionality.
*
* @param SourceAddress is address in FLASH data space
* @param DestinationAddress is address in OCM data space
* @param LengthBytes is the number of bytes to move
*
* @return
* - XST_SUCCESS if the write completes correctly
* - XST_FAILURE if the write fails to completes correctly
*
* @note None.
*
****************************************************************************/
u32 SDAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes)
{
FRESULT rc; /* Result code */
UINT br;
rc = f_lseek(&fil, SourceAddress);
if (rc) {
fsbl_printf(DEBUG_INFO,"SD: Unable to seek to %lx\n", SourceAddress);
return XST_FAILURE;
}
rc = f_read(&fil, (void*)DestinationAddress, LengthBytes, &br);
if (rc) {
fsbl_printf(DEBUG_GENERAL,"*** ERROR: f_read returned %d\r\n", rc);
}
return XST_SUCCESS;
} /* End of SDAccess */
/******************************************************************************/
/**
*
* This function closes the file object
*
* @param None
*
* @return None.
*
* @note None.
*
****************************************************************************/
void ReleaseSD(void) {
f_close(&fil);
return;
}
#endif
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/sd.h
+53
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@@ -0,0 +1,53 @@
/******************************************************************************
* Copyright (c) 2012 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file sd.h
*
* This file contains the interface for the Secure Digital (SD) card
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a bh 03/10/11 Initial release
* 7.00a kc 10/18/13 Integrated SD/MMC driver
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___SD_H___
#define ___SD_H___
#ifdef __cplusplus
extern "C" {
#endif
/************************** Function Prototypes ******************************/
#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR)
u32 InitSD(const char *);
u32 SDAccess( u32 SourceAddress,
u32 DestinationAddress,
u32 LengthWords);
void ReleaseSD(void);
#endif
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* ___SD_H___ */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/Makefile
+49
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# Makefile generated by Xilinx.
DRIVER_LIB_VERSION = 1.0
PROCESSOR = ps7_cortexa9_0
LIBRARIES = ${PROCESSOR}/lib/libxil.a
BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
BSP_SEQUENTIAL_MAKEFILES := ps7_cortexa9_0/libsrc/xilrsa_v1_7/src/Makefile
BSP_PARALLEL_MAKEFILES := $(filter-out $(BSP_SEQUENTIAL_MAKEFILES),$(BSP_MAKEFILES))
SEQ_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_SEQUENTIAL_MAKEFILES))
PAR_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_PARALLEL_MAKEFILES))
ifneq (,$(findstring win,$(RDI_PLATFORM)))
SHELL = CMD
endif
all:
$(MAKE) --no-print-directory seq_libs
$(MAKE) -j 30 --no-print-directory par_libs
$(MAKE) --no-print-directory archive
@echo 'Finished building libraries'
include: $(addsuffix /make.include,$(SUBDIRS))
seq_libs: $(addsuffix /make.libs,$(SEQ_SUBDIRS))
@echo 'Finished building libraries sequentially.'
par_libs: $(addsuffix /make.libs,$(PAR_SUBDIRS))
@echo 'Finished building libraries parallelly.'
archive:
arm-none-eabi-ar -r $(LIBRARIES) $(sort $(wildcard $(PROCESSOR)/lib/*.o))
clean: $(addsuffix /make.clean,$(SUBDIRS))
rm -f ${PROCESSOR}/lib/libxil.a
$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
cp -f $< $@
%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
@echo "Running Make include in $(subst /make.include,,$@)"
$(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
%/make.libs: include
@echo "Running Make libs in $(subst /make.libs,,$@)"
$(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns"
%/make.clean:
$(MAKE) -C $(subst /make.clean,,$@) -s clean
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/dep.mk
+3
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@@ -0,0 +1,3 @@
# generated by Xilinx.
DEPENDENCY_FLAGS= -MMD -MP
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h
+281
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@@ -0,0 +1,281 @@
/******************************************************************************
* Copyright (c) 2004 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef PROFILE_TIMER_HW_H
#define PROFILE_TIMER_HW_H
#include "profile.h"
#ifdef PROC_PPC
#if defined __GNUC__
# define SYNCHRONIZE_IO __asm__ volatile ("eieio")
#elif defined __DCC__
# define SYNCHRONIZE_IO __asm volatile(" eieio")
#else
# define SYNCHRONIZE_IO
#endif
#endif
#ifdef PROC_PPC
#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
#else
#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
#endif
#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \
(u32)(RegOffset)), (u32)(ValueToWrite))
#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \
ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \
(RegisterValue))
#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \
ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
#ifdef __cplusplus
extern "C" {
#endif
#ifdef PROC_PPC
#include "xexception_l.h"
#include "xtime_l.h"
#include "xpseudo_asm.h"
#endif
#ifdef TIMER_CONNECT_INTC
#include "xintc_l.h"
#include "xintc.h"
#endif /* TIMER_CONNECT_INTC */
#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
#include "xtmrctr_l.h"
#endif
#ifdef PROC_CORTEXA9
#include "xscutimer_hw.h"
#include "xscugic.h"
#endif
extern u32 timer_clk_ticks ;
/*--------------------------------------------------------------------
* PowerPC Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_PPC
#ifdef PPC_PIT_INTERRUPT
u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */
#endif
#ifdef PROC_PPC440
#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
#define XREG_SPR_PIT XREG_SPR_DEC
#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
#endif
/* --------------------------------------------------------------------
* Disable the Timer - During Profiling
*
* For PIT Timer -
* 1. XTime_PITDisableInterrupt() ;
* 2. Store the remaining timer clk tick
* 3. Stop the PIT Timer
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
#define disable_timer() \
{ \
u32 val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \
timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \
mtspr(XREG_SPR_PIT, 0); \
}
#else
#define disable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
/* --------------------------------------------------------------------
* Enable the Timer
*
* For PIT Timer -
* 1. Load the remaining timer clk ticks
* 2. XTime_PITEnableInterrupt() ;
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
#define enable_timer() \
{ \
u32 val; \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \
mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
}
#else
#define enable_timer() \
{ \
u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(addr); \
tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
}
#endif
/* --------------------------------------------------------------------
* Send Ack to Timer Interrupt
*
* For PIT Timer -
* 1. Load the timer clk ticks
* 2. Enable AutoReload and Interrupt
* 3. Clear PIT Timer Status bits
*-------------------------------------------------------------------- */
#ifdef PPC_PIT_INTERRUPT
#define timer_ack() \
{ \
u32 val; \
mtspr(XREG_SPR_PIT, timer_clk_ticks); \
mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \
val=mfspr(XREG_SPR_TCR); \
mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
}
#else
#define timer_ack() \
{ \
u32 csr; \
csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \
ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \
}
#endif
/*-------------------------------------------------------------------- */
#endif /* PROC_PPC */
/* -------------------------------------------------------------------- */
/* --------------------------------------------------------------------
* MicroBlaze Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_MICROBLAZE
/* --------------------------------------------------------------------
* Disable the Timer during Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define disable_timer() \
{ \
u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
Addr += (u32)XTC_TCSR_OFFSET; \
u32 tmp_v = ProfIo_In32(Addr); \
tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
OutAddr += (u32)XTC_TCSR_OFFSET; \
ProfIo_Out32(OutAddr, (u32)tmp_v); \
}
/* --------------------------------------------------------------------
* Enable the Timer after Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define enable_timer() \
{ \
u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
Addr += (u32)XTC_TCSR_OFFSET; \
u32 tmp_v = (u32)ProfIo_In32(Addr); \
tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \
ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
}
/* --------------------------------------------------------------------
* Send Ack to Timer Interrupt
*
*-------------------------------------------------------------------- */
#define timer_ack() \
{ \
u32 csr; \
csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \
ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \
}
/*-------------------------------------------------------------------- */
#endif /* PROC_MICROBLAZE */
/*-------------------------------------------------------------------- */
/* --------------------------------------------------------------------
* Cortex A9 Target - Timer related functions
*-------------------------------------------------------------------- */
#ifdef PROC_CORTEXA9
/* --------------------------------------------------------------------
* Disable the Timer during Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define disable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
}
/* --------------------------------------------------------------------
* Enable the Timer after Call-Graph Data collection
*
*-------------------------------------------------------------------- */
#define enable_timer() \
{ \
u32 Reg; \
Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
}
/* --------------------------------------------------------------------
* Send Ack to Timer Interrupt
*
*-------------------------------------------------------------------- */
#define timer_ack() \
{ \
Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
(u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
}
/*-------------------------------------------------------------------- */
#endif /* PROC_CORTEXA9 */
/*-------------------------------------------------------------------- */
#ifdef __cplusplus
}
#endif
#endif
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/bspconfig.h
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/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version: 2023.2
* DO NOT EDIT.
*
* Copyright (C) 2010-2026 Xilinx, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*
* Description: Configurations for Standalone BSP
*
*******************************************************************/
#ifndef BSPCONFIG_H /* prevent circular inclusions */
#define BSPCONFIG_H /* by using protection macros */
#define MICROBLAZE_PVR_NONE
/* Definition for hard-float ABI */
#define FPU_HARD_FLOAT_ABI_ENABLED 1
#endif /*end of __BSPCONFIG_H_*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/diskio.h
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/*-----------------------------------------------------------------------/
/ Low level disk interface modlue include file (C)ChaN, 2022 /
/-----------------------------------------------------------------------*/
#ifndef _DISKIO_DEFINED
#define _DISKIO_DEFINED
#ifdef __cplusplus
extern "C" {
#endif
#define USE_WRITE 1 /* 1: Enable disk_write function */
#define USE_IOCTL 1 /* 1: Enable disk_ioctl function */
#include "ff.h"
#include "xil_types.h"
/* Status of Disk Functions */
typedef BYTE DSTATUS;
/* Results of Disk Functions */
typedef enum {
RES_OK = 0, /* 0: Successful */
RES_ERROR, /* 1: R/W Error */
RES_WRPRT, /* 2: Write Protected */
RES_NOTRDY, /* 3: Not Ready */
RES_PARERR /* 4: Invalid Parameter */
} DRESULT;
/*---------------------------------------*/
/* Prototypes for disk control functions */
DSTATUS disk_initialize (BYTE pdrv);
DSTATUS disk_status (BYTE pdrv);
DRESULT disk_read (BYTE pdrv, BYTE* buff, LBA_t sector, UINT count);
DRESULT disk_write (BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count);
DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
/* Disk Status Bits (DSTATUS) */
#define STA_NOINIT 0x01U /* Drive not initialized */
#define STA_NODISK 0x02U /* No medium in the drive */
#define STA_PROTECT 0x04U /* Write protected */
/* Command code for disk_ioctrl fucntion */
/* Generic command (Used by FatFs) */
#define CTRL_SYNC 0U /* Complete pending write process (needed at FF_FS_READONLY == 0) */
#define GET_SECTOR_COUNT 1U /* Get media size (needed at FF_USE_MKFS == 1) */
#define GET_SECTOR_SIZE 2U /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
#define GET_BLOCK_SIZE 3U /* Get erase block size (needed at FF_USE_MKFS == 1) */
#define CTRL_TRIM 4U /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
/* Generic command (Not used by FatFs) */
#define CTRL_POWER 5U /* Get/Set power status */
#define CTRL_LOCK 6U /* Lock/Unlock media removal */
#define CTRL_EJECT 7U /* Eject media */
#define CTRL_FORMAT 8U /* Create physical format on the media */
/* MMC/SDC specific ioctl command */
#define MMC_GET_TYPE 10U /* Get card type */
#define MMC_GET_CSD 11U /* Get CSD */
#define MMC_GET_CID 12U /* Get CID */
#define MMC_GET_OCR 13U /* Get OCR */
#define MMC_GET_SDSTAT 14U /* Get SD status */
#define ISDIO_READ 55 /* Read data form SD iSDIO register */
#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */
#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */
/* ATA/CF specific ioctl command */
#define ATA_GET_REV 20U /* Get F/W revision */
#define ATA_GET_MODEL 21U /* Get model name */
#define ATA_GET_SN 22U /* Get serial number */
#ifdef __cplusplus
}
#endif
#endif
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/ff.h
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/*----------------------------------------------------------------------------/
/ FatFs - Generic FAT Filesystem module R0.15 /
/-----------------------------------------------------------------------------/
/
/ Copyright (C) 2022, ChaN, all right reserved.
/
/ FatFs module is an open source software. Redistribution and use of FatFs in
/ source and binary forms, with or without modification, are permitted provided
/ that the following condition is met:
/ 1. Redistributions of source code must retain the above copyright notice,
/ this condition and the following disclaimer.
/
/ This software is provided by the copyright holder and contributors "AS IS"
/ and any warranties related to this software are DISCLAIMED.
/ The copyright owner or contributors be NOT LIABLE for any damages caused
/ by use of this software.
/
/----------------------------------------------------------------------------*/
#ifndef FF_DEFINED
#define FF_DEFINED 80286 /* Revision ID */
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_types.h"
#include "ffconf.h" /* FatFs configuration options */
#if FF_DEFINED != FFCONF_DEF
#error Wrong configuration file (ffconf.h).
#endif
/* Integer types used for FatFs API */
#if defined(_WIN32) /* Windows VC++ (for development only) */
#define FF_INTDEF 2
#include <windows.h>
typedef unsigned __int64 QWORD;
#include <float.h>
#define isnan(v) _isnan(v)
#define isinf(v) (!_finite(v))
#elif (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || defined(__cplusplus) /* C99 or later */
#define FF_INTDEF 2
#include <stdint.h>
typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
typedef unsigned char BYTE; /* char must be 8-bit */
typedef uint16_t WORD; /* 16-bit unsigned integer */
typedef uint32_t DWORD; /* 32-bit unsigned integer */
typedef uint64_t QWORD; /* 64-bit unsigned integer */
typedef WORD WCHAR; /* UTF-16 character type */
#else /* Earlier than C99 */
#define FF_INTDEF 1
typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
typedef unsigned char BYTE; /* char must be 8-bit */
typedef unsigned short WORD; /* 16-bit unsigned integer */
typedef unsigned long DWORD; /* 32-bit unsigned integer */
typedef WORD WCHAR; /* UTF-16 character type */
#endif
/* Type of file size and LBA variables */
#if FF_FS_EXFAT
#if FF_INTDEF != 2
#error exFAT feature wants C99 or later
#endif
typedef QWORD FSIZE_t;
#if FF_LBA64
typedef QWORD LBA_t;
#else
typedef DWORD LBA_t;
#endif
#else
#if FF_LBA64
#error exFAT needs to be enabled when enable 64-bit LBA
#endif
typedef DWORD FSIZE_t;
typedef DWORD LBA_t;
#endif
/* Type of path name strings on FatFs API (TCHAR) */
#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
typedef WCHAR TCHAR;
#define _T(x) L ## x
#define _TEXT(x) L ## x
#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
typedef char TCHAR;
#define _T(x) u8 ## x
#define _TEXT(x) u8 ## x
#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
typedef DWORD TCHAR;
#define _T(x) U ## x
#define _TEXT(x) U ## x
#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
#error Wrong FF_LFN_UNICODE setting
#else /* ANSI/OEM code in SBCS/DBCS */
typedef char TCHAR;
#define _T(x) x
#define _TEXT(x) x
#endif
/* Definitions of volume management */
#if FF_MULTI_PARTITION /* Multiple partition configuration */
typedef struct {
BYTE pd; /* Physical drive number */
BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
} PARTITION;
extern PARTITION VolToPart[]; /* Volume - Partition mapping table */
#endif
#if FF_STR_VOLUME_ID
#ifndef FF_VOLUME_STRS
extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
#endif
#endif
/* Filesystem object structure (FATFS) */
typedef struct {
BYTE fs_type; /* Filesystem type (0:not mounted) */
BYTE pdrv; /* Volume hosting physical drive */
BYTE ldrv; /* Logical drive number (used only when FF_FS_REENTRANT) */
BYTE n_fats; /* Number of FATs (1 or 2) */
BYTE wflag; /* win[] status (b0:dirty) */
BYTE fsi_flag; /* FSINFO status (b7:disabled, b0:dirty) */
WORD id; /* Volume mount ID */
WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
WORD csize; /* Cluster size [sectors] */
#if FF_MAX_SS != FF_MIN_SS
WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
#endif
#if FF_USE_LFN
WCHAR* lfnbuf; /* LFN working buffer */
#endif
#if FF_FS_EXFAT
BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
#endif
#if !FF_FS_READONLY
DWORD last_clst; /* Last allocated cluster */
DWORD free_clst; /* Number of free clusters */
#endif
#if FF_FS_RPATH
DWORD cdir; /* Current directory start cluster (0:root) */
#if FF_FS_EXFAT
DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
#endif
#endif
DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
DWORD fsize; /* Number of sectors per FAT */
LBA_t volbase; /* Volume base sector */
LBA_t fatbase; /* FAT base sector */
LBA_t dirbase; /* Root directory base sector (FAT12/16) or cluster (FAT32/exFAT) */
LBA_t database; /* Data base sector */
#if FF_FS_EXFAT
LBA_t bitbase; /* Allocation bitmap base sector */
#endif
LBA_t winsect; /* Current sector appearing in the win[] */
#ifdef __ICCARM__
#pragma data_alignment = 32
BYTE win[FF_MAX_SS];
#else
#ifdef __aarch64__
BYTE win[FF_MAX_SS] __attribute__ ((aligned(64))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
#else
BYTE win[FF_MAX_SS] __attribute__ ((aligned(32))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */
#endif
#endif
} FATFS;
/* Object ID and allocation information (FFOBJID) */
typedef struct {
FATFS* fs; /* Pointer to the hosting volume of this object */
WORD id; /* Hosting volume's mount ID */
BYTE attr; /* Object attribute */
BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:fragmented in this session, b2:sub-directory stretched) */
DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
FSIZE_t objsize; /* Object size (valid when sclust != 0) */
#if FF_FS_EXFAT
DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
#endif
#if FF_FS_LOCK
UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
#endif
} FFOBJID;
/* File object structure (FIL) */
typedef struct {
FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
BYTE flag; /* File status flags */
BYTE err; /* Abort flag (error code) */
FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
LBA_t sect; /* Sector number appearing in buf[] (0:invalid) */
#if !FF_FS_READONLY
LBA_t dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
#endif
#if FF_USE_FASTSEEK
DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
#endif
#if !FF_FS_TINY
#ifdef __ICCARM__
#pragma data_alignment = 32
BYTE buf[FF_MAX_SS]; /* File private data read/write window */
#else
#ifdef __aarch64__
BYTE buf[FF_MAX_SS] __attribute__ ((aligned(64))); /* File private data read/write window */
#else
BYTE buf[FF_MAX_SS] __attribute__ ((aligned(32))); /* File private data read/write window */
#endif
#endif
#endif
} FIL;
/* Directory object structure (DIR) */
typedef struct {
FFOBJID obj; /* Object identifier */
DWORD dptr; /* Current read/write offset */
DWORD clust; /* Current cluster */
LBA_t sect; /* Current sector (0:Read operation has terminated) */
BYTE* dir; /* Pointer to the directory item in the win[] */
BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
#if FF_USE_LFN
DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
#endif
#if FF_USE_FIND
const TCHAR* pat; /* Pointer to the name matching pattern */
#endif
} DIR;
/* File information structure (FILINFO) */
typedef struct {
FSIZE_t fsize; /* File size */
WORD fdate; /* Modified date */
WORD ftime; /* Modified time */
BYTE fattrib; /* File attribute */
#if FF_USE_LFN
TCHAR altname[FF_SFN_BUF + 1];/* Alternative file name */
TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
#else
TCHAR fname[12 + 1]; /* File name */
#endif
} FILINFO;
/* Format parameter structure (MKFS_PARM) */
typedef struct {
BYTE fmt; /* Format option (FM_FAT, FM_FAT32, FM_EXFAT and FM_SFD) */
BYTE n_fat; /* Number of FATs */
UINT align; /* Data area alignment (sector) */
UINT n_root; /* Number of root directory entries */
DWORD au_size; /* Cluster size (byte) */
} MKFS_PARM;
/* File function return code (FRESULT) */
typedef enum {
FR_OK = 0, /* (0) Succeeded */
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
FR_INT_ERR, /* (2) Assertion failed */
FR_NOT_READY, /* (3) The physical drive cannot work */
FR_NO_FILE, /* (4) Could not find the file */
FR_NO_PATH, /* (5) Could not find the path */
FR_INVALID_NAME, /* (6) The path name format is invalid */
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
FR_EXIST, /* (8) Access denied due to prohibited access */
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
FR_NOT_ENABLED, /* (12) The volume has no work area */
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
} FRESULT;
/*--------------------------------------------------------------*/
/* FatFs Module Application Interface */
/*--------------------------------------------------------------*/
FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
FRESULT f_close (FIL* fp); /* Close an open file object */
FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
FRESULT f_truncate (FIL* fp); /* Truncate the file */
FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
FRESULT f_closedir (DIR* dp); /* Close an open directory */
FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
FRESULT f_chdir (const TCHAR* path); /* Change current directory */
FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt); /* Allocate a contiguous block to the file */
FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len); /* Create a FAT volume */
FRESULT f_fdisk (BYTE pdrv, const LBA_t ptbl[], void* work); /* Divide a physical drive into some partitions */
FRESULT f_setcp (WORD cp); /* Set current code page */
int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
/* Some API fucntions are implemented as macro */
#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
#define f_error(fp) ((fp)->err)
#define f_tell(fp) ((fp)->fptr)
#define f_size(fp) ((fp)->obj.objsize)
#define f_rewind(fp) f_lseek((fp), 0)
#define f_rewinddir(dp) f_readdir((dp), 0)
#define f_rmdir(path) f_unlink(path)
#define f_unmount(path) f_mount(0, path, 0)
/*--------------------------------------------------------------*/
/* Additional Functions */
/*--------------------------------------------------------------*/
/* RTC function (provided by user) */
#if !FF_FS_READONLY && !FF_FS_NORTC
DWORD get_fattime (void); /* Get current time */
#endif
/* LFN support functions (defined in ffunicode.c) */
#if FF_USE_LFN >= 1
WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
#endif
/* O/S dependent functions (samples available in ffsystem.c) */
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
void* ff_memalloc (UINT msize); /* Allocate memory block */
void ff_memfree (void* mblock); /* Free memory block */
#endif
#if FF_FS_REENTRANT /* Sync functions */
int ff_mutex_create (int vol); /* Create a sync object */
void ff_mutex_delete (int vol); /* Delete a sync object */
int ff_mutex_take (int vol); /* Lock sync object */
void ff_mutex_give (int vol); /* Unlock sync object */
#endif
/*--------------------------------------------------------------*/
/* Flags and Offset Address */
/*--------------------------------------------------------------*/
/* File access mode and open method flags (3rd argument of f_open) */
#define FA_READ 0x01
#define FA_WRITE 0x02
#define FA_OPEN_EXISTING 0x00
#define FA_CREATE_NEW 0x04
#define FA_CREATE_ALWAYS 0x08
#define FA_OPEN_ALWAYS 0x10
#define FA_OPEN_APPEND 0x30
/* Fast seek controls (2nd argument of f_lseek) */
#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
/* Format options (2nd argument of f_mkfs) */
#define FM_FAT 0x01
#define FM_FAT32 0x02
#define FM_EXFAT 0x04
#define FM_ANY 0x07
#define FM_SFD 0x08
/* Filesystem type (FATFS.fs_type) */
#define FS_FAT12 1
#define FS_FAT16 2
#define FS_FAT32 3
#define FS_EXFAT 4
/* File attribute bits for directory entry (FILINFO.fattrib) */
#define AM_RDO 0x01 /* Read only */
#define AM_HID 0x02 /* Hidden */
#define AM_SYS 0x04 /* System */
#define AM_DIR 0x10 /* Directory */
#define AM_ARC 0x20 /* Archive */
#ifdef __cplusplus
}
#endif
#endif /* FF_DEFINED */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/ffconf.h
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/*---------------------------------------------------------------------------/
/ Configurations of FatFs Module
/---------------------------------------------------------------------------*/
#define FFCONF_DEF 80286 /* Revision ID */
#ifdef __cplusplus
extern "C" {
#endif
#ifdef SDT
#include "xilffs_config.h"
#else
#include "xparameters.h"
#endif
/*---------------------------------------------------------------------------/
/ Function Configurations
/---------------------------------------------------------------------------*/
#ifdef FILE_SYSTEM_READ_ONLY
#define FF_FS_READONLY 1 /* 1:Read only */
#else
#define FF_FS_READONLY 0 /* 0:Read/Write */
#endif
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
/ and optional writing functions as well. */
#define FF_FS_MINIMIZE 0
/* This option defines minimization level to remove some basic API functions.
/
/ 0: Basic functions are fully enabled.
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
/ are removed.
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
/ 3: f_lseek() function is removed in addition to 2. */
#if FILE_SYSTEM_USE_STRFUNC == 0
#define FF_USE_STRFUNC 0 /* 0:Disable */
#elif FILE_SYSTEM_USE_STRFUNC == 1
#define FF_USE_STRFUNC 1 /* 1:Enable */
#elif FILE_SYSTEM_USE_STRFUNC == 2
#define FF_USE_STRFUNC 2 /* 2:Enable */
#endif
/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
/
/ 0: Disable string functions.
/ 1: Enable without LF-CRLF conversion.
/ 2: Enable with LF-CRLF conversion. */
#define FF_USE_FIND 0
/* This option switches filtered directory read functions, f_findfirst() and
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
#ifdef FILE_SYSTEM_USE_MKFS
#define FF_USE_MKFS 1 /* 1:Enable */
#else
#define FF_USE_MKFS 0 /* 0:Disable */
#endif
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
#define FF_USE_FASTSEEK 0
/* This option switches fast seek function. (0:Disable or 1:Enable) */
#define FF_USE_EXPAND 0
/* This option switches f_expand function. (0:Disable or 1:Enable) */
#ifdef FILE_SYSTEM_USE_CHMOD
#define FF_USE_CHMOD 1 /* 1:Enable */
#else
#define FF_USE_CHMOD 0 /* 0:Disable */
#endif
/* This option switches attribute manipulation functions, f_chmod() and f_utime().
/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
#define FF_USE_LABEL 0
/* This option switches volume label functions, f_getlabel() and f_setlabel().
/ (0:Disable or 1:Enable) */
#define FF_USE_FORWARD 0
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
#define FF_USE_STRFUNC 0
#define FF_PRINT_LLI 1
#define FF_PRINT_FLOAT 1
#define FF_STRF_ENCODE 3
/* FF_USE_STRFUNC switches string functions, f_gets(), f_putc(), f_puts() and
/ f_printf().
/
/ 0: Disable. FF_PRINT_LLI, FF_PRINT_FLOAT and FF_STRF_ENCODE have no effect.
/ 1: Enable without LF-CRLF conversion.
/ 2: Enable with LF-CRLF conversion.
/
/ FF_PRINT_LLI = 1 makes f_printf() support long long argument and FF_PRINT_FLOAT = 1/2
/ makes f_printf() support floating point argument. These features want C99 or later.
/ When FF_LFN_UNICODE >= 1 with LFN enabled, string functions convert the character
/ encoding in it. FF_STRF_ENCODE selects assumption of character encoding ON THE FILE
/ to be read/written via those functions.
/
/ 0: ANSI/OEM in current CP
/ 1: Unicode in UTF-16LE
/ 2: Unicode in UTF-16BE
/ 3: Unicode in UTF-8
*/
/*---------------------------------------------------------------------------/
/ Locale and Namespace Configurations
/---------------------------------------------------------------------------*/
#define FF_CODE_PAGE 932
/* This option specifies the OEM code page to be used on the target system.
/ Incorrect code page setting can cause a file open failure.
/
/ 437 - U.S.
/ 720 - Arabic
/ 737 - Greek
/ 771 - KBL
/ 775 - Baltic
/ 850 - Latin 1
/ 852 - Latin 2
/ 855 - Cyrillic
/ 857 - Turkish
/ 860 - Portuguese
/ 861 - Icelandic
/ 862 - Hebrew
/ 863 - Canadian French
/ 864 - Arabic
/ 865 - Nordic
/ 866 - Russian
/ 869 - Greek 2
/ 932 - Japanese (DBCS)
/ 936 - Simplified Chinese (DBCS)
/ 949 - Korean (DBCS)
/ 950 - Traditional Chinese (DBCS)
/ 0 - Include all code pages above and configured by f_setcp()
*/
#ifdef FILE_SYSTEM_USE_LFN
#define FF_USE_LFN FILE_SYSTEM_USE_LFN /* 0 to 3 */
#else
#define FF_USE_LFN 0 /* 0 to 3 */
#endif
#define FF_MAX_LFN 255
/* The FF_USE_LFN switches the support for LFN (long file name).
/
/ 0: Disable LFN. FF_MAX_LFN has no effect.
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
/ 2: Enable LFN with dynamic working buffer on the STACK.
/ 3: Enable LFN with dynamic working buffer on the HEAP.
/
/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
/ be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN
/ specification.
/ When use stack for the working buffer, take care on stack overflow. When use heap
/ memory for the working buffer, memory management functions, ff_memalloc() and
/ ff_memfree() exemplified in ffsystem.c, need to be added to the project. */
#define FF_LFN_UNICODE 0
/* This option switches the character encoding on the API when LFN is enabled.
/
/ 0: ANSI/OEM in current CP (TCHAR = char)
/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
/ 2: Unicode in UTF-8 (TCHAR = char)
/ 3: Unicode in UTF-32 (TCHAR = DWORD)
/
/ Also behavior of string I/O functions will be affected by this option.
/ When LFN is not enabled, this option has no effect. */
#define FF_LFN_BUF 255
#define FF_SFN_BUF 12
/* This set of options defines size of file name members in the FILINFO structure
/ which is used to read out directory items. These values should be suffcient for
/ the file names to read. The maximum possible length of the read file name depends
/ on character encoding. When LFN is not enabled, these options have no effect. */
#if FILE_SYSTEM_SET_FS_RPATH == 0
#define FF_FS_RPATH 0U
#elif FILE_SYSTEM_SET_FS_RPATH == 1
#define FF_FS_RPATH 1U
#elif FILE_SYSTEM_SET_FS_RPATH == 2
#define FF_FS_RPATH 2U
#endif
/* This option configures support for relative path.
/
/ 0: Disable relative path and remove related functions.
/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
/ 2: f_getcwd() function is available in addition to 1.
*/
/*---------------------------------------------------------------------------/
/ Drive/Volume Configurations
/---------------------------------------------------------------------------*/
#if FILE_SYSTEM_NUM_LOGIC_VOL == 1
#define FF_VOLUMES 1U
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 2
#define FF_VOLUMES 2U
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 3
#define FF_VOLUMES 3U
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 4
#define FF_VOLUMES 4U
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 5
#define FF_VOLUMES 5U
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 6
#define FF_VOLUMES 6U
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 7
#define FF_VOLUMES 7U
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 8
#define FF_VOLUMES 8U
#elif FILE_SYSTEM_NUM_LOGIC_VOL == 9
#define FF_VOLUMES 9U
#else
#define FF_VOLUMES 10U
#endif
/* Number of volumes (logical drives) to be used. (1-10) */
#define FF_STR_VOLUME_ID 0
#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
/ not defined, a user defined volume string table is needed as:
/
/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
*/
#ifdef FILE_SYSTEM_MULTI_PARTITION
#define FF_MULTI_PARTITION 1 /* 1:Enable multiple partition */
#else
#define FF_MULTI_PARTITION 0 /* 0:Single partition */
#endif
/* This option switches support for multiple volumes on the physical drive.
/ By default (0), each logical drive number is bound to the same physical drive
/ number and only an FAT volume found on the physical drive will be mounted.
/ When this function is enabled (1), each logical drive number can be bound to
/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
/ function will be available. */
#define FF_MIN_SS 512
#define FF_MAX_SS 512
/* This set of options configures the range of sector size to be supported. (512,
/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
/ harddisk, but a larger value may be required for on-board flash memory and some
/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
/ for variable sector size mode and disk_ioctl() function needs to implement
/ GET_SECTOR_SIZE command. */
#define FF_LBA64 0
/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable)
/ To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */
#define FF_MIN_GPT 0x10000000
/* Minimum number of sectors to switch GPT as partitioning format in f_mkfs and
/ f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */
#ifdef FILE_SYSTEM_USE_TRIM
#define FF_USE_TRIM 1
#else
#define FF_USE_TRIM 0
#endif
/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
/ To enable Trim function, also CTRL_TRIM command should be implemented to the
/ disk_ioctl() function. */
/*---------------------------------------------------------------------------/
/ System Configurations
/---------------------------------------------------------------------------*/
#define FF_FS_TINY 0
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
/ Instead of private sector buffer eliminated from the file object, common sector
/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
#ifdef FILE_SYSTEM_FS_EXFAT
#define FF_FS_EXFAT 1
#else
#define FF_FS_EXFAT 0
#endif
/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
#define FF_FS_NORTC 0
#define FF_NORTC_MON 1
#define FF_NORTC_MDAY 1
#define FF_NORTC_YEAR 2022
/* The option FF_FS_NORTC switches timestamp feature. If the system does not have
/ an RTC or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable the
/ timestamp feature. Every object modified by FatFs will have a fixed timestamp
/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
/ added to the project to read current time form real-time clock. FF_NORTC_MON,
/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
/ These options have no effect in read-only configuration (FF_FS_READONLY = 1). */
#define FF_FS_NOFSINFO 0
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
/ option, and f_getfree() function at the first time after volume mount will force
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
/
/ bit0=0: Use free cluster count in the FSINFO if available.
/ bit0=1: Do not trust free cluster count in the FSINFO.
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
*/
#define FF_FS_LOCK 0
/* The option FF_FS_LOCK switches file lock function to control duplicated file open
/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
/ is 1.
/
/ 0: Disable file lock function. To avoid volume corruption, application program
/ should avoid illegal open, remove and rename to the open objects.
/ >0: Enable file lock function. The value defines how many files/sub-directories
/ can be opened simultaneously under file lock control. Note that the file
/ lock control is independent of re-entrancy. */
#define FF_FS_REENTRANT 0
#define FF_FS_TIMEOUT 1000
/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
/ module itself. Note that regardless of this option, file access to different
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
/ and f_fdisk() function, are always not re-entrant. Only file/directory access
/ to the same volume is under control of this featuer.
/
/ 0: Disable re-entrancy. FF_FS_TIMEOUT have no effect.
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
/ ff_mutex_create(), ff_mutex_delete(), ff_mutex_take() and ff_mutex_give()
/ function, must be added to the project. Samples are available in ffsystem.c.
/
/ The FF_FS_TIMEOUT defines timeout period in unit of O/S time tick.
*/
#ifdef FILE_SYSTEM_WORD_ACCESS
#define FF_WORD_ACCESS 1
#else
#define FF_WORD_ACCESS 0
#endif
/* The FF_WORD_ACCESS option is an only platform dependent option. It defines
/ which access method is used to the word data on the FAT volume.
/
/ 0: Byte-by-byte access. Always compatible with all platforms.
/ 1: Word access. Do not choose this unless under both the following conditions.
/
/ * Address misaligned memory access is always allowed for ALL instructions.
/ * Byte order on the memory is little-endian.
/
/ If it is the case, FF_WORD_ACCESS can also be set to 1 to improve performance and
/ reduce code size. Following table shows an example of some processor types.
/
/ ARM7TDMI 0 ColdFire 0 V850E 0
/ Cortex-M3 0 Z80 0/1 V850ES 0/1
/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1
/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1
/ AVR32 0 RL78 0 R32C 0
/ PIC18 0/1 SH-2 0 M16C 0/1
/ PIC24 0 H8S 0 MSP430 0
/ PIC32 0 H8/300H 0 x86 0/1
*/
#ifdef __cplusplus
}
#endif
/*--- End of configuration options ---*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h
+28
View File
@@ -0,0 +1,28 @@
/******************************************************************************
* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef _MBLAZE_NT_TYPES_H
#define _MBLAZE_NT_TYPES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef char byte;
typedef short half;
typedef int word;
typedef unsigned char ubyte;
typedef unsigned short uhalf;
typedef unsigned int uword;
typedef ubyte boolean;
#ifdef __cplusplus
}
#endif
#endif
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/pm_api_version.h
+269
View File
@@ -0,0 +1,269 @@
/******************************************************************************
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file pm_api_version.h
*
* @addtogroup xpm_versal_apis XilPM APIs
*****************************************************************************/
#ifndef PM_API_VERSION_H_
#define PM_API_VERSION_H_
/*****************************************************************************/
/**
* @section EEMI_API_DETAIL XilPM EEMI API Version Detail
*
* This section provides details of EEMI API version and it's history for PM APIs of XilPM library.
*
* | NAME | ID | Platform | Version| Description |
* |----------------------------|-------|---------------|:------:|---------------------------------------------------------------------------|
* | PM_GET_API_VERSION | 0x1 | Both | 1 | The API is used to request the version number of the API |
* | PM_SET_CONFIGURATION | 0x2 | ZynqMP | 1 | The API is used to configure the power management framework |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_GET_NODE_STATUS | 0x3 | Both | 1 | The API is used to obtain information about current status of a device |
* | PM_GET_OP_CHARACTERISTIC | 0x4 | Both | 2 | V1 - The API is used to get operating characteristics of a device |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n "type" first before performing the actual functionality |
* | PM_REGISTER_NOTIFIER | 0x5 | Both | 2 | V1 - The API is used to register a subsystem to be notified about the\n device event |
* | ^ | ^ | ^ | ^ | V2 - Added support of event management functionality |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_REQUEST_SUSPEND | 0x6 | Both | 1 | The API is used to send suspend request to another subsystem |
* | PM_SELF_SUSPEND | 0x7 | Both | 2 | V1 - The API is used to suspend a child subsystem |
* | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_FORCE_POWERDOWN | 0x8 | Both | 2 | V1 - The API is used to Powerdown other processor or node |
* | ^ | ^ | ^ | ^ | V2 - Added support of cpu idle functionality during force powerdown |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_ABORT_SUSPEND | 0x9 | Both | 1 | The API is used by a subsystem to abort suspend of a child subsystem |
* | PM_REQUEST_WAKEUP | 0xA | Both | 1 | The API is used to start-up and wake-up a child subsystem |
* | PM_SET_WAKEUP_SOURCE | 0xB | Both | 1 | The API is used to set wakeup source |
* | PM_SYSTEM_SHUTDOWN | 0xC | Both | 1 | The API is used to shutdown or restart the system |
* | PM_REQUEST_NODE | 0xD | Both | 2 | V1 - The API is used to request the usage of a device |
* | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_RELEASE_NODE | 0xE | Both | 2 | V1 - The API is used to release the usage of a device |
* | ^ | ^ | ^ | ^ | V2 - Added support of security policy handling during request device |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in Versal but ZynqMP supports only V1 |
* | PM_SET_REQUIREMENT | 0xF | Both | 1 | The API is used to announce a change in requirement for a specific slave\n node which is currently in use |
* | PM_SET_MAX_LATENCY | 0x10 | Both | 1 | The API is used to set maximum allowed latency for the device |
* | PM_RESET_ASSERT | 0x11 | Both | 1 | The API is used to reset or de-reset a device |
* | PM_RESET_GET_STATUS | 0x12 | Both | 1 | The API is used to read the device reset state |
* | PM_MMIO_WRITE | 0x13 | ZynqMP | 1 | The API is used to write a value into a register |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_MMIO_READ | 0x14 | ZynqMP | 1 | The API is used to read a value from a register |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_INIT_FINALIZE | 0x15 | Both | 1 | The API is used to initialize subsystem and release unused devices |
* | PM_GET_CHIPID | 0x18 | Both | 1 | The API is used to request the version and ID code of a chip |
* | PM_PINCTRL_REQUEST | 0x1C | Both | 1 | The API is used to request the pin |
* | PM_PINCTRL_RELEASE | 0x1D | Both | 1 | The API is used to release the pin |
* | PM_PINCTRL_GET_FUNCTION | 0x1E | Both | 1 | The API is used to read the pin function |
* | PM_PINCTRL_SET_FUNCTION | 0x1F | Both | 1 | The API is used to set the pin function |
* | PM_PINCTRL_CONFIG_PARAM_GET| 0x20 | Both | 1 | The API is used to read the pin parameter value |
* | PM_PINCTRL_CONFIG_PARAM_SET| 0x21 | Both | 2 | V1 - The API is used to set the pin parameter value |
* | ^ | ^ | ^ | ^ | V2 - Added support of MIO tri-state controlling functionality |
* | ^ | ^ | ^ | ^ | Note: V2 is supported in ZynqMP but Versal supports only V1 |
* | PM_IOCTL | 0x22 | Both | 3 | V1 - The API is used to perform driver-like IOCTL functions on shared\n system devices |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality |
* | ^ | ^ | ^ | ^ | V3 - Add support of zeroization of AIE data and program memory separately |
* | ^ | ^ | ^ | ^ | Note: V3 is supported in Versal but ZynqMP supports only V2 |
* | PM_QUERY_DATA | 0x23 | Both | 2 | V1 - The API is used to query information about the platform resources |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask functionality, user can check the supported\n ID first before performing the actual functionality |
* | PM_CLOCK_ENABLE | 0x24 | Both | 1 | The API is used to enable the clock |
* | PM_CLOCK_DISABLE | 0x25 | Both | 1 | The API is used to disable the clock |
* | PM_CLOCK_GETSTATE | 0x26 | Both | 1 | The API is used to read the clock state |
* | PM_CLOCK_SETDIVIDER | 0x27 | Both | 1 | The API is used to set the divider value of the clock |
* | PM_CLOCK_GETDIVIDER | 0x28 | Both | 1 | The API is used to read the clock divider |
* | PM_CLOCK_SETPARENT | 0x2B | Both | 1 | The API is used to set the parent of the clock |
* | PM_CLOCK_GETPARENT | 0x2C | Both | 1 | The API is used to read the clock parent |
* | PM_PLL_SET_PARAM | 0x30 | Both | 1 | The API is used to set the parameter of PLL clock |
* | PM_PLL_GET_PARAM | 0x31 | Both | 1 | The API is used to read the parameter of PLL clock |
* | PM_PLL_SET_MODE | 0x32 | Both | 1 | The API is used to set the mode of PLL clock |
* | PM_PLL_GET_MODE | 0x33 | Both | 1 | The API is used to read the mode of PLL clock |
* | PM_REGISTER_ACCESS | 0x34 | ZynqMP | 1 | The API is used for register read/write access data |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_EFUSE_ACCESS | 0x35 | ZynqMP | 1 | The API is used to provide access to efuse memory |
* | ^ | ^ | ^ | ^ | Note: Deprecated in Versal but supported in ZynqMP |
* | PM_FEATURE_CHECK | 0x3F | Both | 2 | V1 - The API is used to return supported version of the given API |
* | ^ | ^ | ^ | ^ | V2 - Added support of bitmask payload functionality |
*
*****************************************************************************/
/*****************************************************************************/
/**
* @section IOCTL_ID_DETAIL XilPM IOCTL IDs Detail
*
* This section provides the details of the IOCTL IDs which are supported across the different platforms and their brief descriptions.
*
* | Name | ID | Platform | Description |
* |------------------------------------|-------|---------------|---------------------------------------|
* | IOCTL_GET_RPU_OPER_MODE | 0 | Both | Get RPU mode |
* | IOCTL_SET_RPU_OPER_MODE | 1 | Both | Set RPU mode |
* | IOCTL_RPU_BOOT_ADDR_CONFIG | 2 | Both | RPU boot address config |
* | IOCTL_TCM_COMB_CONFIG | 3 | Both | TCM config |
* | IOCTL_SET_TAPDELAY_BYPASS | 4 | Both | TAP delay bypass |
* | IOCTL_SET_SGMII_MODE | 5 | ZynqMP | SGMII mode |
* | IOCTL_SD_DLL_RESET | 6 | Both | SD DLL reset |
* | IOCTL_SET_SD_TAPDELAY | 7 | Both | SD TAP delay |
* | IOCTL_SET_PLL_FRAC_MODE | 8 | Both | Set PLL frac mode |
* | IOCTL_GET_PLL_FRAC_MODE | 9 | Both | Get PLL frac mode |
* | IOCTL_SET_PLL_FRAC_DATA | 10 | Both | Set PLL frac data |
* | IOCTL_GET_PLL_FRAC_DATA | 11 | Both | Get PLL frac data |
* | IOCTL_WRITE_GGS | 12 | Both | Write GGS |
* | IOCTL_READ_GGS | 13 | Both | Read GGS |
* | IOCTL_WRITE_PGGS | 14 | Both | Write PGGS |
* | IOCTL_READ_PGGS | 15 | Both | Read PGGS |
* | IOCTL_ULPI_RESET | 16 | ZynqMP | ULPI reset |
* | IOCTL_SET_BOOT_HEALTH_STATUS | 17 | Both | Set boot status |
* | IOCTL_AFI | 18 | ZynqMP | AFI |
* | IOCTL_PROBE_COUNTER_READ | 19 | Versal | Probe counter read |
* | IOCTL_PROBE_COUNTER_WRITE | 20 | Versal | Probe counter write |
* | IOCTL_OSPI_MUX_SELECT | 21 | Versal | OSPI mux select |
* | IOCTL_USB_SET_STATE | 22 | Versal | USB set state |
* | IOCTL_GET_LAST_RESET_REASON | 23 | Versal | Get last reset reason |
* | IOCTL_AIE_ISR_CLEAR | 24 | Versal | AIE ISR clear |
* | IOCTL_REGISTER_SGI | 25 | None | Register SGI to ATF |
* | IOCTL_SET_FEATURE_CONFIG | 26 | ZynqMP | Set runtime feature config |
* | IOCTL_GET_FEATURE_CONFIG | 27 | ZynqMP | Get runtime feature config |
* | IOCTL_READ_REG | 28 | Versal | Read a 32-bit register |
* | IOCTL_MASK_WRITE_REG | 29 | Versal | RMW a 32-bit register |
* | IOCTL_SET_SD_CONFIG | 30 | ZynqMP | Set SD config register value |
* | IOCTL_SET_GEM_CONFIG | 31 | ZynqMP | Set GEM config register value |
* | IOCTL_SET_USB_CONFIG | 32 | ZynqMP | Set USB config register value |
* | IOCTL_AIE_OPS | 33 | Versal | AIE1/AIEML Run Time Operations |
* | IOCTL_GET_QOS | 34 | Versal | Get Device QoS value |
* | IOCTL_GET_APU_OPER_MODE | 35 | Versal | Get APU operation mode |
* | IOCTL_SET_APU_OPER_MODE | 36 | Versal | Set APU operation mode |
* | IOCTL_PREPARE_DDR_SHUTDOWN | 37 | Versal | Prepare DDR for shut down |
* | IOCTL_GET_SSIT_TEMP | 38 | Versal | Get secondary SLR min/max temperature |
*
*****************************************************************************/
/*****************************************************************************/
/**
* @section QUERY_ID_DETAIL XilPM QUERY IDs Detail
*
* This section provides the details of the QUERY IDs which are supported across the different platforms and their brief descriptions.
*
* | Name | ID | Platform | Description |
* |--------------------------------------------|-------|---------------|---------------------------------------|
* | XPM_QID_INVALID | 0 | Both | Invalid Query ID |
* | XPM_QID_CLOCK_GET_NAME | 1 | Both | Get clock name |
* | XPM_QID_CLOCK_GET_TOPOLOGY | 2 | Both | Get clock topology |
* | XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS | 3 | Both | Get clock fixedfactor parameter |
* | XPM_QID_CLOCK_GET_MUXSOURCES | 4 | Both | Get clock mux sources |
* | XPM_QID_CLOCK_GET_ATTRIBUTES | 5 | Both | Get clock attributes |
* | XPM_QID_PINCTRL_GET_NUM_PINS | 6 | Both | Get total pins |
* | XPM_QID_PINCTRL_GET_NUM_FUNCTIONS | 7 | Both | Get total pin functions |
* | XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS | 8 | Both | Get total pin function groups |
* | XPM_QID_PINCTRL_GET_FUNCTION_NAME | 9 | Both | Get pin function name |
* | XPM_QID_PINCTRL_GET_FUNCTION_GROUPS | 10 | Both | Get pin function groups |
* | XPM_QID_PINCTRL_GET_PIN_GROUPS | 11 | Both | Get pin groups |
* | XPM_QID_CLOCK_GET_NUM_CLOCKS | 12 | Both | Get number of clocks |
* | XPM_QID_CLOCK_GET_MAX_DIVISOR | 13 | Both | Get max clock divisor |
* | XPM_QID_PLD_GET_PARENT | 14 | Versal | Get PLD parent |
* | XPM_QID_PINCTRL_GET_ATTRIBUTES | 15 | Versal | Get pin attributes |
*
*****************************************************************************/
/*****************************************************************************/
/**
* @section GET_OP_CHAR_DETAIL XilPM GET_OP_CHAR IDs Detail
*
* This section provides the details of the GET_OP_CHAR IDs which are supported across the different platforms and their brief descriptions.
*
* | Name | ID | Platform | Description |
* |------------------------------------|-------|---------------|-----------------------------------------------|
* | PM_OPCHAR_TYPE_POWER | 1 | ZynqMP | Operating characteristic ID power |
* | PM_OPCHAR_TYPE_TEMP | 2 | Versal | Operating characteristic ID temperature |
* | PM_OPCHAR_TYPE_LATENCY | 3 | Both | Operating characteristic ID latency |
*
*****************************************************************************/
/**
* PM API IDs
*/
typedef enum {
PM_API_MIN, /**< 0x0 */
PM_GET_API_VERSION, /**< 0x1 */
PM_SET_CONFIGURATION, /**< 0x2 */
PM_GET_NODE_STATUS, /**< 0x3 */
PM_GET_OP_CHARACTERISTIC, /**< 0x4 */
PM_REGISTER_NOTIFIER, /**< 0x5 */
PM_REQUEST_SUSPEND, /**< 0x6 */
PM_SELF_SUSPEND, /**< 0x7 */
PM_FORCE_POWERDOWN, /**< 0x8 */
PM_ABORT_SUSPEND, /**< 0x9 */
PM_REQUEST_WAKEUP, /**< 0xA */
PM_SET_WAKEUP_SOURCE, /**< 0xB */
PM_SYSTEM_SHUTDOWN, /**< 0xC */
PM_REQUEST_NODE, /**< 0xD */
PM_RELEASE_NODE, /**< 0xE */
PM_SET_REQUIREMENT, /**< 0xF */
PM_SET_MAX_LATENCY, /**< 0x10 */
PM_RESET_ASSERT, /**< 0x11 */
PM_RESET_GET_STATUS, /**< 0x12 */
PM_MMIO_WRITE, /**< 0x13 */
PM_MMIO_READ, /**< 0x14 */
PM_INIT_FINALIZE, /**< 0x15 */
PM_FPGA_LOAD, /**< 0x16 */
PM_FPGA_GET_STATUS, /**< 0x17 */
PM_GET_CHIPID, /**< 0x18 */
PM_SECURE_RSA_AES, /**< 0x19 */
PM_SECURE_SHA, /**< 0x1A */
PM_SECURE_RSA, /**< 0x1B */
PM_PINCTRL_REQUEST, /**< 0x1C */
PM_PINCTRL_RELEASE, /**< 0x1D */
PM_PINCTRL_GET_FUNCTION, /**< 0x1E */
PM_PINCTRL_SET_FUNCTION, /**< 0x1F */
PM_PINCTRL_CONFIG_PARAM_GET, /**< 0x20 */
PM_PINCTRL_CONFIG_PARAM_SET, /**< 0x21 */
PM_IOCTL, /**< 0x22 */
PM_QUERY_DATA, /**< 0x23 */
PM_CLOCK_ENABLE, /**< 0x24 */
PM_CLOCK_DISABLE, /**< 0x25 */
PM_CLOCK_GETSTATE, /**< 0x26 */
PM_CLOCK_SETDIVIDER, /**< 0x27 */
PM_CLOCK_GETDIVIDER, /**< 0x28 */
PM_CLOCK_SETRATE, /**< 0x29 */
PM_CLOCK_GETRATE, /**< 0x2A */
PM_CLOCK_SETPARENT, /**< 0x2B */
PM_CLOCK_GETPARENT, /**< 0x2C */
PM_SECURE_IMAGE, /**< 0x2D */
PM_FPGA_READ, /**< 0x2E */
PM_SECURE_AES, /**< 0x2F */
PM_PLL_SET_PARAMETER, /**< 0x30 */
PM_PLL_GET_PARAMETER, /**< 0x31 */
PM_PLL_SET_MODE, /**< 0x32 */
PM_PLL_GET_MODE, /**< 0x33 */
PM_REGISTER_ACCESS, /**< 0x34 */
PM_EFUSE_ACCESS, /**< 0x35 */
PM_ADD_SUBSYSTEM, /**< 0x36 */
PM_DESTROY_SUBSYSTEM, /**< 0x37 */
PM_DESCRIBE_NODES, /**< 0x38 */
PM_ADD_NODE, /**< 0x39 */
PM_ADD_NODE_PARENT, /**< 0x3A */
PM_ADD_NODE_NAME, /**< 0x3B */
PM_ADD_REQUIREMENT, /**< 0x3C */
PM_SET_CURRENT_SUBSYSTEM, /**< 0x3D */
PM_INIT_NODE, /**< 0x3E */
PM_FEATURE_CHECK, /**< 0x3F */
PM_ISO_CONTROL, /**< 0x40 */
PM_ACTIVATE_SUBSYSTEM, /**< 0x41 */
PM_SET_NODE_ACCESS, /**< 0x42 */
PM_BISR, /**< 0x43 */
PM_APPLY_TRIM, /**< 0x44 */
PM_NOC_CLOCK_ENABLE, /**< 0x45 */
PM_IF_NOC_CLOCK_ENABLE, /**< 0x46 */
PM_FORCE_HOUSECLEAN, /**< 0x47 */
PM_FPGA_GET_VERSION, /**< 0x48 */
PM_FPGA_GET_FEATURE_LIST, /**< 0x49 */
PM_API_MAX /**< 0x4A */
} XPm_ApiId;
#endif /* PM_API_VERSION_H_ */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/profile.h
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/******************************************************************************
* Copyright (c) 2002 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef PROFILE_H
#define PROFILE_H 1
#include <stdio.h>
#include "xil_types.h"
#include "profile_config.h"
#ifdef PROC_MICROBLAZE
#include "mblaze_nt_types.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
void _system_init( void ) ;
void _system_clean( void ) ;
void mcount(u32 frompc, u32 selfpc);
void profile_intr_handler( void ) ;
void _profile_init( void );
/****************************************************************************
* Profiling on hardware - Hash table maintained on hardware and data sent
* to xmd for gmon.out generation.
****************************************************************************/
/*
* histogram counters are unsigned shorts (according to the kernel).
*/
#define HISTCOUNTER u16
struct tostruct {
u32 selfpc;
s32 count;
s16 link;
u16 pad;
};
struct fromstruct {
u32 frompc ;
s16 link ;
u16 pad ;
} ;
/*
* general rounding functions.
*/
#define ROUNDDOWN(x,y) (((x)/(y))*(y))
#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y))
/*
* The profiling data structures are housed in this structure.
*/
struct gmonparam {
s32 state;
/* Histogram Information */
u16 *kcount; /* No. of bins in histogram */
u32 kcountsize; /* Histogram samples */
/* Call-graph Information */
struct fromstruct *froms;
u32 fromssize;
struct tostruct *tos;
u32 tossize;
/* Initialization I/Ps */
u32 lowpc;
u32 highpc;
u32 textsize;
/* u32 cg_froms, */
/* u32 cg_tos, */
};
extern struct gmonparam *_gmonparam;
extern s32 n_gmon_sections;
/*
* Possible states of profiling.
*/
#define GMON_PROF_ON 0
#define GMON_PROF_BUSY 1
#define GMON_PROF_ERROR 2
#define GMON_PROF_OFF 3
/*
* Sysctl definitions for extracting profiling information from the kernel.
*/
#define GPROF_STATE 0 /* int: profiling enabling variable */
#define GPROF_COUNT 1 /* struct: profile tick count buffer */
#define GPROF_FROMS 2 /* struct: from location hash bucket */
#define GPROF_TOS 3 /* struct: destination/count structure */
#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */
#ifdef __cplusplus
}
#endif
#endif /* PROFILE_H */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/sleep.h
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/******************************************************************************
* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file sleep.h
*
* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
* related APIs.
*
* <pre>
* MODIFICATION HISTORY :
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 6.6 srm 11/02/17 Added processor specific sleep routines
* function prototypes.
* 7.7 sk 01/10/22 Typecast sleep declaration argument from unsigned int to
* u32 to fix misra_c_2012_directive_4_6 violation.
* 7.7 sk 01/10/22 Modify the return type of sleep_R5 and usleep_R5 from
* unsigned to void to fix misra_c_2012_rule_17_7 violation.
* 8.0 sk 03/02/22 Update usleep_R5 and usleep parameter types to fix misra_
* c_2012_directive_4_6 violation.
* 8.0 sk 03/17/22 Modify the return type of usleep_MB from int to void and
* sleep_MB from unsigned to void to fix misra_c_2012_rule_
* 17_7 violation.
* 8.0 sk 03/17/22 Modify sleep_MB parameter type from unsigned int to
* u32 and usleep_MB parameter type from unsigned long to
* ULONG to fix misra_c_2012_rule_4_6 violation.
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
******************************************************************************/
#ifndef SLEEP_H
#define SLEEP_H
#include "xil_types.h"
#include "xil_io.h"
#ifdef __cplusplus
extern "C" {
#endif
/*****************************************************************************/
/**
*
* This macro polls an address periodically until a condition is met or till the
* timeout occurs.
* The minimum timeout for calling this macro is 100us. If the timeout is less
* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
* If the timeout is not a multiple of 100us, it waits for a timeout of
* the next usec value which is a multiple of 100us.
*
* @param IO_func - accessor function to read the register contents.
* Depends on the register width.
* @param ADDR - Address to be polled
* @param VALUE - variable to read the value
* @param COND - Condition to checked (usually involves VALUE)
* @param TIMEOUT_US - timeout in micro seconds
*
* @return 0 - when the condition is met
* -1 - when the condition is not met till the timeout period
*
* @note none
*
*****************************************************************************/
#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
( { \
u64 timeout = TIMEOUT_US/100; \
if(TIMEOUT_US%100!=0) \
timeout++; \
for(;;) { \
VALUE = IO_func(ADDR); \
if(COND) \
break; \
else { \
usleep(100); \
timeout--; \
if(timeout==0) \
break; \
} \
} \
(timeout>0) ? 0 : -1; \
} )
/************************** Function Prototypes ******************************/
void usleep(ULONG useconds);
void sleep(u32 seconds);
void usleep_R5(ULONG useconds);
void sleep_R5(u32 seconds);
void usleep_MB(ULONG useconds);
void sleep_MB(u32 seconds);
int usleep_A53(unsigned long useconds);
unsigned sleep_A53(unsigned int seconds);
int usleep_A9(unsigned long useconds);
unsigned sleep_A9(unsigned int seconds);
/*****************************************************************************/
#ifdef __cplusplus
}
#endif
#endif
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/smc.h
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/******************************************************************************
* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file smc.h
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a sdm 11/03/09 Initial release.
* 4.2 pkp 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
* as smc.c is removed
* </pre>
*
* @note None.
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef SMC_H /* prevent circular inclusions */
#define SMC_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xparameters.h"
#include "xil_io.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/* Memory controller configuration register offset */
#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */
#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */
#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */
#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */
#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */
#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */
#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */
#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */
#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */
/* Chip select configuration register offset */
#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */
#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */
#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */
#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */
#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */
#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */
#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */
#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */
/* User configuration register offset */
#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */
#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */
/* Integration test register offset */
#define XSMCPSS_IT_OFFSET 0xE00U
/* ID configuration register offset */
#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U
#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U
#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U
#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU
#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U
#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U
#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U
#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* SMC_H */
/**
*@endcond
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/vectors.h
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/******************************************************************************
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file vectors.h
*
* This file contains the C level vector prototypes for the ARM Cortex A9 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a ecm 10/20/10 Initial version, moved over from bsp area
* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors
* 8.0 sk 03/02/22 Update _VECTORS_H_ with VECTORS_H_ to fix misra_c_
* 2012_rule_21_1 violation.
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
#ifndef VECTORS_H_
#define VECTORS_H_
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/************************** Function Prototypes ******************************/
void FIQInterrupt(void);
void IRQInterrupt(void);
#if !defined (__aarch64__)
void SWInterrupt(void);
void DataAbortInterrupt(void);
void PrefetchAbortInterrupt(void);
void UndefinedException(void);
#else
void SynchronousInterrupt(void);
void SErrorInterrupt(void);
#endif
#ifdef __cplusplus
}
#endif
#endif /* protection macro */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps.h
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/******************************************************************************
* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xadcps.h
* @addtogroup Overview
* @{
* @details
*
* The XAdcPs driver supports the Xilinx XADC/ADC device.
*
* The XADC/ADC device has the following features:
* - 10-bit, 200-KSPS (kilo samples per second)
* Analog-to-Digital Converter (ADC)
* - Monitoring of on-chip supply voltages and temperature
* - 1 dedicated differential analog-input pair and
* 16 auxiliary differential analog-input pairs
* - Automatic alarms based on user defined limits for the on-chip
* supply voltages and temperature
* - Automatic Channel Sequencer, programmable averaging, programmable
* acquisition time for the external inputs, unipolar or differential
* input selection for the external inputs
* - Inbuilt Calibration
* - Optional interrupt request generation
*
*
* The user should refer to the hardware device specification for detailed
* information about the device.
*
* This header file contains the prototypes of driver functions that can
* be used to access the XADC/ADC device.
*
*
* <b> XADC Channel Sequencer Modes </b>
*
* The XADC Channel Sequencer supports the following operating modes:
*
* - <b> Default </b>: This is the default mode after power up.
* In this mode of operation the XADC operates in
* a sequence mode, monitoring the on chip sensors:
* Temperature, VCCINT, and VCCAUX.
* - <b> One pass through sequence </b>: In this mode the XADC
* converts the channels enabled in the Sequencer Channel Enable
* registers for a single pass and then stops.
* - <b> Continuous cycling of sequence </b>: In this mode the XADC
* converts the channels enabled in the Sequencer Channel Enable
* registers continuously.
* - <b> Single channel mode</b>: In this mode the XADC Channel
* Sequencer is disabled and the XADC operates in a
* Single Channel Mode.
* The XADC can operate either in a Continuous or Event
* driven sampling mode in the single channel mode.
* - <b> Simultaneous Sampling Mode</b>: In this mode the XADC Channel
* Sequencer will automatically sequence through eight fixed pairs
* of auxiliary analog input channels for simulataneous conversion.
* - <b> Independent ADC mode</b>: In this mode the first ADC (A) is used to
* is used to implement a fixed monitoring mode similar to the
* default mode but the alarm fucntions ar eenabled.
* The second ADC (B) is available to be used with external analog
* input channels only.
*
* Read the XADC spec for more information about the sequencer modes.
*
* <b> Initialization and Configuration </b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the XADC/ADC device.
*
* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
* device. The user needs to first call the XAdcPs_LookupConfig() API which
* returns the Configuration structure pointer which is passed as a parameter to
* the XAdcPs_CfgInitialize() API.
*
*
* <b>Interrupts</b>
*
* The XADC/ADC device supports interrupt driven mode and the default
* operation mode is polling mode.
*
* The interrupt mode is available only if hardware is configured to support
* interrupts.
*
* This driver does not provide a Interrupt Service Routine (ISR) for the device.
* It is the responsibility of the application to provide one if needed. Refer to
* the interrupt example provided with this driver for details on using the
* device in interrupt mode.
*
*
* <b> Virtual Memory </b>
*
* This driver supports Virtual Memory. The RTOS is responsible for calculating
* the correct device base address in Virtual Memory space.
*
*
* <b> Threads </b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
*
* <b> Asserts </b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
*
* <b> Building the driver </b>
*
* The XAdcPs driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
*
* <b> Limitations of the driver </b>
*
* XADC/ADC device can be accessed through the JTAG port and the PLB
* interface. The driver implementation does not support the simultaneous access
* of the device by both these interfaces. The user has to care of this situation
* in the user application code.
*
* <br><br>
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a ssb 12/22/11 First release based on the XPS/AXI xadc driver
* 1.01a bss 02/18/13 Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
* XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
* in xadcps.c to fix CR #693371
* 1.03a bss 11/01/13 Modified xadcps_hw.h to use correct Register offsets
* CR#749687
* 2.1 bss 08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
* XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
* XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
* functions.
* Modified Assert for XAdcPs_SetSingleChParams in
* xadcps.c to fix CR #807563.
* 2.2 bss 04/27/14 Modified to use correct Device Config base address in
* xadcps.c (CR#854437).
* ms 01/23/17 Added xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/05/17 Modified Comment lines in functions of xadcps
* examples to recognize it as documentation block
* for doxygen generation.
* 2.3 mn 07/09/18 Fix Doxygen warning
* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
* aad 12/17/20 Added missing function declarations and removed
* functions with no definitions.
* 2.7 cog 07/24/23 Added support for SDT flow
*
*
* </pre>
*
*****************************************************************************/
#ifndef XADCPS_H /* Prevent circular inclusions */
#define XADCPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xadcps_hw.h"
/************************** Constant Definitions ****************************/
/**
* @name Indexes for the different channels.
* @{
*/
#define XADCPS_CH_TEMP 0x0U /**< On Chip Temperature */
#define XADCPS_CH_VCCINT 0x1U /**< VCCINT */
#define XADCPS_CH_VCCAUX 0x2U /**< VCCAUX */
#define XADCPS_CH_VPVN 0x3U /**< VP/VN Dedicated analog inputs */
#define XADCPS_CH_VREFP 0x4U /**< VREFP */
#define XADCPS_CH_VREFN 0x5U /**< VREFN */
#define XADCPS_CH_VBRAM 0x6U /**< On-chip VBRAM Data Reg, 7 series */
#define XADCPS_CH_SUPPLY_CALIB 0x07U /**< Supply Calib Data Reg */
#define XADCPS_CH_ADC_CALIB 0x08U /**< ADC Offset Channel Reg */
#define XADCPS_CH_GAINERR_CALIB 0x09U /**< Gain Error Channel Reg */
#define XADCPS_CH_VCCPINT 0x0DU /**< On-chip PS VCCPINT Channel , Zynq */
#define XADCPS_CH_VCCPAUX 0x0EU /**< On-chip PS VCCPAUX Channel , Zynq */
#define XADCPS_CH_VCCPDRO 0x0FU /**< On-chip PS VCCPDRO Channel , Zynq */
#define XADCPS_CH_AUX_MIN 16U /**< Channel number for 1st Aux Channel */
#define XADCPS_CH_AUX_MAX 31U /**< Channel number for Last Aux channel */
/*@}*/
/**
* @name Indexes for reading the Calibration Coefficient Data.
* @{
*/
#define XADCPS_CALIB_SUPPLY_COEFF 0U /**< Supply Offset Calib Coefficient */
#define XADCPS_CALIB_ADC_COEFF 1U /**< ADC Offset Calib Coefficient */
#define XADCPS_CALIB_GAIN_ERROR_COEFF 2U /**< Gain Error Calib Coefficient*/
/*@}*/
/**
* @name Indexes for reading the Minimum/Maximum Measurement Data.
* @{
*/
#define XADCPS_MAX_TEMP 0U /**< Maximum Temperature Data */
#define XADCPS_MAX_VCCINT 1U /**< Maximum VCCINT Data */
#define XADCPS_MAX_VCCAUX 2U /**< Maximum VCCAUX Data */
#define XADCPS_MAX_VBRAM 3U /**< Maximum VBRAM Data */
#define XADCPS_MIN_TEMP 4U /**< Minimum Temperature Data */
#define XADCPS_MIN_VCCINT 5U /**< Minimum VCCINT Data */
#define XADCPS_MIN_VCCAUX 6U /**< Minimum VCCAUX Data */
#define XADCPS_MIN_VBRAM 7U /**< Minimum VBRAM Data */
#define XADCPS_MAX_VCCPINT 8U /**< Maximum VCCPINT Register , Zynq */
#define XADCPS_MAX_VCCPAUX 9U /**< Maximum VCCPAUX Register , Zynq */
#define XADCPS_MAX_VCCPDRO 0xAU /**< Maximum VCCPDRO Register , Zynq */
#define XADCPS_MIN_VCCPINT 0xCU /**< Minimum VCCPINT Register , Zynq */
#define XADCPS_MIN_VCCPAUX 0xDU /**< Minimum VCCPAUX Register , Zynq */
#define XADCPS_MIN_VCCPDRO 0xEU /**< Minimum VCCPDRO Register , Zynq */
/*@}*/
/**
* @name Alarm Threshold(Limit) Register (ATR) indexes.
* @{
*/
#define XADCPS_ATR_TEMP_UPPER 0U /**< High user Temperature */
#define XADCPS_ATR_VCCINT_UPPER 1U /**< VCCINT high voltage limit register */
#define XADCPS_ATR_VCCAUX_UPPER 2U /**< VCCAUX high voltage limit register */
#define XADCPS_ATR_OT_UPPER 3U /**< VCCAUX high voltage limit register */
#define XADCPS_ATR_TEMP_LOWER 4U /**< Upper Over Temperature limit Reg */
#define XADCPS_ATR_VCCINT_LOWER 5U /**< VCCINT high voltage limit register */
#define XADCPS_ATR_VCCAUX_LOWER 6U /**< VCCAUX low voltage limit register */
#define XADCPS_ATR_OT_LOWER 7U /**< Lower Over Temperature limit */
#define XADCPS_ATR_VBRAM_UPPER_ 8U /**< VRBAM Upper Alarm Reg, 7 Series */
#define XADCPS_ATR_VCCPINT_UPPER 9U /**< VCCPINT Upper Alarm Reg, Zynq */
#define XADCPS_ATR_VCCPAUX_UPPER 0xAU /**< VCCPAUX Upper Alarm Reg, Zynq */
#define XADCPS_ATR_VCCPDRO_UPPER 0xBU /**< VCCPDRO Upper Alarm Reg, Zynq */
#define XADCPS_ATR_VBRAM_LOWER 0xCU /**< VRBAM Lower Alarm Reg, 7 Series */
#define XADCPS_ATR_VCCPINT_LOWER 0xDU /**< VCCPINT Lower Alarm Reg , Zynq */
#define XADCPS_ATR_VCCPAUX_LOWER 0xEU /**< VCCPAUX Lower Alarm Reg , Zynq */
#define XADCPS_ATR_VCCPDRO_LOWER 0xFU /**< VCCPDRO Lower Alarm Reg , Zynq */
/*@}*/
/**
* @name Averaging to be done for the channels.
* @{
*/
#define XADCPS_AVG_0_SAMPLES 0U /**< No Averaging */
#define XADCPS_AVG_16_SAMPLES 1U /**< Average 16 samples */
#define XADCPS_AVG_64_SAMPLES 2U /**< Average 64 samples */
#define XADCPS_AVG_256_SAMPLES 3U /**< Average 256 samples */
/*@}*/
/**
* @name Channel Sequencer Modes of operation
* @{
*/
#define XADCPS_SEQ_MODE_SAFE 0U /**< Default Safe Mode */
#define XADCPS_SEQ_MODE_ONEPASS 1U /**< Onepass through Sequencer */
#define XADCPS_SEQ_MODE_CONTINPASS 2U /**< Continuous Cycling Sequencer */
#define XADCPS_SEQ_MODE_SINGCHAN 3U /**< Single channel -No Sequencing */
#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4U /**< Simultaneous sampling */
#define XADCPS_SEQ_MODE_INDEPENDENT 8U /**< Independent mode */
/*@}*/
/**
* @name Power Down Modes
* @{
*/
#define XADCPS_PD_MODE_NONE 0U /**< No Power Down */
#define XADCPS_PD_MODE_ADCB 1U /**< Power Down ADC B */
#define XADCPS_PD_MODE_XADC 2U /**< Power Down ADC A and ADC B */
/*@}*/
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the XADC/ADC
* device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddress; /**< Device base address */
} XAdcPs_Config;
/**
* The driver's instance data. The user is required to allocate a variable
* of this type for every XADC/ADC device in the system. A pointer to
* a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XAdcPs_Config Config; /**< XAdcPs_Config of current device */
u32 IsReady; /**< Device is initialized and ready */
} XAdcPs;
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
*
* This macro checks if the XADC device is in Event Sampling mode.
*
* @param InstancePtr is a pointer to the XAdcPs instance.
*
* @return
* - TRUE if the device is in Event Sampling Mode.
* - FALSE if the device is in Continuous Sampling Mode.
*
* @note C-Style signature:
* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
*
*****************************************************************************/
#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \
(((XAdcPs_ReadInternalReg(InstancePtr, \
XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \
TRUE : FALSE))
/****************************************************************************/
/**
*
* This macro checks if the XADC device is in External Mux mode.
*
* @param InstancePtr is a pointer to the XAdcPs instance.
*
* @return
* - TRUE if the device is in External Mux Mode.
* - FALSE if the device is NOT in External Mux Mode.
*
* @note C-Style signature:
* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
*
*****************************************************************************/
#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \
(((XAdcPs_ReadInternalReg(InstancePtr, \
XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \
TRUE : FALSE))
/****************************************************************************/
/**
*
* This macro converts XADC Raw Data to Temperature(centigrades).
*
* @param AdcData is the Raw ADC Data from XADC.
*
* @return The Temperature in centigrades.
*
* @note C-Style signature:
* float XAdcPs_RawToTemperature(u32 AdcData);
*
*****************************************************************************/
#define XAdcPs_RawToTemperature(AdcData) \
((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
/****************************************************************************/
/**
*
* This macro converts XADC/ADC Raw Data to Voltage(volts).
*
* @param AdcData is the XADC/ADC Raw Data.
*
* @return The Voltage in volts.
*
* @note C-Style signature:
* float XAdcPs_RawToVoltage(u32 AdcData);
*
*****************************************************************************/
#define XAdcPs_RawToVoltage(AdcData) \
((((float)(AdcData))* (3.0f))/65536.0f)
/****************************************************************************/
/**
*
* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
*
* @param Temperature is the Temperature in centigrades to be
* converted to XADC/ADC Raw Data.
*
* @return The XADC/ADC Raw Data.
*
* @note C-Style signature:
* int XAdcPs_TemperatureToRaw(float Temperature);
*
*****************************************************************************/
#define XAdcPs_TemperatureToRaw(Temperature) \
((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
/****************************************************************************/
/**
*
* This macro converts Voltage in Volts to XADC/ADC Raw Data.
*
* @param Voltage is the Voltage in volts to be converted to
* XADC/ADC Raw Data.
*
* @return The XADC/ADC Raw Data.
*
* @note C-Style signature:
* int XAdcPs_VoltageToRaw(float Voltage);
*
*****************************************************************************/
#define XAdcPs_VoltageToRaw(Voltage) \
((int)((Voltage)*65536.0f/3.0f))
/****************************************************************************/
/**
*
* This macro is used for writing to the XADC Registers using the
* command FIFO.
*
* @param InstancePtr is a pointer to the XAdcPs instance.
* @param Data is the value to be written to XADC register.
*
* @return None.
*
* @note C-Style signature:
* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
*
*****************************************************************************/
#define XAdcPs_WriteFifo(InstancePtr, Data) \
XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XADCPS_CMDFIFO_OFFSET, Data);
/****************************************************************************/
/**
*
* This macro is used for reading from the XADC Registers using the
* data FIFO.
*
* @param InstancePtr is a pointer to the XAdcPs instance.
*
* @return Data read from the FIFO
*
* @note C-Style signature:
* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
*
*****************************************************************************/
#define XAdcPs_ReadFifo(InstancePtr) \
XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XADCPS_RDFIFO_OFFSET);
/************************** Function Prototypes *****************************/
/**
* Functions in xadcps_sinit.c
*/
#ifndef SDT
XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
#else
XAdcPs_Config *XAdcPs_LookupConfig(u32 BaseAddress);
#endif
/**
* Functions in xadcps.c
*/
int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
XAdcPs_Config *ConfigPtr,
u32 EffectiveAddr);
void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data);
u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr);
u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr);
void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data);
u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr);
void XAdcPs_Reset(XAdcPs *InstancePtr);
u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
u8 Channel,
int IncreaseAcqCycles,
int IsEventMode,
int IsDifferentialMode);
void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
/**
* Functions in xadcps_selftest.c
*/
int XAdcPs_SelfTest(XAdcPs *InstancePtr);
/**
* Functions in xadcps_intr.c
*/
void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps_hw.h
+478
View File
@@ -0,0 +1,478 @@
/******************************************************************************
* Copyright (C) 2011 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xadcps_hw.h
* @addtogroup Overview
* @{
*
* This header file contains identifiers and basic driver functions (or
* macros) that can be used to access the XADC device through the Device
* Config Interface of the Zynq.
*
*
* Refer to the device specification for more information about this driver.
*
* @note None.
*
*
* <pre>
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------------
* 1.00a bss 12/22/11 First release based on the XPS/AXI xadc driver
* 1.03a bss 11/01/13 Modified macros to use correct Register offsets
* CR#749687
* 2.6 aad 11/02/20 Fix MISRAC Mandatory and Advisory errors.
*
* </pre>
*
*****************************************************************************/
#ifndef XADCPS_HW_H /* Prevent circular inclusions */
#define XADCPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions ****************************/
/**@name Register offsets of XADC in the Device Config
*
* The following constants provide access to each of the registers of the
* XADC device.
* @{
*/
#define XADCPS_CFG_OFFSET 0x00U /**< Configuration Register */
#define XADCPS_INT_STS_OFFSET 0x04U /**< Interrupt Status Register */
#define XADCPS_INT_MASK_OFFSET 0x08U /**< Interrupt Mask Register */
#define XADCPS_MSTS_OFFSET 0x0CU /**< Misc status register */
#define XADCPS_CMDFIFO_OFFSET 0x10U /**< Command FIFO Register */
#define XADCPS_RDFIFO_OFFSET 0x14U /**< Read FIFO Register */
#define XADCPS_MCTL_OFFSET 0x18U /**< Misc control register */
/* @} */
/** @name XADC Config Register Bit definitions
* @{
*/
#define XADCPS_CFG_ENABLE_MASK 0x80000000U /**< Enable access from PS mask */
#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000U /**< Command FIFO Threshold mask */
#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000U /**< Data FIFO Threshold mask */
#define XADCPS_CFG_WEDGE_MASK 0x00002000U /**< Write Edge Mask */
#define XADCPS_CFG_REDGE_MASK 0x00001000U /**< Read Edge Mask */
#define XADCPS_CFG_TCKRATE_MASK 0x00000300U /**< Clock freq control */
#define XADCPS_CFG_IGAP_MASK 0x0000001FU /**< Idle Gap between
* successive commands */
/* @} */
/** @name XADC Interrupt Status/Mask Register Bit definitions
*
* The definitions are same for the Interrupt Status Register and
* Interrupt Mask Register. They are defined only once.
* @{
*/
#define XADCPS_INTX_ALL_MASK 0x000003FFU /**< Alarm Signals Mask */
#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200U /**< CMD FIFO less than threshold */
#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100U /**< Data FIFO greater than threshold */
#define XADCPS_INTX_OT_MASK 0x00000080U /**< Over temperature Alarm Status */
#define XADCPS_INTX_ALM_ALL_MASK 0x0000007FU /**< Alarm Signals Mask */
#define XADCPS_INTX_ALM6_MASK 0x00000040U /**< Alarm 6 Mask */
#define XADCPS_INTX_ALM5_MASK 0x00000020U /**< Alarm 5 Mask */
#define XADCPS_INTX_ALM4_MASK 0x00000010U /**< Alarm 4 Mask */
#define XADCPS_INTX_ALM3_MASK 0x00000008U /**< Alarm 3 Mask */
#define XADCPS_INTX_ALM2_MASK 0x00000004U /**< Alarm 2 Mask */
#define XADCPS_INTX_ALM1_MASK 0x00000002U /**< Alarm 1 Mask */
#define XADCPS_INTX_ALM0_MASK 0x00000001U /**< Alarm 0 Mask */
/* @} */
/** @name XADC Miscellaneous Register Bit definitions
* @{
*/
#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000U /**< Command FIFO Level mask */
#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000U /**< Data FIFO Level Mask */
#define XADCPS_MSTS_CFIFOF_MASK 0x00000800U /**< Command FIFO Full Mask */
#define XADCPS_MSTS_CFIFOE_MASK 0x00000400U /**< Command FIFO Empty Mask */
#define XADCPS_MSTS_DFIFOF_MASK 0x00000200U /**< Data FIFO Full Mask */
#define XADCPS_MSTS_DFIFOE_MASK 0x00000100U /**< Data FIFO Empty Mask */
#define XADCPS_MSTS_OT_MASK 0x00000080U /**< Over Temperature Mask */
#define XADCPS_MSTS_ALM_MASK 0x0000007FU /**< Alarms Mask */
/* @} */
/** @name XADC Miscellaneous Control Register Bit definitions
* @{
*/
#define XADCPS_MCTL_RESET_MASK 0x00000010U /**< Reset XADC */
#define XADCPS_MCTL_FLUSH_MASK 0x00000001U /**< Flush the FIFOs */
/* @} */
/**@name Internal Register offsets of the XADC
*
* The following constants provide access to each of the internal registers of
* the XADC device.
* @{
*/
/*
* XADC Internal Channel Registers
*/
#define XADCPS_TEMP_OFFSET 0x00U /**< On-chip Temperature Reg */
#define XADCPS_VCCINT_OFFSET 0x01U /**< On-chip VCCINT Data Reg */
#define XADCPS_VCCAUX_OFFSET 0x02U /**< On-chip VCCAUX Data Reg */
#define XADCPS_VPVN_OFFSET 0x03U /**< ADC out of VP/VN */
#define XADCPS_VREFP_OFFSET 0x04U /**< On-chip VREFP Data Reg */
#define XADCPS_VREFN_OFFSET 0x05U /**< On-chip VREFN Data Reg */
#define XADCPS_VBRAM_OFFSET 0x06U /**< On-chip VBRAM , 7 Series */
#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08U /**< ADC A Supply Offset Reg */
#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09U /**< ADC A Offset Data Reg */
#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0AU /**< ADC A Gain Error Reg */
#define XADCPS_VCCPINT_OFFSET 0x0DU /**< On-chip VCCPINT Reg, Zynq */
#define XADCPS_VCCPAUX_OFFSET 0x0EU /**< On-chip VCCPAUX Reg, Zynq */
#define XADCPS_VCCPDRO_OFFSET 0x0FU /**< On-chip VCCPDRO Reg, Zynq */
/*
* XADC External Channel Registers
*/
#define XADCPS_AUX00_OFFSET 0x10U /**< ADC out of VAUXP0/VAUXN0 */
#define XADCPS_AUX01_OFFSET 0x11U /**< ADC out of VAUXP1/VAUXN1 */
#define XADCPS_AUX02_OFFSET 0x12U /**< ADC out of VAUXP2/VAUXN2 */
#define XADCPS_AUX03_OFFSET 0x13U /**< ADC out of VAUXP3/VAUXN3 */
#define XADCPS_AUX04_OFFSET 0x14U /**< ADC out of VAUXP4/VAUXN4 */
#define XADCPS_AUX05_OFFSET 0x15U /**< ADC out of VAUXP5/VAUXN5 */
#define XADCPS_AUX06_OFFSET 0x16U /**< ADC out of VAUXP6/VAUXN6 */
#define XADCPS_AUX07_OFFSET 0x17U /**< ADC out of VAUXP7/VAUXN7 */
#define XADCPS_AUX08_OFFSET 0x18U /**< ADC out of VAUXP8/VAUXN8 */
#define XADCPS_AUX09_OFFSET 0x19U /**< ADC out of VAUXP9/VAUXN9 */
#define XADCPS_AUX10_OFFSET 0x1AU /**< ADC out of VAUXP10/VAUXN10 */
#define XADCPS_AUX11_OFFSET 0x1BU /**< ADC out of VAUXP11/VAUXN11 */
#define XADCPS_AUX12_OFFSET 0x1CU /**< ADC out of VAUXP12/VAUXN12 */
#define XADCPS_AUX13_OFFSET 0x1DU /**< ADC out of VAUXP13/VAUXN13 */
#define XADCPS_AUX14_OFFSET 0x1EU /**< ADC out of VAUXP14/VAUXN14 */
#define XADCPS_AUX15_OFFSET 0x1FU /**< ADC out of VAUXP15/VAUXN15 */
/*
* XADC Registers for Maximum/Minimum data captured for the
* on chip Temperature/VCCINT/VCCAUX data.
*/
#define XADCPS_MAX_TEMP_OFFSET 0x20U /**< Max Temperature Reg */
#define XADCPS_MAX_VCCINT_OFFSET 0x21U /**< Max VCCINT Register */
#define XADCPS_MAX_VCCAUX_OFFSET 0x22U /**< Max VCCAUX Register */
#define XADCPS_MAX_VCCBRAM_OFFSET 0x23U /**< Max BRAM Register, 7 series */
#define XADCPS_MIN_TEMP_OFFSET 0x24U /**< Min Temperature Reg */
#define XADCPS_MIN_VCCINT_OFFSET 0x25U /**< Min VCCINT Register */
#define XADCPS_MIN_VCCAUX_OFFSET 0x26U /**< Min VCCAUX Register */
#define XADCPS_MIN_VCCBRAM_OFFSET 0x27U /**< Min BRAM Register, 7 series */
#define XADCPS_MAX_VCCPINT_OFFSET 0x28U /**< Max VCCPINT Register, Zynq */
#define XADCPS_MAX_VCCPAUX_OFFSET 0x29U /**< Max VCCPAUX Register, Zynq */
#define XADCPS_MAX_VCCPDRO_OFFSET 0x2AU /**< Max VCCPDRO Register, Zynq */
#define XADCPS_MIN_VCCPINT_OFFSET 0x2CU /**< Min VCCPINT Register, Zynq */
#define XADCPS_MIN_VCCPAUX_OFFSET 0x2DU /**< Min VCCPAUX Register, Zynq */
#define XADCPS_MIN_VCCPDRO_OFFSET 0x2EU /**< Min VCCPDRO Register,Zynq */
/* Undefined 0x2F to 0x3E */
#define XADCPS_FLAG_OFFSET 0x3FU /**< Flag Register */
/*
* XADC Configuration Registers
*/
#define XADCPS_CFR0_OFFSET 0x40U /**< Configuration Register 0 */
#define XADCPS_CFR1_OFFSET 0x41U /**< Configuration Register 1 */
#define XADCPS_CFR2_OFFSET 0x42U /**< Configuration Register 2 */
/* Test Registers 0x43 to 0x47 */
/*
* XADC Sequence Registers
*/
#define XADCPS_SEQ00_OFFSET 0x48U /**< Seq Reg 00 Adc Channel Selection */
#define XADCPS_SEQ01_OFFSET 0x49U /**< Seq Reg 01 Adc Channel Selection */
#define XADCPS_SEQ02_OFFSET 0x4AU /**< Seq Reg 02 Adc Average Enable */
#define XADCPS_SEQ03_OFFSET 0x4BU /**< Seq Reg 03 Adc Average Enable */
#define XADCPS_SEQ04_OFFSET 0x4CU /**< Seq Reg 04 Adc Input Mode Select */
#define XADCPS_SEQ05_OFFSET 0x4DU /**< Seq Reg 05 Adc Input Mode Select */
#define XADCPS_SEQ06_OFFSET 0x4EU /**< Seq Reg 06 Adc Acquisition Select */
#define XADCPS_SEQ07_OFFSET 0x4FU /**< Seq Reg 07 Adc Acquisition Select */
/*
* XADC Alarm Threshold/Limit Registers (ATR)
*/
#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50U /**< Temp Upper Alarm Register */
#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51U /**< VCCINT Upper Alarm Reg */
#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52U /**< VCCAUX Upper Alarm Reg */
#define XADCPS_ATR_OT_UPPER_OFFSET 0x53U /**< Over Temp Upper Alarm Reg */
#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54U /**< Temp Lower Alarm Register */
#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55U /**< VCCINT Lower Alarm Reg */
#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56U /**< VCCAUX Lower Alarm Reg */
#define XADCPS_ATR_OT_LOWER_OFFSET 0x57U /**< Over Temp Lower Alarm Reg */
#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58U /**< VBRAM Upper Alarm, 7 series */
#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59U /**< VCCPINT Upper Alarm, Zynq */
#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5AU /**< VCCPAUX Upper Alarm, Zynq */
#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5BU /**< VCCPDRO Upper Alarm, Zynq */
#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5CU /**< VRBAM Lower Alarm, 7 Series */
#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5DU /**< VCCPINT Lower Alarm, Zynq */
#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5EU /**< VCCPAUX Lower Alarm, Zynq */
#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5FU /**< VCCPDRO Lower Alarm, Zynq */
/* Undefined 0x60 to 0x7F */
/*@}*/
/**
* @name Configuration Register 0 (CFR0) mask(s)
* @{
*/
#define XADCPS_CFR0_CAL_AVG_MASK 0x00008000U /**< Averaging enable Mask */
#define XADCPS_CFR0_AVG_VALID_MASK 0x00003000U /**< Averaging bit Mask */
#define XADCPS_CFR0_AVG1_MASK 0x00000000U /**< No Averaging */
#define XADCPS_CFR0_AVG16_MASK 0x00001000U /**< Average 16 samples */
#define XADCPS_CFR0_AVG64_MASK 0x00002000U /**< Average 64 samples */
#define XADCPS_CFR0_AVG256_MASK 0x00003000U /**< Average 256 samples */
#define XADCPS_CFR0_AVG_SHIFT 12U /**< Averaging bits shift */
#define XADCPS_CFR0_MUX_MASK 0x00000800U /**< External Mask Enable */
#define XADCPS_CFR0_DU_MASK 0x00000400U /**< Bipolar/Unipolar mode */
#define XADCPS_CFR0_EC_MASK 0x00000200U /**< Event driven/
* Continuous mode selection
*/
#define XADCPS_CFR0_ACQ_MASK 0x00000100U /**< Add acquisition by 6 ADCCLK */
#define XADCPS_CFR0_CHANNEL_MASK 0x0000001FU /**< Channel number bit Mask */
/*@}*/
/**
* @name Configuration Register 1 (CFR1) mask(s)
* @{
*/
#define XADCPS_CFR1_SEQ_VALID_MASK 0x0000F000U /**< Sequence bit Mask */
#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x00000000U /**< Default Safe Mode */
#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x00001000U /**< Onepass through Seq */
#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x00002000U /**< Continuous Cycling Seq */
#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x00003000U /**< Single channel - No Seq */
#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x00004000U /**< Simulataneous Sampling Mask */
#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x00008000U /**< Independent Mode */
#define XADCPS_CFR1_SEQ_SHIFT 12U /**< Sequence bit shift */
#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x00000800U /**< Alm 6 - VCCPDRO, Zynq */
#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x00000400U /**< Alm 5 - VCCPAUX, Zynq */
#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x00000200U /**< Alm 4 - VCCPINT, Zynq */
#define XADCPS_CFR1_ALM_VBRAM_MASK 0x00000100U /**< Alm 3 - VBRAM, 7 series */
#define XADCPS_CFR1_CAL_VALID_MASK 0x000000F0U /**< Valid Calibration Mask */
#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x00000080U /**< Calibration 3 -Power
Supply Gain/Offset
Enable */
#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x00000040U /**< Calibration 2 -Power
Supply Offset Enable */
#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x00000020U /**< Calibration 1 -ADC Gain
Offset Enable */
#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x00000010U /**< Calibration 0 -ADC Offset
Enable */
#define XADCPS_CFR1_CAL_DISABLE_MASK 0x00000000U /**< No Calibration */
#define XADCPS_CFR1_ALM_ALL_MASK 0x00000F0FU /**< Mask for all alarms */
#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x00000008U /**< Alarm 2 - VCCAUX Enable */
#define XADCPS_CFR1_ALM_VCCINT_MASK 0x00000004U /**< Alarm 1 - VCCINT Enable */
#define XADCPS_CFR1_ALM_TEMP_MASK 0x00000002U /**< Alarm 0 - Temperature */
#define XADCPS_CFR1_OT_MASK 0x00000001U /**< Over Temperature Enable */
/*@}*/
/**
* @name Configuration Register 2 (CFR2) mask(s)
* @{
*/
#define XADCPS_CFR2_CD_VALID_MASK 0xFF00U /**<Clock Divisor bit Mask */
#define XADCPS_CFR2_CD_SHIFT 8U /**<Num of shift on division */
#define XADCPS_CFR2_CD_MIN 8U /**<Minimum value of divisor */
#define XADCPS_CFR2_CD_MAX 255U /**<Maximum value of divisor */
#define XADCPS_CFR2_CD_MIN 8U /**<Minimum value of divisor */
#define XADCPS_CFR2_PD_MASK 0x0030U /**<Power Down Mask */
#define XADCPS_CFR2_PD_XADC_MASK 0x0030U /**<Power Down XADC Mask */
#define XADCPS_CFR2_PD_ADC1_MASK 0x0020U /**<Power Down ADC1 Mask */
#define XADCPS_CFR2_PD_SHIFT 4U /**<Power Down Shift */
/*@}*/
/**
* @name Sequence Register (SEQ) Bit Definitions
* @{
*/
#define XADCPS_SEQ_CH_CALIB 0x00000001U /**< ADC Calibration Channel */
#define XADCPS_SEQ_CH_VCCPINT 0x00000020U /**< VCCPINT, Zynq Only */
#define XADCPS_SEQ_CH_VCCPAUX 0x00000040U /**< VCCPAUX, Zynq Only */
#define XADCPS_SEQ_CH_VCCPDRO 0x00000080U /**< VCCPDRO, Zynq Only */
#define XADCPS_SEQ_CH_TEMP 0x00000100U /**< On Chip Temperature Channel */
#define XADCPS_SEQ_CH_VCCINT 0x00000200U /**< VCCINT Channel */
#define XADCPS_SEQ_CH_VCCAUX 0x00000400U /**< VCCAUX Channel */
#define XADCPS_SEQ_CH_VPVN 0x00000800U /**< VP/VN analog inputs Channel */
#define XADCPS_SEQ_CH_VREFP 0x00001000U /**< VREFP Channel */
#define XADCPS_SEQ_CH_VREFN 0x00002000U /**< VREFN Channel */
#define XADCPS_SEQ_CH_VBRAM 0x00004000U /**< VBRAM Channel, 7 series */
#define XADCPS_SEQ_CH_AUX00 0x00010000U /**< 1st Aux Channel */
#define XADCPS_SEQ_CH_AUX01 0x00020000U /**< 2nd Aux Channel */
#define XADCPS_SEQ_CH_AUX02 0x00040000U /**< 3rd Aux Channel */
#define XADCPS_SEQ_CH_AUX03 0x00080000U /**< 4th Aux Channel */
#define XADCPS_SEQ_CH_AUX04 0x00100000U /**< 5th Aux Channel */
#define XADCPS_SEQ_CH_AUX05 0x00200000U /**< 6th Aux Channel */
#define XADCPS_SEQ_CH_AUX06 0x00400000U /**< 7th Aux Channel */
#define XADCPS_SEQ_CH_AUX07 0x00800000U /**< 8th Aux Channel */
#define XADCPS_SEQ_CH_AUX08 0x01000000U /**< 9th Aux Channel */
#define XADCPS_SEQ_CH_AUX09 0x02000000U /**< 10th Aux Channel */
#define XADCPS_SEQ_CH_AUX10 0x04000000U /**< 11th Aux Channel */
#define XADCPS_SEQ_CH_AUX11 0x08000000U /**< 12th Aux Channel */
#define XADCPS_SEQ_CH_AUX12 0x10000000U /**< 13th Aux Channel */
#define XADCPS_SEQ_CH_AUX13 0x20000000U /**< 14th Aux Channel */
#define XADCPS_SEQ_CH_AUX14 0x40000000U /**< 15th Aux Channel */
#define XADCPS_SEQ_CH_AUX15 0x80000000U /**< 16th Aux Channel */
#define XADCPS_SEQ00_CH_VALID_MASK 0x7FE1U /**< Mask for the valid channels */
#define XADCPS_SEQ01_CH_VALID_MASK 0xFFFFU /**< Mask for the valid channels */
#define XADCPS_SEQ02_CH_VALID_MASK 0x7FE0U /**< Mask for the valid channels */
#define XADCPS_SEQ03_CH_VALID_MASK 0xFFFFU /**< Mask for the valid channels */
#define XADCPS_SEQ04_CH_VALID_MASK 0x0800U /**< Mask for the valid channels */
#define XADCPS_SEQ05_CH_VALID_MASK 0xFFFFU /**< Mask for the valid channels */
#define XADCPS_SEQ06_CH_VALID_MASK 0x0800U /**< Mask for the valid channels */
#define XADCPS_SEQ07_CH_VALID_MASK 0xFFFFU /**< Mask for the valid channels */
#define XADCPS_SEQ_CH_AUX_SHIFT 16U /**< Shift for the Aux Channel */
/*@}*/
/**
* @name OT Upper Alarm Threshold Register Bit Definitions
* @{
*/
#define XADCPS_ATR_OT_UPPER_ENB_MASK 0x000FU /**< Mask for OT enable */
#define XADCPS_ATR_OT_UPPER_VAL_MASK 0xFFF0U /**< Mask for OT value */
#define XADCPS_ATR_OT_UPPER_VAL_SHIFT 4U /**< Shift for OT value */
#define XADCPS_ATR_OT_UPPER_ENB_VAL 0x0003U /**< Value for OT enable */
#define XADCPS_ATR_OT_UPPER_VAL_MAX 0x0FFFU /**< Max OT value */
/*@}*/
/**
* @name JTAG DRP Bit Definitions
* @{
*/
#define XADCPS_JTAG_DATA_MASK 0x0000FFFFU /**< Mask for the Data */
#define XADCPS_JTAG_ADDR_MASK 0x03FF0000U /**< Mask for the Addr */
#define XADCPS_JTAG_ADDR_SHIFT 16U /**< Shift for the Addr */
#define XADCPS_JTAG_CMD_MASK 0x3C000000U /**< Mask for the Cmd */
#define XADCPS_JTAG_CMD_WRITE_MASK 0x08000000U /**< Mask for CMD Write */
#define XADCPS_JTAG_CMD_READ_MASK 0x04000000U /**< Mask for CMD Read */
#define XADCPS_JTAG_CMD_SHIFT 26U /**< Shift for the Cmd */
/*@}*/
/** @name Unlock Register Definitions
* @{
*/
#define XADCPS_UNLK_OFFSET 0x034U /**< Unlock Register */
#define XADCPS_UNLK_VALUE 0x757BDF0DU /**< Unlock Value */
/* @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* Read a register of the XADC device. This macro provides register
* access to all registers using the register offsets defined above.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset is the offset of the register to read.
*
* @return The contents of the register.
*
* @note C-style Signature:
* u32 XAdcPs_ReadReg(u32 BaseAddress, u32 RegOffset);
*
******************************************************************************/
#define XAdcPs_ReadReg(BaseAddress, RegOffset) \
(Xil_In32((BaseAddress) + (RegOffset)))
/*****************************************************************************/
/**
*
* Write a register of the XADC device. This macro provides
* register access to all registers using the register offsets defined above.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset is the offset of the register to write.
* @param Data is the value to write to the register.
*
* @return None.
*
* @note C-style Signature:
* void XAdcPs_WriteReg(u32 BaseAddress,
* u32 RegOffset,u32 Data)
*
******************************************************************************/
#define XAdcPs_WriteReg(BaseAddress, RegOffset, Data) \
(Xil_Out32((BaseAddress) + (RegOffset), (Data)))
/************************** Function Prototypes ******************************/
/*****************************************************************************/
/**
*
* Formats the data to be written to the the XADC registers.
*
* @param RegOffset is the offset of the Register
* @param Data is the data to be written to the Register if it is
* a write.
* @param ReadWrite specifies whether it is a Read or a Write.
* Use 0 for Read, 1 for Write.
*
* @return None.
*
* @note C-style Signature:
* void XAdcPs_FormatWriteData(u32 RegOffset,
* u16 Data, int ReadWrite)
*
******************************************************************************/
#define XAdcPs_FormatWriteData(RegOffset, Data, ReadWrite) \
((ReadWrite ? XADCPS_JTAG_CMD_WRITE_MASK : XADCPS_JTAG_CMD_READ_MASK ) | \
((RegOffset << XADCPS_JTAG_ADDR_SHIFT) & XADCPS_JTAG_ADDR_MASK) | \
(Data & XADCPS_JTAG_DATA_MASK))
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro. */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbasic_types.h
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/******************************************************************************
* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xbasic_types.h
*
*
* @note Dummy File for backwards compatibility
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility
* 7.0 aru 01/21/19 Modified the typedef of u32,u16,u8
* 7.0 aru 02/06/19 Included stdint.h and stddef.h
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XBASIC_TYPES_H /* prevent circular inclusions */
#define XBASIC_TYPES_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stddef.h>
/** @name Legacy types
* Deprecated legacy types.
* @{
*/
typedef uint8_t Xuint8; /**< unsigned 8-bit */
typedef char Xint8; /**< signed 8-bit */
typedef uint16_t Xuint16; /**< unsigned 16-bit */
typedef short Xint16; /**< signed 16-bit */
typedef uint32_t Xuint32; /**< unsigned 32-bit */
typedef long Xint32; /**< signed 32-bit */
typedef float Xfloat32; /**< 32-bit floating point */
typedef double Xfloat64; /**< 64-bit double precision FP */
typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */
#if !defined __XUINT64__
typedef struct
{
Xuint32 Upper;
Xuint32 Lower;
} Xuint64;
#endif
/** @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XIL_TYPES_H
typedef Xuint32 u32;
typedef Xuint16 u16;
typedef Xuint8 u8;
#endif
#else
#include <linux/types.h>
#endif
#ifndef TRUE
# define TRUE 1U
#endif
#ifndef FALSE
# define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
/*
* Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
* Please use NULL, TRUE and FALSE
*/
#define XNULL NULL
#define XTRUE TRUE
#define XFALSE FALSE
/*
* This file is deprecated and users
* should use xil_types.h and xil_assert.h\n\r
*/
#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
#warning Please refer the Standalone BSP UG647 for further details
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
*@endcond
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h
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/******************************************************************************
* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcoresightpsdcc.h
* @addtogroup coresightps_dcc Overview
* @{
* @details
*
* CoreSight driver component.
*
* The coresight is a part of debug communication channel (DCC) group. Jtag UART
* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an
* ARM target in XSDB console before running the jtag terminal command. Using the
* coresight driver component, the output stream can be directed to a log file.
*
* @note None.
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.00 kvn 02/14/15 First release
* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
* kvn 08/18/15 Modified Makefile according to compiler changes.
* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile
* for MB BSPs. Instead it throws up a warning. This
* fixes the CR#953056.
* 1.5 sne 01/19/19 Fixed MISRA-C Violations CR#1025101.
*
* </pre>
*
******************************************************************************/
/***************************** Include Files *********************************/
#ifndef XCORESIGHTPSDCC_H /* prevent circular inclusions */
#define XCORESIGHTPSDCC_H /* by using protection macros */
#ifndef __MICROBLAZE__
#include <xil_types.h>
void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data);
u8 XCoresightPs_DccRecvByte(u32 BaseAddress);
#endif
#endif
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcortexa9.h
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/******************************************************************************
* Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XIL_XCORTEXA9_H_ /* prevent circular inclusions */
#define XIL_XCORTEXA9_H_ /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
/**************************** Type Definitions ******************************/
typedef struct {
u32 CpuFreq;
} XCortexa9_Config;
#endif /* XIL_XCORTEXA9_H_ */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcortexa9_config.h
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/******************************************************************************
* Copyright (c) 2021-2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XIL_XCORTEXA9_CONFIG_H_ /* prevent circular inclusions */
#define XIL_XCORTEXA9_CONFIG_H_ /* by using protection macros */
/***************************** Include Files ********************************/
#include "xcortexa9.h"
/************************** Variable Definitions ****************************/
extern XCortexa9_Config XCortexa9_ConfigTable;
/***************** Macros (Inline Functions) Definitions ********************/
#define XGet_CpuFreq() XCortexa9_ConfigTable.CpuFreq
#endif /* XIL_XCORTEXA9_CONFIG_H_ */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h
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/******************************************************************************
* Copyright (C) 2011 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xcpu_cortexa9.h
* @addtogroup cpu_cortexa9 Overview
* @{
* @details
*
* dummy file
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------------
* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID
* parameter of cpu_cortexa9 in xparameters.h
# 2.7 mus 07/03/18 Updated tcl to not to add default flags forcefully into
# extra compiler flags. Now, user can remove default flags
# from extra compiler flags. It fixes CR#998768.
******************************************************************************/
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xddrps.h
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/*******************************************************************************
* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
/******************************************************************************/
/**
*
* @file xddrps.h
* @addtogroup ddrps Overview
* @{
* @details
*
* The Xilinx DdrPs driver. This driver supports the Xilinx ddrps
* IP core.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 nsk 08/06/15 First Release
* 1.0 nsk 08/20/15 Updated define_addr_params in ddrps.tcl
* to support PBD Designs (CR #876857)
*
* </pre>
*
*******************************************************************************/
#ifndef XDDRPS_H_
/* Prevent circular inclusions by using protection macros. */
#define XDDRPS_H_
/******************************* Include Files ********************************/
#endif /* XDDRPS_H_ */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdebug.h
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/******************************************************************************
* Copyright (C) 2002 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
#ifndef XDEBUG
#define XDEBUG
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_printf.h"
#if defined(DEBUG) && !defined(NDEBUG)
#ifndef XDEBUG_WARNING
#define XDEBUG_WARNING
#warning DEBUG is enabled
#endif
int printf(const char *format, ...);
#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */
#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */
#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */
#define XDBG_DEBUG_FIFO_REG 0x00000100U /* display register reads/writes */
#define XDBG_DEBUG_FIFO_RX 0x00000101U /* receive debug messages */
#define XDBG_DEBUG_FIFO_TX 0x00000102U /* transmit debug messages */
#define XDBG_DEBUG_FIFO_ALL 0x0000010FU /* all fifo debug messages */
#define XDBG_DEBUG_TEMAC_REG 0x00000400U /* display register reads/writes */
#define XDBG_DEBUG_TEMAC_RX 0x00000401U /* receive debug messages */
#define XDBG_DEBUG_TEMAC_TX 0x00000402U /* transmit debug messages */
#define XDBG_DEBUG_TEMAC_ALL 0x0000040FU /* all temac debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800U /* receive debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801U /* transmit debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802U /* ioctl debug messages */
#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803U /* debug msg for other routines */
#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080FU /* all temac adapter debug messages */
#define xdbg_current_types (XDBG_DEBUG_GENERAL | XDBG_DEBUG_ERROR | XDBG_DEBUG_TEMAC_REG | XDBG_DEBUG_FIFO_RX | XDBG_DEBUG_FIFO_TX | XDBG_DEBUG_FIFO_REG)
#define xdbg_stmnt(x) x
/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
* macros that accept variable number of arguments
*/
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
#else /* ANSI Syntax */
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
#endif
#define xdbg_exception_printf(type, ...) (((type) & xdbg_current_types) ? xil_printf (__VA_ARGS__) : 0)
#else /* defined(DEBUG) && !defined(NDEBUG) */
#define xdbg_stmnt(x) /**< Debug statement */
/* See VxWorks comments above */
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
#define xdbg_printf(type, args...)
#else /* ANSI Syntax */
#define xdbg_printf(...) /**< Debug printf */
#endif
#endif /* defined(DEBUG) && !defined(NDEBUG) */
#ifdef __cplusplus
}
#endif
#endif /* XDEBUG */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg.h
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/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xdevcfg.h
* @addtogroup devcfg Overview
* @{
* @details
*
* The is the main header file for the Device Configuration Interface of the Zynq
* device. The device configuration interface has three main functionality.
* 1. AXI-PCAP
* 2. Security Policy
* 3. XADC
* This current version of the driver supports only the AXI-PCAP and Security
* Policy blocks. There is a separate driver for XADC.
*
* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream.
* DMA embedded in the AXI PCAP provides the master interface to
* the Device configuration block for any DMA transfers. The data transfer can
* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip
* RAM/DDR/peripheral memory).
*
* The current driver only supports the downloading the FPGA bitstream and
* readback of the decrypted image (sort of loopback).
* The driver does not know what information needs to be written to the FPGA to
* readback FPGA configuration register or memory data. The application above the
* driver should take care of creating the data that needs to be downloaded to
* the FPGA so that the bitstream can be readback.
* This driver also does not support the reading of the internal registers of the
* PCAP. The driver has no knowledge of the PCAP internals.
*
* <b> Initialization and Configuration </b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate with the Device Configuration device.
*
* XDcfg_CfgInitialize() API is used to initialize the Device Configuration
* Interface. The user needs to first call the XDcfg_LookupConfig() API which
* returns the Configuration structure pointer which is passed as a parameter to
* the XDcfg_CfgInitialize() API.
*
* <b>Interrupts</b>
* The Driver implements an interrupt handler to support the interrupts provided
* by this interface.
*
* <b> Threads </b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b> Asserts </b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b> Building the driver </b>
*
* The XDcfg driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
*
* <br><br>
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 1.00a hvm 02/07/11 First release
* 2.00a nm 05/31/12 Updated the driver for CR 660835 so that input length for
* source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
* APIs is words (32 bit) and not bytes.
* Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
* to add information that 2 LSBs of the Source/Destination
* address when equal to 2�b01 indicate the last DMA command
* of an overall transfer.
* Destination Address passed to this API for secure transfers
* instead of using 0xFFFFFFFF for CR 662197. This issue was
* resulting in the failure of secure transfers of
* non-bitstream images.
* 2.01a nm 07/07/12 Updated the XDcfg_IntrClear function to directly
* set the mask instead of oring it with the
* value read from the interrupt status register
* Added defines for the PS Version bits,
* removed the FIFO Flush bits from the
* Miscellaneous Control Reg.
* Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
* and XDcfg_SelectPcapInterface APIs for CR 643295
* The user has to call the XDcfg_SelectIcapInterface API
* for the PL reconfiguration using AXI HwIcap.
* Updated the XDcfg_Transfer API to clear the
* QUARTER_PCAP_RATE_EN bit in the control register for
* non secure writes for CR 675543.
* 2.02a nm 01/31/13 Fixed CR# 679335.
* Added Setting and Clearing the internal PCAP loopback.
* Removed code for enabling/disabling AES engine as BootROM
* locks down this setting.
* Fixed CR# 681976.
* Skip Checking the PCFG_INIT in case of non-secure DMA
* loopback.
* Fixed CR# 699558.
* XDcfg_Transfer fails to transfer data in loopback mode.
* Fixed CR# 701348.
* Peripheral test fails with Running
* DcfgSelfTestExample() in SECURE bootmode.
* 2.03a nm 04/19/13 Fixed CR# 703728.
* Updated the register definitions as per the latest TRM
* version UG585 (v1.4) November 16, 2012.
* 3.0 adk 10/12/13 Updated as per the New Tcl API's
* 3.0 kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
* 3.2 sb 08/25/14 Fixed XDcfg_PcapReadback() function
* updated driver code with != instead of ==,
* while checking for Interrupt Status with DMA and
* PCAP Done Mask
* ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
* XDCFG_INT_STS_OFFSET) &
* XDCFG_IXR_D_P_DONE_MASK) !=
* XDCFG_IXR_D_P_DONE_MASK);
* A new example has been added to read back the
* configuration registers from the PL region.
* xdevcfg_reg_readback_example.c
* 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/10/17 Modified filename tag in interrupt and polled examples
* to include them in doxygen examples.
* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros
* definitions of devcfg in xparameters.h
* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
#ifndef XDCFG_H /* prevent circular inclusions */
#define XDCFG_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xdevcfg_hw.h"
#include "xstatus.h"
#include "xil_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/* Types of PCAP transfers */
#define XDCFG_NON_SECURE_PCAP_WRITE 1
#define XDCFG_SECURE_PCAP_WRITE 2
#define XDCFG_PCAP_READBACK 3
#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4
#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5
/**************************** Type Definitions *******************************/
/**
* The handler data type allows the user to define a callback function to
* respond to interrupt events in the system. This function is executed
* in interrupt context, so amount of processing should be minimized.
*
* @param CallBackRef is the callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* unimportant to the driver component, so it is a void pointer.
* @param Status is the Interrupt status of the XDcfg device.
*/
typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status);
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddr; /**< Base address of the device */
#ifdef SDT
u32 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XDcfg_Config;
/**
* The XDcfg driver instance data.
*/
typedef struct {
XDcfg_Config Config; /**< Hardware Configuration */
u32 IsReady; /**< Device is initialized and ready */
u32 IsStarted; /**< Device Configuration Interface
* is running
*/
XDcfg_IntrHandler StatusHandler; /* Event handler function */
void *CallBackRef; /* Callback reference for event handler */
} XDcfg;
/****************************************************************************/
/**
*
* Unlock the Device Config Interface block.
*
* @param InstancePtr is a pointer to the instance of XDcfg driver.
*
* @return None.
*
* @note C-style signature:
* void XDcfg_Unlock(XDcfg* InstancePtr)
*
*****************************************************************************/
#define XDcfg_Unlock(InstancePtr) \
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \
XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA)
/****************************************************************************/
/**
*
* Get the version number of the PS from the Miscellaneous Control Register.
*
* @param InstancePtr is a pointer to the instance of XDcfg driver.
*
* @return Version of the PS.
*
* @note C-style signature:
* void XDcfg_GetPsVersion(XDcfg* InstancePtr)
*
*****************************************************************************/
#define XDcfg_GetPsVersion(InstancePtr) \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
XDCFG_MCTRL_OFFSET)) & \
XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \
XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT
/****************************************************************************/
/**
*
* Read the multiboot config register value.
*
* @param InstancePtr is a pointer to the instance of XDcfg driver.
*
* @return None.
*
* @note C-style signature:
* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr)
*
*****************************************************************************/
#define XDcfg_ReadMultiBootConfig(InstancePtr) \
XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \
XDCFG_MULTIBOOT_ADDR_OFFSET)
/****************************************************************************/
/**
*
* Selects ICAP interface for reconfiguration after the initial configuration
* of the PL.
*
* @param InstancePtr is a pointer to the instance of XDcfg driver.
*
* @return None.
*
* @note C-style signature:
* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr)
*
*****************************************************************************/
#define XDcfg_SelectIcapInterface(InstancePtr) \
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
& ( ~XDCFG_CTRL_PCAP_PR_MASK)))
/****************************************************************************/
/**
*
* Selects PCAP interface for reconfiguration after the initial configuration
* of the PL.
*
* @param InstancePtr is a pointer to the instance of XDcfg driver.
*
* @return None.
*
* @note C-style signature:
* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr)
*
*****************************************************************************/
#define XDcfg_SelectPcapInterface(InstancePtr) \
XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \
((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \
| XDCFG_CTRL_PCAP_PR_MASK))
/************************** Function Prototypes ******************************/
/*
* Lookup configuration in xdevcfg_sinit.c.
*/
#ifndef SDT
XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId);
#else
XDcfg_Config *XDcfg_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Selftest function in xdevcfg_selftest.c
*/
int XDcfg_SelfTest(XDcfg *InstancePtr);
/*
* Interface functions in xdevcfg.c
*/
int XDcfg_CfgInitialize(XDcfg *InstancePtr,
XDcfg_Config *ConfigPtr, u32 EffectiveAddress);
void XDcfg_EnablePCAP(XDcfg *InstancePtr);
void XDcfg_DisablePCAP(XDcfg *InstancePtr);
void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask);
void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask);
u32 XDcfg_GetControlRegister(XDcfg *InstancePtr);
void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data);
u32 XDcfg_GetLockRegister(XDcfg *InstancePtr);
void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data);
u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr);
void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data);
u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr);
void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data);
u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr);
void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask);
u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr);
u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr);
void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr,
u32 SrcWordLength, u32 DestWordLength);
u32 XDcfg_Transfer(XDcfg *InstancePtr,
void *SourcePtr, u32 SrcWordLength,
void *DestPtr, u32 DestWordLength,
u32 TransferType);
/*
* Interrupt related function prototypes implemented in xdevcfg_intr.c
*/
void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask);
void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask);
u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr);
u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr);
void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask);
void XDcfg_InterruptHandler(XDcfg *InstancePtr);
void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc,
void *CallBackRef);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h
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/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xdevcfg_hw.h
* @addtogroup devcfg Overview
* @{
*
* This file contains the hardware interface to the Device Config Interface.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- ---------------------------------------------
* 1.00a hvm 02/07/11 First release
* 2.01a nm 08/01/12 Added defines for the PS Version bits,
* removed the FIFO Flush bits from the
* Miscellaneous Control Reg
* 2.03a nm 04/19/13 Fixed CR# 703728.
* Updated the register definitions as per the latest TRM
* version UG585 (v1.4) November 16, 2012.
* 2.04a kpc 10/07/13 Added function prototype.
* 3.00a kpc 25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
* 3.8 Nava 06/21/23 Added support for system device-tree flow.
* </pre>
*
******************************************************************************/
#ifndef XDCFG_HW_H /* prevent circular inclusions */
#define XDCFG_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
* Offsets of registers from the start of the device
* @{
*/
#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */
#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */
#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */
#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */
#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */
#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */
#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */
#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */
#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */
#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */
#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */
#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */
#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */
#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */
#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */
/* @} */
/** @name Control Register Bit definitions
* @{
*/
#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into
* Secure Reset
*/
#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to
* Reset FPGA
*/
#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */
#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */
#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */
#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data
* to FPGA every 4 PCAP
* cycles
*/
#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */
#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */
#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */
#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */
#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */
#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */
#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure
* Status mask
*/
#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive
* Debug Enable
*/
#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive
* Debug Enable
*/
#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug
* Enable
*/
#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug
* Enable
*/
#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */
/* @} */
/** @name Lock register bit definitions
* @{
*/
#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */
#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */
#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */
#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and
* USER_MODE
*/
#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks
* security config
* including: DAP_En,
* DBGEN,,
* NIDEN, SPNIEN
*/
/*@}*/
/** @name Config Register Bit definitions
* @{
*/
#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO
* Threshold Mask
*/
#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold
* Mask
*/
#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active
* clock edge
*/
#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active
* clock edge
*/
#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address
* increment mask
*/
#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination
* address increment
* mask
*/
/* @} */
/** @name Interrupt Status/Mask Register Bit definitions
* @{
*/
#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during
* HIZ
*/
#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration
* done
*/
#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */
#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during
* configuration
*/
#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration
* reset
*/
#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address
* or Data or response
* timeout
*/
#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response
* error
*/
#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or
* response timeout
*/
#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response
* error
*/
#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */
#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than
* threshold */
#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than
* threshold */
#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */
#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue
* overflow
*/
#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */
#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP
* transfers Done
*/
#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer
* length error
*/
#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */
#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */
#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */
#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */
#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */
#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge
* of Init Signal
*/
#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge
* of Init Signal
*/
#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \
XDCFG_IXR_AXI_WERR_MASK | \
XDCFG_IXR_AXI_RTO_MASK | \
XDCFG_IXR_AXI_RERR_MASK | \
XDCFG_IXR_RX_FIFO_OV_MASK | \
XDCFG_IXR_DMA_CMD_ERR_MASK |\
XDCFG_IXR_DMA_Q_OV_MASK | \
XDCFG_IXR_P2D_LEN_ERR_MASK |\
XDCFG_IXR_PCFG_HMAC_ERR_MASK)
#define XDCFG_IXR_ALL_MASK 0x00F7F8EF
/* @} */
/** @name Status Register Bit definitions
* @{
*/
#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command
* Queue full
*/
#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command
* Queue empty
*/
#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of
* completed DMA
* transfers
*/
#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */
#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */
#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO
* during HIZ
*/
#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config
* done
*/
#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */
#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during
* config
*/
#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset
* POR Status
*/
#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB
* access
*/
#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config
* reset status
*/
#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init
* Status
*/
#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008
/**< BBRAM key
* disable
*/
#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security
* Enable Status
*/
#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG
* Disable
* status
*/
/* @} */
/** @name DMA Source/Destination Transfer Length Register Bit definitions
* @{
*/
#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */
/*@}*/
/** @name Miscellaneous Control Register Bit definitions
* @{
*/
#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */
#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */
#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */
/* @} */
/** @name FIFO Threshold Bit definitions
* @{
*/
#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */
#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */
#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */
#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */
/* @}*/
/* Miscellaneous constant values */
#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */
#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/
#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base
* address
*/
#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* Read the given register.
*
* @param BaseAddr is the base address of the device
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note C-style signature:
* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset)
*
*****************************************************************************/
#define XDcfg_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (RegOffset))
/****************************************************************************/
/**
*
* Write to the given register.
*
* @param BaseAddr is the base address of the device
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note C-style signature:
* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
*
*****************************************************************************/
#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (RegOffset), (Data))
/************************** Function Prototypes ******************************/
/*
* Perform reset operation to the devcfg interface
*/
void XDcfg_ResetHw(u32 BaseAddr);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps.h
+347
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/******************************************************************************
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xdmaps.h
* @addtogroup dmaps Overview
* @{
* @details
*
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------ -------- ----------------------------------------------
* 1.00 hbm 08/19/10 First Release
* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
* the maximum number of channels.
* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
* Added the tcl file to automatically generate the
* xparameters.h
* 1.02a sg 05/16/12 Made changes for doxygen and moved some function
* header from the xdmaps.h file to xdmaps.c file
* Other cleanup for coding guidelines and CR 657109
* and CR 657898
* The xdmaps_example_no_intr.c example is removed
* as it is using interrupts and is similar to
* the interrupt example - CR 652477
* 1.03a sg 07/16/2012 changed inline to __inline for CR665681
* 1.04a nm 10/22/2012 Fixed CR# 681671.
* 1.05a nm 04/15/2013 Fixed CR# 704396. Removed warnings when compiled
* with -Wall and -Wextra option in bsp.
* 05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
* function description.
* Fixed CR# 704396. Removed unused variables
* UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
* function.
* 1.07a asa 11/02/13. Made changes to fix compilation issues for iarcc.
* Removed the PDBG prints. By default they were always
* defined out and never used. The PDBG is non-standard for
* Xilinx drivers and no other driver does something similar.
* Since there is no easy way to fix compilation issues with
* the IARCC compiler around PDBG, it is better to remove it.
* Users can always use xil_printfs if they want to debug.
* 2.0 adk 10/12/13 Updated as per the New Tcl API's
* 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors
* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid
* linker error for IAR compiler
* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* 2.4 adk 13/08/18 Fixed armcc compiler warnings in the driver CR-1008310.
* 2.8 sk 05/18/21 Modify all inline functions declarations from extern inline
* to static inline to avoid the linkage conflict for IAR compiler.
* 2.9 aj 11/07/23 Added support for system device tree
* </pre>
*
*****************************************************************************/
#ifndef XDMAPS_H /* prevent circular inclusions */
#define XDMAPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xparameters.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xdmaps_hw.h"
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddress; /**< Base address of device (IPIF) */
#ifdef SDT
u32 IntrId[9]; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XDmaPs_Config;
/** DMA channle control structure. It's for AXI bus transaction.
* This struct will be translated into a 32-bit channel control register value.
*/
typedef struct {
unsigned int EndianSwapSize; /**< Endian swap size. */
unsigned int DstCacheCtrl; /**< Destination cache control */
unsigned int DstProtCtrl; /**< Destination protection control */
unsigned int DstBurstLen; /**< Destination burst length */
unsigned int DstBurstSize; /**< Destination burst size */
unsigned int DstInc; /**< Destination incrementing or fixed
* address */
unsigned int SrcCacheCtrl; /**< Source cache control */
unsigned int SrcProtCtrl; /**< Source protection control */
unsigned int SrcBurstLen; /**< Source burst length */
unsigned int SrcBurstSize; /**< Source burst size */
unsigned int SrcInc; /**< Source incrementing or fixed
* address */
} XDmaPs_ChanCtrl;
/** DMA block descriptor stucture.
*/
typedef struct {
u32 SrcAddr; /**< Source starting address */
u32 DstAddr; /**< Destination starting address */
unsigned int Length; /**< Number of bytes for the block */
} XDmaPs_BD;
/**
* A DMA command consisits of a channel control struct, a block descriptor,
* a user defined program, a pointer pointing to generated DMA program, and
* execution result.
*
*/
typedef struct {
XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */
XDmaPs_BD BD; /**< Together with SgLength field,
* it's a scatter-gather list.
*/
void *UserDmaProg; /**< If user wants the driver to
* execute their own DMA program,
* this field points to the DMA
* program.
*/
int UserDmaProgLength; /**< The length of user defined
* DMA program.
*/
void *GeneratedDmaProg; /**< The DMA program genreated
* by the driver. This field will be
* set if a user invokes the DMA
* program generation function. Or
* the DMA command is finished and
* a user informs the driver not to
* release the program buffer.
* This field has two purposes, one
* is to ask the driver to generate
* a DMA program while the DMAC is
* performaning DMA transactions. The
* other purpose is to debug the
* driver.
*/
int GeneratedDmaProgLength; /**< The length of the DMA program
* generated by the driver
*/
int DmaStatus; /**< 0 on success, otherwise error code
*/
u32 ChanFaultType; /**< Channel fault type in case of fault
*/
u32 ChanFaultPCAddr; /**< Channel fault PC address
*/
} XDmaPs_Cmd;
/**
* It's the done handler a user can set for a channel
*/
typedef void (*XDmaPsDoneHandler) (unsigned int Channel,
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
/**
* It's the fault handler a user can set for a channel
*/
typedef void (*XDmaPsFaultHandler) (unsigned int Channel,
XDmaPs_Cmd *DmaCmd,
void *CallbackRef);
#define XDMAPS_MAX_CHAN_BUFS 2
#define XDMAPS_CHAN_BUF_LEN 128
/**
* The XDmaPs_ProgBuf is the struct for a DMA program buffer.
*/
typedef struct {
char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the
* content */
unsigned Len; /**< The actual length of the DMA
* program in bytes. */
int Allocated; /**< A tag indicating whether the
* buffer is allocated or not */
} XDmaPs_ProgBuf;
/**
* The XDmaPs_ChannelData is a struct to book keep individual channel of
* the DMAC.
*/
typedef struct {
unsigned DevId; /**< Device id indicating which DMAC */
unsigned ChanId; /**< Channel number of the DMAC */
XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of
program buffers*/
XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */
void *DoneRef; /**< Done interrupt callback data */
XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */
XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished.
* This field is for debugging purpose
*/
int HoldDmaProg; /**< A tag indicating whether to hold the
* DMA program after the DMA is done.
*/
} XDmaPs_ChannelData;
/**
* The XDmaPs driver instance data structure. A pointer to an instance data
* structure is passed around by functions to refer to a specific driver
* instance.
*/
typedef struct {
XDmaPs_Config Config; /**< Configuration data structure */
int IsReady; /**< Device is Ready */
int CacheLength; /**< icache length */
XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */
void *FaultRef; /**< fault call back data */
XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV];
/**<
* channel data
*/
} XDmaPs;
/*
* Functions implemented in xdmaps.c
*/
int XDmaPs_CfgInitialize(XDmaPs *InstPtr,
XDmaPs_Config *Config,
u32 EffectiveAddr);
int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd,
int HoldDmaProg);
int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel);
int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd);
int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel,
XDmaPs_Cmd *Cmd);
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
int XDmaPs_ResetManager(XDmaPs *InstPtr);
int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel);
int XDmaPs_SetDoneHandler(XDmaPs *InstPtr,
unsigned Channel,
XDmaPsDoneHandler DoneHandler,
void *CallbackRef);
int XDmaPs_SetFaultHandler(XDmaPs *InstPtr,
XDmaPsFaultHandler FaultHandler,
void *CallbackRef);
void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd);
int XDmaPs_Instr_DMARMB(char *DmaProg);
int XDmaPs_Instr_DMAWMB(char *DmaProg);
/**
* To avoid linkage error,modify all inline functions from extern
* inline to static inline for IAR compiler
*/
#ifdef __ICCARM__
static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg);
static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src);
static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn,
u32 Imm, unsigned int Ns);
static INLINE int XDmaPs_Instr_DMALD(char *DmaProg);
static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc,
unsigned LoopIterations);
static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc);
static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm);
static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg);
static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber);
static INLINE int XDmaPs_Instr_DMAST(char *DmaProg);
static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize);
static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize);
#endif
/**
* Driver done interrupt service routines for the channels.
* We need this done ISR mainly because the driver needs to release the
* DMA program buffer. This is the one that connects the GIC
*/
void XDmaPs_DoneISR_0(XDmaPs *InstPtr);
void XDmaPs_DoneISR_1(XDmaPs *InstPtr);
void XDmaPs_DoneISR_2(XDmaPs *InstPtr);
void XDmaPs_DoneISR_3(XDmaPs *InstPtr);
void XDmaPs_DoneISR_4(XDmaPs *InstPtr);
void XDmaPs_DoneISR_5(XDmaPs *InstPtr);
void XDmaPs_DoneISR_6(XDmaPs *InstPtr);
void XDmaPs_DoneISR_7(XDmaPs *InstPtr);
/**
* Driver fault interrupt service routine
*/
void XDmaPs_FaultISR(XDmaPs *InstPtr);
/*
* Static loopup function implemented in xdmaps_sinit.c
*/
#ifndef SDT
XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId);
#else
XDmaPs_Config *XDmaPs_LookupConfig(UINTPTR BaseAddress);
u32 XDmaPs_GetDrvIndex(XDmaPs *InstancePtr, UINTPTR BaseAddress);
#endif
/*
* self-test functions in xdmaps_selftest.c
*/
int XDmaPs_SelfTest(XDmaPs *InstPtr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps_hw.h
+268
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@@ -0,0 +1,268 @@
/******************************************************************************
* Copyright (C) 2009 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xdmaps_hw.h
* @addtogroup dmaps Overview
* @{
*
* This header file contains the hardware interface of an XDmaPs device.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ----------------------------------------------
* 1.00a hbm 08/18/10 First Release
* 1.01a nm 12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
* the maximum number of channels.
* Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
* with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
* 1.02a sg 05/16/12 Made changes for doxygen
* 1.06a kpc 07/10/13 Added function prototype
* </pre>
*
******************************************************************************/
#ifndef XDMAPS_HW_H /* prevent circular inclusions */
#define XDMAPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
*
* Register offsets for the DMAC.
* @{
*/
#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */
#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */
#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */
#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */
#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register
*/
#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */
#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager
* Register
*/
#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register
*/
#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */
#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */
/*
* The offset for the rest of the FTC registers is calculated as
* FTC0 + dev_chan_num * 4
*/
#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4)
#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */
/*
* The offset for the rest of the CS registers is calculated as
* CS0 + * dev_chan_num * 0x08
*/
#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8)
#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA
* Channel 0
*/
/*
* The offset for the rest of the CPC registers is calculated as
* CPC0 + dev_chan_num * 0x08
*/
#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8)
#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA
* Channel 0
*/
/* The offset for the rest of the SA registers is calculated as
* SA_0 + dev_chan_num * 0x20
*/
#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20)
#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for
* DMA Channel 0
*/
/* The offset for the rest of the DA registers is calculated as
* DA_0 + dev_chan_num * 0x20
*/
#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20)
#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for
* DMA Channel 0
*/
/*
* The offset for the rest of the CC registers is calculated as
* CC_0 + dev_chan_num * 0x20
*/
#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20)
#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */
/*
* The offset for the rest of the LC0 registers is calculated as
* LC_0 + dev_chan_num * 0x20
*/
#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20)
#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */
/*
* The offset for the rest of the LC1 registers is calculated as
* LC_0 + dev_chan_num * 0x20
*/
#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20)
#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */
#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */
#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */
#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */
#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */
#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */
#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */
#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */
#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */
#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */
#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification
* Register 0
*/
#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification
* Register 1
*/
#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification
* Register 2
*/
#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification
* Register 3
*/
#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification
* Register 0
*/
#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification
* Register 1
*/
#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification
* Register 2
*/
#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification
* Register 3
*/
/*
* Some useful register masks
*/
#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */
#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */
#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */
#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask,
* llast 3 bits of CS register
*/
#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */
/*
* XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register.
* @b1: Instruction byte 1
* @b0: Instruction byte 0
* @ch: Channel number
* @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel
*/
#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \
(((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1)))
/* @} */
/** @name Control Register
*
* The Control register (CR) controls the major functions of the device.
*
* Control Register Bit Definition
*/
/* @}*/
#define XDMAPS_CHANNELS_PER_DEV 8
/** @name Mode Register
*
* The mode register (MR) defines the mode of transfer as well as the data
* format. If this register is modified during transmission or reception,
* data validity cannot be guaranteed.
*
* Mode Register Bit Definition
* @{
*/
/* @} */
/** @name Interrupt Registers
*
* Interrupt control logic uses the interrupt enable register (IER) and the
* interrupt disable register (IDR) to set the value of the bits in the
* interrupt mask register (IMR). The IMR determines whether to pass an
* interrupt to the interrupt status register (ISR).
* Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
* interrupt. IMR and ISR are read only, and IER and IDR are write only.
* Reading either IER or IDR returns 0x00.
*
* All four registers have the same bit definitions.
*
* @{
*/
/* @} */
#define XDMAPS_INTCLR_ALL_MASK 0xFF
#define XDmaPs_ReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
* Write a DMAC register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the base address of the device.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note
* C-Style signature:
* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset,
* u32 RegisterValue)
******************************************************************************/
#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))
/************************** Variable Definitions *****************************/
/************************** Function Prototypes *****************************/
/*
* Perform reset operation to the dmaps interface
*/
void XDmaPs_ResetHw(u32 BaseAddr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps.h
+857
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/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file xemacps.h
* @addtogroup emacps Overview
* @{
* @details
*
* The Xilinx Embedded Processor Block Ethernet driver.
*
* For a full description of XEMACPS features, please see the hardware spec.
* This driver supports the following features:
* - Memory mapped access to host interface registers
* - Statistics counter registers for RMON/MIB
* - API for interrupt driven frame transfers for hardware configured DMA
* - Virtual memory support
* - Unicast, broadcast, and multicast receive address filtering
* - Full and half duplex operation
* - Automatic PAD & FCS insertion and stripping
* - Flow control
* - Support up to four 48bit addresses
* - Address checking for four specific 48bit addresses
* - VLAN frame support
* - Pause frame support
* - Large frame support up to 1536 bytes
* - Checksum offload
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the XEmacPs. The driver handles transmission and reception
* of Ethernet frames, as well as configuration and control. No pre or post
* processing of frame data is performed. The driver does not validate the
* contents of an incoming frame in addition to what has already occurred in
* hardware.
* A single device driver can support multiple devices even when those devices
* have significantly different configurations.
*
* <b>Initialization & Configuration</b>
*
* The XEmacPs_Config structure is used by the driver to configure itself.
* This configuration structure is typically created by the tool-chain based
* on hardware build properties.
*
* The driver instance can be initialized in
*
* - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a
* configuration structure provided by the caller. If running in a system
* with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* The device supports DMA only as current development plan. No FIFO mode is
* supported. The driver expects to start the DMA channels and expects that
* the user has set up the buffer descriptor lists.
*
* <b>Interrupts and Asynchronous Callbacks</b>
*
* The driver has no dependencies on the interrupt controller. When an
* interrupt occurs, the handler will perform a small amount of
* housekeeping work, determine the source of the interrupt, and call the
* appropriate callback function. All callbacks are registered by the user
* level application.
*
* <b>Virtual Memory</b>
*
* All virtual to physical memory mappings must occur prior to accessing the
* driver API.
*
* For DMA transactions, user buffers supplied to the driver must be in terms
* of their physical address.
*
* <b>DMA</b>
*
* The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames.
* These BDs are typically chained together into a list the hardware follows
* when transferring data in and out of the packet buffers. Each BD describes
* a memory region containing either a full or partial Ethernet packet.
*
* Interrupt coalescing is not supported from this built-in DMA engine.
*
* This API requires the user to understand how the DMA operates. The
* following paragraphs provide some explanation, but the user is encouraged
* to read documentation in xemacps_bdring.h as well as study example code
* that accompanies this driver.
*
* The API is designed to get BDs to and from the DMA engine in the most
* efficient means possible. The first step is to establish a memory region
* to contain all BDs for a specific channel. This is done with
* XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will
* follow as BDs are processed. The ring will consist of a user defined number
* of BDs which will all be partially initialized. For example on the transmit
* channel, the driver will initialize all BDs' so that they are configured
* for transmit. The more fields that can be permanently setup at
* initialization, then the fewer accesses will be needed to each BD while
* the DMA engine is in operation resulting in better throughput and CPU
* utilization. The best case initialization would require the user to set
* only a frame buffer address and length prior to submitting the BD to the
* engine.
*
* BDs move through the engine with the help of functions
* XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(),
* and XEmacPs_BdRingFree().
* All these functions handle BDs that are in place. That is, there are no
* copies of BDs kept anywhere and any BD the user interacts with is an actual
* BD from the same ring hardware accesses.
*
* BDs in the ring go through a series of states as follows:
* 1. Idle. The driver controls BDs in this state.
* 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to
* reserve BD(s). Once allocated, the user may setup the BD(s) with
* frame buffer address, length, and other attributes. The user controls
* BDs in this state.
* 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs
* in this state are either waiting to be processed by hardware, are in
* process, or have been processed. The DMA engine controls BDs in this
* state.
* 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the
* user. Once retrieved, the user can examine each BD for the outcome of
* the DMA transfer. The user controls BDs in this state. After examining
* the BDs the user calls XEmacPs_BdRingFree() which places the BDs back
* into state 1.
*
* Each of the four BD accessor functions operate on a set of BDs. A set is
* defined as a segment of the BD ring consisting of one or more BDs. The user
* views the set as a pointer to the first BD along with the number of BDs for
* that set. The set can be navigated by using macros XEmacPs_BdNext(). The
* user must exercise extreme caution when changing BDs in a set as there is
* nothing to prevent doing a mBdNext past the end of the set and modifying a
* BD out of bounds.
*
* XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as
* XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in
* tandem. The same BD set retrieved with BdRingAlloc should be the same one
* provided to hardware with BdRingToHw. Same goes with BdRingFromHw and
* BdRIngFree.
*
* <b>Alignment & Data Cache Restrictions</b>
*
* Due to the design of the hardware, all RX buffers, BDs need to be 4-byte
* aligned. Please reference xemacps_bd.h for cache related macros.
*
* DMA Tx:
*
* - If frame buffers exist in cached memory, then they must be flushed
* prior to committing them to hardware.
*
* DMA Rx:
*
* - If frame buffers exist in cached memory, then the cache must be
* invalidated for the memory region containing the frame prior to data
* access
*
* Both cache invalidate/flush are taken care of in driver code.
*
* <b>Buffer Copying</b>
*
* The driver is designed for a zero-copy buffer scheme. That is, the driver
* will not copy buffers. This avoids potential throughput bottlenecks within
* the driver. If byte copying is required, then the transfer will take longer
* to complete.
*
* <b>Checksum Offloading</b>
*
* The Embedded Processor Block Ethernet can be configured to perform IP, TCP
* and UDP checksum offloading in both receive and transmit directions.
*
* IP packets contain a 16-bit checksum field, which is the 16-bit 1s
* complement of the 1s complement sum of all 16-bit words in the header.
* TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit
* 1s complement of the 1s complement sum of all 16-bit words in the header,
* the data and a conceptual pseudo header.
*
* To calculate these checksums in software requires each byte of the packet
* to be read. For TCP and UDP this can use a large amount of processing power.
* Offloading the checksum calculation to hardware can result in significant
* performance improvements.
*
* The transmit checksum offload is only available to use DMA in packet buffer
* mode. This is because the complete frame to be transmitted must be read
* into the packet buffer memory before the checksum can be calculated and
* written to the header at the beginning of the frame.
*
* For IP, TCP or UDP receive checksum offload to be useful, the operating
* system containing the protocol stack must be aware that this offload is
* available so that it can make use of the fact that the hardware has verified
* the checksum.
*
* When receive checksum offloading is enabled in the hardware, the IP header
* checksum is checked, where the packet meets the following criteria:
*
* 1. If present, the VLAN header must be four octets long and the CFI bit
* must not be set.
* 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP
* encoding.
* 3. IP v4 packet.
* 4. IP header is of a valid length.
* 5. Good IP header checksum.
* 6. No IP fragmentation.
* 7. TCP or UDP packet.
*
* When an IP, TCP or UDP frame is received, the receive buffer descriptor
* gives an indication if the hardware was able to verify the checksums.
* There is also an indication if the frame had SNAP encapsulation. These
* indication bits will replace the type ID match indication bits when the
* receive checksum offload is enabled.
*
* If any of the checksums are verified incorrect by the hardware, the packet
* is discarded and the appropriate statistics counter incremented.
*
* <b>PHY Interfaces</b>
*
* RGMII 1.3 is the only interface supported.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on
* parameters. Asserts can be turned off on a system-wide basis by defining,
* at compile time, the NDEBUG identifier. By default, asserts are turned on
* and it is recommended that users leave asserts on during development. For
* deployment use -DNDEBUG compiler switch to remove assert code.
*
* @note
*
* Xilinx drivers are typically composed of two parts, one is the driver
* and the other is the adapter. The driver is independent of OS and processor
* and is intended to be highly portable. The adapter is OS-specific and
* facilitates communication between the driver and an OS.
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, or cache
* control must be satisfied bythe layer above this driver.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 1.00a asa 11/21/11 The function XEmacPs_BdRingFromHwTx in file
* xemacps_bdring.c is modified. Earlier it was checking for
* "BdLimit"(passed argument) number of BDs for finding out
* which BDs are successfully processed. Now one more check
* is added. It looks for BDs till the current BD pointer
* reaches HwTail. By doing this processing time is saved.
* 1.00a asa 01/24/12 The function XEmacPs_BdRingFromHwTx in file
* xemacps_bdring.c is modified. Now start of packet is
* searched for returning the number of BDs processed.
* 1.02a asa 11/05/12 Added a new API for deleting an entry from the HASH
* registers. Added a new API to set the bust length.
* Added some new hash-defines.
* 1.03a asa 01/23/12 Fix for CR #692702 which updates error handling for
* Rx errors. Under heavy Rx traffic, there will be a large
* number of errors related to receive buffer not available.
* Because of a HW bug (SI #692601), under such heavy errors,
* the Rx data path can become unresponsive. To reduce the
* probabilities for hitting this HW bug, the SW writes to
* bit 18 to flush a packet from Rx DPRAM immediately. The
* changes for it are done in the function
* XEmacPs_IntrHandler.
* 1.05a asa 09/23/13 Cache operations on BDs are not required and hence
* removed. It is expected that all BDs are allocated in
* from uncached area.
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* Made changes in example file xemacps_example.h to fix compilation
* issues with iarcc compiler.
* 2.0 adk 10/12/13 Updated as per the New Tcl API's
* 2.1 adk 11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
* 2.1 bss 09/08/14 Modified driver tcl to fix CR#820349 to export phy
* address in xparameters.h when GMII to RGMII converter
* is present in hw.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
* changes.
* 2.2 adk 29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
* 1000BASE-X mode export proper values to the xparameters.h
* file. Changes are made in the driver tcl file.
* 3.0 adk 08/1/15 Don't include gem in peripheral test when gem is
* configured with PCS/PMA Core. Changes are made in the
* test app tcl(CR:827686).
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 03/18/15 Added support for jumbo frames. Increase AHB burst.
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
* Remove "used bit set" from TX error interrupt masks.
* 3.1 hk 07/27/15 Do not call error handler with '0' error code when
* there is no error. CR# 869403
* 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
* 3.4 ms 01/23/17 Modified xil_printf statement in main function for all
* examples to ensure that "Successfully ran" and "Failed"
* strings are available in all examples. This is a fix
* for CR-965028.
* ms 03/17/17 Modified text file in examples folder for doxygen
* generation.
* ms 04/05/17 Added tabspace for return statements in functions of
* xemacps_ieee1588_example.c for proper documentation
* while generating doxygen.
* 3.5 hk 08/14/17 Update cache coherency information of the interface in
* its config structure.
* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
* changed to volatile.
* Add API XEmacPs_BdRingPtrReset() to reset pointers
* 3.8 hk 07/19/18 Fixed CPP, GCC and doxygen warnings - CR-1006327
* hk 09/17/18 Fix PTP interrupt masks and cleanup comments.
* 3.9 hk 01/23/19 Add RX watermark support
* 3.11 sd 02/14/20 Add clock support
* 3.13 nsk 12/14/20 Updated the tcl to not to use the instance names.
*
* </pre>
*
****************************************************************************/
#ifndef XEMACPS_H /* prevent circular inclusions */
#define XEMACPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xemacps_hw.h"
#include "xemacps_bd.h"
#include "xemacps_bdring.h"
#if defined (XCLOCKING)
#include "xil_clocking.h"
#endif
/************************** Constant Definitions ****************************/
/*
* Device information
*/
#define XEMACPS_DEVICE_NAME "xemacps"
#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC"
/** @name Configuration options
*
* Device configuration options. See the XEmacPs_SetOptions(),
* XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to
* use options.
*
* The default state of the options are noted and are what the device and
* driver will be set to after calling XEmacPs_Reset() or
* XEmacPs_Initialize().
*
* @{
*/
#define XEMACPS_PROMISC_OPTION 0x00000001U
/**< Accept all incoming packets.
* This option defaults to disabled (cleared) */
#define XEMACPS_FRAME1536_OPTION 0x00000002U
/**< Frame larger than 1516 support for Tx & Rx.
* This option defaults to disabled (cleared) */
#define XEMACPS_VLAN_OPTION 0x00000004U
/**< VLAN Rx & Tx frame support.
* This option defaults to disabled (cleared) */
#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U
/**< Enable recognition of flow control frames on Rx
* This option defaults to enabled (set) */
#define XEMACPS_FCS_STRIP_OPTION 0x00000020U
/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
* stripped.
* This option defaults to enabled (set) */
#define XEMACPS_FCS_INSERT_OPTION 0x00000040U
/**< Generate FCS field and add PAD automatically for outgoing frames.
* This option defaults to disabled (cleared) */
#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U
/**< Enable Length/Type error checking for incoming frames. When this option is
* set, the MAC will filter frames that have a mismatched type/length field
* and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these
* types of frames are encountered. When this option is cleared, the MAC will
* allow these types of frames to be received.
*
* This option defaults to disabled (cleared) */
#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U
/**< Enable the transmitter.
* This option defaults to enabled (set) */
#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U
/**< Enable the receiver
* This option defaults to enabled (set) */
#define XEMACPS_BROADCAST_OPTION 0x00000400U
/**< Allow reception of the broadcast address
* This option defaults to enabled (set) */
#define XEMACPS_MULTICAST_OPTION 0x00000800U
/**< Allows reception of multicast addresses programmed into hash
* This option defaults to disabled (clear) */
#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U
/**< Enable the RX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U
/**< Enable the TX checksum offload
* This option defaults to enabled (set) */
#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U
#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U
#define XEMACPS_DEFAULT_OPTIONS \
((u32)XEMACPS_FLOW_CONTROL_OPTION | \
(u32)XEMACPS_FCS_INSERT_OPTION | \
(u32)XEMACPS_FCS_STRIP_OPTION | \
(u32)XEMACPS_BROADCAST_OPTION | \
(u32)XEMACPS_LENTYPE_ERR_OPTION | \
(u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \
(u32)XEMACPS_RECEIVER_ENABLE_OPTION | \
(u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \
(u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION)
/**< Default options set when device is initialized or reset */
/*@}*/
/** @name Callback identifiers
*
* These constants are used as parameters to XEmacPs_SetHandler()
* @{
*/
#define XEMACPS_HANDLER_DMASEND 1U
#define XEMACPS_HANDLER_DMARECV 2U
#define XEMACPS_HANDLER_ERROR 3U
/*@}*/
/* Constants to determine the configuration of the hardware device. They are
* used to allow the driver to verify it can operate with the hardware.
*/
#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */
/* The next few constants help upper layers determine the size of memory
* pools used for Ethernet buffers and descriptor lists.
*/
#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */
#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */
#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */
#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */
#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */
#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */
#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \
XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE)
/* DMACR Bust length hash defines */
#define XEMACPS_SINGLE_BURST 0x00000001
#define XEMACPS_4BYTE_BURST 0x00000004
#define XEMACPS_8BYTE_BURST 0x00000008
#define XEMACPS_16BYTE_BURST 0x00000010
/**************************** Type Definitions ******************************/
/** @name Typedefs for callback functions
*
* These callbacks are invoked in interrupt context.
* @{
*/
/**
* Callback invoked when frame(s) have been sent or received in interrupt
* driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler().
*
* @param CallBackRef is user data assigned when the callback was set.
*
* @note
* See xemacps_hw.h for bitmasks definitions and the device hardware spec for
* further information on their meaning.
*
*/
typedef void (*XEmacPs_Handler) (void *CallBackRef);
/**
* Callback when an asynchronous error occurs. To set this callback, invoke
* XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType
* parameter.
*
* @param CallBackRef is user data assigned when the callback was set.
* @param Direction defines either receive or transmit error(s) has occurred.
* @param ErrorWord definition varies with Direction
*
*/
typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
u32 ErrorWord);
/*@}*/
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
#ifdef SDT
char *Name; /**< Unique name of the device */
#else
u16 DeviceId; /**< Unique ID of device */
#endif
UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
* describes whether Cache Coherent or not */
#ifdef SDT
u16 IntrId;
UINTPTR IntrParent;
#endif
#if defined (XCLOCKING)
u32 RefClk; /**< Input clock */
#endif
u16 S1GDiv0; /**< 1Gbps Clock Divider 0 */
u8 S1GDiv1; /**< 1Gbps Clock Divider 1 */
u16 S100MDiv0; /**< 100Mbps Clock Divider 0 */
u8 S100MDiv1; /**< 100Mbps Clock Divider 1 */
u16 S10MDiv0; /**< 10Mbps Clock Divider 0 */
u8 S10MDiv1; /**< 10Mbps Clock Divider 1 */
} XEmacPs_Config;
/**
* The XEmacPs driver instance data. The user is required to allocate a
* structure of this type for every XEmacPs device in the system. A pointer
* to a structure of this type is then passed to the driver API functions.
*/
typedef struct XEmacPs_Instance {
XEmacPs_Config Config; /* Hardware configuration */
u32 IsStarted; /* Device is currently started */
u32 IsReady; /* Device is initialized and ready */
u32 Options; /* Current options word */
XEmacPs_BdRing TxBdRing; /* Transmit BD ring */
XEmacPs_BdRing RxBdRing; /* Receive BD ring */
XEmacPs_Handler SendHandler;
XEmacPs_Handler RecvHandler;
void *SendRef;
void *RecvRef;
XEmacPs_ErrHandler ErrorHandler;
void *ErrorRef;
u32 Version;
u32 RxBufMask;
u32 MaxMtuSize;
u32 MaxFrameSize;
u32 MaxVlanFrameSize;
} XEmacPs;
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
* Retrieve the Tx ring object. This object can be used in the various Ring
* API functions.
*
* @param InstancePtr is the DMA channel to operate on.
*
* @return TxBdRing attribute
*
* @note
* C-style signature:
* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing)
/****************************************************************************/
/**
* Retrieve the Rx ring object. This object can be used in the various Ring
* API functions.
*
* @param InstancePtr is the DMA channel to operate on.
*
* @return RxBdRing attribute
*
* @note
* C-style signature:
* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing)
/****************************************************************************/
/**
*
* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to enable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntEnable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IER_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to disable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntDisable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_IDR_OFFSET, \
((Mask) & XEMACPS_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Enable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to enable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IER_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* Disable interrupts specified in <i>Mask</i>. The corresponding interrupt for
* each bit set to 1 in <i>Mask</i>, will be enabled.
*
* @param InstancePtr is a pointer to the instance to be worked on.
* @param Mask contains a bit mask of interrupts to disable. The mask can
* be formed using a set of bitwise or'd values.
*
* @note
* The state of the transmitter and receiver are not modified by this function.
* C-style signature
* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask)
*
*****************************************************************************/
#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_INTQ1_IDR_OFFSET, \
((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK));
/****************************************************************************/
/**
*
* This macro triggers trasmit circuit to send data currently in TX buffer(s).
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* @note
*
* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_Transmit(InstancePtr) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET, \
(XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK))
/****************************************************************************/
/**
*
* This macro determines if the device is configured with checksum offloading
* on the receive channel
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured with checksum offloading, or
* FALSE otherwise.
*
* @note
*
* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_IsRxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \
? TRUE : FALSE)
/****************************************************************************/
/**
*
* This macro determines if the device is configured with checksum offloading
* on the transmit channel
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return
*
* Boolean TRUE if the device is configured with checksum offloading, or
* FALSE otherwise.
*
* @note
*
* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_IsTxCsum(InstancePtr) \
((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \
? TRUE : FALSE)
/************************** Function Prototypes *****************************/
/****************************************************************************/
/**
*
* This macro sets RX watermark register.
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
* @param High is the non-zero RX high watermark value. When SRAM fill level
* is above this, a pause frame will be sent.
* @param Low is the non-zero RX low watermark value. When SRAM fill level
* is below this, a zero length pause frame will be sent IF the last
* pause frame sent was non-zero.
*
* @return None
*
* @note
*
* Signature: void XEmacPs_SetRXWatermark(XEmacPs *InstancePtr, u16 High,
* u16 Low)
*
*****************************************************************************/
#define XEmacPs_SetRXWatermark(InstancePtr, High, Low) \
XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET, \
(High & XEMACPS_RXWM_HIGH_MASK) | \
((Low << XEMACPS_RXWM_LOW_SHFT_MSK) & XEMACPS_RXWM_LOW_MASK) |)
/****************************************************************************/
/**
*
* This macro gets RX watermark register.
*
* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
*
* @return RX watermark register value
*
* @note
*
* Signature: void XEmacPs_GetRXWatermark(XEmacPs *InstancePtr)
*
*****************************************************************************/
#define XEmacPs_GetRXWatermark(InstancePtr) \
XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
XEMACPS_RXWATERMARK_OFFSET)
/*
* Initialization functions in xemacps.c
*/
LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr,
UINTPTR EffectiveAddress);
void XEmacPs_Start(XEmacPs *InstancePtr);
void XEmacPs_Stop(XEmacPs *InstancePtr);
void XEmacPs_Reset(XEmacPs *InstancePtr);
void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
u16 Direction);
/*
* Lookup configuration in xemacps_sinit.c
*/
#ifndef SDT
XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId);
#else
XEmacPs_Config *XEmacPs_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Interrupt-related functions in xemacps_intr.c
* DMA only and FIFO is not supported. This DMA does not support coalescing.
*/
LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
void *FuncPointer, void *CallBackRef);
void XEmacPs_IntrHandler(void *XEmacPsPtr);
/*
* MAC configuration/control functions in XEmacPs_control.c
*/
LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options);
LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options);
u32 XEmacPs_GetOptions(XEmacPs *InstancePtr);
LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index);
LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_ClearHash(XEmacPs *InstancePtr);
void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr);
void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr,
XEmacPs_MdcDiv Divisor);
void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed);
u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr);
LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 *PhyDataPtr);
LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
u32 RegisterNum, u16 PhyData);
LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index);
LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr);
void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bd.h
+763
View File
@@ -0,0 +1,763 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_bd.h
* @addtogroup emacps Overview
* @{
*
* This header provides operations to manage buffer descriptors in support
* of scatter-gather DMA.
*
* The API exported by this header defines abstracted macros that allow the
* user to read/write specific BD fields.
*
* <b>Buffer Descriptors</b>
*
* A buffer descriptor (BD) defines a DMA transaction. The macros defined by
* this header file allow access to most fields within a BD to tailor a DMA
* transaction according to user and hardware requirements. See the hardware
* IP DMA spec for more information on BD fields and how they affect transfers.
*
* The XEmacPs_Bd structure defines a BD. The organization of this structure
* is driven mainly by the hardware for use in scatter-gather DMA transfers.
*
* <b>Performance</b>
*
* Limiting I/O to BDs can improve overall performance of the DMA channel.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale MP GEM specification
* and 64-bit changes.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 02/20/15 Added support for jumbo frames.
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
* 3.2 hk 11/18/15 Change BD typedef and number of words.
* 3.8 hk 08/18/18 Remove duplicate definition of XEmacPs_BdSetLength
* 3.8 mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
*
* </pre>
*
* ***************************************************************************
*/
#ifndef XEMACPS_BD_H /* prevent circular inclusions */
#define XEMACPS_BD_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include <string.h>
#include "xil_types.h"
#include "xil_assert.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
#ifdef __aarch64__
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U
#define XEMACPS_BD_NUM_WORDS 4U
#else
/* Minimum BD alignment */
#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U
#define XEMACPS_BD_NUM_WORDS 2U
#endif
/**
* The XEmacPs_Bd is the type for buffer descriptors (BDs).
*/
typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS];
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Zero out BD fields
*
* @param BdPtr is the BD pointer to operate on
*
* @return Nothing
*
* @note
* C-style signature:
* void XEmacPs_BdClear(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClear(BdPtr) \
memset((BdPtr), 0, sizeof(XEmacPs_Bd))
/****************************************************************************/
/**
*
* Read the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to read
* @param Offset is the word offset to be read
*
* @return The 32-bit value of the field
*
* @note
* C-style signature:
* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset)
*
*****************************************************************************/
#define XEmacPs_BdRead(BaseAddress, Offset) \
(*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset)))
/****************************************************************************/
/**
*
* Write the given Buffer Descriptor word.
*
* @param BaseAddress is the base address of the BD to write
* @param Offset is the word offset to be written
* @param Data is the 32-bit value to write to the field
*
* @return None.
*
* @note
* C-style signature:
* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data)
*
*****************************************************************************/
#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \
(*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data))
/*****************************************************************************/
/**
* Set the BD's Address field (word 0).
*
* @param BdPtr is the BD pointer to operate on
* @param Addr is the value to write to BD's status field.
*
* @note :
*
* C-style signature:
* void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
*
*****************************************************************************/
#if defined(__aarch64__) || defined(__arch64__)
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
(u32)((Addr) & ULONG64_LO_MASK)); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
#else
#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr))
#endif
/*****************************************************************************/
/**
* Set the BD's Address field (word 0).
*
* @param BdPtr is the BD pointer to operate on
* @param Addr is the value to write to BD's status field.
*
* @note : Due to some bits are mixed within receive BD's address field,
* read-modify-write is performed.
*
* C-style signature:
* void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr)
*
*****************************************************************************/
#ifdef __aarch64__
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \
(u32)(((Addr) & ULONG64_HI_MASK) >> 32U));
#else
#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr)))
#endif
/*****************************************************************************/
/**
* Set the BD's Status field (word 1).
*
* @param BdPtr is the BD pointer to operate on
* @param Data is the value to write to BD's status field.
*
* @note
* C-style signature:
* void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data)
*
*****************************************************************************/
#define XEmacPs_BdSetStatus(BdPtr, Data) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data))
/*****************************************************************************/
/**
* Retrieve the BD's Packet DMA transfer status word (word 1).
*
* @param BdPtr is the BD pointer to operate on
*
* @return Status word
*
* @note
* C-style signature:
* u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr)
*
* Due to the BD bit layout differences in transmit and receive. User's
* caution is required.
*****************************************************************************/
#define XEmacPs_BdGetStatus(BdPtr) \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET)
/*****************************************************************************/
/**
* Get the address (bits 0..31) of the BD's buffer address (word 0)
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#if defined(__aarch64__) || defined(__arch64__)
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U)
#else
#define XEmacPs_BdGetBufAddr(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET))
#endif
/*****************************************************************************/
/**
* Set transfer length in bytes for the given BD. The length must be set each
* time a BD is submitted to hardware.
*
* @param BdPtr is the BD pointer to operate on
* @param LenBytes is the number of bytes to transfer.
*
* @note
* C-style signature:
* void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes)
*
*****************************************************************************/
#define XEmacPs_BdSetLength(BdPtr, LenBytes) \
XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LEN_MASK) | (LenBytes)))
/*****************************************************************************/
/**
* Retrieve the BD length field.
*
* For Tx channels, the returned value is the same as that written with
* XEmacPs_BdSetLength().
*
* For Rx channels, the returned value is the size of the received packet.
*
* @param BdPtr is the BD pointer to operate on
*
* @return Length field processed by hardware or set by
* XEmacPs_BdSetLength().
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr)
* XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK.
*
*****************************************************************************/
#define XEmacPs_BdGetLength(BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_LEN_MASK)
/*****************************************************************************/
/**
* Retrieve the RX frame size.
*
* The returned value is the size of the received packet.
* This API supports jumbo frame sizes if enabled.
*
* @param InstancePtr is the pointer to XEmacps instance
*
* @param BdPtr is the BD pointer to operate on
*
* @return Length field processed by hardware or set by
* XEmacPs_BdSetLength().
*
* @note
* C-style signature:
* UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr)
* RxBufMask is dependent on whether jumbo is enabled or not.
*
*****************************************************************************/
#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \
(XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
(InstancePtr)->RxBufMask)
/*****************************************************************************/
/**
* Test whether the given BD has been marked as the last BD of a packet.
*
* @param BdPtr is the BD pointer to operate on
*
* @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsLast(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Tell the DMA engine that the given transmit BD marks the end of the current
* packet to be processed.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetLast(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_LAST_MASK))
/*****************************************************************************/
/**
* Tell the DMA engine that the current packet does not end with the given
* BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearLast(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_LAST_MASK))
/*****************************************************************************/
/**
* Set this bit to mark the last descriptor in the receive buffer descriptor
* list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
/*#define XEmacPs_BdSetRxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \
XEMACPS_RXBUF_WRAP_MASK))
*/
/*****************************************************************************/
/**
* Determine the wrap bit of the receive BD which indicates end of the
* BD list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxWrap(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Sets this bit to mark the last descriptor in the transmit buffer
* descriptor list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
/*#define XEmacPs_BdSetTxWrap(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_WRAP_MASK))
*/
/*****************************************************************************/
/**
* Determine the wrap bit of the transmit BD which indicates end of the
* BD list.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxWrap(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/*
* Must clear this bit to enable the MAC to write data to the receive
* buffer. Hardware sets this bit once it has successfully written a frame to
* memory. Once set, software has to clear the bit before the buffer can be
* used again. This macro clear the new bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearRxNew(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
~XEMACPS_RXBUF_NEW_MASK))
/*****************************************************************************/
/**
* Determine the new bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxNew(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \
XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Software sets this bit to disable the buffer to be read by the hardware.
* Hardware sets this bit for the first buffer of a frame once it has been
* successfully transmitted. This macro sets this bit of transmit BD to avoid
* confusion.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxUsed(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_USED_MASK))
/*****************************************************************************/
/**
* Software clears this bit to enable the buffer to be read by the hardware.
* Hardware sets this bit for the first buffer of a frame once it has been
* successfully transmitted. This macro clears this bit of transmit BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearTxUsed(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_USED_MASK))
/*****************************************************************************/
/**
* Determine the used bit of the transmit BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxUsed(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to too many retries.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxRetry(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to data can not be
* feteched in time or buffers are exhausted.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxUrun(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if a frame fails to be transmitted due to buffer is exhausted
* mid-frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsTxExh(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Sets this bit, no CRC will be appended to the current frame. This control
* bit must be set for the first buffer in a frame and will be ignored for
* the subsequent buffers of a frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* This bit must be clear when using the transmit checksum generation offload,
* otherwise checksum generation and substitution will not occur.
*
* C-style signature:
* UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdSetTxNoCRC(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \
XEMACPS_TXBUF_NOCRC_MASK))
/*****************************************************************************/
/**
* Clear this bit, CRC will be appended to the current frame. This control
* bit must be set for the first buffer in a frame and will be ignored for
* the subsequent buffers of a frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* This bit must be clear when using the transmit checksum generation offload,
* otherwise checksum generation and substitution will not occur.
*
* C-style signature:
* UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdClearTxNoCRC(BdPtr) \
(XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \
XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
~XEMACPS_TXBUF_NOCRC_MASK))
/*****************************************************************************/
/**
* Determine the broadcast bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxBcast(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the multicast hash bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxMultiHash(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the unicast hash bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxUniHash(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame is a VLAN Tagged frame.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxVlan(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame has Type ID of 8100h and null VLAN
* identifier(Priority tag).
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxPri(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine if the received frame's Concatenation Format Indicator (CFI) of
* the frames VLANTCI field was set.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxCFI(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the End Of Frame (EOF) bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxEOF(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE)
/*****************************************************************************/
/**
* Determine the Start Of Frame (SOF) bit of the receive BD.
*
* @param BdPtr is the BD pointer to operate on
*
* @note
* C-style signature:
* UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdIsRxSOF(BdPtr) \
((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \
XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE)
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_bdring.h
+216
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@@ -0,0 +1,216 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_bdring.h
* @addtogroup emacps Overview
* @{
*
* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
* DMA functionalities.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
* changed to volatile.
*
* </pre>
*
******************************************************************************/
#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */
#define XEMACPS_BDRING_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/**************************** Type Definitions *******************************/
/** This is an internal structure used to maintain the DMA list */
typedef struct {
UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */
UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */
u32 Length; /**< Total size of ring in bytes */
u32 RunState; /**< Flag to indicate DMA is started */
u32 Separation; /**< Number of bytes between the starting address
of adjacent BDs */
XEmacPs_Bd *FreeHead;
/**< First BD in the free group */
XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
XEmacPs_Bd *HwHead; /**< First BD in the work group */
XEmacPs_Bd *HwTail; /**< Last BD in the work group */
XEmacPs_Bd *PostHead;
/**< First BD in the post-work group */
XEmacPs_Bd *BdaRestart;
/**< BDA to load when channel is started */
volatile u32 HwCnt; /**< Number of BDs in work group */
u32 PreCnt; /**< Number of BDs in pre-work group */
u32 FreeCnt; /**< Number of allocatable BDs in the free group */
u32 PostCnt; /**< Number of BDs in post-work group */
u32 AllCnt; /**< Total Number of BDs for channel */
} XEmacPs_BdRing;
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many BDs will fit
* in a BD list within the given memory constraints.
*
* The results of this macro can be provided to XEmacPs_BdRingCreate().
*
* @param Alignment specifies what byte alignment the BDs must fall on and
* must be a power of 2 to get an accurate calculation (32, 64, 128,...)
* @param Bytes is the number of bytes to be used to store BDs.
*
* @return Number of BDs that can fit in the given memory area
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
*
******************************************************************************/
#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \
(u32)((Bytes) / (sizeof(XEmacPs_Bd)))
/*****************************************************************************/
/**
* Use this macro at initialization time to determine how many bytes of memory
* is required to contain a given number of BDs at a given alignment.
*
* @param Alignment specifies what byte alignment the BDs must fall on. This
* parameter must be a power of 2 to get an accurate calculation (32, 64,
* 128,...)
* @param NumBd is the number of BDs to calculate memory size requirements for
*
* @return The number of bytes of memory required to create a BD list with the
* given memory constraints.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
*
******************************************************************************/
#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \
(u32)(sizeof(XEmacPs_Bd) * (NumBd))
/****************************************************************************/
/**
* Return the total number of BDs allocated by this channel with
* XEmacPs_BdRingCreate().
*
* @param RingPtr is the DMA channel to operate on.
*
* @return The total number of BDs allocated for this channel.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
/****************************************************************************/
/**
* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
* processing.
*
* @param RingPtr is the DMA channel to operate on.
*
* @return The number of BDs currently allocatable.
*
* @note
* C-style signature:
* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt)
/****************************************************************************/
/**
* Return the next BD from BdPtr in a list.
*
* @param RingPtr is the DMA channel to operate on.
* @param BdPtr is the BD to operate on.
*
* @return The next BD in the list relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
* XEmacPs_Bd *BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingNext(RingPtr, BdPtr) \
(((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \
(XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \
(XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
/****************************************************************************/
/**
* Return the previous BD from BdPtr in the list.
*
* @param RingPtr is the DMA channel to operate on.
* @param BdPtr is the BD to operate on
*
* @return The previous BD in the list relative to the BdPtr parameter.
*
* @note
* C-style signature:
* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
* XEmacPs_Bd *BdPtr)
*
*****************************************************************************/
#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \
(((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \
(XEmacPs_Bd*)(RingPtr)->HighBdAddr : \
(XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
/************************** Function Prototypes ******************************/
/*
* Scatter gather DMA related functions in xemacps_bdring.c
*/
LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
u8 Direction);
LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
XEmacPs_Bd * BdSetPtr);
u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
XEmacPs_Bd ** BdSetPtr);
LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macros */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xemacps_hw.h
+664
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@@ -0,0 +1,664 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xemacps_hw.h
* @addtogroup emacps Overview
* @{
*
* This header file contains identifiers and low-level driver functions (or
* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
* High-level driver functions are defined in xemacps.h.
*
* @note
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a wsy 01/10/10 First release.
* 1.02a asa 11/05/12 Added hash defines for DMACR burst length configuration.
* 1.05a kpc 28/06/13 Added XEmacPs_ResetHw function prototype
* 1.06a asa 11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
* to 0x1fff. This fixes the CR#744902.
* 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
* 3.0 kvn 12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
* XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
* 3.0 kpc 1/23/15 Corrected the extended descriptor macro values.
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 03/18/15 Added support for jumbo frames.
* Remove "used bit set" from TX error interrupt masks.
* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
* 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
* 3.8 hk 09/17/18 Fix PTP interrupt masks.
* 3.9 hk 01/23/19 Add RX watermark support
* 3.10 hk 05/16/19 Clear status registers properly in reset
* 3.18 sne 01/11/23 Add PCS control and status registers information.
* </pre>
*
******************************************************************************/
#ifndef XEMACPS_HW_H /* prevent circular inclusions */
#define XEMACPS_HW_H /* by using protection macros */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address
supported */
#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */
#ifdef __aarch64__
#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment
on the local bus */
#else
#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment
on the local bus */
#endif
#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using
options that impose alignment
restrictions on the buffer data on
the local bus */
/** @name Direction identifiers
*
* These are used by several functions and callbacks that need
* to specify whether an operation specifies a send or receive channel.
* @{
*/
#define XEMACPS_SEND 1U /**< send direction */
#define XEMACPS_RECV 2U /**< receive direction */
/*@}*/
/** @name MDC clock division
* currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
* @{
*/
typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
} XEmacPs_MdcDiv;
/*@}*/
#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
bytes, 64, 128, ... 10240 */
#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a
unit, this is HW setup */
#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */
#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */
#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
/* Register offset definitions. Unless otherwise noted, register access is
* 32 bit. Names are self explained here.
*/
#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */
#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */
#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */
#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */
#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */
#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */
#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */
#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */
#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */
#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */
#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */
#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */
#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */
#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */
#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */
#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */
#define XEMACPS_RXWATERMARK_OFFSET 0x0000007CU /**< RX watermark reg */
#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */
#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */
#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */
#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */
#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */
#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */
#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */
#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */
#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */
#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */
#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */
#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */
#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */
#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */
#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */
#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low
reg */
#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High
reg */
#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes
transmitted counter */
#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast
Frames counter*/
#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast
Frame counter */
#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted
Counter */
#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames
Transmitted counter */
#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte
Frames Transmitted
counter */
#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte
Frames Transmitted
counter*/
#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte
Frames transmitted
counter */
#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte
Frames transmitted
counter */
#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte
Frames transmitted
counter */
#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than
1519 byte Frames
transmitted counter */
#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error
counter */
#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame
Counter */
#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame
Counter */
#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
Counter */
#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame
Counter */
#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission
Frame Counter */
#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense
Error Counter */
#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register
Low */
#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register
High */
#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames
Received Counter */
#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast
Frames Received Counter */
#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast
Frames Received Counter */
#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames
Received Counter */
#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames
Received Counter */
#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte
Frames Received Counter */
#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte
Frames Received Counter */
#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte
Frames Received Counter */
#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte
Frames Received Counter */
#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte
Frames Received Counter */
#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte
Frames Received Counter */
#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received
Counter */
#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received
Counter */
#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received
Counter */
#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence
Error Counter */
#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error
Counter */
#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */
#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */
#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error
Counter */
#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */
#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error
Counter */
#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error
Counter */
#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error
Counter */
#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter
offset, for clearing */
#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */
#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */
#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond
adjustment counter */
#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond
increment counter */
#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second
counter */
#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
nanosecond counter */
#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second
counter */
#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
nanosecond counter */
#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit
second counter */
#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
nanosecond counter */
#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive
second counter */
#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
nanosecond counter */
#define XEMACPS_PCS_CONTROL_OFFSET 0x00000200U /** PCS control register */
#define XEMACPS_PCS_STATUS_OFFSET 0x00000204U /** PCS status register */
#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status
reg */
#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address
reg */
#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
reg */
#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
reg */
#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
reg */
#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
reg */
#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable
reg */
#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask
reg */
/* Define some bit positions for registers. */
/** @name network control register bit definitions
* @{
*/
#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from
Rx SRAM */
#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
pause frame */
#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */
#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission
after current frame */
#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */
#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to
stat counters */
#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic
registers */
#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic
registers */
#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */
#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */
#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */
#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */
/*@}*/
/** @name network configuration register bit definitions
* @{
*/
#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
non-standard preamble */
#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */
#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */
#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of
FCS error */
#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */
#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum
offload */
#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
Frames to memory */
#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */
#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */
#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */
#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from
received frames */
#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
/**< RX length error discard */
#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */
#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */
#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
/**< External address match enable */
#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */
#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */
#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte
frames reception */
#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
frames */
#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
frames */
#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive
broadcast frames */
#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */
#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */
#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN
frames */
#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */
#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */
#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */
/*@}*/
/** @name network status register bit definitaions
* @{
*/
#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */
#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */
/*@}*/
/** @name MAC address register word 1 mask
* @{
*/
#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32]
bit[31:0] are in BOTTOM */
/*@}*/
/** @name DMA control register bit definitions
* @{
*/
#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer
size */
#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer
size */
#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX
checksum offload */
#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */
#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */
#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */
#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */
#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */
#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */
#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */
#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */
/*@}*/
/** @name transmit status register bit definitions
* @{
*/
#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */
#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */
#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */
#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted
mid frame */
#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */
#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */
#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */
#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */
#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
(u32)XEMACPS_TXSR_URUN_MASK | \
(u32)XEMACPS_TXSR_BUFEXH_MASK | \
(u32)XEMACPS_TXSR_RXOVR_MASK | \
(u32)XEMACPS_TXSR_FRAMERX_MASK | \
(u32)XEMACPS_TXSR_USEDREAD_MASK)
/*@}*/
/**
* @name receive status register bit definitions
* @{
*/
#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */
#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */
#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */
#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */
#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
(u32)XEMACPS_RXSR_RXOVR_MASK | \
(u32)XEMACPS_RXSR_BUFFNA_MASK)
#define XEMACPS_SR_ALL_MASK 0xFFFFFFFFU /**< Mask for full register */
/*@}*/
/**
* @name PCS control register bit definitions
* @{
*/
#define XEMACPS_PCS_CON_AUTO_NEG_MASK 0x00001000U /**< Auto-negotiation */
/*@}*/
/**
* @name PCS status register bit definitions
* @{
*/
#define XEMACPS_PCS_STATUS_LINK_STATUS_MASK 0x00000004U /**< Link status */
/*@}*/
/**
* @name Interrupt Q1 status register bit definitions
* @{
*/
#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */
#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */
#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
(u32)XEMACPS_INTQ1SR_TXERR_MASK)
/*@}*/
/**
* @name interrupts bit definitions
* Bits definitions are same in XEMACPS_ISR_OFFSET,
* XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
* @{
*/
#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Pdelay_resp TXed */
#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req TXed */
#define XEMACPS_IXR_PTPPSRX_MASK 0x00800000U /**< PTP Pdelay_resp RXed */
#define XEMACPS_IXR_PTPPDRRX_MASK 0x00400000U /**< PTP Pdelay_req RXed */
#define XEMACPS_IXR_PTPSTX_MASK 0x00200000U /**< PTP Sync TXed */
#define XEMACPS_IXR_PTPDRTX_MASK 0x00100000U /**< PTP Delay_req TXed */
#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync RXed */
#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req RXed */
#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */
#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached
zero */
#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */
#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */
#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */
#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */
#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or
no buffers*/
#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */
#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */
#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */
#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */
#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */
#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */
#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */
#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \
(u32)XEMACPS_IXR_RETRY_MASK | \
(u32)XEMACPS_IXR_URUN_MASK)
#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \
(u32)XEMACPS_IXR_RXUSED_MASK | \
(u32)XEMACPS_IXR_RXOVR_MASK)
/*@}*/
/** @name PHY Maintenance bit definitions
* @{
*/
#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */
#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */
#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */
#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */
#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */
#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */
#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */
#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */
/*@}*/
/** @name RX watermark bit definitions
* @{
*/
#define XEMACPS_RXWM_HIGH_MASK 0x0000FFFFU /**< RXWM high mask */
#define XEMACPS_RXWM_LOW_MASK 0xFFFF0000U /**< RXWM low mask */
#define XEMACPS_RXWM_LOW_SHFT_MSK 16U /**< Shift for RXWM low */
/*@}*/
/* Transmit buffer descriptor status words offset
* @{
*/
#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */
#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */
#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */
/*
* @}
*/
/* Transmit buffer descriptor status words bit positions.
* Transmit buffer descriptor consists of two 32-bit registers,
* the first - word0 contains a 32-bit address pointing to the location of
* the transmit data.
* The following register - word1, consists of various information to control
* the XEmacPs transmit process. After transmit, this is updated with status
* information, whether the frame was transmitted OK or why it had failed.
* @{
*/
#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */
#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */
#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */
#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */
#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */
#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */
#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */
/*
* @}
*/
/* Receive buffer descriptor status words bit positions.
* Receive buffer descriptor consists of two 32-bit registers,
* the first - word0 contains a 32-bit word aligned address pointing to the
* address of the buffer. The lower two bits make up the wrap bit indicating
* the last descriptor and the ownership bit to indicate it has been used by
* the XEmacPs.
* The following register - word1, contains status information regarding why
* the frame was received (the filter match condition) as well as other
* useful info.
* @{
*/
#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */
#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */
#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */
#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address
matched */
#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */
#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */
#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */
#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */
#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */
#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */
#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */
#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */
#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */
#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */
#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */
#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */
/*
* @}
*/
/*
* Define appropriate I/O access method to memory mapped I/O or other
* interface if necessary.
*/
#define XEmacPs_In32 Xil_In32
#define XEmacPs_Out32 Xil_Out32
/****************************************************************************/
/**
*
* Read the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be read
*
* @return The 32-bit value of the register
*
* @note
* C-style signature:
* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
*
*****************************************************************************/
#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
/****************************************************************************/
/**
*
* Write the given register.
*
* @param BaseAddress is the base address of the device
* @param RegOffset is the register offset to be written
* @param Data is the 32-bit value to write to the register
*
* @return None.
*
* @note
* C-style signature:
* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
* u32 Data)
*
*****************************************************************************/
#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes *****************************/
/*
* Perform reset operation to the emacps interface
*/
void XEmacPs_ResetHw(u32 BaseAddr);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv.h
+169
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@@ -0,0 +1,169 @@
/******************************************************************************
* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv.h
*
* Defines common services that are typically found in a host operating.
* environment. This include file simply includes an OS specific file based
* on the compile-time constant BUILD_ENV_*, where * is the name of the target
* environment.
*
* All services are defined as macros.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00b ch 10/24/02 Added XENV_LINUX
* 1.00a rmm 04/17/02 First release
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XENV_H /* prevent circular inclusions */
#define XENV_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/*
* Select which target environment we are operating under
*/
/* VxWorks target environment */
#if defined XENV_VXWORKS
#include "xenv_vxworks.h"
/* Linux target environment */
#elif defined XENV_LINUX
#include "xenv_linux.h"
/* Unit test environment */
#elif defined XENV_UNITTEST
#include "ut_xenv.h"
/* Integration test environment */
#elif defined XENV_INTTEST
#include "int_xenv.h"
/* Standalone environment selected */
#else
#include "xenv_standalone.h"
#endif
/*
* The following comments specify the types and macro wrappers that are
* expected to be defined by the target specific header files
*/
/**************************** Type Definitions *******************************/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP
*
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
/***************** Macros (Inline Functions) Definitions *********************/
/*****************************************************************************/
/**
*
* XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr is the destination address to copy data to.
* @param SrcPtr is the source address to copy data from.
* @param Bytes is the number of bytes to copy.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
*
* Fills an area of memory with constant data.
*
* @param DestPtr is the destination address to set.
* @param Data contains the value to set.
* @param Bytes is the number of bytes to set.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
*
* Samples the processor's or external timer's time base counter.
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of microseconds.
*/
/*****************************************************************************/
/**
*
* XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
*
* Computes the delta between the two time stamps.
*
* @param Stamp1Ptr - First sampled time stamp.
* @param Stamp1Ptr - Sedond sampled time stamp.
*
* @return An unsigned int value with units of milliseconds.
*/
/*****************************************************************************//**
*
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds.
*
* @param delay is the number of microseconds to delay.
*
* @return None
*/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
*@endcond
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv_standalone.h
+350
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@@ -0,0 +1,350 @@
/******************************************************************************
* Copyright (c) 2002 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xenv_standalone.h
*
* Defines common services specified by xenv.h.
*
* @note
* This file is not intended to be included directly by driver code.
* Instead, the generic xenv.h file is intended to be included by driver
* code.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a wgr 02/28/07 Added cache handling macros.
* 1.00a wgr 02/27/07 Simplified code. Deprecated old-style macro names.
* 1.00a rmm 01/24/06 Implemented XENV_USLEEP. Assume implementation is being
* used under Xilinx standalone BSP.
* 1.00a xd 11/03/04 Improved support for doxygen.
* 1.00a rmm 03/21/02 First release
* 1.00a wgr 03/22/07 Converted to new coding style.
* 1.00a rpm 06/29/07 Added udelay macro for standalone
* 1.00a xd 07/19/07 Included xparameters.h as XPAR_ constants are referred
* to in MICROBLAZE section
* 1.00a ecm 09/19/08 updated for v7.20 of Microblaze, new functionality
*
* </pre>
*
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XENV_STANDALONE_H
#define XENV_STANDALONE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/******************************************************************************
*
* Get the processor dependent includes
*
******************************************************************************/
#include <string.h>
#if defined __MICROBLAZE__
# include "mb_interface.h"
# include "xparameters.h" /* XPAR constants used below in MB section */
#elif defined __PPC__
# include "sleep.h"
# include "xcache_l.h" /* also include xcache_l.h for caching macros */
#endif
/******************************************************************************
*
* MEMCPY / MEMSET related macros.
*
* The following are straight forward implementations of memset and memcpy.
*
* NOTE: memcpy may not work if source and target memory area are overlapping.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* Copies a non-overlapping block of memory.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param SrcPtr
* Source address to copy data from.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
*
* @note
* This implementation MAY BREAK work if source and target memory
* area are overlapping.
*
*****************************************************************************/
#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
/*****************************************************************************/
/**
*
* Fills an area of memory with constant data.
*
* @param DestPtr
* Destination address to copy data to.
*
* @param Data
* Value to set.
*
* @param Bytes
* Number of bytes to copy.
*
* @return None.
*
* @note
* The use of XENV_MEM_FILL is deprecated. Use memset() instead.
*
*****************************************************************************/
#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
/******************************************************************************
*
* TIME related macros
*
******************************************************************************/
/**
* A structure that contains a time stamp used by other time stamp macros
* defined below. This structure is processor dependent.
*/
typedef s32 XENV_TIME_STAMP;
/*****************************************************************************/
/**
*
* Time is derived from the 64 bit PPC timebase register
*
* @param StampPtr is the storage for the retrieved time stamp.
*
* @return None.
*
* @note
*
* Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
* <br><br>
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_GET(StampPtr)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
*
* This macro is not yet implemented and always returns 0.
*
* @param Stamp1Ptr is the first sampled time stamp.
* @param Stamp2Ptr is the second sampled time stamp.
*
* @return 0
*
* @note
*
* This macro must be implemented by the user.
*
*****************************************************************************/
#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0)
/*****************************************************************************/
/**
* XENV_USLEEP(unsigned delay)
*
* Delay the specified number of microseconds. Not implemented without OS
* support.
*
* @param delay
* Number of microseconds to delay.
*
* @return None.
*
*****************************************************************************/
#ifdef __PPC__
#define XENV_USLEEP(delay) usleep(delay)
#define udelay(delay) usleep(delay)
#else
#define XENV_USLEEP(delay)
#define udelay(delay)
#endif
/******************************************************************************
*
* CACHE handling macros / mappings
*
******************************************************************************/
/******************************************************************************
*
* Processor independent macros
*
******************************************************************************/
#define XCACHE_ENABLE_CACHE() \
{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
#define XCACHE_DISABLE_CACHE() \
{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
/******************************************************************************
*
* MicroBlaze case
*
* NOTE: Currently the following macros will only work on systems that contain
* only ONE MicroBlaze processor. Also, the macros will only be enabled if the
* system is built using a xparameters.h file.
*
******************************************************************************/
#if defined __MICROBLAZE__
/* Check if MicroBlaze data cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache()
# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache()
# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache()
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
#else
# define XCACHE_ENABLE_DCACHE()
# define XCACHE_DISABLE_DCACHE()
# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
#endif /*XPAR_MICROBLAZE_USE_DCACHE*/
/* Check if MicroBlaze instruction cache was built into the core.
*/
#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache()
# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache()
# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache()
# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
#else
# define XCACHE_ENABLE_ICACHE()
# define XCACHE_DISABLE_ICACHE()
#endif /*XPAR_MICROBLAZE_USE_ICACHE*/
/******************************************************************************
*
* PowerPC case
*
* Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
* specific memory region (0x80000001). Each bit (0-30) in the regions
* bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
* range.
*
* regions --> cached address range
* ------------|--------------------------------------------------
* 0x80000000 | [0, 0x7FFFFFF]
* 0x00000001 | [0xF8000000, 0xFFFFFFFF]
* 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
*
******************************************************************************/
#elif defined __PPC__
#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001)
#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache()
#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001)
#define XCACHE_DISABLE_ICACHE() XCache_DisableICache()
#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache()
/******************************************************************************
*
* Unknown processor / architecture
*
******************************************************************************/
#else
/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
#endif
#ifdef __cplusplus
}
#endif
#endif /* #ifndef XENV_STANDALONE_H */
/**
*@endcond
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops.h
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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops.h
* @addtogroup gpiops Overview
* @{
* @details
*
* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
* Controller.
*
* The GPIO Controller supports the following features:
* - 6 banks
* - Masked writes (There are no masked reads)
* - Bypass mode
* - Configurable Interrupts (Level/Edge)
*
* This driver is intended to be RTOS and processor independent. Any needs for
* dynamic memory management, threads or thread mutual exclusion, virtual
* memory, or cache control must be satisfied by the layer above this driver.
*
* Here is GPIO Bank and Pin mapping information for different platforms.
* Zynq:
* PS GPIO contain 4 banks and 118 pins
* Bank 0 MIO pins 0 - 31
* Bank 1 MIO pins 32 - 53
* Bank 2 MIO pins 54 - 85
* Bank 3 EMIO signals 86 - 117
*
* Zynq Ultrascale+ MP:
* PS GPIO contain 6 banks and 174 pins
* Bank 0 MIO pins 0 - 25
* Bank 1 MIO pins 26 - 51
* Bank 2 MIO pins 52 - 77
* Bank 3 EMIO signals 78 - 109
* Bank 4 EMIO signals 110 - 141
* Bank 5 EMIO signals 142 - 173
* Versal: Two GPIOPS instances PMC GPIO and PS GPIO
* PMC GPIO contain 4 banks and 116 pins
* Bank 0 MIO pins 0 - 25
* Bank 1 MIO pins 26 - 51
* Bank 3 EMIO signals 52 - 83
* Bank 4 EMIO signals 84 - 115
* PS GPIO contains 2 banks and 58 pins
* Bank 0 MIO pins 0 - 25
* Bank 3 EMIO signals 26-57
*
* This driver supports all the features listed above, if applicable.
*
* <b>Driver Description</b>
*
* The device driver enables higher layer software (e.g., an application) to
* communicate to the GPIO.
*
* <b>Interrupts</b>
*
* The driver provides interrupt management functions and an interrupt handler.
* Users of this driver need to provide callback functions. An interrupt handler
* example is available with the driver.
*
* <b>Threads</b>
*
* This driver is not thread safe. Any needs for threads or thread mutual
* exclusion must be satisfied by the layer above this driver.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and it
* is recommended that users leave asserts on during development.
*
* <b>Building the driver</b>
*
* The XGpioPs driver is composed of several source files. This allows the user
* to build and link only those parts of the driver that are necessary.
* <br><br>
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sv 01/15/10 First Release
* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
* relevant to Zynq device.The interrupts are disabled
* for output pins on all banks during initialization.
* 1.02a hk 08/22/13 Added low level reset API
* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
* passed to APIs. CR# 822636
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/05/17 Added tabspace for return statements in functions of
* gpiops examples for proper documentation while
* generating doxygen.
* 3.3 ms 04/17/17 Added notes about gpio input and output pin description
* for zcu102 and zc702 boards in polled and interrupt
* example, configured Interrupt pin to input pin for
* proper functioning of interrupt example.
* 3.4 aru 08/17/18 Resolved MISRA-C mandatory violations. CR# 1007751
* 3.5 sne 03/01/19 Fixes violations according to MISRAC-2012
* in safety mode and modified the code such as
* Use of mixed mode arithmetic,Declared the pointer param
* as Pointer to const,Casting operation to a pointer,
* Literal value requires a U suffix.
* 3.5 sne 03/14/19 Added Versal support.
* 3.6 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
* sync with standalone BSP
* 3.6 sne 06/12/19 Fixed IAR compiler warning.
* 3.6 sne 08/14/19 Added interrupt handler support on versal.
* 3.7 sne 12/04/19 Reverted versal examples support.
* 3.8 sne 08/28/20 Modify Makefile to support parallel make execution.
* 3.8 sne 09/17/20 Added description for Versal PS and PMC GPIO pins.
* 3.9 sne 03/15/21 Fixed MISRA-C violations.
* 3.11 sg 02/23/23 Update bank and pin mapping information.
* 3.12 gm 07/11/23 Added SDT support.
*
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_H /* prevent circular inclusions */
#define XGPIOPS_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xgpiops_hw.h"
#include "xplatform_info.h"
/************************** Constant Definitions *****************************/
/** @name Interrupt types
* @{
* The following constants define the interrupt types that can be set for each
* GPIO pin.
*/
#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
/** @}*/
#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */
#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */
#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a
* Zynq Ultrascale+ MP GPIO device
*/
#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */
#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the
* Zynq Ultrascale+ MP GPIO device
* 0 - 25, Bank 0
* 26 - 51, Bank 1
* 52 - 77, Bank 2
* 78 - 109, Bank 3
* 110 - 141, Bank 4
* 142 - 173, Bank 5
*/
#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device
* 0 - 31, Bank 0
* 32 - 53, Bank 1
* 54 - 85, Bank 2
* 86 - 117, Bank 3
*/
/**************************** Type Definitions *******************************/
/****************************************************************************/
/**
* This handler data type allows the user to define a callback function to
* handle the interrupts for the GPIO device. The application using this
* driver is expected to define a handler of this type, to support interrupt
* driven mode. The handler executes in an interrupt context such that minimal
* processing should be performed.
*
* @param CallBackRef is a callback reference passed in by the upper layer
* when setting the callback functions for a GPIO bank. It is
* passed back to the upper layer when the callback is invoked. Its
* type is not important to the driver component, so it is a void
* pointer.
* @param Bank is the bank for which the interrupt status has changed.
* @param Status is the Interrupt status of the GPIO bank.
*
*****************************************************************************/
typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
/**
* This typedef contains configuration information for a device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
UINTPTR BaseAddr; /**< Register base address */
#ifdef SDT
u16 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XGpioPs_Config;
/**
* The XGpioPs driver instance data. The user is required to allocate a
* variable of this type for the GPIO device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XGpioPs_Config GpioConfig; /**< Device configuration */
u32 IsReady; /**< Device is initialized and ready */
XGpioPs_Handler Handler; /**< Status handlers for all banks */
void *CallBackRef; /**< Callback ref for bank handlers */
u32 Platform; /**< Platform data */
u32 MaxPinNum; /**< Max pins in the GPIO device */
u8 MaxBanks; /**< Max banks in a GPIO device */
u32 PmcGpio; /**< Flag for accessing PS GPIO for versal*/
} XGpioPs;
/************************** Variable Definitions *****************************/
extern XGpioPs_Config XGpioPs_ConfigTable[];
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/* Functions in xgpiops.c */
s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, const XGpioPs_Config *ConfigPtr,
u32 EffectiveAddr);
/* Bank APIs in xgpiops.c */
u32 XGpioPs_Read(const XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_Write(const XGpioPs *InstancePtr, u8 Bank, u32 Data);
void XGpioPs_SetDirection(const XGpioPs *InstancePtr, u8 Bank, u32 Direction);
u32 XGpioPs_GetDirection(const XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_SetOutputEnable(const XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
u32 XGpioPs_GetOutputEnable(const XGpioPs *InstancePtr, u8 Bank);
#ifdef versal
void XGpioPs_GetBankPin(const XGpioPs *InstancePtr,u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
#else
void XGpioPs_GetBankPin(u8 PinNumber,u8 *BankNumber, u8 *PinNumberInBank);
#endif
/* Pin APIs in xgpiops.c */
u32 XGpioPs_ReadPin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_WritePin(const XGpioPs *InstancePtr, u32 Pin, u32 Data);
void XGpioPs_SetDirectionPin(const XGpioPs *InstancePtr, u32 Pin, u32 Direction);
u32 XGpioPs_GetDirectionPin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_SetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
u32 XGpioPs_GetOutputEnablePin(const XGpioPs *InstancePtr, u32 Pin);
/* Diagnostic functions in xgpiops_selftest.c */
s32 XGpioPs_SelfTest(const XGpioPs *InstancePtr);
/* Functions in xgpiops_intr.c */
/* Bank APIs in xgpiops_intr.c */
void XGpioPs_IntrEnable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_IntrDisable(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
u32 XGpioPs_IntrGetEnabled(const XGpioPs *InstancePtr, u8 Bank);
u32 XGpioPs_IntrGetStatus(const XGpioPs *InstancePtr, u8 Bank);
void XGpioPs_IntrClear(const XGpioPs *InstancePtr, u8 Bank, u32 Mask);
void XGpioPs_SetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
u32 IntrPolarity, u32 IntrOnAny);
void XGpioPs_GetIntrType(const XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
u32 *IntrPolarity, u32 *IntrOnAny);
void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
XGpioPs_Handler FuncPointer);
void XGpioPs_IntrHandler(const XGpioPs *InstancePtr);
/* Pin APIs in xgpiops_intr.c */
void XGpioPs_SetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
u8 XGpioPs_GetIntrTypePin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrEnablePin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrDisablePin(const XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetEnabledPin(const XGpioPs *InstancePtr, u32 Pin);
u32 XGpioPs_IntrGetStatusPin(const XGpioPs *InstancePtr, u32 Pin);
void XGpioPs_IntrClearPin(const XGpioPs *InstancePtr, u32 Pin);
/* Functions in xgpiops_sinit.c */
#ifndef SDT
XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
#else
XGpioPs_Config *XGpioPs_LookupConfig(u32 BaseAddress);
#endif
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops_hw.h
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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xgpiops_hw.h
* @addtogroup gpiops Overview
* @{
*
* This header file contains the identifiers and basic driver functions (or
* macros) that can be used to access the device. Other driver functions
* are defined in xgpiops.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------
* 1.00a sv 01/15/10 First Release
* 1.02a hk 08/22/13 Added low level reset API function prototype and
* related constant definitions
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.1 kvn 04/13/15 Corrected reset values of banks.
* 3.5 sne 03/14/19 Added versal support.
* </pre>
*
******************************************************************************/
#ifndef XGPIOPS_HW_H /* prevent circular inclusions */
#define XGPIOPS_HW_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/** @name Register offsets for the GPIO. Each register is 32 bits.
* @{
*/
#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /**< Mask and Data Register LSW, WO */
#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /**< Mask and Data Register MSW, WO */
#define XGPIOPS_DATA_OFFSET 0x00000040U /**< Data Register, RW */
#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /**< Data Register - Input, RO */
#define XGPIOPS_DIRM_OFFSET 0x00000204U /**< Direction Mode Register, RW */
#define XGPIOPS_OUTEN_OFFSET 0x00000208U /**< Output Enable Register, RW */
#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /**< Interrupt Mask Register, RO */
#define XGPIOPS_INTEN_OFFSET 0x00000210U /**< Interrupt Enable Register, WO */
#define XGPIOPS_INTDIS_OFFSET 0x00000214U /**< Interrupt Disable Register, WO*/
#define XGPIOPS_INTSTS_OFFSET 0x00000218U /**< Interrupt Status Register, RO */
#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /**< Interrupt Type Register, RW */
#define XGPIOPS_INTPOL_OFFSET 0x00000220U /**< Interrupt Polarity Register, RW */
#define XGPIOPS_INTANY_OFFSET 0x00000224U /**< Interrupt On Any Register, RW */
/** @} */
/** @name Register offsets for each Bank.
* @{
*/
#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /**< Data/Mask Registers offset */
#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /**< Data Registers offset */
#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /**< Registers offset */
/** @} */
/* For backwards compatibility */
#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 /**< Mask for backward support */
/** @name Interrupt type reset values for each bank
* @{
*/
#ifdef XPAR_PSU_GPIO_0_BASEADDR
#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
#else
#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU /**< Resets specific to Zynq */
#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU /**< Resets specific to Zynq */
#endif
#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /**< Reset common to both platforms */
#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU /**< Resets specific to Zynq Ultrascale+ MP */
/** @} */
#define XGPIOPS_PS_GPIO_BASEADDR 0xFF0B0000U /**< Flag for Base Address for PS_GPIO in Versal */
#define XGPIOPS_ZERO 0U /**< Flag for 0 Value */
#define XGPIOPS_ONE 1U /**< Flag for 1 Value */
#define XGPIOPS_TWO 2U /**< Flag for 2 Value */
#define XGPIOPS_THREE 3U /**< Flag for 3 Value */
#define XGPIOPS_FOUR 4U /**< Flag for 4 Value */
#define XGPIOPS_SIX 6U /**< Flag for 6 Value */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/**
*
* This macro reads the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the register offset to be read.
*
* @return The 32-bit value of the register
*
* @note None.
*
*****************************************************************************/
#define XGpioPs_ReadReg(BaseAddr, RegOffset) \
Xil_In32((BaseAddr) + (u32)(RegOffset))
/****************************************************************************/
/**
*
* This macro writes to the given register.
*
* @param BaseAddr is the base address of the device.
* @param RegOffset is the offset of the register to be written.
* @param Data is the 32-bit value to write to the register.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \
Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
/************************** Function Prototypes ******************************/
void XGpioPs_ResetHw(UINTPTR BaseAddress);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XGPIOPS_HW_H */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_assert.h
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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_assert.h
*
* @addtogroup common_assert_apis Assert APIs and Macros
*
* The xil_assert.h file contains assert related functions and macros.
* Assert APIs/Macros specifies that a application program satisfies certain
* conditions at particular points in its execution. These function can be
* used by application programs to ensure that, application code is satisfying
* certain conditions.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_ASSERT_H /* prevent circular inclusions */
#define XIL_ASSERT_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
#define XIL_ASSERT_NONE 0U
#define XIL_ASSERT_OCCURRED 1U
#define XNULL NULL
extern u32 Xil_AssertStatus;
extern s32 Xil_AssertWait;
extern void Xil_Assert(const char8 *File, s32 Line);
/**
*@endcond
*/
void XNullHandler(void *NullParameter);
/**
* This data type defines a callback to be invoked when an
* assert occurs. The callback is invoked only when asserts are enabled
*/
typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
/***************** Macros (Inline Functions) Definitions *********************/
#ifndef NDEBUG
/*****************************************************************************/
/**
* @brief This assert macro is to be used for void functions. This in
* conjunction with the Xil_AssertWait boolean can be used to
* accommodate tests so that asserts which fail allow execution to
* continue.
*
* @param Expression: expression to be evaluated. If it evaluates to
* false, the assert occurs.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertVoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
} \
}
/*****************************************************************************/
/**
* @brief This assert macro is to be used for functions that do return a
* value. This in conjunction with the Xil_AssertWait boolean can be
* used to accommodate tests so that asserts which fail allow execution
* to continue.
*
* @param Expression: expression to be evaluated. If it evaluates to false,
* the assert occurs.
*
* @return Returns 0 unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertNonvoid(Expression) \
{ \
if (Expression) { \
Xil_AssertStatus = XIL_ASSERT_NONE; \
} else { \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
} \
}
/*****************************************************************************/
/**
* @brief Always assert. This assert macro is to be used for void functions.
* Use for instances where an assert should always occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertVoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return; \
}
/*****************************************************************************/
/**
* @brief Always assert. This assert macro is to be used for functions that
* do return a value. Use for instances where an assert should always
* occur.
*
* @return Returns void unless the Xil_AssertWait variable is true, in which
* case no return is made and an infinite loop is entered.
*
******************************************************************************/
#define Xil_AssertNonvoidAlways() \
{ \
Xil_Assert(__FILE__, __LINE__); \
Xil_AssertStatus = XIL_ASSERT_OCCURRED; \
return 0; \
}
#else
#define Xil_AssertVoid(Expression)
#define Xil_AssertVoidAlways()
#define Xil_AssertNonvoid(Expression)
#define Xil_AssertNonvoidAlways()
#endif
/************************** Function Prototypes ******************************/
void Xil_AssertSetCallback(Xil_AssertCallback Routine);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_assert_apis".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache.h
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/******************************************************************************
* Copyright (C) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache.h
*
* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
*
* Cache functions provide access to cache related operations such as flush
* and invalidate for instruction and data caches. It gives option to perform
* the cache operations on a single cacheline, a range of memory and an entire
* cache.
*
* @{
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 01/29/10 First release
* 3.04a sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
* APIs.
* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
* 9.0 ml 03/03/23 Updated function prototypes.
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_CACHE_H
#define XIL_CACHE_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __GNUC__
#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
#elif defined (__ICCARM__)
#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
#endif
/**
*@endcond
*/
void Xil_DCacheEnable(void);
void Xil_DCacheDisable(void);
void Xil_DCacheInvalidate(void);
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
void Xil_DCacheFlush(void);
void Xil_DCacheFlushRange(INTPTR adr, u32 len);
void Xil_ICacheEnable(void);
void Xil_ICacheDisable(void);
void Xil_ICacheInvalidate(void);
void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
#ifdef __cplusplus
}
#endif
#endif
/**
* @} End of "addtogroup a9_cache_apis".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_l.h
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/******************************************************************************
* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache_l.h
*
* Contains L1 and L2 specific functions for the ARM cache functionality
* used by xcache.c. This functionality is being made available here for
* more sophisticated users.
*
* @addtogroup a9_cache_apis
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 01/24/10 First release
* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
* </pre>
*
******************************************************************************/
#ifndef XIL_CACHE_MACH_H
#define XIL_CACHE_MACH_H
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/************************** Function Prototypes ******************************/
void Xil_DCacheInvalidateLine(u32 adr);
void Xil_DCacheFlushLine(u32 adr);
void Xil_DCacheStoreLine(u32 adr);
void Xil_ICacheInvalidateLine(u32 adr);
void Xil_L1DCacheEnable(void);
void Xil_L1DCacheDisable(void);
void Xil_L1DCacheInvalidate(void);
void Xil_L1DCacheInvalidateLine(u32 adr);
void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
void Xil_L1DCacheFlush(void);
void Xil_L1DCacheFlushLine(u32 adr);
void Xil_L1DCacheFlushRange(u32 adr, u32 len);
void Xil_L1DCacheStoreLine(u32 adr);
void Xil_L1ICacheEnable(void);
void Xil_L1ICacheDisable(void);
void Xil_L1ICacheInvalidate(void);
void Xil_L1ICacheInvalidateLine(u32 adr);
void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
void Xil_L2CacheEnable(void);
void Xil_L2CacheDisable(void);
void Xil_L2CacheInvalidate(void);
void Xil_L2CacheInvalidateLine(u32 adr);
void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
void Xil_L2CacheFlush(void);
void Xil_L2CacheFlushLine(u32 adr);
void Xil_L2CacheFlushRange(u32 adr, u32 len);
void Xil_L2CacheStoreLine(u32 adr);
#ifdef __cplusplus
}
#endif
#endif
/**
* @} End of "addtogroup a9_cache_apis".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h
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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_cache_vxworks.h
*
* Contains the cache related functions for VxWorks that is wrapped by
* xil_cache.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 12/11/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_CACHE_VXWORKS_H
#define XIL_CACHE_VXWORKS_H
#ifdef __cplusplus
extern "C" {
#endif
#include "vxWorks.h"
#include "vxLib.h"
#include "sysLibExtra.h"
#include "cacheLib.h"
#if (CPU_FAMILY==PPC)
#define Xil_DCacheEnable() cacheEnable(DATA_CACHE)
#define Xil_DCacheDisable() cacheDisable(DATA_CACHE)
#define Xil_DCacheInvalidateRange(Addr, Len) \
cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_DCacheFlushRange(Addr, Len) \
cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE)
#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE)
#define Xil_ICacheInvalidateRange(Addr, Len) \
cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
#else
#error "Unknown processor / architecture. Must be PPC for VxWorks."
#endif
#ifdef __cplusplus
}
#endif
#endif
/**
*@endcond
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_clocking.h
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/******************************************************************************
* Copyright (c) 2020 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_clocking.h
*
* The xil_clocking.h file contains clocking related functions and macros.
* certain conditions.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 7.2 sd 12/11/19 First release
* 7.2 sd 03/20/20 Added checking for isolation case
* 7.7 sk 01/10/22 Add function prototype for Xil_ClockGetRate to fix
* misra_c_2012_rule_8_4 violation.
* 9.0 ml 03/03/23 Added description to fix doxygen warnings.
* </pre>
*
******************************************************************************/
#ifndef XIL_CLOCKING_H /**< prevent circular inclusions */
#define XIL_CLOCKING_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#include "xdebug.h"
#include "xil_printf.h"
#include "xil_types.h"
#include "xil_assert.h"
#include "xparameters.h"
#include "xstatus.h"
#if defined (XPAR_XCRPSU_0_DEVICE_ID) || defined(XPAR_PSU_CRL_APB_BASEADDR)
#include "xclockps.h"
#else
typedef u32 XClock_OutputClks;
typedef u64 XClockRate;
#endif
/***************************** Include Files *********************************/
/************************** Constant Definitions *****************************/
XStatus Xil_ClockDisable(XClock_OutputClks ClockId);
XStatus Xil_ClockEnable(XClock_OutputClks ClockId);
XStatus Xil_ClockInit(void);
XStatus Xil_ClockGet(void);
XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate);
XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cryptoalginfo.h
+50
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/******************************************************************************/
/**
* Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
* @file xil_cryptoalginfo.h
* @{
* @details
*
* Crypto algotithm information structure declaration.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 9.0 mmd 07/04/23 First release.
* </pre>
*
*****************************************************************************/
#ifndef XIL_CRYPTOALGINFO_H
#define XIL_CRYPTOALGINFO_H
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/**************************** Type Definitions *******************************/
typedef enum _Xil_CryptoAlgNistStatus {
NOT_APPLICABLE = 0x00,
NIST_COMPLIANT = 0x11,
NIST_NON_COMPLIANT = 0xFE,
} Xil_CryptoAlgNistStatus;
typedef struct _Xil_CryptoAlgInfo {
u32 Version;
Xil_CryptoAlgNistStatus NistStatus;
} Xil_CryptoAlgInfo;
#ifdef __cplusplus
}
#endif
#endif /* XIL_CRYPTOALGINFO_H */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_errata.h
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/******************************************************************************
* Copyright (c) 2013 - 2022 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_errata.h
*
* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
* @{
* Various ARM errata are handled in the standalone BSP. The implementation for
* errata handling follows ARM guidelines and is based on the open source Linux
* support for these errata.
*
* @note The errata handling is enabled by default. To disable handling of all the
* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
* disable errata on a per-erratum basis, un-define relevant macros in
* xil_errata.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a srt 04/18/13 First release
* 6.6 mus 12/07/17 Removed errata 753970, It fixes CR#989132
* 7.7 asa 01/06/22 Removed errata 742230 and 743622. These are
* already fixed in Cortex-A9 r3p0, the revision
* that is being used in Zynq platforms.
* </pre>
*
******************************************************************************/
#ifndef XIL_ERRATA_H
#define XIL_ERRATA_H
#ifdef __cplusplus
extern "C" {
#endif
/**
*@cond nocomments
*/
/**
* @name errata_definitions
*
* The errata conditions handled in the standalone BSP are listed below
* @{
*/
#define ENABLE_ARM_ERRATA 1
/**
*@endcond
*/
#ifdef ENABLE_ARM_ERRATA
/**
* Errata No: 775420
* Description: A data cache maintenance operation which aborts,
* might lead to deadlock
*/
#define CONFIG_ARM_ERRATA_775420 1
/**
* Errata No: 794073
* Description: Speculative instruction fetches with MMU disabled
* might not comply with architectural requirements
*/
#define CONFIG_ARM_ERRATA_794073 1
/** PL310 L2 Cache Errata */
/**
* Errata No: 588369
* Description: Clean & Invalidate maintenance operations do not
* invalidate clean lines
*/
#define CONFIG_PL310_ERRATA_588369 1
/**
* Errata No: 727915
* Description: Background Clean and Invalidate by Way operation
* can cause data corruption
*/
#define CONFIG_PL310_ERRATA_727915 1
/*@}*/
#endif /* ENABLE_ARM_ERRATA */
#ifdef __cplusplus
}
#endif
#endif /* XIL_ERRATA_H */
/**
* @} End of "addtogroup a9_errata".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_exception.h
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@@ -0,0 +1,532 @@
/******************************************************************************
* Copyright (c) 2015 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_exception.h
*
* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
* For exception related functions that can be used across all Xilinx supported
* processors, please use xil_exception.h.
*
* @addtogroup arm_exception_apis ARM Processor Exception Handling
* @{
* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
* utilized for enabling/disabling IRQ, registering/removing handler for
* exceptions or initializing exception vector table with null handler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.2 pkp 28/05/15 First release
* 6.0 mus 27/07/16 Consolidated file for a53,a9 and r5 processors
* 6.7 mna 26/04/18 Add API Xil_GetExceptionRegisterHandler.
* 6.7 asa 18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
* 7.0 mus 01/03/19 Tweak Xil_ExceptionEnableMask and
* Xil_ExceptionDisableMask macros to support legacy
* examples for Cortexa72 EL3 exception level.
* 7.3 mus 04/15/20 Added Xil_EnableNestedInterrupts and
* Xil_DisableNestedInterrupts macros for ARMv8.
* For Cortexa72, these macro's would not be supported
* at EL3, as Cortexa72 is using GIC-500(GICv3), which
* triggeres only FIQ at EL3. Fix for CR#1062506
* 7.6 mus 09/17/21 Updated flag checking to fix warning reported with
* -Wundef compiler option CR#1110261
* 7.7 mus 01/31/22 Few of the #defines in xil_exception.h in are treated
* in different way based on "versal" flag. In existing
* flow, this flag is defined only in xparameters.h and
* BSP compiler flags, it is not defined in application
* compiler flags. So, including xil_exception.h in
* application source file, without including
* xparameters.h results in incorrect behavior.
* Including xparameters.h in xil_exception.h to avoid
* such issues. It fixes CR#1120498.
* 8.0 mus 02/24/22 Updated few macros to support legacy driver examples
* for CortexR52. This is needed, as by default scugic
* driver configures interrupts as group0 and CortexR52
* GIC triggers FIQ for group0 interrupts.
* 8.0 sk 03/02/22 Define XExc_VectorTableEntry structure to fix
* misra_c_2012_rule_5_6 violation.
* 8.0 sk 03/02/22 Add XExc_VectorTable as extern to fix misra_c_2012_
* rule_8_4 violation.
* 8.1 asa 02/12/23 Updated data abort and prefetch abort fault
* status reporting for ARMv7.
* Updated Sync and SError fault status reporting
* for ARMv8.
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
#define XIL_EXCEPTION_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xpseudo_asm.h"
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#include "xdebug.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions ****************************/
#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE
#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE
#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
#define XIL_EXCEPTION_ID_FIRST 0U
#if defined (__aarch64__)
#define XIL_EXCEPTION_ID_SYNC_INT 1U
#define XIL_EXCEPTION_ID_IRQ_INT 2U
#define XIL_EXCEPTION_ID_FIQ_INT 3U
#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U
#define XIL_EXCEPTION_ID_LAST 5U
#else
#define XIL_EXCEPTION_ID_RESET 0U
#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U
#define XIL_EXCEPTION_ID_SWI_INT 2U
#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U
#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U
#define XIL_EXCEPTION_ID_IRQ_INT 5U
#define XIL_EXCEPTION_ID_FIQ_INT 6U
#define XIL_EXCEPTION_ID_LAST 6U
#endif
#ifdef DEBUG
#if defined (__aarch64__)
#define ARMV8_SYNC_ERROR 0x01U
#define ARMV8_SERROR 0x02U
#define ARMV8_FAR_VALUE_VALID 0x01U
#define ARMV8_ESR_EC_SHIFT 26U
#define ARMV8_ESR_EC_MASK ((0x3FU) << ARMV8_ESR_EC_SHIFT)
#define ARMV8_EXTRACT_ESR_EC(Val) \
(((Val) & ARMV8_ESR_EC_MASK) >> ARMV8_ESR_EC_SHIFT)
#define ARMV8_ESR_IL_SHIFT (25U)
#define ARMV8_ESR_IL_MASK ((1U) << ARMV8_ESR_IL_SHIFT)
#define ARMV8_EXTRACT_ESR_IL(Val) \
(((Val) & ARMV8_ESR_IL_MASK) >> ARMV8_ESR_IL_SHIFT)
#define ARMV8_ESR_ISS_MASK (ARMV8_ESR_IL_MASK - 1U)
#define ARMV8_EXTRACT_ESR_ISS(Val) ((Val) & ARMV8_ESR_ISS_MASK)
#define ARMV8_ESR_EC_UNKNOWN_ERR 0x00U
#define ARMV8_ESR_EC_FP_ASIMD 0x07U
#define ARMV8_ESR_ILL_EXECUTION_STATE 0x0EU
#define ARMV8_ESR_EC_DATA_ABORT_LOWER 0x24U
#define ARMV8_ESR_EC_DATA_ABORT 0x25U
#define ARMV8_ESR_EC_INS_ABORT_LOWER 0x20U
#define ARMV8_ESR_EC_INS_ABORT 0x21U
#define ARMV8_ESR_EC_PC_ALIGNMENT_FAULT 0x22U
#define ARMV8_ESR_EC_SP_ALIGNMENT_FAULT 0x26U
#define ARMV8_ESR_EC_SERROR 0x2FU
/* ISS field definitions shared by different classes */
#define ARMV8_ESR_ISS_WNR_SHIFT (6U)
#define ARMV8_ESR_ISS_WNR_MASK ((1U) << ARMV8_ESR_ISS_WNR_SHIFT)
/* Asynchronous Error Type */
#define ARMV8_ESR_ISS_AET_SHIFT (10U)
#define ARMV8_ESR_ISS_AET_MASK ((0x7U) << ARMV8_ESR_ISS_AET_SHIFT)
#define ARMV8_ESR_ISS_AET_UC ((0U) << ARMV8_ESR_ISS_AET_SHIFT)
#define ARMV8_ESR_ISS_AET_UEU ((1U) << ARMV8_ESR_ISS_AET_SHIFT)
#define ARMV8_ESR_ISS_AET_UEO ((2U) << ARMV8_ESR_ISS_AET_SHIFT)
#define ARMV8_ESR_ISS_AET_UER ((3U) << ARMV8_ESR_ISS_AET_SHIFT)
#define ARMV8_ESR_ISS_AET_CE ((6U) << ARMV8_ESR_ISS_AET_SHIFT)
/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
#define ARMV8_ESR_ISS_FSC (0x3FU)
#define ARMV8_ESR_ISS_CM_SHIFT (8U)
#define ARMV8_ESR_ISS_CM_MASK ((1U) << ARMV8_ESR_ISS_CM_SHIFT)
#define ARMV8_LEVEL_0_ADDR_FAULT 0x00U
#define ARMV8_LEVEL_1_ADDR_FAULT 0x01U
#define ARMV8_LEVEL_2_ADDR_FAULT 0x02U
#define ARMV8_LEVEL_3_ADDR_FAULT 0x03U
#define ARMV8_LEVEL_0_TRANS_FAULT 0x04U
#define ARMV8_LEVEL_1_TRANS_FAULT 0x05U
#define ARMV8_LEVEL_2_TRANS_FAULT 0x06U
#define ARMV8_LEVEL_3_TRANS_FAULT 0x07U
#define ARMV8_LEVEL_0_ACCS_FLAG_FAULT 0x08U
#define ARMV8_LEVEL_1_ACCS_FLAG_FAULT 0x09U
#define ARMV8_LEVEL_2_ACCS_FLAG_FAULT 0x0AU
#define ARMV8_LEVEL_3_ACCS_FLAG_FAULT 0x0BU
#define ARMV8_LEVEL_0_PERMISSION_FAULT 0x0CU
#define ARMV8_LEVEL_1_PERMISSION_FAULT 0x0DU
#define ARMV8_LEVEL_2_PERMISSION_FAULT 0x0EU
#define ARMV8_LEVEL_3_PERMISSION_FAULT 0x0FU
#define ARMV8_SYNC_EXT_ABORT_NOT_ON_TTW 0x10U
#define ARMV8_LEVEL_0_SYNC_EXT_ABORT 0x14U
#define ARMV8_LEVEL_1_SYNC_EXT_ABORT 0x15U
#define ARMV8_LEVEL_2_SYNC_EXT_ABORT 0x16U
#define ARMV8_LEVEL_3_SYNC_EXT_ABORT 0x17U
#define ARMV8_SYNC_PAR_OR_ECC_ERROR_NOT_ON_TTW 0x18U
#define ARMV8_LEVEL_0_SYNC_PAR_OR_ECC_ERROR 0x1CU
#define ARMV8_LEVEL_1_SYNC_PAR_OR_ECC_ERROR 0x1DU
#define ARMV8_LEVEL_2_SYNC_PAR_OR_ECC_ERROR 0x1EU
#define ARMV8_LEVEL_3_SYNC_PAR_OR_ECC_ERROR 0x1FU
#define ARMV8_ALIGNMENT_FAULT 0x21U
#define ARMV8_TLB_CONFLICT_ABORT 0x30U
#define ARMV8_ASYNC_SEEROR_INTERRUPT 0x11U
#else /* #if defined (__aarch64__) */
#define DATA_ABORT 0x00U
#define INS_PREFETCH_ABORT 0x01U
#define ARMV7_FAULT_STATUS_MASK_BIT3_0 0x0FU
#define ARMV7_DFAR_VALUE_VALID 0x01U
#define ARMV7_FAULT_STATUS_BIT10_MASK 0x400U
#define ARMV7_BACKGROUND_FAULT 0x00U
#define ARMV7_ALIGNMENT_FAULT 0x01U
#define ARMV7_DEBUG_EVENT 0x02U
#define ARMV7_ACCESS_FLAG_FAULT 0x03U
#define ARMV7_ICACHE_MAINTENANCE_FAULT 0x04U
#define ARMV7_TRANSLATION_FAULT 0x05U
#define ARMV7_SYNC_EXT_ABORT 0x08U
#define ARMV7_DOMAIN_FAULT 0x09U
#define ARMV7_SYNC_ABORT_TRANSTAB_WALK 0x0CU
#define ARMV7_PERMISSION_FAULT 0x0DU
#define ARMV7_TLB_CONFLICT_ABORT 0x10U
#define ARMV7_ASYNC_EXT_ABORT 0x16U
#define ARMV7_MEM_ACS_ASYNC_PAR_ERR 0x18U
#define ARMV7_MEM_ACS_SYNC_PAR_ERR 0x19U
#define ARMV7_SYNCPAR_ERR_TRANSTAB_WALK 0x1CU
#define EXTRACT_BITS_10_AND_3_TO_0(Val) \
((Val & (ARMV7_FAULT_STATUS_BIT10_MASK)) >> 6) | \
(Val & ARMV7_FAULT_STATUS_MASK_BIT3_0)
#endif /* #if defined (__aarch64__) */
#endif /* #ifdef DEBUG */
/*
* XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
*/
#if (defined (versal) && !defined(ARMR5) && EL3)
#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_FIQ_INT
#else
#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT
#endif
/**************************** Type Definitions ******************************/
/**
* This typedef is the exception handler function.
*/
typedef void (*Xil_ExceptionHandler)(void *data);
typedef void (*Xil_InterruptHandler)(void *data);
typedef struct {
Xil_ExceptionHandler Handler;
void *Data;
} XExc_VectorTableEntry;
extern XExc_VectorTableEntry XExc_VectorTable[];
/**
*@endcond
*/
/***************** Macros (Inline Functions) Definitions ********************/
/****************************************************************************/
/**
* @brief Enable Exceptions.
*
* @param Mask: Value for enabling the exceptions.
*
* @return None.
*
* @note If bit is 0, exception is enabled.
* C-Style signature: void Xil_ExceptionEnableMask(Mask)
*
******************************************************************************/
#if (defined (versal) && !defined(ARMR5) && EL3)
/*
* Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
* only FIQ at EL3. Hence, tweaking this macro to always enable FIQ
* ignoring argument passed by user.
*/
#define Xil_ExceptionEnableMask(Mask) \
(void)Mask; \
mtcpsr(mfcpsr() & ~ ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
#elif defined (__GNUC__) || defined (__ICCARM__)
#define Xil_ExceptionEnableMask(Mask) \
mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
#else
#define Xil_ExceptionEnableMask(Mask) \
{ \
register u32 Reg __asm("cpsr"); \
mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
}
#endif
/****************************************************************************/
/**
* @brief Enable the IRQ exception.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#if (defined (versal) && !defined(ARMR5) && EL3)
#define Xil_ExceptionEnable() \
Xil_ExceptionEnableMask(XIL_EXCEPTION_FIQ)
#else
#define Xil_ExceptionEnable() \
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
#endif
/****************************************************************************/
/**
* @brief Disable Exceptions.
*
* @param Mask: Value for disabling the exceptions.
*
* @return None.
*
* @note If bit is 1, exception is disabled.
* C-Style signature: Xil_ExceptionDisableMask(Mask)
*
******************************************************************************/
#if (defined (versal) && !defined(ARMR5) && EL3)
/*
* Cortexa72 processor in versal is coupled with GIC-500, and GIC-500 supports
* only FIQ at EL3. Hence, tweaking this macro to always disable FIQ
* ignoring argument passed by user.
*/
#define Xil_ExceptionDisableMask(Mask) \
mtcpsr(mfcpsr() | ((XIL_EXCEPTION_FIQ) & XIL_EXCEPTION_ALL))
#elif defined (__GNUC__) || defined (__ICCARM__)
#define Xil_ExceptionDisableMask(Mask) \
mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
#else
#define Xil_ExceptionDisableMask(Mask) \
{ \
register u32 Reg __asm("cpsr"); \
mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
}
#endif
/****************************************************************************/
/**
* Disable the IRQ exception.
*
* @return None.
*
* @note None.
*
******************************************************************************/
#define Xil_ExceptionDisable() \
Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
#if ( defined (PLATFORM_ZYNQMP) && defined (EL3) && (EL3==1) )
/****************************************************************************/
/**
* @brief Enable nested interrupts by clearing the I bit in DAIF.This
* macro is defined for Cortex-A53 64 bit mode BSP configured to run
* at EL3.. However,it is not defined for Versal Cortex-A72 BSP
* configured to run at EL3. Reason is, Cortex-A72 is coupled
* with GIC-500(GICv3 specifications) and it triggers only FIQ at EL3.
*
* @return None.
*
* @note This macro is supposed to be used from interrupt handlers. In the
* interrupt handler the interrupts are disabled by default (I bit
* is set as 1). To allow nesting of interrupts, this macro should be
* used. It clears the I bit. Once that bit is cleared and provided the
* preemption of interrupt conditions are met in the GIC, nesting of
* interrupts will start happening.
* Caution: This macro must be used with caution. Before calling this
* macro, the user must ensure that the source of the current IRQ
* is appropriately cleared. Otherwise, as soon as we clear the I
* bit, there can be an infinite loop of interrupts with an
* eventual crash (all the stack space getting consumed).
******************************************************************************/
#define Xil_EnableNestedInterrupts() \
__asm__ __volatile__ ("mrs X1, ELR_EL3"); \
__asm__ __volatile__ ("mrs X2, SPSR_EL3"); \
__asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
__asm__ __volatile__ ("mrs X1, DAIF"); \
__asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
__asm__ __volatile__ ("msr DAIF, X1"); \
/****************************************************************************/
/**
* @brief Disable the nested interrupts by setting the I bit in DAIF. This
* macro is defined for Cortex-A53 64 bit mode BSP configured to run
* at EL3.
*
* @return None.
*
* @note This macro is meant to be called in the interrupt service routines.
* This macro cannot be used independently. It can only be used when
* nesting of interrupts have been enabled by using the macro
* Xil_EnableNestedInterrupts(). In a typical flow, the user first
* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
* point. The user then must call this macro before exiting the interrupt
* service routine. This macro puts the ARM back in IRQ mode and
* hence sets back the I bit.
******************************************************************************/
#define Xil_DisableNestedInterrupts() \
__asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
__asm__ __volatile__ ("msr ELR_EL3, X1"); \
__asm__ __volatile__ ("msr SPSR_EL3, X2"); \
__asm__ __volatile__ ("mrs X1, DAIF"); \
__asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
__asm__ __volatile__ ("msr DAIF, X1"); \
#elif (defined (EL1_NONSECURE) && (EL1_NONSECURE==1))
/****************************************************************************/
/**
* @brief Enable nested interrupts by clearing the I bit in DAIF.This
* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
* BSP configured to run at EL1 NON SECURE
*
* @return None.
*
* @note This macro is supposed to be used from interrupt handlers. In the
* interrupt handler the interrupts are disabled by default (I bit
* is set as 1). To allow nesting of interrupts, this macro should be
* used. It clears the I bit. Once that bit is cleared and provided the
* preemption of interrupt conditions are met in the GIC, nesting of
* interrupts will start happening.
* Caution: This macro must be used with caution. Before calling this
* macro, the user must ensure that the source of the current IRQ
* is appropriately cleared. Otherwise, as soon as we clear the I
* bit, there can be an infinite loop of interrupts with an
* eventual crash (all the stack space getting consumed).
******************************************************************************/
#define Xil_EnableNestedInterrupts() \
__asm__ __volatile__ ("mrs X1, ELR_EL1"); \
__asm__ __volatile__ ("mrs X2, SPSR_EL1"); \
__asm__ __volatile__ ("stp X1,X2, [sp,#-0x10]!"); \
__asm__ __volatile__ ("mrs X1, DAIF"); \
__asm__ __volatile__ ("bic X1,X1,#(0x1<<7)"); \
__asm__ __volatile__ ("msr DAIF, X1"); \
/****************************************************************************/
/**
* @brief Disable the nested interrupts by setting the I bit in DAIF. This
* macro is defined for Cortex-A53 64 bit mode and Cortex-A72 64 bit
* BSP configured to run at EL1 NON SECURE
*
* @return None.
*
* @note This macro is meant to be called in the interrupt service routines.
* This macro cannot be used independently. It can only be used when
* nesting of interrupts have been enabled by using the macro
* Xil_EnableNestedInterrupts(). In a typical flow, the user first
* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
* point. The user then must call this macro before exiting the interrupt
* service routine. This macro puts the ARM back in IRQ mode and
* hence sets back the I bit.
******************************************************************************/
#define Xil_DisableNestedInterrupts() \
__asm__ __volatile__ ("ldp X1,X2, [sp,#0x10]!"); \
__asm__ __volatile__ ("msr ELR_EL1, X1"); \
__asm__ __volatile__ ("msr SPSR_EL1, X2"); \
__asm__ __volatile__ ("mrs X1, DAIF"); \
__asm__ __volatile__ ("orr X1, X1, #(0x1<<7)"); \
__asm__ __volatile__ ("msr DAIF, X1"); \
#elif (!defined (__aarch64__) && !defined (ARMA53_32))
/****************************************************************************/
/**
* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This
* API is defined for cortex-a9 and cortex-r5.
*
* @return None.
*
* @note This macro is supposed to be used from interrupt handlers. In the
* interrupt handler the interrupts are disabled by default (I and F
* are 1). To allow nesting of interrupts, this macro should be
* used. It clears the I and F bits by changing the ARM mode to
* system mode. Once these bits are cleared and provided the
* preemption of interrupt conditions are met in the GIC, nesting of
* interrupts will start happening.
* Caution: This macro must be used with caution. Before calling this
* macro, the user must ensure that the source of the current IRQ
* is appropriately cleared. Otherwise, as soon as we clear the I and
* F bits, there can be an infinite loop of interrupts with an
* eventual crash (all the stack space getting consumed).
******************************************************************************/
#define Xil_EnableNestedInterrupts() \
__asm__ __volatile__ ("stmfd sp!, {lr}"); \
__asm__ __volatile__ ("mrs lr, spsr"); \
__asm__ __volatile__ ("stmfd sp!, {lr}"); \
__asm__ __volatile__ ("msr cpsr_c, #0x1F"); \
__asm__ __volatile__ ("stmfd sp!, {lr}");
/****************************************************************************/
/**
* @brief Disable the nested interrupts by setting the I and F bits. This API
* is defined for cortex-a9 and cortex-r5.
*
* @return None.
*
* @note This macro is meant to be called in the interrupt service routines.
* This macro cannot be used independently. It can only be used when
* nesting of interrupts have been enabled by using the macro
* Xil_EnableNestedInterrupts(). In a typical flow, the user first
* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
* point. The user then must call this macro before exiting the interrupt
* service routine. This macro puts the ARM back in IRQ/FIQ mode and
* hence sets back the I and F bits.
******************************************************************************/
#define Xil_DisableNestedInterrupts() \
__asm__ __volatile__ ("ldmfd sp!, {lr}"); \
__asm__ __volatile__ ("msr cpsr_c, #0x92"); \
__asm__ __volatile__ ("ldmfd sp!, {lr}"); \
__asm__ __volatile__ ("msr spsr_cxsf, lr"); \
__asm__ __volatile__ ("ldmfd sp!, {lr}"); \
#endif
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
Xil_ExceptionHandler Handler,
void *Data);
extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
Xil_ExceptionHandler *Handler, void **Data);
extern void Xil_ExceptionInit(void);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_EXCEPTION_H */
/**
* @} End of "addtogroup arm_exception_apis".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_hal.h
+43
View File
@@ -0,0 +1,43 @@
/******************************************************************************
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_hal.h
*
* Contains all the HAL header files.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/28/09 Initial release
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef XIL_HAL_H
#define XIL_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
#include "xil_cache.h"
#include "xil_io.h"
#include "xil_assert.h"
#include "xil_exception.h"
#include "xil_types.h"
#ifdef __cplusplus
}
#endif
#endif
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_io.h
+433
View File
@@ -0,0 +1,433 @@
/******************************************************************************
* Copyright (C) 2014 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_io.h
*
* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
*
* The xil_io.h file contains the interface for the general I/O component, which
* encapsulates the Input/Output functions for the processors that do not
* require any special I/O handling.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/29/14 First release
* 6.00 mus 08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
* ARM processors
* 7.20 har 01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
* CR-1049218
* 7.30 kpt 09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to
* xil_io.h and made them as static inline
* am 10/13/20 Changed the return type of Xil_SecureOut32 function
* from u32 to int
* 7.50 dp 02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
* when -Werror=conversion compiler flag is enabled
* 7.5 mus 05/17/21 Update the functions with comments. It fixes CR#1067739.
* 9.0 ml 03/03/23 Add description and remove comments to fix doxygen warnings.
* </pre>
******************************************************************************/
#ifndef XIL_IO_H /**< prevent circular inclusions */
#define XIL_IO_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_printf.h"
#include "xstatus.h"
#if defined (__MICROBLAZE__)
#include "mb_interface.h"
#else
#include "xpseudo_asm.h"
#endif
/************************** Function Prototypes ******************************/
#ifdef ENABLE_SAFETY
extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
#endif
/***************** Macros (Inline Functions) Definitions *********************/
#if defined __GNUC__
#if defined (__MICROBLAZE__)
# define INST_SYNC mbar(0) /**< Instruction Synchronization Barrier */
# define DATA_SYNC mbar(1) /**< Data Synchronization Barrier */
# else
# define SYNCHRONIZE_IO dmb() /**< Data Memory Barrier */
# define INST_SYNC isb() /**< Instruction Synchronization Barrier */
# define DATA_SYNC dsb() /**< Data Synchronization Barrier */
# endif
#else
# define SYNCHRONIZE_IO /**< Data Memory Barrier */
# define INST_SYNC /**< Instruction Synchronization Barrier */
# define DATA_SYNC /**< Data Synchronization Barrier */
# define INST_SYNC /**< Instruction Synchronization Barrier */
# define DATA_SYNC /**< Data Synchronization Barrier */
#endif
#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
#define INLINE inline /**< static inline keyword */
#else
#define INLINE __inline /**<static inline keyword */
#endif
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading
* from the specified address and returning the 8 bit Value read from
* that address.
*
* @param Addr contains the address to perform the input operation
*
* @return The 8 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u8 Xil_In8(UINTPTR Addr)
{
return *(volatile u8 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading from
* the specified address and returning the 16 bit Value read from that
* address.
*
* @param Addr contains the address to perform the input operation
*
* @return The 16 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u16 Xil_In16(UINTPTR Addr)
{
return *(volatile u16 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by
* reading from the specified address and returning the 32 bit Value
* read from that address.
*
* @param Addr contains the address to perform the input operation
*
* @return The 32 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u32 Xil_In32(UINTPTR Addr)
{
return *(volatile u32 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an input operation for a memory location by reading the
* 64 bit Value read from that address.
*
*
* @param Addr contains the address to perform the input operation
*
* @return The 64 bit Value read from the specified input address.
*
******************************************************************************/
static INLINE u64 Xil_In64(UINTPTR Addr)
{
return *(volatile u64 *) Addr;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for an memory location by
* writing the 8 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains the 8 bit Value to be written at the specified
* address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
{
/* write 8 bit value to specified address */
volatile u8 *LocalAddr = (volatile u8 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 16 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains the Value to be written at the specified address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
{
/* write 16 bit value to specified address */
volatile u16 *LocalAddr = (volatile u16 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 32 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains the 32 bit Value to be written at the specified
* address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
{
/* write 32 bit value to specified address */
#ifndef ENABLE_SAFETY
volatile u32 *LocalAddr = (volatile u32 *)Addr;
*LocalAddr = Value;
#else
XStl_RegUpdate(Addr, Value);
#endif
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 64 bit Value to the the specified address.
*
* @param Addr contains the address to perform the output operation
* @param Value contains 64 bit Value to be written at the specified address.
*
* @return None.
*
******************************************************************************/
static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
{
/* write 64 bit value to specified address */
volatile u64 *LocalAddr = (volatile u64 *)Addr;
*LocalAddr = Value;
}
/*****************************************************************************/
/**
*
* @brief Performs an output operation for a memory location by writing the
* 32 bit Value to the the specified address and then reading it
* back to verify the value written in the register.
*
* @param Addr contains the address to perform the output operation
* @param Value contains 32 bit Value to be written at the specified address
*
* @return Returns Status
* - XST_SUCCESS on success
* - XST_FAILURE on failure
*
*****************************************************************************/
static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
{
int Status = XST_FAILURE;
u32 ReadReg;
u32 ReadRegTemp;
/* writing 32 bit value to specified address */
Xil_Out32(Addr, Value);
/* verify value written to specified address with multiple reads */
ReadReg = Xil_In32(Addr);
ReadRegTemp = Xil_In32(Addr);
if( (ReadReg == Value) && (ReadRegTemp == Value) ) {
Status = XST_SUCCESS;
}
return Status;
}
/*****************************************************************************/
/**
*
* @brief Perform a 16-bit endian conversion.
*
* @param Data 16 bit value to be converted
*
* @return 16 bit Data with converted endianness
*
******************************************************************************/
static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
{
return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
}
/*****************************************************************************/
/**
*
* @brief Perform a 32-bit endian conversion.
*
* @param Data : 32 bit value to be converted
*
* @return 32 bit data with converted endianness
*
******************************************************************************/
static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
{
u16 LoWord;
u16 HiWord;
/* get each of the half words from the 32 bit word */
LoWord = (u16) (Data & 0x0000FFFFU);
HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
/* byte swap each of the 16 bit half words */
LoWord = (u16)(((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
HiWord = (u16)(((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
/* swap the half words before returning the value */
return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
# define Xil_In16LE Xil_In16 /**< Register Read of 16 Bits in Little Endian */
# define Xil_In32LE Xil_In32 /**< Register Read of 32 Bits in Little Endian */
# define Xil_Out16LE Xil_Out16 /**< Register Write of 16 Bits in Little Endian */
# define Xil_Out32LE Xil_Out32 /**< Register Write of 32 Bits in Little Endian */
# define Xil_Htons Xil_EndianSwap16 /**< Endian swap of 16 bits */
# define Xil_Htonl Xil_EndianSwap32 /**< Endian swap of 32 bits */
# define Xil_Ntohs Xil_EndianSwap16 /**< Endian swap of 16 bits */
# define Xil_Ntohl Xil_EndianSwap32 /**< Endian swap of 32 bits */
# else
# define Xil_In16BE Xil_In16 /**< Register Read of 16 Bits in Big Endian */
# define Xil_In32BE Xil_In32 /**< Register Read of 32 Bits in Big Endian */
# define Xil_Out16BE Xil_Out16 /**< Register Write of 16 Bits in Big Endian */
# define Xil_Out32BE Xil_Out32 /**< Register Write of 32 Bits in Big Endian */
# define Xil_Htons(Data) (Data) /**< Endian swap of 16 bits */
# define Xil_Htonl(Data) (Data) /**< Endian swap of 32 bits */
# define Xil_Ntohs(Data) (Data) /**< Endian swap of 16 bits */
# define Xil_Ntohl(Data) (Data) /**< Endian swap of 32 bits */
#endif
#else
# define Xil_In16LE Xil_In16 /**< Register Read of 16 Bits in Little Endian */
# define Xil_In32LE Xil_In32 /**< Register Read of 32 Bits in Little Endian */
# define Xil_Out16LE Xil_Out16 /**< Register Write of 16 Bits in Little Endian */
# define Xil_Out32LE Xil_Out32 /**< Register Write of 32 Bits in Little Endian */
# define Xil_Htons Xil_EndianSwap16 /**< Endian swap of 16 bits */
# define Xil_Htonl Xil_EndianSwap32 /**< Endian swap of 32 bits */
# define Xil_Ntohs Xil_EndianSwap16 /**< Endian swap of 16 bits */
# define Xil_Ntohl Xil_EndianSwap32 /**< Endian swap of 32 bits */
#endif
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u16 Xil_In16BE(UINTPTR Addr) /**< Static inline function to Read
Register of 16 Bits in Big Endian */
#else
static INLINE u16 Xil_In16LE(UINTPTR Addr) /**< Static inline function to Read
Register of 16 Bits in Little Endian */
#endif
#else
/**
* Static inline function to Read Register of 16 Bits in Big Endian.
**********************************************************************************/
static INLINE u16 Xil_In16BE(UINTPTR Addr)
#endif
{
u16 value = Xil_In16(Addr);
return Xil_EndianSwap16(value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE u32 Xil_In32BE(UINTPTR Addr) /**< Static inline function to Read
Register of 32 Bits in Big Endian */
#else
static INLINE u32 Xil_In32LE(UINTPTR Addr) /**< Static inline function to Read
Register of 32 Bits in Little Endian */
#endif
#else
/**
* Static inline function to Read Register of 32 Bits in Big Endian.
**********************************************************************************/
static INLINE u32 Xil_In32BE(UINTPTR Addr)
#endif
{
u32 value = Xil_In32(Addr);
return Xil_EndianSwap32(value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) /**< Static inline function to write
Register of 16 Bits in Big Endian */
#else
static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value) /**< Static inline function to write
Register of 16 Bits in Little Endian */
#endif
#else
/**
* Static inline function to write Register of 16 Bits in Big Endian.
**********************************************************************************/
static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
#endif
{
Value = Xil_EndianSwap16(Value);
Xil_Out16(Addr, Value);
}
#if defined (__MICROBLAZE__)
#ifdef __LITTLE_ENDIAN__
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) /**< Static inline function to write
Register of 32 Bits in Big Endian */
#else
static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value) /**< Static inline function to write
Register of 32 Bits in Little Endian */
#endif
#else
/**
* Static inline function to Read Register of 16 Bits in Big Endian.
**********************************************************************************/
static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
#endif
{
Value = Xil_EndianSwap32(Value);
Xil_Out32(Addr, Value);
}
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_io_interfacing_apis".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_macroback.h
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Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mem.h
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/******************************************************************************/
/**
* Copyright (C) 2015 - 2020 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
* @file xil_mem.h
*
* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
*
* The xil_mem.h file contains prototype for functions related
* to memory operations. These APIs are applicable for all processors supported
* by Xilinx.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 6.1 nsk 11/07/16 First release.
* 7.0 mus 01/07/19 Add cpp extern macro
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
*****************************************************************************/
#ifndef XIL_MEM_H /**< prevent circular inclusions */
#define XIL_MEM_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/************************** Function Prototypes *****************************/
void Xil_MemCpy(void* dst, const void* src, u32 cnt);
#ifdef __cplusplus
}
#endif
#endif /* XIL_MEM_H */
/**
* @} End of "addtogroup common_mem_operation_api".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h
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/******************************************************************************
* Copyright (C) 2013 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xil_misc_psreset_api.h
*
* This file contains the various register definitions and function prototypes for
* implementing the reset functionality of zynq ps devices
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00b kpc 03/07/13 First release.
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
******************************************************************************/
#ifndef XIL_MISC_RESET_H /**< prevent circular inclusions */
#define XIL_MISC_RESET_H /**< by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_io.h"
/************************** Constant Definitions *****************************/
/**
*@cond nocomments
*/
#define XDDRC_CTRL_BASEADDR 0xF8006000U
#define XSLCR_BASEADDR 0xF8000000U
/**< OCM configuration register */
#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U)
/**< SLCR unlock register */
#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U)
/**< SLCR GEM0 rx clock control register */
#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U)
/**< SLCR GEM1 rx clock control register */
#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU)
/**< SLCR GEM0 clock control register */
#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U)
/**< SLCR GEM1 clock control register */
#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U)
/**< SLCR SMC clock control register */
#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U)
/**< SLCR GEM reset control register */
#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)
/**< SLCR USB0 clock control register */
#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U)
/**< SLCR USB1 clock control register */
#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U)
/**< SLCR USB1 reset control register */
#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)
/**< SLCR SMC reset control register */
#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)
/**< SLCR Level shifter enable register */
#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U)
/**< SLCR ARM pll control register */
#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U)
/**< SLCR DDR pll control register */
#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U)
/**< SLCR IO pll control register */
#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U)
/**< SLCR ARM pll configuration register */
#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U)
/**< SLCR DDR pll configuration register */
#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U)
/**< SLCR IO pll configuration register */
#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U)
/**< SLCR ARM clock control register */
#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U)
/**< SLCR DDR clock control register */
#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U)
/**< SLCR MIO pin address register */
#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U)
/**< SLCR DMAC reset control address register */
#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU)
/**< SLCR USB reset control address register */
/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/
/**< SLCR GEM reset control address register */
/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/
/**< SLCR SDIO reset control address register */
#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U)
/**< SLCR SPI reset control address register */
#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU)
/**< SLCR CAN reset control address register */
#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U)
/**< SLCR I2C reset control address register */
#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U)
/**< SLCR UART reset control address register */
#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U)
/**< SLCR GPIO reset control address register */
#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU)
/**< SLCR LQSPI reset control address register */
#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U)
/**< SLCR SMC reset control address register */
/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/
/**< SLCR OCM reset control address register */
#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U)
/**< SMC mem controller clear config register */
#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU
/**< SMC idlecount configuration register */
#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U
#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U
/**< SMC ECC configuration register */
#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U
/**< SMC ECC command 1 register */
#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U
/**< SMC ECC command 2 register */
#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U
/**< SLCR unlock code */
#define XSLCR_UNLOCK_CODE 0x0000DF0DU
/**< SMC mem clear configuration mask */
#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU
/**< SMC ECC memconfig 1 reset value */
#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U
/**< SMC ECC memcommand 1 reset value */
#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U
/**< SMC ECC memcommand 2 reset value */
#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U
/**< DDR controller reset bit mask */
#define XDDRPS_CTRL_RESET_MASK 0x00000001U
/**< SLCR OCM configuration reset value*/
#define XSLCR_OCM_CFG_RESETVAL 0x00000008U
/**< SLCR OCM bank selection mask*/
#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU
/**< SLCR level shifter enable mask*/
#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU
/**< SLCR PLL register reset values */
#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U
#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U
#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U
#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U
#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U
#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U
#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U
#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U
/**< SLCR MIO register default values */
#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U
#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U
/**< SLCR Reset control registers default values */
#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U
#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U
#define XSLCR_USB_RST_CTRL_VAL 0x00000003U
#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U
#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU
#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU
#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U
#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U
#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U
#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U
#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U
#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U
/**
*@endcond
*/
/**************************** Type Definitions *******************************/
/* the following data type is used to hold a null terminated version string
* consisting of the following format, "X.YYX"
*/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/*
* Performs reset operation to the ddr interface
*/
void XDdr_ResetHw(void);
/*
* Map the ocm region to post bootrom state
*/
void XOcm_Remap(void);
/*
* Performs the smc interface reset
*/
void XSmc_ResetHw(u32 BaseAddress);
/*
* updates the MIO registers with reset values
*/
void XSlcr_MioWriteResetValues(void);
/*
* updates the PLL and clock registers with reset values
*/
void XSlcr_PllWriteResetValues(void);
/*
* Disables the level shifters
*/
void XSlcr_DisableLevelShifters(void);
/*
* provides softreset to the GPIO interface
*/
void XSlcr_GpioPsReset(void);
/*
* provides softreset to the DMA interface
*/
void XSlcr_DmaPsReset(void);
/*
* provides softreset to the SMC interface
*/
void XSlcr_SmcPsReset(void);
/*
* provides softreset to the CAN interface
*/
void XSlcr_CanPsReset(void);
/*
* provides softreset to the Uart interface
*/
void XSlcr_UartPsReset(void);
/*
* provides softreset to the I2C interface
*/
void XSlcr_I2cPsReset(void);
/*
* provides softreset to the SPI interface
*/
void XSlcr_SpiPsReset(void);
/*
* provides softreset to the QSPI interface
*/
void XSlcr_QspiPsReset(void);
/*
* provides softreset to the USB interface
*/
void XSlcr_UsbPsReset(void);
/*
* provides softreset to the GEM interface
*/
void XSlcr_EmacPsReset(void);
/*
* provides softreset to the OCM interface
*/
void XSlcr_OcmReset(void);
#ifdef __cplusplus
}
#endif
#endif /* XIL_MISC_RESET_H */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mmu.h
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/******************************************************************************
* Copyright (c) 2012 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xil_mmu.h
*
* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
*
* MMU functions equip users to enable MMU, disable MMU and modify default
* memory attributes of MMU table as per the need.
*
* @{
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a sdm 01/12/12 Initial version
* 4.2 pkp 07/21/14 Included xil_types.h file which contains definition for
* u32 which resolves issue of CR#805869
* 5.4 pkp 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
* </pre>
*
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_MMU_H
#define XIL_MMU_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/***************************** Include Files *********************************/
#include "xil_types.h"
/***************** Macros (Inline Functions) Definitions *********************/
/**************************** Type Definitions *******************************/
/************************** Constant Definitions *****************************/
/* Memory type */
#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */
#define STRONG_ORDERED 0xC02 /* Strongly ordered */
#define DEVICE_MEMORY 0xC06 /* Device memory */
#define RESERVED 0x0 /* reserved memory */
/* Normal write-through cacheable shareable */
#define NORM_WT_CACHE 0x16DEA
/* Normal write back cacheable shareable */
#define NORM_WB_CACHE 0x15DE6
/* shareability attribute */
#define SHAREABLE (0x1 << 16)
#define NON_SHAREABLE (~(0x1 << 16))
/* Execution type */
#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
/**
*@endcond
*/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
void Xil_EnableMMU(void);
void Xil_DisableMMU(void);
void* Xil_MemMap(UINTPTR PhysAddr, size_t size, u32 flags);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_MMU_H */
/**
* @} End of "addtogroup a9_mmu_apis".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_printf.h
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/******************************************************************************
* Copyright (C) 1995 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/
#ifndef XIL_PRINTF_H
#define XIL_PRINTF_H
#ifdef __cplusplus
extern "C" {
#endif
#include <ctype.h>
#include <string.h>
#include <stdarg.h>
#include "xil_types.h"
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#endif
#if defined (__aarch64__) && HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
#include "xen_console.h"
#endif
/*----------------------------------------------------*/
/* Use the following parameter passing structure to */
/* make xil_printf re-entrant. */
/*----------------------------------------------------*/
struct params_s;
/*---------------------------------------------------*/
/* The purpose of this routine is to output data the */
/* same as the standard printf function without the */
/* overhead most run-time libraries involve. Usually */
/* the printf brings in many kilobytes of code and */
/* that is unacceptable in most embedded systems. */
/*---------------------------------------------------*/
typedef char8* charptr;
typedef s32 (*func_ptr)(int c);
/************************** Function Prototypes ******************************/
/**< prints the statement */
void xil_printf( const char8 *ctrl1, ...);
/**< This routine is equivalent to vprintf routine */
void xil_vprintf(const char8 *ctrl1, va_list argp);
void print( const char8 *ptr);
extern void outbyte (char c); /**< To send byte */
extern char inbyte(void); /**< To receive byte */
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h
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/******************************************************************************
* Copyright (C) 2017 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_sleeptimer.h
*
* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
* For sleep related functions that can be used across all Xilinx supported
* processors, please use xil_sleeptimer.h.
*
*
* <pre>
* MODIFICATION HISTORY :
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 6.6 srm 10/18/17 First Release.
* 7.0 mus 01/07/19 Add cpp extern macro
* 7.7 sk 01/10/22 Add explicit parentheses for EL3==1 to fix
* misra_c_2012_rule_12_1 violation.
* 7.7 sk 01/10/22 Add void to XTime_StartTTCTimer function declaration
* to fix misra_c_2012_rule_8_2 violation.
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*****************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */
#define XIL_SLEEPTIMER_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/**************************** Include Files ********************************/
#include "xil_io.h"
#include "xparameters.h"
#include "bspconfig.h"
/************************** Constant Definitions *****************************/
#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
#define XSLEEP_TIMER_REG_SHIFT 32U
#define XSleep_ReadCounterVal Xil_In32
#define XCntrVal u32
#else
#define XSLEEP_TIMER_REG_SHIFT 16U
#define XSleep_ReadCounterVal Xil_In16
#define XCntrVal u16
#endif
#if defined(ARMR5) || (defined (__aarch64__) && (EL3==1)) || defined (ARMA53_32)
#if defined (versal)
#define CRL_TTC_RST 0xFF5E0344U
#define CRL_TTC_BASE_RST_MASK 0x1U
#else
#define RST_LPD_IOU2 0xFF5E0238U
#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U
#endif
#endif
#if defined (SLEEP_TIMER_BASEADDR)
/** @name Register Map
*
* Register offsets from the base address of the TTC device
*
* @{
*/
#define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U
/**< Clock Control Register */
#define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU
/**< Counter Control Register*/
#define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U
/**< Current Counter Value */
/* @} */
/** @name Clock Control Register
* Clock Control Register definitions of TTC
* @{
*/
#define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U
/**< Prescale enable */
/* @} */
/** @name Counter Control Register
* Counter Control Register definitions of TTC
* @{
*/
#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U
/**< Disable the counter */
#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U
/**< Reset counter */
/* @} */
/**************************** Type Definitions *******************************/
/**
*@endcond
*/
/************************** Function Prototypes ******************************/
/**< This is a helper function used by sleep/usleep APIs to
* have delay in sec/usec */
void Xil_SleepTTCCommon(u32 delay, u64 frequency);
void XTime_StartTTCTimer(void); /**< This API starts the Triple
* Timer Counter */
#endif
#ifdef __cplusplus
}
#endif
#endif /* XIL_SLEEPTIMER_H */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_spinlock.h
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/******************************************************************************
* Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_spinlock.h
*
* This header file contains function prototypes to be used while using Xilinx
* spinlocking mechanism.
* Please refer to file header contents of xil_spinlock.c to understand in
* detail the spinlocking mechanism.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 7.5 asa 02/16/21 First release
* 7.6 sk 08/05/21 Add Boolean check and braces for Xil_IsSpinLockEnabled
* if condition to fix misrac violations.
* 7.7 sk 01/10/22 Update XIL_SPINLOCK_ENABLED from signed to unsigned to
* fix misra_c_2012_rule_10_4 violation.
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
******************************************************************************/
#ifndef XIL_SPINLOCK_H /**< prevent circular inclusions */
#define XIL_SPINLOCK_H /**< by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "xstatus.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
/************************** Function Prototypes *****************************/
u32 Xil_SpinLock(void);
u32 Xil_SpinUnlock(void);
u32 Xil_InitializeSpinLock(UINTPTR lockaddr, UINTPTR lockflagaddr,
u32 lockflag);
void Xil_ReleaseSpinLock(void);
u32 Xil_IsSpinLockEnabled(void);
/************************** MACRO Definitions ****************************/
#define XIL_SPINLOCK_LOCKVAL 0x10203040
#define XIL_SPINLOCK_RESETVAL 0x40302010
#define XIL_SPINLOCK_ENABLE 0x17273747
#define XIL_SPINLOCK_ENABLED 0x17273747U
/***************** Macros (Inline Functions) Definitions ********************/
#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
/***************************************************************************/
#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
#define XIL_SPINLOCK() \
if(Xil_IsSpinLockEnabled()!=(u32)0) { \
Xil_SpinLock(); }
#else
#define XIL_SPINLOCK() /**< protect multiple applications running at separate
* CPUs to write to the same register */
#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
#if !defined (__aarch64__) && defined(__GNUC__) && !defined(__clang__)
#define XIL_SPINUNLOCK() \
if(Xil_IsSpinLockEnabled()!=(u32)0) { \
Xil_SpinUnlock(); }
#else
#define XIL_SPINUNLOCK() /**< Release the lock previously taken */
#endif /* !(__aarch64__) && (__GNUC__) && !(__clang__)*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XIL_SPINLOCK_H */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testcache.h
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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testcache.h
*
* @addtogroup common_test_utils
* <h2>Cache test </h2>
* The xil_testcache.h file contains utility functions to test cache.
*
* @{
* <pre>
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 07/29/09 First release
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */
#define XIL_TESTCACHE_H /* by using protection macros */
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif
extern s32 Xil_TestDCacheRange(void);
extern s32 Xil_TestDCacheAll(void);
extern s32 Xil_TestICacheRange(void);
extern s32 Xil_TestICacheAll(void);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
*@endcond
*/
/**
* @} End of "addtogroup common_test_utils".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testio.h
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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testio.h
*
* @addtogroup common_test_utils Test Utilities for Memory and Caches
* <h2>I/O test </h2>
* The xil_testio.h file contains utility functions to test endian related memory
* IO functions.
*
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests
* are selected.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00 hbm 08/05/09 First release
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_TESTIO_H /* prevent circular inclusions */
#define XIL_TESTIO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#define XIL_TESTIO_DEFAULT 0
#define XIL_TESTIO_LE 1
#define XIL_TESTIO_BE 2
/**
*@endcond
*/
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_test_utils".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testmem.h
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/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_testmem.h
* @addtogroup common_test_utils Test Utilities for Memory and Caches
*
* - Cache test: xil_testcache.h contains utility functions to test cache.
*
* - I/O test: The Xil_testio.h file contains endian related memory IO functions. A
* subset of the memory tests can be selected or all of the tests can be run in order.
* If there is an error detected by a subtest, the test stops and the failure code is
* returned. Further tests are not run even if all of the tests are selected.
*
* - Memory test: The xil_testmem.h file contains utility functions to test memory.
* A subset of the memory tests can be selected or all of the tests can be run
* in order. If there is an error detected by a subtest, the test stops and the
* failure code is returned. Further tests are not run even if all of the tests are selected.
*
*
* Following list describes the supported memory tests:
*
* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
*
* - XIL_TESTMEM_INCREMENT: This test
* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
* test value for memory.
*
* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
* uses a walking '1' as the test value for memory.
* @code
* location 1 = 0x00000001
* location 2 = 0x00000002
* ...
* @endcode
*
* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
* This test uses the inverse value of the walking ones test
* as the test value for memory.
* @code
* location 1 = 0xFFFFFFFE
* location 2 = 0xFFFFFFFD
* ...
*@endcode
*
* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
* This test uses the inverse of the address of the location under test
* as the test value for memory.
*
* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
* This test uses the provided patters as the test value for memory.
* If zero is provided as the pattern the test uses '0xDEADBEEF".
*
* @warning
* The tests are <b>DESTRUCTIVE</b>. Run before any initialized memory spaces
* have been set up.
* The address provided to the memory tests is not checked for
* validity except for the NULL case. It is possible to provide a code-space
* pointer for this test to start with and ultimately destroy executable code
* causing random failures.
*
* @note
* Used for spaces where the address range of the region is smaller than
* the data width. If the memory range is greater than 2 ** width,
* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
* repeat on a boundary of a power of two making it more difficult to detect
* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
* tests suffer the same problem. Ideally, if large blocks of memory are to be
* tested, break them up into smaller regions of memory to allow the test
* patterns used not to repeat over the region tested.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a hbm 08/25/09 First release
* 7.5 mus 03/10/21 Added new set of Xil_TestMem32, Xil_TestMem16 and
* Xil_TestMem8 APIs to support memory test for memory
* regions mapped at extended addresses
* (addresses > 4 GB). These new set of APIs would be
* compiled only for 32 bit Microblaze processor, if
* XPAR_MICROBLAZE_ADDR_SIZE is greater than 32.
* It fixes CR#1089129.
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_TESTMEM_H /* prevent circular inclusions */
#define XIL_TESTMEM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/* xutil_memtest defines */
#define XIL_TESTMEM_INIT_VALUE 1U
/** @name Memory subtests
* @{
*/
/**
* See the detailed description of the subtests in the file description.
*/
#define XIL_TESTMEM_ALLMEMTESTS 0x00U
#define XIL_TESTMEM_INCREMENT 0x01U
#define XIL_TESTMEM_WALKONES 0x02U
#define XIL_TESTMEM_WALKZEROS 0x03U
#define XIL_TESTMEM_INVERSEADDR 0x04U
#define XIL_TESTMEM_FIXEDPATTERN 0x05U
#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN
/* @} */
#if !defined(__aarch64__) && !defined(__arch64__)
#define NUM_OF_BITS_IN_BYTE 8U
#define NUM_OF_BYTES_IN_HW 2U
#define NUM_OF_BITS_IN_HW 16U
#define NUM_OF_BYTES_IN_WORD 4U
#define NUM_OF_BITS_IN_WORD 32U
#endif
/***************** Macros (Inline Functions) Definitions *********************/
/**
*@endcond
*/
/************************** Function Prototypes ******************************/
/* xutil_testmem prototypes */
#if defined(__MICROBLAZE__) && !defined(__arch64__) && (XPAR_MICROBLAZE_ADDR_SIZE > 32)
extern s32 Xil_TestMem32(u32 AddrLow, u32 AddrHigh, u32 Words, u32 Pattern, u8 Subtest);
extern s32 Xil_TestMem16(u32 AddrLow, u32 AddrHigh, u32 Words, u16 Pattern, u8 Subtest);
extern s32 Xil_TestMem8(u32 AddrLow, u32 AddrHigh, u32 Words, u8 Pattern, u8 Subtest);
#else
extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
#endif
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_test_utils".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_types.h
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/******************************************************************************
* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xil_types.h
*
* @addtogroup common_types Basic Data types for Xilinx&reg; Software IP
*
* The xil_types.h file contains basic types for Xilinx software IP. These data types
* are applicable for all processors supported by Xilinx.
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00a hbm 07/14/09 First release
* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
* 5.00 pkp 05/29/14 Made changes for 64 bit architecture
* srt 07/14/14 Use standard definitions from stdint.h and stddef.h
* Define LONG and ULONG datatypes and mask values
* 7.00 mus 01/07/19 Add cpp extern macro
* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it
* is 64-bit processor
* 8.1 dp 12/23/22 Updated UINTPTR and INTPTR to point to 64bit data types
* incase of microblaze 32-bit with extended address enabled
* 9.0 ml 14/04/23 Add parenthesis on sub-expression to fix misra-c violation.
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XIL_TYPES_H /* prevent circular inclusions */
#define XIL_TYPES_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stddef.h>
#include "bspconfig.h"
#ifndef SDT
#include "xparameters.h"
#endif
/************************** Constant Definitions *****************************/
#ifndef TRUE
# define TRUE 1U
#endif
#ifndef FALSE
# define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be
assigend to "IsReady" member of driver
instance to indicate that driver
instance is initialized and ready to use. */
#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to
"IsStarted" member of driver instance
to indicate that driver instance is
started and it can be enabled. */
/* @name New types
* New simple types.
* @{
*/
#ifndef __KERNEL__
#ifndef XBASIC_TYPES_H
/*
* guarded against xbasic_types.h.
*/
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
/** @}*/
#define __XUINT64__
typedef struct
{
u32 Upper;
u32 Lower;
} Xuint64;
/*****************************************************************************/
/**
* @brief Return the most significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The upper 32 bits of the 64 bit word.
*
******************************************************************************/
#define XUINT64_MSW(x) ((x).Upper)
/*****************************************************************************/
/**
* @brief Return the least significant half of the 64 bit data type.
*
* @param x is the 64 bit word.
*
* @return The lower 32 bits of the 64 bit word.
*
******************************************************************************/
#define XUINT64_LSW(x) ((x).Lower)
#endif /* XBASIC_TYPES_H */
/*
* xbasic_types.h does not typedef s* or u64
*/
/** @{ */
typedef char char8;
typedef int8_t s8;
typedef int16_t s16;
typedef int32_t s32;
typedef int64_t s64;
typedef uint64_t u64;
typedef int sint32;
#if defined(__MICROBLAZE__) && !defined(__arch64__) && \
(XPAR_MICROBLAZE_ADDR_SIZE > 32)
typedef uint64_t UINTPTR;
typedef int64_t INTPTR;
#else
typedef uintptr_t UINTPTR;
typedef intptr_t INTPTR;
#endif
typedef ptrdiff_t PTRDIFF;
/** @}*/
#if !defined(LONG) || !defined(ULONG)
typedef long LONG;
typedef unsigned long ULONG;
#endif
#define ULONG64_HI_MASK 0xFFFFFFFF00000000U
#define ULONG64_LO_MASK ~ULONG64_HI_MASK
#else
#include <linux/types.h>
#endif
/** @{ */
/**
* This data type defines an interrupt handler for a device.
* The argument points to the instance of the component
*/
typedef void (*XInterruptHandler) (void *InstancePtr);
/**
* This data type defines an exception handler for a processor.
* The argument points to the instance of the component
*/
typedef void (*XExceptionHandler) (void *InstancePtr);
#if defined (__riscv_xlen) && (__riscv_xlen == 64)
#define __arch64__
#endif
/**
* @brief Returns 32-63 bits of a number.
* @param n : Number being accessed.
* @return Bits 32-63 of number.
*
* @note A basic shift-right of a 64- or 32-bit quantity.
* Use this to suppress the "right shift count >= width of type"
* warning when that quantity is 32-bits.
*/
#if defined (__aarch64__) || defined (__arch64__)
#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
#else
#define UPPER_32_BITS(n) 0U
#endif
/**
* @brief Returns 0-31 bits of a number
* @param n : Number being accessed.
* @return Bits 0-31 of number
*/
#define LOWER_32_BITS(n) ((u32)(n))
/**
* @brief Returns 0-31 bits of a number .
* @param n : Number being accessed.
* @return Bits 0-31 of number.
*/
#if defined (__aarch64__) || defined (__arch64__)
#define LEFT_SHIFT_BY_32_BITS(n) (u64)(((u64)n) << 32)
#else
#define LEFT_SHIFT_BY_32_BITS(n) 0U
#endif
/************************** Constant Definitions *****************************/
#ifndef TRUE
#define TRUE 1U
#endif
#ifndef FALSE
#define FALSE 0U
#endif
#ifndef NULL
#define NULL 0U
#endif
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
*@endcond
*/
/**
* @} End of "addtogroup common_types".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_util.h
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/******************************************************************************/
/**
* Copyright (C) 2019 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
* @file xil_util.h
* @addtogroup common_utilities Common Utility APIs
* @{
* @details
*
* xil_util.h file contains xil utility functions declarations
* Except few functions, most of these functions are wrappers to standard functions.
* The standard string functions do not validate the input and that results into
* buffer overflows. To avoid it, the wrapper function validates the input and
* then passed to standard function. There are few constant time functions
* ( xxx_CT() ) which are used to compare the data in constant time.
* The constant time functions should be used while comparing secure data
* like password, keys which prevent disclosing of the data using
* timing analysis.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 6.4 mmd 04/21/19 First release.
* 6.5 kal 02/29/20 Added Xil_ConvertStringToHexBE API
* 7.3 kal 06/30/20 Converted Xil_Ceil macro to API
* rpo 08/19/20 Added function for read, modify and write
* bsv 08/21/20 Added XSECURE_TEMPORAL_CHECK macro to add
* redundancy in security critical functions, to avoid
* glitches from altering the return values of security
* critical functions. The macro requires a label to be
* passed to "go to" in case of error.
* kpt 09/03/20 Added XSECURE_TEMPORAL_IMPL macro for redundancy
* kal 09/22/20 Changed the param type from const char to const char*
* to avoid copying key onto stack
* td 10/16/20 Added Xil_Strcpy, Xil_Strcat, Xil_SecureMemCpy and
* Xil_MemCmp functions
* am 10/13/20 Resolved Coverity warning
* td 11/19/20 Updated XSECURE_TEMPORAL_CHECK and
* XSECURE_TEMPORAL_IMPL to fix MISRA C Rule 15.3
* 7.4 am 11/26/20 Added Xil_StrCpyRange function
* 7.6 kpt 07/15/21 Added Xil_SecureZeroize function
* 7.7 kpt 11/09/21 Added Xil_SMemCmp, Xil_SMemCmp_CT, Xil_SMemCpy,
* Xil_SMemSet, Xil_SStrCat, Xil_SStrCmp, Xil_SStrCmp_CT
* Xil_SStrCpy functions
* 7.7 sk 01/10/22 Update functions return type to fix misra_c_2012_
* directive_4_6 violations.
* mmd 02/28/22 Added Xil_SMemMove function prototype
* 8.0 adk 04/18/22 Added Xil_WaitForEventSet function prototype.
* ssc 08/25/22 Added Xil_SecureRMW32 prototype
* 8.1 sa 09/29/22 Change the type of first argument passed to Xil_WaitForEvent
* API from u32 to UINTPTR for supporting 64 bit addressing.
* 8.1 sa 10/20/22 Change the type of first argument passed to Xil_WaitForEvents
* API from u32 to UINTPTR for supporting 64 bit addressing.
* 8.1 akm 01/02/23 Added Xil_RegisterPlmHandler() & Xil_PlmStubHandler() APIs.
* bm 03/14/23 Added XSECURE_REDUNDANT_CALL and XSECURE_REDUNDANT_IMPL macros
* sk 03/14/23 Added Status Check Glitch detect Macro
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* mmd 07/09/23 Added macro to build version
* ml 09/13/23 Replaced numerical types (int) with proper typedefs(s32) to
* fix MISRA-C violations for Rule 4.6
* </pre>
*
*****************************************************************************/
#ifndef XIL_UTIL_H_
#define XIL_UTIL_H_
#ifdef __cplusplus
extern "C" {
#endif
/******************************* Include Files ********************************/
#include "xil_types.h"
#include "xil_io.h"
#include "xstatus.h"
/*************************** Constant Definitions *****************************/
#define XIL_SIZE_OF_NIBBLE_IN_BITS 4U /**< size of nibble in bits */
#define XIL_SIZE_OF_BYTE_IN_BITS 8U /**< size of byte in bits */
#define XIL_MAX_HEX_STR_LEN 512U /**< Maximum string length handled by
Xil_ValidateHexStr function */
/****************** Macros (Inline Functions) Definitions *********************/
/******************************************************************************/
/**
*
* Builds version number by concatenates 16-bit Major version and Minor version.
*
* @param Major is the 16-bit major version number
* @param Minor is the 16-bit minor version number
*
* @return 32-bit version number
*
******************************************************************************/
#define XIL_BUILD_VERSION(Major, Minor) (((Major) << 16U) | (Minor))
#ifdef __GNUC__
/******************************************************************************/
/**
*
* Updates the return value of the called function into Var and VarTmp variables
* for redundancy. This is to avoid glitches from altering the return values of
* security critical functions.
*
* @param Var is the variable which holds the return value of function
* executed
* @param VarTmp is the variable which holds the value stored in Var
* @param Function is the function to be executed
* @param Other params are arguments to the called function
*
* @return None
*
******************************************************************************/
#define XSECURE_TEMPORAL_IMPL(Var, VarTmp, Function, ...) \
{ \
Var = XST_FAILURE; \
VarTmp = XST_FAILURE; \
Var = Function(__VA_ARGS__); \
VarTmp = Var; \
}
/******************************************************************************/
/**
*
* Adds redundancy while checking the status of the called function.
* This is to avoid glitches from altering the return values of security
* critical functions. The macro requires a label to be passed to "go to"
* in case of error.
*
* @param Label is the label defined in function and the control
* will jump to the label in case of XST_FAILURE
* @param Status is the variable which holds the return value of
* function executed
* @param Function is the function to be executed
* @param Other params are arguments to the called function
*
* @return None
*
******************************************************************************/
#define XSECURE_TEMPORAL_CHECK(Label, Status, Function, ...) \
{ \
volatile int StatusTmp; \
XSECURE_TEMPORAL_IMPL(Status, StatusTmp, Function, __VA_ARGS__); \
if ((Status != XST_SUCCESS) || \
(StatusTmp != XST_SUCCESS)) { \
if (((Status) != (StatusTmp)) || \
(Status == XST_SUCCESS)) { \
Status = XST_GLITCH_ERROR; \
}\
goto Label; \
} \
}
/******************************************************************************/
/**
*
* Adds redundancy to the function call. This is to avoid glitches which can skip
* a function call and cause altering of the code flow in security critical
* functions.
*
* @param Status is the variable which holds the return value of
* function executed
* @param StatusTmp is the variable which holds the return value of
* redundant function call executed
* @param Function is the function to be executed
* @param Other params are arguments to the called function
*
* @return None
*
******************************************************************************/
#define XSECURE_REDUNDANT_CALL(Status, StatusTmp, Function, ...) \
{ \
Status = Function(__VA_ARGS__); \
StatusTmp = Function(__VA_ARGS__); \
}
/******************************************************************************/
/**
*
* Adds redundancy to the function call. This is to avoid glitches which can skip
* a function call and cause altering of the code flow in security critical
* functions.
*
* @param Function is the function to be executed
* @param Other params are arguments to the called function
*
* @return None
*
******************************************************************************/
#define XSECURE_REDUNDANT_IMPL(Function, ...) \
{ \
Function(__VA_ARGS__); \
Function(__VA_ARGS__); \
}
/******************************************************************************/
/**
*
* This Macro helps to detect glitches skipping the Status check
* in case of error.
*
* @param None
*
* @return None
*
******************************************************************************/
#define XSECURE_STATUS_CHK_GLITCH_DETECT(Status) \
{ \
if (Status == XST_SUCCESS) { \
Status = (int)XST_GLITCH_ERROR; \
} \
}
#endif
/*************************** Function Prototypes ******************************/
/**< Ceils the provided float value */
s32 Xil_Ceil(float Value);
/**< Converts input character to nibble */
u32 Xil_ConvertCharToNibble(u8 InChar, u8 *Num);
/**< Convert input hex string to array of 32-bits integers */
u32 Xil_ConvertStringToHex(const char *Str, u32 *buf, u8 Len);
#ifdef VERSAL_PLM
/**< Register PLM handler */
void Xil_RegisterPlmHandler(void (*PlmAlive) (void));
/**< Call PLM handler */
void Xil_PlmStubHandler(void);
#endif
/**< Waits for specified event */
u32 Xil_WaitForEvent(UINTPTR RegAddr, u32 EventMask, u32 Event, u32 Timeout);
/**< Waits for specified events */
u32 Xil_WaitForEvents(UINTPTR EventsRegAddr, u32 EventsMask, u32 WaitEvents,
u32 Timeout, u32 *Events);
/**< Validate input hex character */
u32 Xil_IsValidHexChar(const char *Ch);
/**< Validate the input string contains only hexadecimal characters */
u32 Xil_ValidateHexStr(const char *HexStr);
/**< Convert string to hex numbers in little enidian format */
u32 Xil_ConvertStringToHexLE(const char *Str, u8 *Buf, u32 Len);
/**< Returns length of the input string */
u32 Xil_Strnlen(const char *Str, u32 MaxLen);
/**< Convert string to hex numbers in big endian format */
u32 Xil_ConvertStringToHexBE(const char *Str, u8 *Buf, u32 Len);
/**< Read, Modify and Write to an address*/
void Xil_UtilRMW32(u32 Addr, u32 Mask, u32 Value);
/**< Copies source string to destination string */
s32 Xil_Strcpy(char *DestPtr, const char *SrcPtr, const u32 Size);
/**< Copies specified range from source string to destination string */
s32 Xil_StrCpyRange(const u8 *Src, u8 *Dest, u32 From, u32 To, u32 MaxSrcLen,
u32 MaxDstLen);
/**< Appends string2 to string1 */
s32 Xil_Strcat(char *Str1Ptr, const char *Str2Ptr, const u32 Size);
/**< Copies Len bytes from source memory to destination memory */
s32 Xil_SecureMemCpy(void *DestPtr, u32 DestPtrLen, const void *SrcPtr, u32 Len);
/**< Compares Len bytes from memory1 and memory2 */
s32 Xil_MemCmp(const void *Buf1Ptr, const void *Buf2Ptr, u32 Len);
/**< Zeroizes the memory of given length */
s32 Xil_SecureZeroize(u8 *DataPtr, const u32 Length);
/**< Copies Len bytes from source memory to destination memory */
s32 Xil_SMemCpy (void *Dest, const u32 DestSize,
const void *Src, const u32 SrcSize, const u32 CopyLen);
/**< Copies Len bytes from source memory to destination memory, allows
overlapped memory between source and destination */
s32 Xil_SMemMove(void *Dest, const u32 DestSize,
const void *Src, const u32 SrcSize, const u32 CopyLen);
/**< Compares Len bytes between source and destination memory */
s32 Xil_SMemCmp (const void *Src1, const u32 Src1Size,
const void *Src2, const u32 Src2Size, const u32 CmpLen);
/**< Compares Len bytes between source and destination memory with constant time */
s32 Xil_SMemCmp_CT (const void *Src1, const u32 Src1Size,
const void *Src2, const u32 Src2Size, const u32 CmpLen);
/**< Sets the destination memory of given length with given data */
s32 Xil_SMemSet (void *Dest, const u32 DestSize,
const u8 Data, const u32 Len);
/**< Copies source string to destination string */
s32 Xil_SStrCpy (u8 *DestStr, const u32 DestSize,
const u8 *SrcStr, const u32 SrcSize);
/**< Compares source string with destination string */
s32 Xil_SStrCmp (const u8 *Str1, const u32 Str1Size,
const u8 *Str2, const u32 Str2Size);
/**< Compares source string with destination string with constant time */
s32 Xil_SStrCmp_CT (const u8 *Str1, const u32 Str1Size,
const u8 *Str2, const u32 Str2Size);
/**< Concatenates source string to destination string */
s32 Xil_SStrCat (u8 *DestStr, const u32 DestSize,
const u8 *SrcStr, const u32 SrcSize);
/**< Waits for event timeout */
u32 Xil_WaitForEventSet(u32 Timeout, u32 NumOfEvents, volatile u32 *EventAddr, ...);
/**< Implements Read Modify Writes securely */
s32 Xil_SecureRMW32(UINTPTR Addr, u32 Mask, u32 Value);
#ifdef __cplusplus
}
#endif
#endif /* XIL_UTIL_H_ */
/**
* @} End of "addtogroup common_utilities".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xilrsa.h
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/******************************************************************************
* Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xilrsa.h
* @addtogroup xilrsa_apis XilRSA APIs and Descriptions
* @{
* @cond xilrsa_internal
* This file contains the RSA algorithm functions
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.0 hk 27/01/14 First release
* 1.4 vns 07/06/17 Added dooxygen tags.
*
* </pre>
*
* @note
*
******************************************************************************/
#ifndef ___XIL_RSA_H___
#define ___XIL_RSA_H___
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
/*
* Digit size selection (32 or 16-bit). If supported by the CPU/compiler,
* 32-bit digits are approximately 4 times faster
*/
//#define RSA_DIGIT_16
#define RSA_DIGIT_32
/*
* RSA loop unrolling selection
* RSA main loop can be unrolled 2, 4 or 8 ways
*/
#define RSA_UNROLL 1
/*
* Select if ARM-optimized code is to be used. Only GCC for ARM is supported
*/
//#define RSA_ARM_OPTIMIZED
/*
* Check the compatibility of the selection
*/
#if defined(RSA_DIGIT_16) && defined(RSA_DIGIT_32)
#error Please select a digit size
#endif
#if !defined(RSA_DIGIT_16) && !defined(RSA_DIGIT_32)
#error Please select just one digit size
#endif
#if (!defined(__GNUC__) || !defined(__arm__)) && defined(RSA_ARM_OPTIMIZED)
#error Assembly level code is only supported for the GCC/ARM combination
#endif
#if (RSA_UNROLL != 1) && (RSA_UNROLL != 2) && (RSA_UNROLL != 4) && (RSA_UNROLL != 8)
#error Only 1, 2, 4, and 8 unrolling are supported
#endif
#ifdef RSA_DIGIT_16
#define RSA_DIGIT unsigned short
#define RSA_SDIGIT short
#define RSA_DDIGIT unsigned long
#endif
#ifdef RSA_DIGIT_32
#define RSA_DIGIT unsigned long
#define RSA_SDIGIT long
#define RSA_DDIGIT unsigned long long
#endif
#define RSA_NUMBER RSA_DIGIT *
#define RSA_NBITS 2048
#define RSA_NDIGITS (RSA_NBITS/(sizeof(RSA_DIGIT)*8))
#define RSA_NBYTES (RSA_NDIGITS*sizeof(RSA_DIGIT))
/*
* Double-digit to single digit conversion
*/
#define RSA_MSB(x) (x >> (sizeof(RSA_DIGIT)*8))
#define RSA_LSB(x) (x & (RSA_DIGIT)~0)
#define SHA_BLKSIZE 512
#define SHA_BLKBYTES (SHA_BLKSIZE/8)
#define SHA_BLKWORDS (SHA_BLKBYTES/4)
#define SHA_VALSIZE 256
#define SHA_VALBYTES (SHA_VALSIZE/8)
#define SHA_VALWORDS (SHA_VALBYTES/4)
/*
* SHA-256 context structure
* Includes SHA-256 state, coalescing buffer to collect the processed strings, and
* total byte length counter (used both to manage the buffer and for padding)
*/
//! [sha2_context]
typedef struct
{
unsigned int state[8];
unsigned char buffer[SHA_BLKBYTES];
unsigned long long bytes;
} sha2_context;
//! [sha2_context]
/** @}
@endcond */
/*
* RSA-2048 user interfaces
*/
/*****************************************************************************/
/**
* @brief
* This function is used to encrypt the data using 2048 bit private key.
*
* @param modular A char pointer which contains the key modulus
* @param modular_ext A char pointer which contains the key modulus
* extension
* @param exponent A char pointer which contains the private key
* exponent
* @param result A char pointer which contains the encrypted data
*
* @return None
*
******************************************************************************/
void rsa2048_exp(const unsigned char *base, const unsigned char * modular,
const unsigned char *modular_ext, const unsigned char *exponent,
unsigned char *result);
/*****************************************************************************/
/**
* @brief
* This function is used to decrypt the data using 2048 bit public key
*
* @param a RSA_NUMBER containing the decrypted data.
* @param x RSA_NUMBER containing the input data
* @param e Unsigned number containing the public key exponent
* @param m RSA_NUMBER containing the public key modulus
* @param rrm RSA_NUMBER containing the public key modulus extension.
*
* @return None
*
******************************************************************************/
void rsa2048_pubexp(RSA_NUMBER a, RSA_NUMBER x,
unsigned long e, RSA_NUMBER m, RSA_NUMBER rrm);
/*
* SHA-256 user interfaces
*/
/*****************************************************************************/
/**
* @brief
* This function calculates the hash for the input data using SHA-256
* algorithm. This function internally calls the sha2_init, updates and
* finishes functions and updates the result.
*
* @param In Char pointer which contains the input data.
* @param Size Length of the input data
* @param Out Pointer to location where resulting hash will be
* written.
*
* @return None
*
******************************************************************************/
void sha_256(const unsigned char *in, const unsigned int size, unsigned char *out);
/*****************************************************************************/
/**
* @brief
* This function initializes the SHA2 context.
*
* @param ctx Pointer to sha2_context structure that stores status and
* buffer.
*
* @return None
*
******************************************************************************/
void sha2_starts(sha2_context *ctx);
/*****************************************************************************/
/**
* @brief
* This function adds the input data to SHA256 calculation.
*
* @param ctx Pointer to sha2_context structure that stores status and
* buffer.
* @param input Pointer to the data to add.
* @param Out Length of the input data.
*
* @return None
*
******************************************************************************/
void sha2_update(sha2_context *ctx, unsigned char* input, unsigned int ilen);
/*****************************************************************************/
/**
* @brief
* This function finishes the SHA calculation.
*
* @param ctx Pointer to sha2_context structure that stores status and
* buffer.
* @param output Pointer to the calculated hash data.
*
* @return None
*
*
******************************************************************************/
void sha2_finish(sha2_context *ctx, unsigned char* output);
/*
* Preprocessing interface (pre-computation of R*R mod M)
*/
/**@cond xilrsa_internal */
void modular_ext(const unsigned char *modular, unsigned char *res);
/** @}
@endcond */
#ifdef __cplusplus
}
#endif
#endif /* ___XIL_RSA_H___ */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xinterrupt_wrap.h
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/******************************************************************************
* Copyright (C) 2021 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xinterrupt_wrap.h
*
* The xinterrupt_wrap.h file contains interrupt related functions and macros.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 7.2 mus 22/11/21 First release of xil interrupt support
* 8.0 sk 03/17/22 Update XINTC_BASEADDR_MASK macro to unsigned to
* fix misra_c_2012_rule_7_2 violation.
* 9.0 ml 03/03/23 Add description to fix doxygen warnings.
* </pre>
*
******************************************************************************/
#ifndef XINTERRUPT_WRAP_H /**< prevent circular inclusions */
#define XINTERRUPT_WRAP_H /**< by using protection macros */
#include "xil_types.h"
#include "xstatus.h"
#ifdef XIL_INTERRUPT
#ifdef SDT
#include "xcommon_drv_config.h"
#else
#include "xparameters.h"
#endif
#include "xil_exception.h"
#if defined(XPAR_AXI_INTC)
#include "xintc.h"
#endif
#if defined(XPAR_SCUGIC)
#include "xscugic.h"
#define XSPI_INTR_OFFSET 32U
#endif
#define XINTERRUPT_DEFAULT_PRIORITY 0xA0U /* AXI INTC doesnt support priority setting, it is default priority for GIC interrupts */
#define XINTC_TYPE_IS_SCUGIC 0U
#define XINTC_TYPE_IS_INTC 1U
#define XINTR_IS_EDGE_TRIGGERED 3U
#define XINTR_IS_LEVEL_TRIGGERED 1U
#define XINTC_TYPE_MASK 0x1
#define XINTC_INTR_TYPE_MASK 0x100000
#define XINTC_BASEADDR_MASK 0xFFFFFFFFFFFFFFFEU
#define XINTC_INTRID_MASK 0xFFF
#define XINTC_TRIGGER_MASK 0xF000
#define XINTC_TRIGGER_SHIFT 12
#define XINTC_INTR_TYPE_SHIFT 20U
#define XGet_IntcType(IntParent) (IntParent & XINTC_TYPE_MASK)
#define XGet_IntrType(IntId) ((IntId & XINTC_INTR_TYPE_MASK) >> XINTC_INTR_TYPE_SHIFT)
#define XGet_BaseAddr(IntParent) (IntParent & XINTC_BASEADDR_MASK)
#define XGet_IntrId(IntId) (IntId & XINTC_INTRID_MASK)
#define XGet_TriggerType(IntId) ((IntId & XINTC_TRIGGER_MASK) >> XINTC_TRIGGER_SHIFT)
#define XGet_IntrOffset(IntId) (( XGet_IntrType(IntId) == 1) ? 16 : 32) /* For PPI offset is 16 and for SPI it is 32 */
extern int XConfigInterruptCntrl(UINTPTR IntcParent);
extern int XConnectToInterruptCntrl(u32 IntrId, void *IntrHandler, void *CallBackRef, UINTPTR IntcParent);
extern int XDisconnectInterruptCntrl(u32 IntrId, UINTPTR IntcParent);
extern int XStartInterruptCntrl(u32 Mode, UINTPTR IntcParent);
extern void XEnableIntrId( u32 IntrId, UINTPTR IntcParent);
extern void XDisableIntrId( u32 IntrId, UINTPTR IntcParent);
extern void XSetPriorityTriggerType( u32 IntrId, u8 Priority, UINTPTR IntcParent);
extern void XGetPriorityTriggerType( u32 IntrId, u8 *Priority, u8 *Trigger, UINTPTR IntcParent);
extern void XStopInterruptCntrl( UINTPTR IntcParent);
extern void XRegisterInterruptHandler( void *IntrHandler, UINTPTR IntcParent);
extern int XSetupInterruptSystem(void *DriverInstance, void *IntrHandler, u32 IntrId, UINTPTR IntcParent,
u16 Priority);
#endif
#endif /* end of protection macro */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc.h
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/******************************************************************************
* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xl2cc.h
*
* This file contains the address definitions for the PL310 Level-2 Cache
* Controller.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- ---------------------------------------------------
* 1.00a sdm 02/01/10 Initial version
* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
* 'xil_errata.h' for errata description
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef _XL2CC_H_
#define _XL2CC_H_
#ifdef __cplusplus
extern "C" {
#endif
/************************** Constant Definitions *****************************/
/* L2CC Register Offsets */
#define XPS_L2CC_ID_OFFSET 0x0000U
#define XPS_L2CC_TYPE_OFFSET 0x0004U
#define XPS_L2CC_CNTRL_OFFSET 0x0100U
#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U
#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U
#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU
#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U
#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U
#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U
#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU
#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U
#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */
#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */
#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */
#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */
#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */
#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */
#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */
#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */
#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */
#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */
#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */
#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */
#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */
#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */
#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */
#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */
#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */
#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */
#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */
#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */
#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */
#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */
#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */
#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */
#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */
#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */
#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */
#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */
#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */
#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */
#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */
#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */
#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */
#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */
#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */
/* XPS_L2CC_CNTRL_OFFSET bit masks */
#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */
/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */
#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */
#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */
#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */
#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */
#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */
#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */
#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */
#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */
#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */
#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */
#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */
#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */
#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */
#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */
#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */
#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */
#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */
/* Cache replacement policy, Parity enable, */
/* Event monitor bus enable and Way Size (64 KB) */
#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */
#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */
#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */
/* Interrupt bit masks */
#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */
#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */
#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */
#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */
#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */
#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */
#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */
#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */
#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */
/* Address filtering mask and enable bit */
#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/
#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/
/* Debug control bits */
#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */
#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */
#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */
#ifdef __cplusplus
}
#endif
#endif /* protection macro */
/**
*@endcond
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc_counter.h
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/******************************************************************************
* Copyright (c) 2011 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xl2cc_counter.h
*
* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
*
* xl2cc_counter.h contains APIs for configuring and controlling the event
* counters in PL310 L2 cache controller.
* PL310 has two event counters which can be used to count variety of events
* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
* for different configurations which can be used for the event counters to
* count a set of events.
*
*
* @{
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sdm 07/11/11 First release
* 3.07a asa 08/30/12 Updated for CR 675636 to provide the L2 Base Address
* inside the APIs
* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
#define L2CCCOUNTER_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xpseudo_asm.h"
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/************************** Constant Definitions ****************************/
/*
* The following constants define the event codes for the event counters.
*/
#define XL2CC_CO 0x1
#define XL2CC_DRHIT 0x2
#define XL2CC_DRREQ 0x3
#define XL2CC_DWHIT 0x4
#define XL2CC_DWREQ 0x5
#define XL2CC_DWTREQ 0x6
#define XL2CC_IRHIT 0x7
#define XL2CC_IRREQ 0x8
#define XL2CC_WA 0x9
#define XL2CC_IPFALLOC 0xa
#define XL2CC_EPFHIT 0xb
#define XL2CC_EPFALLOC 0xc
#define XL2CC_SRRCVD 0xd
#define XL2CC_SRCONF 0xe
#define XL2CC_EPFRCVD 0xf
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/************************** Variable Definitions ****************************/
/**
*@endcond
*/
/************************** Function Prototypes *****************************/
void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
void XL2cc_EventCtrStart(void);
void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* L2CCCOUNTER_H */
/**
* @} End of "addtogroup l2_event_counter_apis".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters.h
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#ifndef XPARAMETERS_H /* prevent circular inclusions */
#define XPARAMETERS_H /* by using protection macros */
/* Definition for CPU ID */
#define XPAR_CPU_ID 0U
/* Definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
/******************************************************************/
/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
/******************************************************************/
#include "xparameters_ps.h"
#define STDIN_BASEADDRESS 0xE0001000
#define STDOUT_BASEADDRESS 0xE0001000
/******************************************************************/
/* Platform specific definitions */
#define PLATFORM_ZYNQ
/* Definitions for sleep timer configuration */
#define XSLEEP_TIMER_IS_DEFAULT_TIMER
/******************************************************************/
/* Definitions for peripheral PS7_DDR_0 */
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF
/******************************************************************/
/* Definitions for driver DEVCFG */
#define XPAR_XDCFG_NUM_INSTANCES 1U
/* Definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
/******************************************************************/
/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
#define XPAR_XDCFG_0_BASEADDR 0xF8007000U
#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
/******************************************************************/
/* Definitions for driver DMAPS */
#define XPAR_XDMAPS_NUM_INSTANCES 2
/* Definitions for peripheral PS7_DMA_NS */
#define XPAR_PS7_DMA_NS_DEVICE_ID 0
#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
/* Definitions for peripheral PS7_DMA_S */
#define XPAR_PS7_DMA_S_DEVICE_ID 1
#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_DMA_NS */
#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
/* Canonical definitions for peripheral PS7_DMA_S */
#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
/******************************************************************/
/* Definitions for driver EMACPS */
#define XPAR_XEMACPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0
/******************************************************************/
#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0
#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
/* Canonical definitions for peripheral PS7_ETHERNET_0 */
#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0
/******************************************************************/
/* Peripheral Definitions for peripheral MYDNA_READ_V1_0_0 */
#define XPAR_MYDNA_READ_V1_0_0_BASEADDR 0x43C00000
#define XPAR_MYDNA_READ_V1_0_0_HIGHADDR 0x43C0FFFF
/* Peripheral Definitions for peripheral PS7_AFI_0 */
#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
/* Peripheral Definitions for peripheral PS7_AFI_1 */
#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
/* Peripheral Definitions for peripheral PS7_AFI_2 */
#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
/* Peripheral Definitions for peripheral PS7_AFI_3 */
#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
/* Peripheral Definitions for peripheral PS7_DDRC_0 */
#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
/* Peripheral Definitions for peripheral PS7_GLOBALTIMER_0 */
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
/* Peripheral Definitions for peripheral PS7_GPV_0 */
#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
/* Peripheral Definitions for peripheral PS7_INTC_DIST_0 */
#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
/* Peripheral Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
/* Peripheral Definitions for peripheral PS7_L2CACHEC_0 */
#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
/* Peripheral Definitions for peripheral PS7_OCMC_0 */
#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
/* Peripheral Definitions for peripheral PS7_PL310_0 */
#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
/* Peripheral Definitions for peripheral PS7_PMU_0 */
#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
/* Peripheral Definitions for peripheral PS7_QSPI_LINEAR_0 */
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
/* Peripheral Definitions for peripheral PS7_RAM_0 */
#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
/* Peripheral Definitions for peripheral PS7_RAM_1 */
#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
/* Peripheral Definitions for peripheral PS7_SCUC_0 */
#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
/* Peripheral Definitions for peripheral PS7_SLCR_0 */
#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
/******************************************************************/
/* Canonical Definitions for peripheral MYDNA_READ_V1_0_0 */
#define XPAR_MYDNA_READ_V1_0_BASEADDR 0x43C00000
#define XPAR_MYDNA_READ_V1_0_HIGHADDR 0x43C0FFFF
/******************************************************************/
/* Definitions for driver GPIOPS */
#define XPAR_XGPIOPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_GPIO_0 */
#define XPAR_PS7_GPIO_0_DEVICE_ID 0
#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Canonical definitions for peripheral PS7_GPIO_0 */
#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
/******************************************************************/
/* Definitions for driver QSPIPS */
#define XPAR_XQSPIPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_QSPI_0 */
#define XPAR_PS7_QSPI_0_DEVICE_ID 0
#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 142857132
#define XPAR_PS7_QSPI_0_QSPI_MODE 0
#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2
/******************************************************************/
/* Canonical definitions for peripheral PS7_QSPI_0 */
#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 142857132
#define XPAR_XQSPIPS_0_QSPI_MODE 0
#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2
/******************************************************************/
/* Definitions for driver SCUGIC */
#define XPAR_XSCUGIC_NUM_INSTANCES 1U
/* Definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_SCUGIC_0_DEVICE_ID 0U
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
/******************************************************************/
/* Definitions for driver SCUTIMER */
#define XPAR_XSCUTIMER_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUTIMER_0 */
#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
/******************************************************************/
/* Definitions for driver SCUWDT */
#define XPAR_XSCUWDT_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
/******************************************************************/
/* Canonical definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
/******************************************************************/
/* Definitions for driver SDPS */
#define XPAR_XSDPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_SD_0 */
#define XPAR_PS7_SD_0_DEVICE_ID 0
#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
#define XPAR_PS7_SD_0_HAS_CD 1
#define XPAR_PS7_SD_0_HAS_WP 1
#define XPAR_PS7_SD_0_BUS_WIDTH 0
#define XPAR_PS7_SD_0_MIO_BANK 0
#define XPAR_PS7_SD_0_HAS_EMIO 0
#define XPAR_PS7_SD_0_SLOT_TYPE 0
#define XPAR_PS7_SD_0_CLK_50_SDR_ITAP_DLY 0
#define XPAR_PS7_SD_0_CLK_50_SDR_OTAP_DLY 0
#define XPAR_PS7_SD_0_CLK_50_DDR_ITAP_DLY 0
#define XPAR_PS7_SD_0_CLK_50_DDR_OTAP_DLY 0
#define XPAR_PS7_SD_0_CLK_100_SDR_OTAP_DLY 0
#define XPAR_PS7_SD_0_CLK_200_SDR_OTAP_DLY 0
/******************************************************************/
#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0
/* Canonical definitions for peripheral PS7_SD_0 */
#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
#define XPAR_XSDPS_0_BASEADDR 0xE0100000
#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
#define XPAR_XSDPS_0_HAS_CD 1
#define XPAR_XSDPS_0_HAS_WP 1
#define XPAR_XSDPS_0_BUS_WIDTH 0
#define XPAR_XSDPS_0_MIO_BANK 0
#define XPAR_XSDPS_0_HAS_EMIO 0
#define XPAR_XSDPS_0_SLOT_TYPE 0
#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0
#define XPAR_XSDPS_0_CLK_50_SDR_ITAP_DLY 0
#define XPAR_XSDPS_0_CLK_50_SDR_OTAP_DLY 0
#define XPAR_XSDPS_0_CLK_50_DDR_ITAP_DLY 0
#define XPAR_XSDPS_0_CLK_50_DDR_OTAP_DLY 0
#define XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY 0
#define XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY 0
/******************************************************************/
/* Definitions for driver UARTPS */
#define XPAR_XUARTPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_UART_1 */
#define XPAR_PS7_UART_1_DEVICE_ID 0
#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 100000000
#define XPAR_PS7_UART_1_HAS_MODEM 0
/******************************************************************/
/* Canonical definitions for peripheral PS7_UART_1 */
#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 100000000
#define XPAR_XUARTPS_0_HAS_MODEM 0
/******************************************************************/
/* Definition for input Clock */
/* Definitions for driver XADCPS */
#define XPAR_XADCPS_NUM_INSTANCES 1
/* Definitions for peripheral PS7_XADC_0 */
#define XPAR_PS7_XADC_0_DEVICE_ID 0
#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
/******************************************************************/
/* Canonical definitions for peripheral PS7_XADC_0 */
#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
#define XPAR_XADCPS_0_BASEADDR 0xF8007100
#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
/******************************************************************/
/* Xilinx FAT File System Library (XilFFs) User Settings */
#define FILE_SYSTEM_INTERFACE_SD
#define FILE_SYSTEM_USE_MKFS
#define FILE_SYSTEM_NUM_LOGIC_VOL 2
#define FILE_SYSTEM_USE_STRFUNC 0
#define FILE_SYSTEM_SET_FS_RPATH 0
#define FILE_SYSTEM_WORD_ACCESS
#endif /* end of protection macro */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters_ps.h
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/******************************************************************************
* Copyright (c) 2010 - 2021 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
* @file xparameters_ps.h
*
* This file contains the address definitions for the hard peripherals
* attached to the ARM Cortex A9 core.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ------- -------- ---------------------------------------------------
* 1.00a ecm/sdm 02/01/10 Initial version
* 3.04a sdm 02/02/12 Removed some of the defines as they are being generated through
* driver tcl
* 5.0 pkp 01/16/15 Added interrupt ID definition of ttc for TEST APP
* 6.6 srm 10/18/17 Added ARMA9 macro to identify CortexA9
*
* </pre>
*
* @note
*
* None.
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef _XPARAMETERS_PS_H_
#define _XPARAMETERS_PS_H_
#ifdef __cplusplus
extern "C" {
#endif
/**************************** Include Files *******************************/
/************************** Constant Definitions *****************************/
/*
* This block contains constant declarations for the peripherals
* within the hardblock
*/
/* Canonical definitions for DDR MEMORY */
#define XPAR_DDR_MEM_BASEADDR 0x00000000U
#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU
/* Canonical definitions for Interrupts */
#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID
#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID
#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID
#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID
#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID
#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID
#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID
#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID
#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID
#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID
#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID
#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID
#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID
#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID
#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID
#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID
#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID
#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID
#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID
#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID
#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID
#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID
#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR
#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR
/* Canonical definitions for DMAC */
/* Canonical definitions for WDT */
/* Canonical definitions for SLCR */
#define XPAR_XSLCR_NUM_INSTANCES 1U
#define XPAR_XSLCR_0_DEVICE_ID 0U
#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR
/* Canonical definitions for SCU GIC */
#define XPAR_SCUGIC_NUM_INSTANCES 1U
#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U
#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U)
#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U)
#define XPAR_SCUGIC_ACK_BEFORE 0U
/* Canonical definitions for Global Timer */
#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U
#define XPAR_GLOBAL_TMR_DEVICE_ID 0U
#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U)
#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID
/* Xilinx Parallel Flash Library (XilFlash) User Settings */
#define XPAR_AXI_EMC
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
/*
* This block contains constant declarations for the peripherals
* within the hardblock. These have been put for bacwards compatibility
*/
#define XPS_PERIPHERAL_BASEADDR 0xE0000000U
#define XPS_UART0_BASEADDR 0xE0000000U
#define XPS_UART1_BASEADDR 0xE0001000U
#define XPS_USB0_BASEADDR 0xE0002000U
#define XPS_USB1_BASEADDR 0xE0003000U
#define XPS_I2C0_BASEADDR 0xE0004000U
#define XPS_I2C1_BASEADDR 0xE0005000U
#define XPS_SPI0_BASEADDR 0xE0006000U
#define XPS_SPI1_BASEADDR 0xE0007000U
#define XPS_CAN0_BASEADDR 0xE0008000U
#define XPS_CAN1_BASEADDR 0xE0009000U
#define XPS_GPIO_BASEADDR 0xE000A000U
#define XPS_GEM0_BASEADDR 0xE000B000U
#define XPS_GEM1_BASEADDR 0xE000C000U
#define XPS_QSPI_BASEADDR 0xE000D000U
#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U
#define XPS_SDIO0_BASEADDR 0xE0100000U
#define XPS_SDIO1_BASEADDR 0xE0101000U
#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U
#define XPS_NAND_BASEADDR 0xE1000000U
#define XPS_PARPORT0_BASEADDR 0xE2000000U
#define XPS_PARPORT1_BASEADDR 0xE4000000U
#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U
#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */
#define XPS_TTC0_BASEADDR 0xF8001000U
#define XPS_TTC1_BASEADDR 0xF8002000U
#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U
#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U
#define XPS_WDT_BASEADDR 0xF8005000U
#define XPS_DDR_CTRL_BASEADDR 0xF8006000U
#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U
#define XPS_AFI0_BASEADDR 0xF8008000U
#define XPS_AFI1_BASEADDR 0xF8009000U
#define XPS_AFI2_BASEADDR 0xF800A000U
#define XPS_AFI3_BASEADDR 0xF800B000U
#define XPS_OCM_BASEADDR 0xF800C000U
#define XPS_EFUSE_BASEADDR 0xF800D000U
#define XPS_CORESIGHT_BASEADDR 0xF8800000U
#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U
#define XPS_SCU_PERIPH_BASE 0xF8F00000U
#define XPS_L2CC_BASEADDR 0xF8F02000U
#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U
#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U
#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U
#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U
#define XPS_PERIPH_APB_BASEADDR 0xF8000000U
/* Shared Peripheral Interrupts (SPI) */
#define XPS_CORE_PARITY0_INT_ID 32U
#define XPS_CORE_PARITY1_INT_ID 33U
#define XPS_L2CC_INT_ID 34U
#define XPS_OCMINTR_INT_ID 35U
#define XPS_ECC_INT_ID 36U
#define XPS_PMU0_INT_ID 37U
#define XPS_PMU1_INT_ID 38U
#define XPS_SYSMON_INT_ID 39U
#define XPS_DVC_INT_ID 40U
#define XPS_WDT_INT_ID 41U
#define XPS_TTC0_0_INT_ID 42U
#define XPS_TTC0_1_INT_ID 43U
#define XPS_TTC0_2_INT_ID 44U
#define XPS_DMA0_ABORT_INT_ID 45U
#define XPS_DMA0_INT_ID 46U
#define XPS_DMA1_INT_ID 47U
#define XPS_DMA2_INT_ID 48U
#define XPS_DMA3_INT_ID 49U
#define XPS_SMC_INT_ID 50U
#define XPS_QSPI_INT_ID 51U
#define XPS_GPIO_INT_ID 52U
#define XPS_USB0_INT_ID 53U
#define XPS_GEM0_INT_ID 54U
#define XPS_GEM0_WAKE_INT_ID 55U
#define XPS_SDIO0_INT_ID 56U
#define XPS_I2C0_INT_ID 57U
#define XPS_SPI0_INT_ID 58U
#define XPS_UART0_INT_ID 59U
#define XPS_CAN0_INT_ID 60U
#define XPS_FPGA0_INT_ID 61U
#define XPS_FPGA1_INT_ID 62U
#define XPS_FPGA2_INT_ID 63U
#define XPS_FPGA3_INT_ID 64U
#define XPS_FPGA4_INT_ID 65U
#define XPS_FPGA5_INT_ID 66U
#define XPS_FPGA6_INT_ID 67U
#define XPS_FPGA7_INT_ID 68U
#define XPS_TTC1_0_INT_ID 69U
#define XPS_TTC1_1_INT_ID 70U
#define XPS_TTC1_2_INT_ID 71U
#define XPS_DMA4_INT_ID 72U
#define XPS_DMA5_INT_ID 73U
#define XPS_DMA6_INT_ID 74U
#define XPS_DMA7_INT_ID 75U
#define XPS_USB1_INT_ID 76U
#define XPS_GEM1_INT_ID 77U
#define XPS_GEM1_WAKE_INT_ID 78U
#define XPS_SDIO1_INT_ID 79U
#define XPS_I2C1_INT_ID 80U
#define XPS_SPI1_INT_ID 81U
#define XPS_UART1_INT_ID 82U
#define XPS_CAN1_INT_ID 83U
#define XPS_FPGA8_INT_ID 84U
#define XPS_FPGA9_INT_ID 85U
#define XPS_FPGA10_INT_ID 86U
#define XPS_FPGA11_INT_ID 87U
#define XPS_FPGA12_INT_ID 88U
#define XPS_FPGA13_INT_ID 89U
#define XPS_FPGA14_INT_ID 90U
#define XPS_FPGA15_INT_ID 91U
/* Private Peripheral Interrupts (PPI) */
#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */
#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */
#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */
#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */
#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */
/* REDEFINES for TEST APP */
/* Definitions for UART */
#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID
#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID
#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID
#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID
#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID
#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID
#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID
#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID
#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID
#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID
#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID
#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID
#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID
#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID
#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID
#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID
#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID
#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID
#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID
#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID
#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID
#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID
#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID
#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID
#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID
#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID
#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID
/* For backwards compatibility */
#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
#endif
#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
#endif
#define XPAR_SCUTIMER_DEVICE_ID 0U
#define XPAR_SCUWDT_DEVICE_ID 0U
/*
* Defines for interrupt wrapper API
* For more details about usage please refer xinterrupt_wrap.h
* Here Bits[11:0] represents interrupt id
* Bits[15:12] represents interrupt trigger type and level flags
*/
#define XPAR_PS7_SCUTIMER_0_INTERRUPT_ID 0x10000D
#define XPAR_PS7_TTC_0_INTERRUPT_ID 0x400A
#define XPAR_PS7_TTC_1_INTERRUPT_ID 0x400B
#define XPAR_PS7_TTC_2_INTERRUPT_ID 0x400C
#define XPAR_PS7_TTC_3_INTERRUPT_ID 0x4025
#define XPAR_PS7_TTC_4_INTERRUPT_ID 0x4026
#define XPAR_PS7_TTC_5_INTERRUPT_ID 0x4027
#ifdef __cplusplus
}
#endif
#endif /* protection macro */
/**
*@endcond
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xplatform_info.h
+159
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@@ -0,0 +1,159 @@
/******************************************************************************
* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xplatform_info.h
*
*
* @addtogroup common_platform_info APIs to Get Platform Information
*
*
* The xplatform_info.h file contains definitions for various available Xilinx&reg;
* platforms. Also, it contains prototype of APIs, which can be used to get the
* platform information.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- --------- -------------------------------------------------------
* 6.4 ms 05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
* function for PMUFW.
* 7.2 adk 08/01/20 Added versal support for the XGetPSVersion_Info function.
* 7.6 mus 08/23/21 Updated prototypes for functions which are not taking any
* arguments with void keyword. This has been done to fix
* compilation warnings with "-Wstrict-prototypes" flag.
* It fixes CR#1108601.
* 7.6 mus 08/30/21 Updated flag checking to fix compilation warnings
* reported with "-Wundef" flag.
* 7.7 sk 01/10/22 Update XPLAT_INFO_MASK from signed to unsigned to fix
* misra_c_2012_rule_10_4 violation.
* 8.1 mus 02/13/23 Added new API's XGetCoreId and XGetClusterId. As of now
* they are supported only for VERSAL_NET APU and RPU.
* 9.0 mus 03/28/23 Added new API XGetBootStatus for VERSAL_NET. It can be
* used to identify type of boot (cold/warm).
* 9.0 mus 07/27/23 Updated XGetCoreId API to support A9, R5 and A53 processor
* 9.0 ml 09/14/23 Added U to numerical to fix MISRA-C violation for Rule
* 10.1 and 10.4
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */
#define XPLATFORM_INFO_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
/************************** Constant Definitions *****************************/
#if defined (versal)
#define XPAR_PMC_TAP_BASEADDR 0xF11A0000U
#define XPAR_PMC_TAP_VERSION_OFFSET 0x00000004U
#define XPLAT_PS_VERSION_ADDRESS (XPAR_PMC_TAP_BASEADDR + \
XPAR_PMC_TAP_VERSION_OFFSET)
#else
#define XPAR_CSU_BASEADDR 0xFFCA0000U
#define XPAR_CSU_VER_OFFSET 0x00000044U
#define XPLAT_PS_VERSION_ADDRESS (XPAR_CSU_BASEADDR + \
XPAR_CSU_VER_OFFSET)
#endif
#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
#define XPLAT_ZYNQ_ULTRA_MP 0x1
#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
#define XPLAT_ZYNQ 0x4
#define XPLAT_MICROBLAZE 0x5
#define XPLAT_VERSAL 0x6U
#define XPS_VERSION_1 0x0
#define XPS_VERSION_2 0x1
#define XPLAT_INFO_MASK (0xFU)
#if defined (versal)
#define XPS_VERSION_INFO_MASK 0xFF00U
#define XPS_VERSION_INFO_SHIFT 0x8U
#define XPLAT_INFO_SHIFT 0x18U
#else
#define XPS_VERSION_INFO_MASK 0xFU
#define XPS_VERSION_INFO_SHIFT 0x0U
#define XPLAT_INFO_SHIFT 0xCU
#endif
#if defined (VERSAL_NET)
#if defined (ARMR52)
#define XPS_NUM_OF_CORES_PER_CLUSTER 2U
#define XPS_RPU_PCIL_A0_PWRDWN 0xEB4200C0U
/*
* Offset between RPU_PCIL_X_PWRDWN registers of consecutive
* CPU cores in given cluster
*/
#define XPS_RPU_PCIL_CORE_OFFSET 0x100U
/*
* Offset between RPU_PCIL_A0_PWRDWN registers of 2 clusters
*/
#define XPS_RPU_PCIL_CLUSTER_OFFSET 0x1000U
#define XPS_RPU_PCIL_X_PWRDWN_EN_MASK 1U
#else
#define XPS_NUM_OF_CORES_PER_CLUSTER 4U
#define XPS_CORE_X_PWRDWN_BASEADDR 0xECB10000U
/*
* Offset between CORE_X_PWRDWN registers of consecutive
* CPU cores
*/
#define XPS_CORE_X_PWRDWN_OFFSET 48U
#define XPS_CORE_X_PWRDWN_EN_MASK 1U
#endif
#endif
/**************************** Type Definitions *******************************/
/**
*@endcond
*/
/***************** Macros (Inline Functions) Definitions *********************/
u32 XGetPlatform_Info(void);
#if ! defined(__microblaze__) && ! defined(__riscv)
u8 XGetCoreId(void);
#endif
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) || defined (PSU_PMU) || defined (versal)
u32 XGetPSVersion_Info(void);
#endif
#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
u32 XGet_Zynq_UltraMp_Platform_info(void);
#endif
#if (defined (__aarch64__) && defined (VERSAL_NET)) || defined (ARMR52)
u8 XGetClusterId(void);
u8 XGetCoreId(void);
u8 XGetBootStatus(void);
#endif
/************************** Function Prototypes ******************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/**
* @} End of "addtogroup common_platform_info".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_counter.h
+575
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@@ -0,0 +1,575 @@
/******************************************************************************
* Copyright (c) 2011 - 2022 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpm_counter.h
*
* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
*
* Cortex A9 event counter functions can be utilized to configure and control
* the Cortex-A9 performance monitor events.
*
* Cortex-A9 performance monitor has six event counters which can be used to
* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
* configurations XPM_CNTRCFGx which can be used to program the event counters
* to count a set of events.
*
* @note
* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
* being used for time keeping.
*
* @{
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a sdm 07/11/11 First release
* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
* 8.0 mus 07/07/22 Added prototype for new APIs as per consolidated
* xpm_counter.c.
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XPMCOUNTER_H /* prevent circular inclusions */
#define XPMCOUNTER_H /* by using protection macros */
/***************************** Include Files ********************************/
#include <stdint.h>
#include "xpseudo_asm.h"
#include "xil_types.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/************************** Constant Definitions ****************************/
/* Number of performance counters */
#define XPM_CTRCOUNT 6U
/* The following constants define the Cortex-A9 Performance Monitor Events */
/*
* Software increment. The register is incremented only on writes to the
* Software Increment Register
*/
#define XPM_EVENT_SOFTINCR 0x00U
/*
* Instruction fetch that causes a refill at (at least) the lowest level(s) of
* instruction or unified cache. Includes the speculative linefills in the
* count
*/
#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
/*
* Instruction fetch that causes a TLB refill at (at least) the lowest level of
* TLB. Includes the speculative requests in the count
*/
#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
/*
* Data read or write operation that causes a refill at (at least) the lowest
* level(s)of data or unified cache. Counts the number of allocations performed
* in the Data Cache due to a read or a write
*/
#define XPM_EVENT_DATA_CACHEREFILL 0x03U
/*
* Data read or write operation that causes a cache access at (at least) the
* lowest level(s) of data or unified cache. This includes speculative reads
*/
#define XPM_EVENT_DATA_CACHEACCESS 0x04U
/*
* Data read or write operation that causes a TLB refill at (at least) the
* lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
* CP15 Cache operation by MVA and CP15 VA to PA operations
*/
#define XPM_EVENT_DATA_TLBREFILL 0x05U
/*
* Data read architecturally executed. Counts the number of data read
* instructions accepted by the Load Store Unit. This includes counting the
* speculative and aborted LDR/LDM, as well as the reads due to the SWP
* instructions
*/
#define XPM_EVENT_DATA_READS 0x06U
/*
* Data write architecturally executed. Counts the number of data write
* instructions accepted by the Load Store Unit. This includes counting the
* speculative and aborted STR/STM, as well as the writes due to the SWP
* instructions
*/
#define XPM_EVENT_DATA_WRITE 0x07U
/* Exception taken. Counts the number of exceptions architecturally taken.*/
#define XPM_EVENT_EXCEPTION 0x09U
/* Exception return architecturally executed.*/
#define XPM_EVENT_EXCEPRETURN 0x0AU
/*
* Change to ContextID retired. Counts the number of instructions
* architecturally executed writing into the ContextID Register
*/
#define XPM_EVENT_CHANGECONTEXT 0x0BU
/*
* Software change of PC, except by an exception, architecturally executed.
* Count the number of PC changes architecturally executed, excluding the PC
* changes due to taken exceptions
*/
#define XPM_EVENT_SW_CHANGEPC 0x0CU
/*
* Immediate branch architecturally executed (taken or not taken). This includes
* the branches which are flushed due to a previous load/store which aborts
* late
*/
#define XPM_EVENT_IMMEDBRANCH 0x0DU
/*
* Unaligned access architecturally executed. Counts the number of aborted
* unaligned accessed architecturally executed, and the number of not-aborted
* unaligned accesses, including the speculative ones
*/
#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
/*
* Branch mispredicted/not predicted. Counts the number of mispredicted or
* not-predicted branches executed. This includes the branches which are flushed
* due to a previous load/store which aborts late
*/
#define XPM_EVENT_BRANCHMISS 0x10U
/*
* Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
* event is not exported on the PMUEVENT bus
*/
#define XPM_EVENT_CLOCKCYCLES 0x11U
/*
* Branches or other change in program flow that could have been predicted by
* the branch prediction resources of the processor. This includes the branches
* which are flushed due to a previous load/store which aborts late
*/
#define XPM_EVENT_BRANCHPREDICT 0x12U
/*
* Java bytecode execute. Counts the number of Java bytecodes being decoded,
* including speculative ones
*/
#define XPM_EVENT_JAVABYTECODE 0x40U
/*
* Software Java bytecode executed. Counts the number of software java bytecodes
* being decoded, including speculative ones
*/
#define XPM_EVENT_SWJAVABYTECODE 0x41U
/*
* Jazelle backward branches executed. Counts the number of Jazelle taken
* branches being executed. This includes the branches which are flushed due
* to a previous load/store which aborts late
*/
#define XPM_EVENT_JAVABACKBRANCH 0x42U
/*
* Coherent linefill miss Counts the number of coherent linefill requests
* performed by the Cortex-A9 processor which also miss in all the other
* Cortex-A9 processors, meaning that the request is sent to the external
* memory
*/
#define XPM_EVENT_COHERLINEMISS 0x50U
/*
* Coherent linefill hit. Counts the number of coherent linefill requests
* performed by the Cortex-A9 processor which hit in another Cortex-A9
* processor, meaning that the linefill data is fetched directly from the
* relevant Cortex-A9 cache
*/
#define XPM_EVENT_COHERLINEHIT 0x51U
/*
* Instruction cache dependent stall cycles. Counts the number of cycles where
* the processor is ready to accept new instructions, but does not receive any
* due to the instruction side not being able to provide any and the
* instruction cache is currently performing at least one linefill
*/
#define XPM_EVENT_INSTRSTALL 0x60U
/*
* Data cache dependent stall cycles. Counts the number of cycles where the core
* has some instructions that it cannot issue to any pipeline, and the Load
* Store unit has at least one pending linefill request, and no pending
*/
#define XPM_EVENT_DATASTALL 0x61U
/*
* Main TLB miss stall cycles. Counts the number of cycles where the processor
* is stalled waiting for the completion of translation table walks from the
* main TLB. The processor stalls can be due to the instruction side not being
* able to provide the instructions, or to the data side not being able to
* provide the necessary data, due to them waiting for the main TLB translation
* table walk to complete
*/
#define XPM_EVENT_MAINTLBSTALL 0x62U
/*
* Counts the number of STREX instructions architecturally executed and
* passed
*/
#define XPM_EVENT_STREXPASS 0x63U
/*
* Counts the number of STREX instructions architecturally executed and
* failed
*/
#define XPM_EVENT_STREXFAIL 0x64U
/*
* Data eviction. Counts the number of eviction requests due to a linefill in
* the data cache
*/
#define XPM_EVENT_DATAEVICT 0x65U
/*
* Counts the number of cycles where the issue stage does not dispatch any
* instruction because it is empty or cannot dispatch any instructions
*/
#define XPM_EVENT_NODISPATCH 0x66U
/*
* Counts the number of cycles where the issue stage is empty
*/
#define XPM_EVENT_ISSUEEMPTY 0x67U
/*
* Counts the number of instructions going through the Register Renaming stage.
* This number is an approximate number of the total number of instructions
* speculatively executed, and even more approximate of the total number of
* instructions architecturally executed. The approximation depends mainly on
* the branch misprediction rate.
* The renaming stage can handle two instructions in the same cycle so the event
* is two bits long:
* - b00 no instructions renamed
* - b01 one instruction renamed
* - b10 two instructions renamed
*/
#define XPM_EVENT_INSTRRENAME 0x68U
/*
* Counts the number of procedure returns whose condition codes do not fail,
* excluding all returns from exception. This count includes procedure returns
* which are flushed due to a previous load/store which aborts late.
* Only the following instructions are reported:
* - BX R14
* - MOV PC LR
* - POP {..,pc}
* - LDR pc,[sp],#offset
* The following instructions are not reported:
* - LDMIA R9!,{..,PC} (ThumbEE state only)
* - LDR PC,[R9],#offset (ThumbEE state only)
* - BX R0 (Rm != R14)
* - MOV PC,R0 (Rm != R14)
* - LDM SP,{...,PC} (writeback not specified)
* - LDR PC,[SP,#offset] (wrong addressing mode)
*/
#define XPM_EVENT_PREDICTFUNCRET 0x6EU
/*
* Counts the number of instructions being executed in the main execution
* pipeline of the processor, the multiply pipeline and arithmetic logic unit
* pipeline. The counted instructions are still speculative
*/
#define XPM_EVENT_MAINEXEC 0x70U
/*
* Counts the number of instructions being executed in the processor second
* execution pipeline (ALU). The counted instructions are still speculative
*/
#define XPM_EVENT_SECEXEC 0x71U
/*
* Counts the number of instructions being executed in the Load/Store unit. The
* counted instructions are still speculative
*/
#define XPM_EVENT_LDRSTR 0x72U
/*
* Counts the number of Floating-point instructions going through the Register
* Rename stage. Instructions are still speculative in this stage.
*Two floating-point instructions can be renamed in the same cycle so the event
* is two bitslong:
*0b00 no floating-point instruction renamed
*0b01 one floating-point instruction renamed
*0b10 two floating-point instructions renamed
*/
#define XPM_EVENT_FLOATRENAME 0x73U
/*
* Counts the number of Neon instructions going through the Register Rename
* stage.Instructions are still speculative in this stage.
* Two NEON instructions can be renamed in the same cycle so the event is two
* bits long:
*0b00 no NEON instruction renamed
*0b01 one NEON instruction renamed
*0b10 two NEON instructions renamed
*/
#define XPM_EVENT_NEONRENAME 0x74U
/*
* Counts the number of cycles where the processor is stalled because PLD slots
* are all full
*/
#define XPM_EVENT_PLDSTALL 0x80U
/*
* Counts the number of cycles when the processor is stalled and the data side
* is stalled too because it is full and executing writes to the external
* memory
*/
#define XPM_EVENT_WRITESTALL 0x81U
/*
* Counts the number of stall cycles due to main TLB misses on requests issued
* by the instruction side
*/
#define XPM_EVENT_INSTRTLBSTALL 0x82U
/*
* Counts the number of stall cycles due to main TLB misses on requests issued
* by the data side
*/
#define XPM_EVENT_DATATLBSTALL 0x83U
/*
* Counts the number of stall cycles due to micro TLB misses on the instruction
* side. This event does not include main TLB miss stall cycles that are already
* counted in the corresponding main TLB event
*/
#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
/*
* Counts the number of stall cycles due to micro TLB misses on the data side.
* This event does not include main TLB miss stall cycles that are already
* counted in the corresponding main TLB event
*/
#define XPM_EVENT_DATA_uTLBSTALL 0x85U
/*
* Counts the number of stall cycles because of the execution of a DMB memory
* barrier. This includes all DMB instructions being executed, even
* speculatively
*/
#define XPM_EVENT_DMB_STALL 0x86U
/*
* Counts the number of cycles during which the integer core clock is enabled
*/
#define XPM_EVENT_INT_CLKEN 0x8AU
/*
* Counts the number of cycles during which the Data Engine clock is enabled
*/
#define XPM_EVENT_DE_CLKEN 0x8BU
/*
* Counts the number of ISB instructions architecturally executed
*/
#define XPM_EVENT_INSTRISB 0x90U
/*
* Counts the number of DSB instructions architecturally executed
*/
#define XPM_EVENT_INSTRDSB 0x91U
/*
* Counts the number of DMB instructions speculatively executed
*/
#define XPM_EVENT_INSTRDMB 0x92U
/*
* Counts the number of external interrupts executed by the processor
*/
#define XPM_EVENT_EXTINT 0x93U
/*
* PLE cache line request completed
*/
#define XPM_EVENT_PLE_LRC 0xA0U
/*
* PLE cache line request skipped
*/
#define XPM_EVENT_PLE_LRS 0xA1U
/*
* PLE FIFO flush
*/
#define XPM_EVENT_PLE_FLUSH 0xA2U
/*
* PLE request complete
*/
#define XPM_EVENT_PLE_CMPL 0xA3U
/*
* PLE FIFO overflow
*/
#define XPM_EVENT_PLE_OVFL 0xA4U
/*
* PLE request programmed
*/
#define XPM_EVENT_PLE_PROG 0xA5U
/*
* The following constants define the configurations for Cortex-A9 Performance
* Monitor Events. Each configuration configures the event counters for a set
* of events.
* -----------------------------------------------
* Config PmCtr0... PmCtr5
* -----------------------------------------------
* XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR,
* XPM_EVENT_INSRFETCH_CACHEREFILL,
* XPM_EVENT_INSTRFECT_TLBREFILL,
* XPM_EVENT_DATA_CACHEREFILL,
* XPM_EVENT_DATA_CACHEACCESS,
* XPM_EVENT_DATA_TLBREFILL }
*
* XPM_CNTRCFG2 { XPM_EVENT_DATA_READS,
* XPM_EVENT_DATA_WRITE,
* XPM_EVENT_EXCEPTION,
* XPM_EVENT_EXCEPRETURN,
* XPM_EVENT_CHANGECONTEXT,
* XPM_EVENT_SW_CHANGEPC }
*
* XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH,
* XPM_EVENT_UNALIGNEDACCESS,
* XPM_EVENT_BRANCHMISS,
* XPM_EVENT_CLOCKCYCLES,
* XPM_EVENT_BRANCHPREDICT,
* XPM_EVENT_JAVABYTECODE }
*
* XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE,
* XPM_EVENT_JAVABACKBRANCH,
* XPM_EVENT_COHERLINEMISS,
* XPM_EVENT_COHERLINEHIT,
* XPM_EVENT_INSTRSTALL,
* XPM_EVENT_DATASTALL }
*
* XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL,
* XPM_EVENT_STREXPASS,
* XPM_EVENT_STREXFAIL,
* XPM_EVENT_DATAEVICT,
* XPM_EVENT_NODISPATCH,
* XPM_EVENT_ISSUEEMPTY }
*
* XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME,
* XPM_EVENT_PREDICTFUNCRET,
* XPM_EVENT_MAINEXEC,
* XPM_EVENT_SECEXEC,
* XPM_EVENT_LDRSTR,
* XPM_EVENT_FLOATRENAME }
*
* XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME,
* XPM_EVENT_PLDSTALL,
* XPM_EVENT_WRITESTALL,
* XPM_EVENT_INSTRTLBSTALL,
* XPM_EVENT_DATATLBSTALL,
* XPM_EVENT_INSTR_uTLBSTALL }
*
* XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL,
* XPM_EVENT_DMB_STALL,
* XPM_EVENT_INT_CLKEN,
* XPM_EVENT_DE_CLKEN,
* XPM_EVENT_INSTRISB,
* XPM_EVENT_INSTRDSB }
*
* XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB,
* XPM_EVENT_EXTINT,
* XPM_EVENT_PLE_LRC,
* XPM_EVENT_PLE_LRS,
* XPM_EVENT_PLE_FLUSH,
* XPM_EVENT_PLE_CMPL }
*
* XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL,
* XPM_EVENT_PLE_PROG,
* XPM_EVENT_PLE_LRC,
* XPM_EVENT_PLE_LRS,
* XPM_EVENT_PLE_FLUSH,
* XPM_EVENT_PLE_CMPL }
*
* XPM_CNTRCFG11 { XPM_EVENT_DATASTALL,
* XPM_EVENT_INSRFETCH_CACHEREFILL,
* XPM_EVENT_INSTRFECT_TLBREFILL,
* XPM_EVENT_DATA_CACHEREFILL,
* XPM_EVENT_DATA_CACHEACCESS,
* XPM_EVENT_DATA_TLBREFILL }
*/
#define XPM_CNTRCFG1 0
#define XPM_CNTRCFG2 1
#define XPM_CNTRCFG3 2
#define XPM_CNTRCFG4 3
#define XPM_CNTRCFG5 4
#define XPM_CNTRCFG6 5
#define XPM_CNTRCFG7 6
#define XPM_CNTRCFG8 7
#define XPM_CNTRCFG9 8
#define XPM_CNTRCFG10 9
#define XPM_CNTRCFG11 10
#define XPM_NO_COUNTERS_AVAILABLE 0xFFU
#define XPM_MAX_EVENTHANDLER_ID 0x6U
#define XPM_EVENT_CNTRS_BIT_MASK 0x3FU
#define XPM_ALL_EVENT_CNTRS_IN_USE 0x3FU
#define XPM_EVENT_CNTRS_MASK 0x3FU
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
#if defined(__GNUC__)
#define Xpm_ReadCycleCounterVal() mfcp(XREG_CP15_PERF_CYCLE_COUNTER)
#elif defined (__ICCARM__)
#define Xpm_ReadCycleCounterVal(val) mfcp(XREG_CP15_PERF_CYCLE_COUNTER,val)
#endif
/************************** Variable Definitions ****************************/
/**
*@endcond
*/
/************************** Function Prototypes *****************************/
/* Interface functions to access performance counters from abstraction layer */
void Xpm_SetEvents(s32 PmcrCfg);
void Xpm_GetEventCounters(u32 *PmCtrValue);
u32 Xpm_DisableEvent(u32 EventCntrId);
void Xpm_DisableEventCounters(void);
void Xpm_EnableEventCounters (void);
void Xpm_ResetEventCounters (void);
u32 Xpm_SetUpAnEvent(u32 EventID);
u32 Xpm_GetEventCounter(u32 EventCntrId, u32 *CntVal);
#ifdef __cplusplus
}
#endif
#endif
/**
* @} End of "addtogroup a9_event_counter_apis".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_init.h
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/******************************************************************************
*Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
*SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpm_init.h
* @addtogroup xpm_init xpm_init APIs
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 1.0 gm 14/06/23 Initial release.
* </pre>
******************************************************************************/
#ifndef XPM_INIT_H
#define XPM_INIT_H
/************************** Constant Definitions *****************************/
#if defined (XPM_SUPPORT)
#ifdef VERSAL_NET
#define MAX_NODE_COUNT 38
#elif defined(versal)
#define MAX_NODE_COUNT 33
#endif
/**************************** Type Definitions *******************************/
typedef struct {
UINTPTR BaseAddress;
UINTPTR NodeId;
UINTPTR ResetId;
} XpmNodeInfo;
/************************** Function Prototypes ******************************/
UINTPTR XpmGetNodeId(UINTPTR BaseAddress);
UINTPTR XpmGetResetId(UINTPTR BaseAddress);
#endif
#endif
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm.h
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/******************************************************************************
* Copyright (c) 2009 - 2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpseudo_asm.h
*
* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
*
* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
*
* The xreg_cortexa9.h file contains definitions for inline assembler code.
* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
* co-processor registers and Debug registers.
*
* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
* assembler instructions, available as macros. These can be very useful for
* tasks such as setting or getting special purpose registers, synchronization,
* or cache manipulation etc. These inline assembler instructions can be used
* from drivers and user applications written in C.
*
* @{
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.00a ecm 10/18/09 First release
* 3.04a sdm 01/02/12 Remove redundant dsb in mcr instruction.
* 6.8 aru 09/06/18 Removed compilation warnings for ARMCC toolchain.
* </pre>
*
******************************************************************************/
#ifndef XPSEUDO_ASM_H
#define XPSEUDO_ASM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "xreg_cortexa9.h"
#ifdef __GNUC__
#include "xpseudo_asm_gcc.h"
#elif defined (__ICCARM__)
#include "xpseudo_asm_iccarm.h"
#else
#include "xpseudo_asm_rvct.h"
#endif
#ifdef __cplusplus
}
#endif
#endif /* XPSEUDO_ASM_H */
/**
* @} End of "addtogroup a9_specific".
*/
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h
+285
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/******************************************************************************
* Copyright (c) 2014 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xpseudo_asm_gcc.h
*
* This header file contains macros for using inline assembler code. It is
* written specifically for the GNU compiler.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 5.00 pkp 05/21/14 First release
* 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors
* 7.2 asa 04/03/20 Renamed the str macro to strw.
* 7.2 dp 04/30/20 Added clobber "cc" to mtcpsr for aarch32 processors
* 8.0 mus 02/24/22 Added macro mfcpnotoken and mtcpnotoken.
* 8.1 asa 02/13/23 Create macros to read ESR, FAR and ELR registers.
* </pre>
*
******************************************************************************/
/**
*@cond nocomments
*/
#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */
#define XPSEUDO_ASM_GCC_H /* by using protection macros */
/***************************** Include Files ********************************/
#include "xil_types.h"
#include "bspconfig.h"
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/************************** Constant Definitions ****************************/
/**************************** Type Definitions ******************************/
/***************** Macros (Inline Functions) Definitions ********************/
/* necessary for pre-processor */
#define stringify(s) tostring(s)
#define tostring(s) #s
#if defined (__aarch64__)
/* pseudo assembler instructions */
#define mfcpsr() ({u32 rval = 0U; \
asm volatile("mrs %0, DAIF" : "=r" (rval));\
rval;\
})
#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
#define cpsiei() //__asm__ __volatile__("cpsie i\n")
#define cpsidi() //__asm__ __volatile__("cpsid i\n")
#define cpsief() //__asm__ __volatile__("cpsie f\n")
#define cpsidf() //__asm__ __volatile__("cpsid f\n")
#define mtgpr(rn, v) /*__asm__ __volatile__(\
"mov r" stringify(rn) ", %0 \n"\
: : "r" (v)\
)*/
#define mfgpr(rn) /*({u32 rval; \
__asm__ __volatile__(\
"mov %0,r" stringify(rn) "\n"\
: "=r" (rval)\
);\
rval;\
})*/
/* memory synchronization operations */
/* Instruction Synchronization Barrier */
#define isb() __asm__ __volatile__ ("isb sy")
/* Data Synchronization Barrier */
#define dsb() __asm__ __volatile__("dsb sy")
/* Data Memory Barrier */
#define dmb() __asm__ __volatile__("dmb sy")
/* Memory Operations */
#define ldr(adr) ({u64 rval; \
__asm__ __volatile__(\
"ldr %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
#if (EL3 == 1)
#define mfelrel3() ({u64 rval = 0U; \
asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\
rval;\
})
#define mfesrel3() ({u64 rval = 0U; \
asm volatile("mrs %0, ESR_EL3" : "=r" (rval));\
rval;\
})
#define mffarel3() ({u64 rval = 0U; \
asm volatile("mrs %0, FAR_EL3" : "=r" (rval));\
rval;\
})
#else
#define mfelrel1() ({u64 rval = 0U; \
asm volatile("mrs %0, ELR_EL1" : "=r" (rval));\
rval;\
})
#define mfesrel1() ({u64 rval = 0U; \
asm volatile("mrs %0, ESR_EL1" : "=r" (rval));\
rval;\
})
#define mffarel1() ({u64 rval = 0U; \
asm volatile("mrs %0, FAR_EL1" : "=r" (rval));\
rval;\
})
#endif
#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
#else
/* pseudo assembler instructions */
#define mfcpsr() ({u32 rval = 0U; \
__asm__ __volatile__(\
"mrs %0, cpsr\n"\
: "=r" (rval)\
);\
rval;\
})
#define mtcpsr(v) __asm__ __volatile__(\
"msr cpsr,%0\n"\
: : "r" (v) : "cc" \
)
#define cpsiei() __asm__ __volatile__("cpsie i\n")
#define cpsidi() __asm__ __volatile__("cpsid i\n")
#define cpsief() __asm__ __volatile__("cpsie f\n")
#define cpsidf() __asm__ __volatile__("cpsid f\n")
#define mtgpr(rn, v) __asm__ __volatile__(\
"mov r" stringify(rn) ", %0 \n"\
: : "r" (v)\
)
#define mfgpr(rn) ({u32 rval; \
__asm__ __volatile__(\
"mov %0,r" stringify(rn) "\n"\
: "=r" (rval)\
);\
rval;\
})
/* memory synchronization operations */
/* Instruction Synchronization Barrier */
#define isb() __asm__ __volatile__ ("isb" : : : "memory")
/* Data Synchronization Barrier */
#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
/* Data Memory Barrier */
#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
/* Memory Operations */
#define ldr(adr) ({u32 rval; \
__asm__ __volatile__(\
"ldr %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
#endif
#define ldrb(adr) ({u8 rval; \
__asm__ __volatile__(\
"ldrb %0,[%1]"\
: "=r" (rval) : "r" (adr)\
);\
rval;\
})
#define strw(adr, val) __asm__ __volatile__(\
"str %0,[%1]\n"\
: : "r" (val), "r" (adr)\
)
#define strb(adr, val) __asm__ __volatile__(\
"strb %0,[%1]\n"\
: : "r" (val), "r" (adr)\
)
/* Count leading zeroes (clz) */
#define clz(arg) ({u8 rval; \
__asm__ __volatile__(\
"clz %0,%1"\
: "=r" (rval) : "r" (arg)\
);\
rval;\
})
#if defined (__aarch64__)
#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val))
#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val))
#define mtcpicall(reg) __asm__ __volatile__("ic " #reg)
#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg)
#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val))
/* CP15 operations */
#define mfcp(reg) ({u64 rval = 0U;\
__asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\
rval;\
})
#define mfcpnotoken(reg) ({u64 rval = 0U;\
__asm__ __volatile__("mrs %0, " reg : "=r" (rval));\
rval;\
})
#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val))
#define mtcpnotoken(reg,val) __asm__ __volatile__("msr " reg ",%0" : : "r" (val))
#else
/* CP15 operations */
#define mtcp(rn, v) __asm__ __volatile__(\
"mcr " rn "\n"\
: : "r" (v)\
);
#define mfcp(rn) ({u32 rval = 0U; \
__asm__ __volatile__(\
"mrc " rn "\n"\
: "=r" (rval)\
);\
rval;\
})
#define mtcp2(rn, v) __asm__ __volatile__(\
"mcrr " rn "\n"\
: : "r" (v), "r" (0)\
);
#endif
/************************** Variable Definitions ****************************/
/************************** Function Prototypes *****************************/
#ifdef __cplusplus
}
#endif /* __cplusplus */
/**
*@endcond
*/
#endif /* XPSEUDO_ASM_GCC_H */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips.h
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/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspips.h
* @addtogroup qspips Overview
* @{
* @details
*
* This file contains the implementation of the XQspiPs driver. It supports only
* master mode. User documentation for the driver functions is contained in this
* file in the form of comment blocks at the front of each function.
*
* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
* between one master and one slave. The device is always full-duplex,
* which means that for every byte sent, one is received, and vice-versa.
* The master controls the clock, so it can regulate when it wants to
* send or receive data. The slave is under control of the master, it must
* respond quickly since it has no control of the clock and must send/receive
* data as fast or as slow as the master does.
*
* <b> Linear Mode </b>
* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
* functionality by adding a linear addressing scheme that allows the SPI flash
* memory subsystem to behave like a typical ROM device. The new feature hides
* the normal SPI protocol from a master reading from the SPI flash memory. The
* feature improves both the user friendliness and the overall read memory
* throughput over that of the current Quad-SPI Controller by lessening the
* amount of software overheads required and by the use of the faster AXI
* interface.
*
* <b>Initialization & Configuration</b>
*
* The XQspiPs_Config structure is used by the driver to configure itself. This
* configuration structure is typically created by the tool-chain based on HW
* build properties.
*
* To support multiple runtime loading and initialization strategies employed by
* various operating systems, the driver instance can be initialized in the
* following way:
* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
* static configuration structure defined in xqspips_g.c. This is setup
* by the tools. For some operating systems the config structure will be
* initialized by the software and this call is not needed.
* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
* configuration structure provided by the caller. If running in a system
* with address translation, the provided virtual memory base address
* replaces the physical address present in the configuration structure.
*
* <b>Multiple Masters</b>
*
* More than one master can exist, but arbitration is the responsibility of
* the higher layer software. The device driver does not perform any type of
* arbitration.
*
* <b>Modes of Operation</b>
*
* There are four modes to perform a data transfer and the selection of a mode
* is based on Chip Select(CS) and Start. These two options individually, can
* be controlled either by software(Manual) or hardware(Auto).
* - Auto CS: Chip select is automatically asserted as soon as the first word
* is written into the TXFIFO and de asserted when the TXFIFO becomes
* empty
* - Manual CS: Software must assert and de assert CS.
* - Auto Start: Data transmission starts as soon as there is data in the
* TXFIFO and stalls when the TXFIFO is empty
* - Manual Start: Software must start data transmission at the beginning of
* the transaction or whenever the TXFIFO has become empty
*
* The preferred combination is Manual CS and Auto Start.
* In this combination, the software asserts CS before loading any data into
* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
* data is available. If no further data, software disables CS.
*
* Risks/challenges of other combinations:
* - Manual CS and Manual Start: Manual Start bit should be set after each
* TXFIFO write otherwise there could be a race condition where the TXFIFO
* becomes empty before the new word is written. In that case the
* transmission stops.
* - Auto CS with Manual or Auto Start: It is very difficult for software to
* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
* This results in a single transaction to be split into multiple pieces each
* with its own chip select. This will result in garbage data to be sent.
*
* <b>Interrupts</b>
*
* The user must connect the interrupt handler of the driver,
* XQspiPs_InterruptHandler, to an interrupt system such that it will be
* called when an interrupt occurs. This function does not save and restore
* the processor context such that the user must provide this processing.
*
* The driver handles the following interrupts:
* - Data Transmit Register/FIFO Underflow
* - Data Receive Register/FIFO Not Empty
* - Data Transmit Register/FIFO Overwater
* - Data Receive Register/FIFO Overrun
*
* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
* QSPI device has transmitted the data available to transmit, and now its data
* register and FIFO is ready to accept more data. The driver uses this
* interrupt to indicate progress while sending data. The driver may have
* more data to send, in which case the data transmit register and FIFO is
* filled for subsequent transmission. When this interrupt arrives and all
* the data has been sent, the driver invokes the status callback with a
* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
* all data has been sent.
*
* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
* as slave, the QSPI device was required to transmit but there was no data
* available to transmit in the transmit register (or FIFO). This may not
* be an error if the master is not expecting data. But in the case where
* the master is expecting data, this serves as a notification of such a
* condition. The driver reports this condition to the upper layer
* software through the status handler.
*
* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
* device received data and subsequently dropped the data because the data
* receive register and FIFO was full. The driver reports this condition to the
* upper layer software through the status handler. This likely indicates a
* problem with the higher layer protocol, or a problem with the slave
* performance.
*
*
* <b>Polled Operation</b>
*
* Transfer in polled mode is supported through a separate interface function
* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
* this function blocks until all data has been sent/received.
*
* <b>Device Busy</b>
*
* Some operations are disallowed when the device is busy. The driver tracks
* whether a device is busy. The device is considered busy when a data transfer
* request is outstanding, and is considered not busy only when that transfer
* completes (or is aborted with a mode fault error).
*
* <b>Device Configuration</b>
*
* The device can be configured in various ways during the FPGA implementation
* process. Configuration parameters are stored in the xqspips_g.c file or
* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
* contains configuration information for an QSPI device, including the base
* address for the device.
*
* <b>RTOS Independence</b>
*
* This driver is intended to be RTOS and processor independent. It works with
* physical addresses only. Any needs for dynamic memory management, threads or
* thread mutual exclusion, virtual memory, or cache control must be satisfied
* by the layer above this driver.
*
* NOTE: This driver was always tested with endianness set to little-endian.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
* in xparameters.h
* 2.00a kka 07/25/12 Added a few register defines for CR 670297
* Removed code related to mode fault for CR 671468
* The XQspiPs_SetSlaveSelect has been modified to remove
* the argument of the slave select as the QSPI controller
* only supports one slave.
* XQspiPs_GetSlaveSelect API has been removed
* Added a flag ShiftReadData to the instance structure
*. and is used in the XQspiPs_GetReadData API.
* The ShiftReadData Flag indicates whether the data
* read from the Rx FIFO needs to be shifted
* in cases where the data is less than 4 bytes
* Removed the selection for the following options:
* Master mode (XQSPIPS_MASTER_OPTION) and
* Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
* as the QSPI driver supports the Master mode
* and Flash Interface mode and doesnot support
* Slave mode or the legacy mode.
* Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
* APIs so that the last argument (IsInst) specifying whether
* it is instruction or data has been removed. The first byte
* in the SendBufPtr argument of these APIs specify the
* instruction to be sent to the Flash Device.
* This version of the driver fixes CRs 670197/663787/
* 670297/671468.
* Added the option for setting the Holdb_dr bit in the
* configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
* is the option to be used for setting this bit in the
* configuration register.
* The XQspiPs_PolledTransfer function has been updated
* to fill the data to fifo depth.
* 2.01a sg 02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
* Added macros for Set/Get Rx Watermark. Changed QSPI
* Enable/Disable macro argument from BaseAddress to
* Instance Pointer. Added DelayNss argument to SetDelays
* and GetDelays API's.
* Created macros XQspiPs_IsManualStart and
* XQspiPs_IsManualChipSelect.
* Changed QSPI transfer logic for polled and interrupt
* modes to be based on filled tx fifo count and receive
* based on it. RXNEMPTY interrupt is not used.
* Added assertions to XQspiPs_LqspiRead function.
* SetDelays and GetDelays API's include DelayNss parameter.
* Added defines for DelayNss,Rx Watermark,Interrupts
* which need write to clear. Removed Read zeros mask from
* LQSPI Config register. Renamed Fixed burst error to
* data FSM error in LQSPI Status register.
*
* 2.02a hk 05/07/13 Added ConnectionMode to config structure.
* Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
* Added enable and disable to the XQspiPs_LqspiRead() function
* Removed XQspi_Reset() in Set_Options() function when
* LQSPI_MODE_OPTION is set.
* Added instructions for bank selection, die erase and
* flag status register to the flash instruction table
* Handling for instructions not in flash instruction
* table added. Checking for Tx FIFO empty when switching from
* TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
* byte count 3 (spansion), instruction size and TXD register
* changed accordingly. CR# 712502 and 703869.
* Added prefix to constant definitions for ConnectionMode
* Added (\#ifdef linear base address) in the Linear read function.
* Changed XPAR_XQSPIPS_0_LINEAR_BASEADDR to
* XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
* XQspiPs_LqspiRead function. Fix for CR#718141.
*
* 2.03a hk 09/17/13 Modified polled and interrupt transfers to make use of
* thresholds. This is to improve performance.
* Added API's for QSPI reset and
* linear mode initialization for boot.
* Added RX and TX threshold reset to one in XQspiPs_Abort.
* Added RX threshold reset(1) after transfer in polled and
* interrupt transfers. Made changes to make sure threshold
* change is done only when no transfer is in progress.
* Updated linear init API for parallel and stacked modes.
* CR#737760.
* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
* required bits leaving reserved bits untouched. CR# 796813.
* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
* controller does not update FIFO status flags as expected
* when thresholds are used.
* 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards
* to remove compilation warnings. CR# 868893.
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
* generation.
* ms 04/05/17 Modified Comment lines in functions of qspips
* examples to recognize it as documentation block
* and modified filename tag in
* xqspips_dual_flash_stack_lqspi_example.c to include it in
* doxygen examples.
* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
* 3.5 tjs 08/21/18 Fixed compilation warnings for the ARMCC.
* 3.5 tjs 07/16/18 Added support for low density ISSI flash parts.
* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
* 3.6 akm 04/15/19 Modified FlashQuadEnable, FlashWrie and FlashErase APIs,
* to wait for the on going operation to complete before
* performing the next operation.
* 3.6 akm 04/15/19 Modified the mask in XQspiPs_GetReadData() API to retrieve
* configuration register values of both the Flashes in dual
* parellel connection.
* 3.7 akm 11/19/19 Fixed Coverity unused value warning in XQspiPs_PolledTransfer()
* and XQspiPs_Transfer() APIs.
* 3.7 akm 03/19/20 Modified XQspiPs_PolledTransfer(), XQspiPs_Transfer() and
* XQspiPs_InterruptHandler() APIs to fill TX FIFO with valid
* data when RX buffer is not NULL.
* 3.8 akm 09/02/20 Updated the Makefile to support parallel make execution.
* 3.11 akm 07/10/23 Update the driver to support for system device-tree flow.
*
* </pre>
*
******************************************************************************/
#ifndef XQSPIPS_H /* prevent circular inclusions */
#define XQSPIPS_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xstatus.h"
#include "xqspips_hw.h"
#include <string.h>
/************************** Constant Definitions *****************************/
/** @name Configuration options
*
* The following options are supported to enable/disable certain features of
* an QSPI device. Each of the options is a bit mask, so more than one may be
* specified.
*
*
* The <b>Active Low Clock option</b> configures the device's clock polarity.
* Setting this option means the clock is active low and the SCK signal idles
* high. By default, the clock is active high and SCK idles low.
*
* The <b>Clock Phase option</b> configures the QSPI device for one of two
* transfer formats. A clock phase of 0, the default, means data is valid on
* the first SCK edge (rising or falling) after the slave select (SS) signal
* has been asserted. A clock phase of 1 means data is valid on the second SCK
* edge (rising or falling) after SS has been asserted.
*
*
* The <b>QSPI Force Slave Select option</b> is used to enable manual control of
* the slave select signal.
* 0: The SPI_SS signal is controlled by the QSPI controller during
* transfers. (Default)
* 1: The SPI_SS signal is forced active (driven low) regardless of any
* transfers in progress.
*
* NOTE: The driver will handle setting and clearing the Slave Select when
* the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
* QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
* processor cannot empty and refill the FIFOs before the TX FIFO is empty
* When the QSPI hardware is controlling the Slave Select signals, this
* will cause slave to be de-selected and terminate the transfer.
*
* The <b>Manual Start option</b> is used to enable manual control of
* the Start command to perform data transfer.
* 0: The Start command is controlled by the QSPI controller during
* transfers(Default). Data transmission starts as soon as there is data in
* the TXFIFO and stalls when the TXFIFO is empty
* 1: The Start command must be issued by software to perform data transfer.
* Bit 15 of Configuration register is used to issue Start command. This bit
* must be set whenever TXFIFO is filled with new data.
*
* NOTE: The driver will set the Manual Start Enable bit in Configuration
* Register, if Manual Start option is selected. Software will issue
* Manual Start command whenever TXFIFO is filled with data. When there is
* no further data, driver will clear the Manual Start Enable bit.
*
* @{
*/
#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */
#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */
#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */
#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */
#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */
#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */
/*@}*/
/** @name QSPI Clock Prescaler options
* The QSPI Clock Prescaler Configuration bits are used to program master mode
* bit rate. The bit rate can be programmed in divide-by-two decrements from
* pclk/2 to pclk/256.
*
* @{
*/
#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */
#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */
#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */
#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */
#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */
#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */
#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */
#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */
/*@}*/
/** @name Callback events
*
* These constants specify the handler events that are passed to
* a handler from the driver. These constants are not bit masks such that
* only one will be passed at a time to the handler.
*
* @{
*/
#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */
#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because
* RX FIFO full
*/
/*@}*/
/** @name Flash commands
*
* The following constants define most of the commands supported by flash
* devices. Users can add more commands supported by the flash devices
*
* @{
*/
#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */
#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */
#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */
#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */
#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */
#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */
#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */
#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */
#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */
#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */
#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */
#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */
#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */
#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */
#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */
#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */
#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/
#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */
#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */
/* Extende Address Register Write - Micron's equivalent of Bank Register */
#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5
/* Extende Address Register Read - Micron's equivalent of Bank Register */
#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8
#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4
#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70
#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50
#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock Reg Read */
#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Reg Write */
/*@}*/
/** @name Instruction size
*
* The following constants define numbers 1 to 4.
* Used to identify whether TXD0,1,2 or 3 is to be used.
*
* @{
*/
#define XQSPIPS_SIZE_ONE 1
#define XQSPIPS_SIZE_TWO 2
#define XQSPIPS_SIZE_THREE 3
#define XQSPIPS_SIZE_FOUR 4
/*@}*/
/** @name ConnectionMode
*
* The following constants are the possible values of ConnectionMode in
* Config structure.
*
* @{
*/
#define XQSPIPS_CONNECTION_MODE_SINGLE 0
#define XQSPIPS_CONNECTION_MODE_STACKED 1
#define XQSPIPS_CONNECTION_MODE_PARALLEL 2
/*@}*/
/** @name FIFO threshold value
*
* This is the Rx FIFO threshold (in words) that was found to be most
* optimal in terms of performance
*
* @{
*/
#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32
/*@}*/
/**************************** Type Definitions *******************************/
/**
* The handler data type allows the user to define a callback function to
* handle the asynchronous processing for the QSPI device. The application
* using this driver is expected to define a handler of this type to support
* interrupt driven mode. The handler executes in an interrupt context, so
* only minimal processing should be performed.
*
* @param CallBackRef is the callback reference passed in by the upper
* layer when setting the callback functions, and passed back to
* the upper layer when the callback is invoked. Its type is
* not important to the driver, so it is a void pointer.
* @param StatusEvent holds one or more status events that have occurred.
* See the XQspiPs_SetStatusHandler() for details on the status
* events that can be passed in the callback.
* @param ByteCount indicates how many bytes of data were successfully
* transferred. This may be less than the number of bytes
* requested if the status event indicates an error.
*/
typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
unsigned ByteCount);
/**
* This typedef contains configuration information for the device.
*/
typedef struct {
#ifndef SDT
u16 DeviceId; /**< Unique ID of device */
#else
char *Name;
#endif
u32 BaseAddress; /**< Base address of the device */
u32 InputClockHz; /**< Input clock frequency */
u8 ConnectionMode; /**< Single, Stacked and Parallel mode */
#ifdef SDT
u32 IntrId; /**< Bits[11:0] Interrupt-id Bits[15:12]
* trigger type and level flags */
UINTPTR IntrParent; /**< Bit[0] Interrupt parent type Bit[64/32:1]
* Parent base address */
#endif
} XQspiPs_Config;
/**
* The XQspiPs driver instance data. The user is required to allocate a
* variable of this type for every QSPI device in the system. A pointer
* to a variable of this type is then passed to the driver API functions.
*/
typedef struct {
XQspiPs_Config Config; /**< Configuration structure */
u32 IsReady; /**< Device is initialized and ready */
u8 *SendBufferPtr; /**< Buffer to send (state) */
u8 *RecvBufferPtr; /**< Buffer to receive (state) */
int RequestedBytes; /**< Number of bytes to transfer (state) */
int RemainingBytes; /**< Number of bytes left to transfer(state) */
u32 IsBusy; /**< A transfer is in progress (state) */
XQspiPs_StatusHandler StatusHandler;
void *StatusRef; /**< Callback reference for status handler */
u32 ShiftReadData; /**< Flag to indicate whether the data
* read from the Rx FIFO needs to be shifted
* in cases where the data is less than 4
* bytes
*/
} XQspiPs;
/***************** Macros (Inline Functions) Definitions *********************/
/****************************************************************************/
/*
*
* Check in OptionsTable if Manual Start Option is enabled or disabled.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return
* - TRUE if option is set
* - FALSE if option is not set
*
* @note C-Style signature:
* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
*
*****************************************************************************/
#define XQspiPs_IsManualStart(InstancePtr) \
((XQspiPs_GetOptions(InstancePtr) & \
XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
/****************************************************************************/
/*
*
* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
*
* @param InstancePtr is a pointer to the XSpiPs instance.
*
* @return
* - TRUE if option is set
* - FALSE if option is not set
*
* @note C-Style signature:
* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
*
*****************************************************************************/
#define XQspiPs_IsManualChipSelect(InstancePtr) \
((XQspiPs_GetOptions(InstancePtr) & \
XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
/****************************************************************************/
/**
*
* Set the contents of the slave idle count register.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
* @param RegisterValue is the value to be written, valid values are
* 0-255.
*
* @return None
*
* @note C-Style signature:
* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr,
* u32 RegisterValue)
*
*****************************************************************************/
#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_SICR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
*
* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
* constants defined in xqspips_hw.h to interpret the bit-mask returned.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return An 8-bit value representing Slave Idle Count.
*
* @note C-Style signature:
* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
*
*****************************************************************************/
#define XQspiPs_GetSlaveIdle(InstancePtr) \
XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_SICR_OFFSET)
/****************************************************************************/
/**
*
* Set the contents of the transmit FIFO watermark register.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
* @param RegisterValue is the value to be written, valid values are 1-63.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr,
* u32 RegisterValue)
*
*****************************************************************************/
#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_TXWR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
*
* Get the contents of the transmit FIFO watermark register.
* Valid values are in the range 1-63.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return A 6-bit value representing Tx Watermark level.
*
* @note C-Style signature:
* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
*
*****************************************************************************/
#define XQspiPs_GetTXWatermark(InstancePtr) \
XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
/****************************************************************************/
/**
*
* Set the contents of the receive FIFO watermark register.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
* @param RegisterValue is the value to be written, valid values are 1-63.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr,
* u32 RegisterValue)
*
*****************************************************************************/
#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_RXWR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
*
* Get the contents of the receive FIFO watermark register.
* Valid values are in the range 1-63.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return A 6-bit value representing Rx Watermark level.
*
* @note C-Style signature:
* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
*
*****************************************************************************/
#define XQspiPs_GetRXWatermark(InstancePtr) \
XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
/****************************************************************************/
/**
*
* Enable the device and uninhibit master transactions.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPs_Enable(XQspiPs *InstancePtr)
*
*****************************************************************************/
#define XQspiPs_Enable(InstancePtr) \
XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
XQSPIPS_ER_ENABLE_MASK)
/****************************************************************************/
/**
*
* Disable the device.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPs_Disable(XQspiPs *InstancePtr)
*
*****************************************************************************/
#define XQspiPs_Disable(InstancePtr) \
XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
/****************************************************************************/
/**
*
* Set the contents of the Linear QSPI Configuration register.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
* @param RegisterValue is the value to be written to the Linear QSPI
* configuration register.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
* u32 RegisterValue)
*
*****************************************************************************/
#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \
XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
/****************************************************************************/
/**
*
* Get the contents of the Linear QSPI Configuration register.
*
* @param InstancePtr is a pointer to the XQspiPs instance.
*
* @return A 32-bit value representing the contents of the LQSPI Config
* register.
*
* @note C-Style signature:
* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
*
*****************************************************************************/
#define XQspiPs_GetLqspiConfigReg(InstancePtr) \
XQspiPs_In32((InstancePtr->Config.BaseAddress) + \
XQSPIPS_LQSPI_CR_OFFSET)
/************************** Function Prototypes ******************************/
/*
* Initialization function, implemented in xqspips_sinit.c
*/
#ifndef SDT
XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
#else
XQspiPs_Config *XQspiPs_LookupConfig(UINTPTR BaseAddress);
#endif
/*
* Functions implemented in xqspips.c
*/
int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *Config,
u32 EffectiveAddr);
void XQspiPs_Reset(XQspiPs *InstancePtr);
void XQspiPs_Abort(XQspiPs *InstancePtr);
s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
u32 ByteCount);
s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
u8 *RecvBufPtr, u32 ByteCount);
int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
u32 Address, unsigned ByteCount);
int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
XQspiPs_StatusHandler FuncPtr);
void XQspiPs_InterruptHandler(void *InstancePtr);
/*
* Functions for selftest, in xqspips_selftest.c
*/
int XQspiPs_SelfTest(XQspiPs *InstancePtr);
/*
* Functions for options, in xqspips_options.c
*/
s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
u8 DelayAfter, u8 DelayInit);
void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
u8 *DelayAfter, u8 *DelayInit);
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips_hw.h
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@@ -0,0 +1,400 @@
/******************************************************************************
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xqspips_hw.h
* @addtogroup qspips Overview
* @{
*
* This header file contains the identifiers and basic HW access driver
* functions (or macros) that can be used to access the device. Other driver
* functions are defined in xqspips.h.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- --- -------- -----------------------------------------------
* 1.00 sdm 11/25/10 First release
* 2.00a ka 07/25/12 Added a few register defines for CR 670297
* and removed some defines of reserved fields for
* CR 671468
* Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
* bit in Configuration register.
* 2.01a sg 02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
* which need write to clear. Removed Read zeros mask from
* LQSPI Config register.
* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
* linear mode initialization for boot. Added related
* constant definitions.
* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
* required bits leaving reserved bits untouched. CR# 796813.
* 3.2 sk 02/05/15 Add SLCR reset in abort function as a workaround because
* controller does not update FIFO status flags as expected
* when thresholds are used.
* 3.6 akm 03/28/19 Fixed memory leak issue while reading from qspi.(CR#1016357)
*
* </pre>
*
******************************************************************************/
#ifndef XQSPIPS_HW_H /* prevent circular inclusions */
#define XQSPIPS_HW_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
/***************************** Include Files *********************************/
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#include "xparameters.h"
/************************** Constant Definitions *****************************/
/** @name Register Map
*
* Register offsets from the base address of an QSPI device.
* @{
*/
#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */
#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */
#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */
#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */
#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */
#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */
#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */
#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */
#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */
#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */
#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */
#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */
#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */
#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */
#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */
#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */
#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */
#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */
#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */
#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */
/* @} */
/** @name Configuration Register
*
* This register contains various control bits that
* affect the operation of the QSPI device. Read/Write.
* @{
*/
#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */
#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */
#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */
#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
Enable */
#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */
#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */
#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */
#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be
transferred */
#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */
#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */
#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */
#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */
#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */
#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */
#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */
#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
/* Deselect the Slave select line and set the transfer size to 32 at reset */
#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
XQSPIPS_CR_SSCTRL_MASK | \
XQSPIPS_CR_DATA_SZ_MASK | \
XQSPIPS_CR_MSTREN_MASK | \
XQSPIPS_CR_SSFORCE_MASK | \
XQSPIPS_CR_HOLD_B_MASK
#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
XQSPIPS_CR_CPHA_MASK | \
XQSPIPS_CR_PRESC_MASK | \
XQSPIPS_CR_MANSTRTEN_MASK | \
XQSPIPS_CR_MANSTRT_MASK | \
XQSPIPS_CR_ENDIAN_MASK | \
XQSPIPS_CR_REF_CLK_MASK
/* @} */
/** @name QSPI Interrupt Registers
*
* <b>QSPI Status Register</b>
*
* This register holds the interrupt status flags for an QSPI device. Some
* of the flags are level triggered, which means that they are set as long
* as the interrupt condition exists. Other flags are edge triggered,
* which means they are set once the interrupt condition occurs and remain
* set until they are cleared by software. The interrupts are cleared by
* writing a '1' to the interrupt bit position in the Status Register.
* Read/Write.
*
* <b>QSPI Interrupt Enable Register</b>
*
* This register is used to enable chosen interrupts for an QSPI device.
* Writing a '1' to a bit in this register sets the corresponding bit in the
* QSPI Interrupt Mask register. Write only.
*
* <b>QSPI Interrupt Disable Register </b>
*
* This register is used to disable chosen interrupts for an QSPI device.
* Writing a '1' to a bit in this register clears the corresponding bit in the
* QSPI Interrupt Mask register. Write only.
*
* <b>QSPI Interrupt Mask Register</b>
*
* This register shows the enabled/disabled interrupts of an QSPI device.
* Read only.
*
* All four registers have the same bit definitions. They are only defined once
* for each of the Interrupt Enable Register, Interrupt Disable Register,
* Interrupt Mask Register, and Channel Interrupt Status Register
* @{
*/
#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */
#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */
#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */
#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */
#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */
#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */
#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts
mask */
#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which
need write to clear */
#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */
#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */
/* @} */
/** @name Enable Register
*
* This register is used to enable or disable an QSPI device.
* Read/Write
* @{
*/
#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */
/* @} */
/** @name Delay Register
*
* This register is used to program timing delays in
* slave mode. Read/Write
* @{
*/
#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select
between two words mask */
#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select
between two words shift */
#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers
mask */
#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */
#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */
#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */
#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */
/* @} */
/** @name Slave Idle Count Registers
*
* This register defines the number of pclk cycles the slave waits for a the
* QSPI clock to become stable in quiescent state before it can detect the start
* of the next transfer in CPHA = 1 mode.
* Read/Write
*
* @{
*/
#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */
/* @} */
/** @name Transmit FIFO Watermark Register
*
* This register defines the watermark setting for the Transmit FIFO.
*
* @{
*/
#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */
#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark
* register reset value */
/* @} */
/** @name Receive FIFO Watermark Register
*
* This register defines the watermark setting for the Receive FIFO.
*
* @{
*/
#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */
#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark
* register reset value */
/* @} */
/** @name FIFO Depth
*
* This macro provides the depth of transmit FIFO and receive FIFO.
*
* @{
*/
#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */
/* @} */
/** @name Linear QSPI Configuration Register
*
* This register contains various control bits that
* affect the operation of the Linear QSPI controller. Read/Write.
*
* @{
*/
#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */
#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */
#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Separate memory bus */
#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */
#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */
#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */
#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O
or quad I/O */
#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes
between addr and return
read data */
#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */
#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */
/* @} */
/** @name Linear QSPI Status Register
*
* This register contains various status bits of the Linear QSPI controller.
* Read/Write.
*
* @{
*/
#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error
received */
#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command
received */
/* @} */
/** @name Loopback Delay Adjust Register
*
* This register contains various bit masks of Loopback Delay Adjust Register.
*
* @{
*/
#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
/* @} */
/** @name SLCR Register
*
* Register offsets from SLCR base address.
*
* @{
*/
#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
/* @} */
/** @name SLCR Register
*
* Bit Masks of above SLCR Registers .
*
* @{
*/
#ifndef XPAR_XSLCR_0_BASEADDR
#define XPAR_XSLCR_0_BASEADDR 0xF8000000
#endif
#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
/* @} */
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
#define XQspiPs_In32 Xil_In32
#define XQspiPs_Out32 Xil_Out32
#define XQSPIPS_DUMMY_TX_DATA 0xFFFFFFFF
/****************************************************************************/
/**
* Read a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to the target register.
*
* @return The value read from the register.
*
* @note C-Style signature:
* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
*
******************************************************************************/
#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
XQspiPs_In32((BaseAddress) + (RegOffset))
/***************************************************************************/
/**
* Write to a register.
*
* @param BaseAddress contains the base address of the device.
* @param RegOffset contains the offset from the 1st register of the
* device to target register.
* @param RegisterValue is the value to be written to the register.
*
* @return None.
*
* @note C-Style signature:
* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
* u32 RegisterValue)
*
******************************************************************************/
#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
/************************** Function Prototypes ******************************/
/*
* Functions implemented in xqspips_hw.c
*/
void XQspiPs_ResetHw(u32 BaseAddress);
void XQspiPs_LinearInit(u32 BaseAddress);
/************************** Variable Definitions *****************************/
#ifdef __cplusplus
}
#endif
#endif /* end of protection macro */
/** @} */
Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h
+578
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@@ -0,0 +1,578 @@
/******************************************************************************
* Copyright (c) 2009 - 2021 Xilinx, Inc. All rights reserved.
* Copyright (c) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/*****************************************************************************/
/**
*
* @file xreg_cortexa9.h
*
* This header file contains definitions for using inline assembler code. It is
* written specifically for the GNU, ARMCC compiler.
*
* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
* with the positions of the bits within the registers.
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- -------- -------- -----------------------------------------------
* 1.00a ecm/sdm 10/20/09 First release
* 9.0 mus 07/29/23 Added definitions for processor affinity register.
* </pre>
*
******************************************************************************/
#ifndef XREG_CORTEXA9_H
#define XREG_CORTEXA9_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/**
*@cond nocomments
*/
/* GPRs */
#define XREG_GPR0 r0
#define XREG_GPR1 r1
#define XREG_GPR2 r2
#define XREG_GPR3 r3
#define XREG_GPR4 r4
#define XREG_GPR5 r5
#define XREG_GPR6 r6
#define XREG_GPR7 r7
#define XREG_GPR8 r8
#define XREG_GPR9 r9
#define XREG_GPR10 r10
#define XREG_GPR11 r11
#define XREG_GPR12 r12
#define XREG_GPR13 r13
#define XREG_GPR14 r14
#define XREG_GPR15 r15
#define XREG_CPSR cpsr
/* Coprocessor number defines */
#define XREG_CP0 0
#define XREG_CP1 1
#define XREG_CP2 2
#define XREG_CP3 3
#define XREG_CP4 4
#define XREG_CP5 5
#define XREG_CP6 6
#define XREG_CP7 7
#define XREG_CP8 8
#define XREG_CP9 9
#define XREG_CP10 10
#define XREG_CP11 11
#define XREG_CP12 12
#define XREG_CP13 13
#define XREG_CP14 14
#define XREG_CP15 15
/* Coprocessor control register defines */
#define XREG_CR0 cr0
#define XREG_CR1 cr1
#define XREG_CR2 cr2
#define XREG_CR3 cr3
#define XREG_CR4 cr4
#define XREG_CR5 cr5
#define XREG_CR6 cr6
#define XREG_CR7 cr7
#define XREG_CR8 cr8
#define XREG_CR9 cr9
#define XREG_CR10 cr10
#define XREG_CR11 cr11
#define XREG_CR12 cr12
#define XREG_CR13 cr13
#define XREG_CR14 cr14
#define XREG_CR15 cr15
/* Current Processor Status Register (CPSR) Bits */
#define XREG_CPSR_THUMB_MODE 0x20
#define XREG_CPSR_MODE_BITS 0x1F
#define XREG_CPSR_SYSTEM_MODE 0x1F
#define XREG_CPSR_UNDEFINED_MODE 0x1B
#define XREG_CPSR_DATA_ABORT_MODE 0x17
#define XREG_CPSR_SVC_MODE 0x13
#define XREG_CPSR_IRQ_MODE 0x12
#define XREG_CPSR_FIQ_MODE 0x11
#define XREG_CPSR_USER_MODE 0x10
#define XREG_CPSR_IRQ_ENABLE 0x80
#define XREG_CPSR_FIQ_ENABLE 0x40
#define XREG_CPSR_N_BIT 0x80000000
#define XREG_CPSR_Z_BIT 0x40000000
#define XREG_CPSR_C_BIT 0x20000000
#define XREG_CPSR_V_BIT 0x10000000
/* CP15 defines */
#if defined (__GNUC__) || defined (__ICCARM__)
/* C0 Register defines */
#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0"
#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1"
#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2"
#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3"
#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5"
#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0"
#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1"
#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2"
#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4"
#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5"
#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6"
#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7"
#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0"
#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1"
#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2"
#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3"
#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4"
#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0"
#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1"
#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7"
#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0"
/* C1 Register Defines */
#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0"
#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1"
#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2"
#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0"
#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1"
#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2"
#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3"
#else /* RVCT */
/* C0 Register defines */
#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0"
#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1"
#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2"
#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3"
#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5"
#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0"
#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1"
#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2"
#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4"
#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5"
#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6"
#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7"
#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0"
#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1"
#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2"
#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3"
#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4"
#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0"
#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1"
#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7"
#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0"
/* C1 Register Defines */
#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0"
#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1"
#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2"
#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0"
#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1"
#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2"
#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3"
#endif
/* XREG_CP15_CONTROL bit defines */
#define XREG_CP15_CONTROL_TE_BIT 0x40000000U
#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U
#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U
#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U
#define XREG_CP15_CONTROL_EE_BIT 0x02000000U
#define XREG_CP15_CONTROL_HA_BIT 0x00020000U
#define XREG_CP15_CONTROL_RR_BIT 0x00004000U
#define XREG_CP15_CONTROL_V_BIT 0x00002000U
#define XREG_CP15_CONTROL_I_BIT 0x00001000U
#define XREG_CP15_CONTROL_Z_BIT 0x00000800U
#define XREG_CP15_CONTROL_SW_BIT 0x00000400U
#define XREG_CP15_CONTROL_B_BIT 0x00000080U
#define XREG_CP15_CONTROL_C_BIT 0x00000004U
#define XREG_CP15_CONTROL_A_BIT 0x00000002U
#define XREG_CP15_CONTROL_M_BIT 0x00000001U
#if defined (__GNUC__) || defined (__ICCARM__)
/* C2 Register Defines */
#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0"
#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1"
#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2"
/* C3 Register Defines */
#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0"
/* C4 Register Defines */
/* Not Used */
/* C5 Register Defines */
#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0"
#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1"
#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0"
#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1"
/* C6 Register Defines */
#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0"
#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2"
/* C7 Register Defines */
#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4"
#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0"
#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6"
#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0"
#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0"
#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1"
/* The CP15 register access below has been deprecated in favor of the new
* isb instruction in Cortex A9.
*/
#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4"
#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6"
#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1"
#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2"
#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0"
#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1"
#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2"
#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3"
#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4"
#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5"
#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6"
#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1"
#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2"
/* The next two CP15 register accesses below have been deprecated in favor
* of the new dsb and dmb instructions in Cortex A9.
*/
#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4"
#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1"
#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2"
/* C8 Register Defines */
#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0"
#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1"
#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2"
#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3"
#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0"
#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1"
#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2"
#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0"
#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1"
#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2"
#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0"
#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1"
#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2"
#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3"
/* C9 Register Defines */
#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0"
#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1"
#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2"
#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3"
#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4"
#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5"
#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0"
#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1"
#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2"
#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0"
#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1"
#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2"
/* C10 Register Defines */
#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0"
#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0"
#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1"
/* C11 Register Defines */
/* Not used */
/* C12 Register Defines */
#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0"
#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1"
#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0"
#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1"
/* C13 Register Defines */
#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1"
#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2"
#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3"
#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4"
/* C14 Register Defines */
/* not used */
/* C15 Register Defines */
#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0"
#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0"
#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2"
#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4"
#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2"
#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2"
#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2"
#else
/* C2 Register Defines */
#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0"
#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1"
#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2"
/* C3 Register Defines */
#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0"
/* C4 Register Defines */
/* Not Used */
/* C5 Register Defines */
#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0"
#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1"
#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0"
#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1"
/* C6 Register Defines */
#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0"
#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2"
/* C7 Register Defines */
#define XREG_CP15_NOP "cp15:0:c7:c0:4"
#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0"
#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6"
#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0"
#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0"
#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1"
/* The CP15 register access below has been deprecated in favor of the new
* isb instruction in Cortex A9.
*/
#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4"
#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6"
#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1"
#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2"
#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0"
#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1"
#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2"
#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3"
#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4"
#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5"
#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6"
#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1"
#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2"
/* The next two CP15 register accesses below have been deprecated in favor
* of the new dsb and dmb instructions in Cortex A9.
*/
#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4"
#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5"
#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1"
#define XREG_CP15_NOP2 "cp15:0:c7:c13:1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1"
#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2"
/* C8 Register Defines */
#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0"
#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1"
#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2"
#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3"
#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0"
#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1"
#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2"
#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0"
#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1"
#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2"
#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0"
#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1"
#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2"
#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3"
/* C9 Register Defines */
#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0"
#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1"
#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2"
#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3"
#define XREG_CP15_SW_INC "cp15:0:c9:c12:4"
#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5"
#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0"
#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1"
#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2"
#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0"
#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1"
#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2"
/* C10 Register Defines */
#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0"
#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0"
#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1"
/* C11 Register Defines */
/* Not used */
/* C12 Register Defines */
#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0"
#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1"
#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0"
#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1"
/* C13 Register Defines */
#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1"
#define USER_RW_THREAD_PID "cp15:0:c13:c0:2"
#define USER_RO_THREAD_PID "cp15:0:c13:c0:3"
#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4"
/* C14 Register Defines */
/* not used */
/* C15 Register Defines */
#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0"
#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0"
#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2"
#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4"
#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2"
#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2"
#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2"
#endif
/* Affinity register bits */
#define XREG_MPIDR_MASK 0xFFFFFFFFU
#define XREG_MPIDR_AFFINITY0_MASK 0x3U
#define XREG_MPIDR_AFFINITY0_SHIFT 0x0U
/* MPE register definitions */
#define XREG_FPSID c0
#define XREG_FPSCR c1
#define XREG_MVFR1 c6
#define XREG_MVFR0 c7
#define XREG_FPEXC c8
#define XREG_FPINST c9
#define XREG_FPINST2 c10
/* FPSID bits */
#define XREG_FPSID_IMPLEMENTER_BIT (24)
#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT)
#define XREG_FPSID_SOFTWARE (1<<23)
#define XREG_FPSID_ARCH_BIT (16)
#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
#define XREG_FPSID_PART_BIT (8)
#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
#define XREG_FPSID_VARIANT_BIT (4)
#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
#define XREG_FPSID_REV_BIT (0)
#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT)
/* FPSCR bits */
#define XREG_FPSCR_N_BIT (1 << 31)
#define XREG_FPSCR_Z_BIT (1 << 30)
#define XREG_FPSCR_C_BIT (1 << 29)
#define XREG_FPSCR_V_BIT (1 << 28)
#define XREG_FPSCR_QC (1 << 27)
#define XREG_FPSCR_AHP (1 << 26)
#define XREG_FPSCR_DEFAULT_NAN (1 << 25)
#define XREG_FPSCR_FLUSHTOZERO (1 << 24)
#define XREG_FPSCR_ROUND_NEAREST (0 << 22)
#define XREG_FPSCR_ROUND_PLUSINF (1 << 22)
#define XREG_FPSCR_ROUND_MINUSINF (2 << 22)
#define XREG_FPSCR_ROUND_TOZERO (3 << 22)
#define XREG_FPSCR_RMODE_BIT (22)
#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
#define XREG_FPSCR_STRIDE_BIT (20)
#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
#define XREG_FPSCR_LENGTH_BIT (16)
#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
#define XREG_FPSCR_IDC (1 << 7)
#define XREG_FPSCR_IXC (1 << 4)
#define XREG_FPSCR_UFC (1 << 3)
#define XREG_FPSCR_OFC (1 << 2)
#define XREG_FPSCR_DZC (1 << 1)
#define XREG_FPSCR_IOC (1 << 0)
/* MVFR0 bits */
#define XREG_MVFR0_RMODE_BIT (28)
#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT)
#define XREG_MVFR0_SHORT_VEC_BIT (24)
#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT)
#define XREG_MVFR0_SQRT_BIT (20)
#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT)
#define XREG_MVFR0_DIVIDE_BIT (16)
#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT)
#define XREG_MVFR0_EXEC_TRAP_BIT (12)
#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT)
#define XREG_MVFR0_DP_BIT (8)
#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT)
#define XREG_MVFR0_SP_BIT (4)
#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT)
#define XREG_MVFR0_A_SIMD_BIT (0)
#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT)
/* FPEXC bits */
#define XREG_FPEXC_EX (1 << 31)
#define XREG_FPEXC_EN (1 << 30)
#define XREG_FPEXC_DEX (1 << 29)
/**
*@endcond
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* XREG_CORTEXA9_H */

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