Init Commit
This commit is contained in:
Jeremy Shen
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<?xml version="1.0" encoding="UTF-8"?>
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<section name="Workbench">
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<item value="system_wrapper_hw_platform_0" key="applicationwizard.hw_platform_key"/>
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</section>
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<?xml version="1.0" encoding="UTF-8"?>
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<section name="Workbench">
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<item value="system_wrapper_hw_platform_0" key="programflash.hwplatform"/>
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<item value="Local" key="system_wrapper_hw_platform_0-target"/>
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<item value="G:\CALBOARD\z035_mars1k\debug_bin\bin_8.1\BOOT.bin" key="system_wrapper_hw_platform_0-imgFile"/>
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<item value="G:\CALBOARD\z035_mars1k\debug_bin\bin_8.1\FSBL.elf" key="system_wrapper_hw_platform_0-fsblFile"/>
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<item value="false" key="system_wrapper_hw_platform_0-verifyFlash"/>
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<item value="false" key="system_wrapper_hw_platform_0-blankCheck"/>
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<item value="" key="system_wrapper_hw_platform_0-offSet"/>
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<item value="qspi-x4-single" key="system_wrapper_hw_platform_0-flashType"/>
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<item value="Auto Detect" key="system_wrapper_hw_platform_0-device"/>
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</section>
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<section name="Workbench">
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<item value="E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.14.2" key="bootgen_files_selection"/>
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<item value="G:\CALBOARD\z035_mars1k\debug_bin\bin_8.1" key="zynq_flash_files_selection"/>
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<item value="E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.14.2" key="last_stored_selection"/>
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</section>
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*** SESSION 7月 20, 2023 10:59:21.88 --------------------------------------------
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*** SESSION 11月 13, 2025 13:57:56.63 -------------------------------------------
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*** SESSION 1月 12, 2026 17:48:47.43 --------------------------------------------
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*** SESSION 1月 14, 2026 14:37:51.43 --------------------------------------------
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15:10:04 **** Build of configuration Debug for project FSBL ****
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make pre-build main-build
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a9-linaro-pre-build-step
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' '
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'Building file: ../src/fsbl_hooks.c'
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'Invoking: ARM v7 gcc compiler'
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arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/fsbl_hooks.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/fsbl_hooks.d" -MT"src/fsbl_hooks.o" -o "src/fsbl_hooks.o" "../src/fsbl_hooks.c"
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'Finished building: ../src/fsbl_hooks.c'
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' '
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'Building file: ../src/image_mover.c'
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'Invoking: ARM v7 gcc compiler'
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arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/image_mover.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/image_mover.d" -MT"src/image_mover.o" -o "src/image_mover.o" "../src/image_mover.c"
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'Finished building: ../src/image_mover.c'
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' '
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'Building file: ../src/main.c'
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'Invoking: ARM v7 gcc compiler'
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arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/main.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/main.c"
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In file included from ../src/main.c:137:0:
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../../FSBL_bsp/ps7_cortexa9_0/include/xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
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#pragma message ("For the sleep routines, Global timer is being used")
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^~~~~~~
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'Finished building: ../src/main.c'
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' '
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'Building file: ../src/md5.c'
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'Invoking: ARM v7 gcc compiler'
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arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/md5.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/md5.d" -MT"src/md5.o" -o "src/md5.o" "../src/md5.c"
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'Finished building: ../src/md5.c'
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' '
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'Building file: ../src/nand.c'
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'Invoking: ARM v7 gcc compiler'
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||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/nand.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/nand.d" -MT"src/nand.o" -o "src/nand.o" "../src/nand.c"
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'Finished building: ../src/nand.c'
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' '
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'Building file: ../src/nor.c'
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'Invoking: ARM v7 gcc compiler'
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||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/nor.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/nor.d" -MT"src/nor.o" -o "src/nor.o" "../src/nor.c"
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'Finished building: ../src/nor.c'
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' '
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'Building file: ../src/pcap.c'
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'Invoking: ARM v7 gcc compiler'
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||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/pcap.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/pcap.d" -MT"src/pcap.o" -o "src/pcap.o" "../src/pcap.c"
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In file included from ../src/pcap.c:100:0:
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../../FSBL_bsp/ps7_cortexa9_0/include/xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
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#pragma message ("For the sleep routines, Global timer is being used")
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^~~~~~~
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'Finished building: ../src/pcap.c'
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' '
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||||
'Building file: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c'
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||||
'Invoking: ARM v7 gcc compiler'
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||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/ps7_init.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/ps7_init.d" -MT"src/ps7_init.o" -o "src/ps7_init.o" "E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c"
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||||
'Finished building: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c'
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||||
' '
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||||
'Building file: ../src/qspi.c'
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||||
'Invoking: ARM v7 gcc compiler'
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||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/qspi.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/qspi.d" -MT"src/qspi.o" -o "src/qspi.o" "../src/qspi.c"
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||||
'Finished building: ../src/qspi.c'
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||||
' '
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||||
'Building file: ../src/sd.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/sd.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/sd.d" -MT"src/sd.o" -o "src/sd.o" "../src/sd.c"
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||||
'Finished building: ../src/sd.c'
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||||
' '
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||||
'Building target: FSBL.elf'
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||||
'Invoking: ARM v7 gcc linker'
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arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../FSBL_bsp/ps7_cortexa9_0/lib -o "FSBL.elf" ./src/fsbl_handoff.o ./src/fsbl_hooks.o ./src/image_mover.o ./src/main.o ./src/md5.o ./src/nand.o ./src/nor.o ./src/pcap.o ./src/ps7_init.o ./src/qspi.o ./src/rsa.o ./src/sd.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group
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||||
'Finished building target: FSBL.elf'
|
||||
' '
|
||||
'Invoking: ARM v7 Print Size'
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arm-none-eabi-size FSBL.elf |tee "FSBL.elf.size"
|
||||
text data bss dec hex filename
|
||||
81496 10160 74712 166368 289e0 FSBL.elf
|
||||
'Finished building: FSBL.elf.size'
|
||||
' '
|
||||
|
||||
15:10:09 Build Finished (took 4s.365ms)
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|
||||
@@ -0,0 +1,106 @@
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15:09:36 **** Build of project FSBL_bsp ****
|
||||
make -k all
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
|
||||
make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
|
||||
make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/xilffs_v4_0/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xilffs_v4_0/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xilrsa_v1_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling coresightps_dcc"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling cpu_cortexa9"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
|
||||
make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling ddrps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling devcfg"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling dmaps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling emacps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling gpiops"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling qspips"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling scugic"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling scutimer"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling scuwdt"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
|
||||
make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling sdps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling standalone"
|
||||
In file included from usleep.c:56:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
In file included from sleep.c:53:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
In file included from xil_sleeptimer.c:51:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
In file included from xtime_l.c:49:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling uartps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling xadcps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/xilffs_v4_0/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xilffs_v4_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling XilFFs Library"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/xilrsa_v1_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xilrsa_v1_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
'Finished building libraries'
|
||||
|
||||
15:10:04 Build Finished (took 27s.930ms)
|
||||
|
||||
@@ -0,0 +1,36 @@
|
||||
10:56:55 **** Auto Build of configuration Debug for project calboard ****
|
||||
make pre-build main-build
|
||||
a9-linaro-pre-build-step
|
||||
' '
|
||||
'Building file: ../src/cal_meas.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/cal_meas.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/cal_meas.d" -MT"src/cal_meas.o" -o "src/cal_meas.o" "../src/cal_meas.c"
|
||||
../src/cal_meas.c: In function 'sw_config':
|
||||
../src/cal_meas.c:20:10: warning: unused variable 'memt_areal' [-Wunused-variable]
|
||||
char memt_areal = *(slot_start+6);
|
||||
^~~~~~~~~~
|
||||
../src/cal_meas.c:19:10: warning: unused variable 'load' [-Wunused-variable]
|
||||
char load = *(slot_start+5);
|
||||
^~~~
|
||||
../src/cal_meas.c:18:10: warning: unused variable 'volt_cur' [-Wunused-variable]
|
||||
char volt_cur = *(slot_start+4);
|
||||
^~~~~~~~
|
||||
../src/cal_meas.c:15:10: warning: unused variable 'm_fun' [-Wunused-variable]
|
||||
char m_fun = *(slot_start+1);
|
||||
^~~~~
|
||||
'Finished building: ../src/cal_meas.c'
|
||||
' '
|
||||
'Building target: calboard.elf'
|
||||
'Invoking: ARM v7 gcc linker'
|
||||
arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../calboard_bsp/ps7_cortexa9_0/lib -o "calboard.elf" ./src/GPIO_Driv.o ./src/SPI_Driv.o ./src/cal_meas.o ./src/crc16.o ./src/dna_read.o ./src/echo.o ./src/i2c_access.o ./src/iic_phyreset.o ./src/main.o ./src/platform.o ./src/platform_mb.o ./src/platform_ppc.o ./src/platform_zynq.o ./src/platform_zynqmp.o ./src/sfp.o ./src/si5324.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group
|
||||
'Finished building target: calboard.elf'
|
||||
' '
|
||||
'Invoking: ARM v7 Print Size'
|
||||
arm-none-eabi-size calboard.elf |tee "calboard.elf.size"
|
||||
text data bss dec hex filename
|
||||
132680 3184 5363760 5499624 53eae8 calboard.elf
|
||||
'Finished building: calboard.elf.size'
|
||||
' '
|
||||
|
||||
10:56:56 Build Finished (took 1s.11ms)
|
||||
|
||||
@@ -0,0 +1,102 @@
|
||||
15:10:09 **** Build of project calboard_bsp ****
|
||||
make -k all
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
|
||||
make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/lwip211_v1_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/lwip211_v1_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
|
||||
make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling coresightps_dcc"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling cpu_cortexa9"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
|
||||
make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling ddrps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling devcfg"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling dmaps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling emacps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling gpiops"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/lwip211_v1_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/lwip211_v1_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling lwip src and adapter files"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling qspips"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling scugic"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling scutimer"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling scuwdt"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
|
||||
make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling sdps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling standalone"
|
||||
In file included from usleep.c:56:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
In file included from sleep.c:53:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
In file included from xil_sleeptimer.c:51:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
In file included from xtime_l.c:49:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling uartps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling xadcps"
|
||||
'Finished building libraries'
|
||||
|
||||
15:10:35 Build Finished (took 26s.875ms)
|
||||
|
||||
@@ -0,0 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<section name="Workbench">
|
||||
<section name="org.eclipse.cdt.ui.text.hover.CMacroExpansionExploration">
|
||||
</section>
|
||||
<section name="completion_proposal_size">
|
||||
</section>
|
||||
</section>
|
||||
@@ -0,0 +1,459 @@
|
||||
16:43:51 **** Incremental Build of configuration Debug for project calboard ****
|
||||
make pre-build main-build
|
||||
a9-linaro-pre-build-step
|
||||
' '
|
||||
make: Nothing to be done for 'main-build'.
|
||||
15:09:36 **** Build of project FSBL_bsp ****
|
||||
make -k all
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
|
||||
make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
|
||||
make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/xilffs_v4_0/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xilffs_v4_0/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xilrsa_v1_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling coresightps_dcc"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling cpu_cortexa9"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
|
||||
make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling ddrps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling devcfg"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling dmaps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling emacps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling gpiops"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling qspips"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling scugic"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling scutimer"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling scuwdt"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
|
||||
make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling sdps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling standalone"
|
||||
In file included from usleep.c:56:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
In file included from sleep.c:53:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
In file included from xil_sleeptimer.c:51:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
In file included from xtime_l.c:49:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling uartps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling xadcps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/xilffs_v4_0/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xilffs_v4_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling XilFFs Library"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/xilrsa_v1_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xilrsa_v1_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
'Finished building libraries'
|
||||
15:10:04 **** Build of configuration Debug for project FSBL ****
|
||||
make pre-build main-build
|
||||
a9-linaro-pre-build-step
|
||||
' '
|
||||
'Building file: ../src/fsbl_hooks.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/fsbl_hooks.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/fsbl_hooks.d" -MT"src/fsbl_hooks.o" -o "src/fsbl_hooks.o" "../src/fsbl_hooks.c"
|
||||
'Finished building: ../src/fsbl_hooks.c'
|
||||
' '
|
||||
'Building file: ../src/image_mover.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/image_mover.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/image_mover.d" -MT"src/image_mover.o" -o "src/image_mover.o" "../src/image_mover.c"
|
||||
'Finished building: ../src/image_mover.c'
|
||||
' '
|
||||
'Building file: ../src/main.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/main.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/main.c"
|
||||
In file included from ../src/main.c:137:0:
|
||||
../../FSBL_bsp/ps7_cortexa9_0/include/xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
'Finished building: ../src/main.c'
|
||||
' '
|
||||
'Building file: ../src/md5.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/md5.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/md5.d" -MT"src/md5.o" -o "src/md5.o" "../src/md5.c"
|
||||
'Finished building: ../src/md5.c'
|
||||
' '
|
||||
'Building file: ../src/nand.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/nand.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/nand.d" -MT"src/nand.o" -o "src/nand.o" "../src/nand.c"
|
||||
'Finished building: ../src/nand.c'
|
||||
' '
|
||||
'Building file: ../src/nor.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/nor.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/nor.d" -MT"src/nor.o" -o "src/nor.o" "../src/nor.c"
|
||||
'Finished building: ../src/nor.c'
|
||||
' '
|
||||
'Building file: ../src/pcap.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/pcap.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/pcap.d" -MT"src/pcap.o" -o "src/pcap.o" "../src/pcap.c"
|
||||
In file included from ../src/pcap.c:100:0:
|
||||
../../FSBL_bsp/ps7_cortexa9_0/include/xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
'Finished building: ../src/pcap.c'
|
||||
' '
|
||||
'Building file: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/ps7_init.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/ps7_init.d" -MT"src/ps7_init.o" -o "src/ps7_init.o" "E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c"
|
||||
'Finished building: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.c'
|
||||
' '
|
||||
'Building file: ../src/qspi.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/qspi.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/qspi.d" -MT"src/qspi.o" -o "src/qspi.o" "../src/qspi.c"
|
||||
'Finished building: ../src/qspi.c'
|
||||
' '
|
||||
'Building file: ../src/sd.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -I"E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\system_wrapper_hw_platform_0" -c -fmessage-length=0 -MT"src/sd.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../FSBL_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/sd.d" -MT"src/sd.o" -o "src/sd.o" "../src/sd.c"
|
||||
'Finished building: ../src/sd.c'
|
||||
' '
|
||||
'Building target: FSBL.elf'
|
||||
'Invoking: ARM v7 gcc linker'
|
||||
arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../FSBL_bsp/ps7_cortexa9_0/lib -o "FSBL.elf" ./src/fsbl_handoff.o ./src/fsbl_hooks.o ./src/image_mover.o ./src/main.o ./src/md5.o ./src/nand.o ./src/nor.o ./src/pcap.o ./src/ps7_init.o ./src/qspi.o ./src/rsa.o ./src/sd.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group
|
||||
'Finished building target: FSBL.elf'
|
||||
' '
|
||||
'Invoking: ARM v7 Print Size'
|
||||
arm-none-eabi-size FSBL.elf |tee "FSBL.elf.size"
|
||||
text data bss dec hex filename
|
||||
81496 10160 74712 166368 289e0 FSBL.elf
|
||||
'Finished building: FSBL.elf.size'
|
||||
' '
|
||||
15:10:09 **** Build of project calboard_bsp ****
|
||||
make -k all
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
|
||||
make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/lwip211_v1_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/lwip211_v1_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
|
||||
make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling coresightps_dcc"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling cpu_cortexa9"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_0/src"
|
||||
make -C ps7_cortexa9_0/libsrc/ddrps_v1_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling ddrps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/devcfg_v3_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling devcfg"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/dmaps_v2_4/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling dmaps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/emacps_v3_8/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling emacps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_4/src"
|
||||
make -C ps7_cortexa9_0/libsrc/gpiops_v3_4/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling gpiops"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/lwip211_v1_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/lwip211_v1_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling lwip src and adapter files"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_5/src"
|
||||
make -C ps7_cortexa9_0/libsrc/qspips_v3_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling qspips"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/scugic_v3_10/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scugic_v3_10/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling scugic"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scutimer_v2_1/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling scutimer"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_1/src"
|
||||
make -C ps7_cortexa9_0/libsrc/scuwdt_v2_1/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling scuwdt"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/sdps_v3_6/src"
|
||||
make -C ps7_cortexa9_0/libsrc/sdps_v3_6/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling sdps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/standalone_v6_8/src"
|
||||
make -C ps7_cortexa9_0/libsrc/standalone_v6_8/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling standalone"
|
||||
In file included from usleep.c:56:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
In file included from sleep.c:53:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
In file included from xil_sleeptimer.c:51:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
In file included from xtime_l.c:49:0:
|
||||
xtime_l.h:87:9: note: #pragma message: For the sleep routines, Global timer is being used
|
||||
#pragma message ("For the sleep routines, Global timer is being used")
|
||||
^~~~~~~
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_7/src"
|
||||
make -C ps7_cortexa9_0/libsrc/uartps_v3_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling uartps"
|
||||
"Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_3/src"
|
||||
make -C ps7_cortexa9_0/libsrc/xadcps_v2_3/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra"
|
||||
"Compiling xadcps"
|
||||
'Finished building libraries'
|
||||
15:10:36 **** Build of configuration Debug for project calboard ****
|
||||
make pre-build main-build
|
||||
a9-linaro-pre-build-step
|
||||
' '
|
||||
'Building file: ../src/GPIO_Driv.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/GPIO_Driv.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/GPIO_Driv.d" -MT"src/GPIO_Driv.o" -o "src/GPIO_Driv.o" "../src/GPIO_Driv.c"
|
||||
In file included from ../../calboard_bsp/ps7_cortexa9_0/include/xgpiops.h:119:0,
|
||||
from ../src/GPIO_Driv.h:12,
|
||||
from ../src/GPIO_Driv.c:7:
|
||||
../src/GPIO_Driv.c: In function 'EMIO_config':
|
||||
../../calboard_bsp/ps7_cortexa9_0/include/xstatus.h:61:41: warning: 'return' with a value, in function returning void
|
||||
#define XST_FAILURE 1L
|
||||
^
|
||||
../src/GPIO_Driv.c:21:11: note: in expansion of macro 'XST_FAILURE'
|
||||
return XST_FAILURE;
|
||||
^~~~~~~~~~~
|
||||
../src/GPIO_Driv.c:16:6: note: declared here
|
||||
void EMIO_config(void)
|
||||
^~~~~~~~~~~
|
||||
'Finished building: ../src/GPIO_Driv.c'
|
||||
' '
|
||||
'Building file: ../src/SPI_Driv.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/SPI_Driv.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/SPI_Driv.d" -MT"src/SPI_Driv.o" -o "src/SPI_Driv.o" "../src/SPI_Driv.c"
|
||||
'Finished building: ../src/SPI_Driv.c'
|
||||
' '
|
||||
'Building file: ../src/cal_meas.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/cal_meas.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/cal_meas.d" -MT"src/cal_meas.o" -o "src/cal_meas.o" "../src/cal_meas.c"
|
||||
../src/cal_meas.c: In function 'sw_config':
|
||||
../src/cal_meas.c:20:10: warning: unused variable 'memt_areal' [-Wunused-variable]
|
||||
char memt_areal = *(slot_start+6);
|
||||
^~~~~~~~~~
|
||||
../src/cal_meas.c:19:10: warning: unused variable 'load' [-Wunused-variable]
|
||||
char load = *(slot_start+5);
|
||||
^~~~
|
||||
../src/cal_meas.c:18:10: warning: unused variable 'volt_cur' [-Wunused-variable]
|
||||
char volt_cur = *(slot_start+4);
|
||||
^~~~~~~~
|
||||
../src/cal_meas.c:15:10: warning: unused variable 'm_fun' [-Wunused-variable]
|
||||
char m_fun = *(slot_start+1);
|
||||
^~~~~
|
||||
'Finished building: ../src/cal_meas.c'
|
||||
' '
|
||||
'Building file: ../src/dna_read.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/dna_read.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/dna_read.d" -MT"src/dna_read.o" -o "src/dna_read.o" "../src/dna_read.c"
|
||||
../src/dna_read.c: In function 'dna_port_read':
|
||||
../src/dna_read.c:19:2: warning: implicit declaration of function 'usleep' [-Wimplicit-function-declaration]
|
||||
usleep(20);
|
||||
^~~~~~
|
||||
'Finished building: ../src/dna_read.c'
|
||||
' '
|
||||
'Building file: ../src/echo.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/echo.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/echo.d" -MT"src/echo.o" -o "src/echo.o" "../src/echo.c"
|
||||
../src/echo.c: In function 'recv_callback':
|
||||
../src/echo.c:92:35: warning: pointer targets in passing argument 1 of 'do_crc_table' differ in signedness [-Wpointer-sign]
|
||||
crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
|
||||
^~~~~~~~~
|
||||
In file included from ../src/echo.c:32:0:
|
||||
../src/crc16.h:11:16: note: expected 'unsigned char *' but argument is of type 'char *'
|
||||
unsigned short do_crc_table(unsigned char* ptr, int len);
|
||||
^~~~~~~~~~~~
|
||||
'Finished building: ../src/echo.c'
|
||||
' '
|
||||
'Building file: ../src/i2c_access.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/i2c_access.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/i2c_access.d" -MT"src/i2c_access.o" -o "src/i2c_access.o" "../src/i2c_access.c"
|
||||
'Finished building: ../src/i2c_access.c'
|
||||
' '
|
||||
'Building file: ../src/iic_phyreset.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/iic_phyreset.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/iic_phyreset.d" -MT"src/iic_phyreset.o" -o "src/iic_phyreset.o" "../src/iic_phyreset.c"
|
||||
'Finished building: ../src/iic_phyreset.c'
|
||||
' '
|
||||
'Building file: ../src/main.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/main.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/main.c"
|
||||
'Finished building: ../src/main.c'
|
||||
' '
|
||||
'Building file: ../src/platform_zynq.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform_zynq.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/platform_zynq.d" -MT"src/platform_zynq.o" -o "src/platform_zynq.o" "../src/platform_zynq.c"
|
||||
'Finished building: ../src/platform_zynq.c'
|
||||
' '
|
||||
'Building file: ../src/platform_zynqmp.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform_zynqmp.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/platform_zynqmp.d" -MT"src/platform_zynqmp.o" -o "src/platform_zynqmp.o" "../src/platform_zynqmp.c"
|
||||
'Finished building: ../src/platform_zynqmp.c'
|
||||
' '
|
||||
'Building file: ../src/sfp.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/sfp.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/sfp.d" -MT"src/sfp.o" -o "src/sfp.o" "../src/sfp.c"
|
||||
'Finished building: ../src/sfp.c'
|
||||
' '
|
||||
'Building file: ../src/si5324.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/si5324.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/si5324.d" -MT"src/si5324.o" -o "src/si5324.o" "../src/si5324.c"
|
||||
'Finished building: ../src/si5324.c'
|
||||
' '
|
||||
'Building target: calboard.elf'
|
||||
'Invoking: ARM v7 gcc linker'
|
||||
arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../calboard_bsp/ps7_cortexa9_0/lib -o "calboard.elf" ./src/GPIO_Driv.o ./src/SPI_Driv.o ./src/cal_meas.o ./src/crc16.o ./src/dna_read.o ./src/echo.o ./src/i2c_access.o ./src/iic_phyreset.o ./src/main.o ./src/platform.o ./src/platform_mb.o ./src/platform_ppc.o ./src/platform_zynq.o ./src/platform_zynqmp.o ./src/sfp.o ./src/si5324.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group
|
||||
'Finished building target: calboard.elf'
|
||||
' '
|
||||
'Invoking: ARM v7 Print Size'
|
||||
arm-none-eabi-size calboard.elf |tee "calboard.elf.size"
|
||||
text data bss dec hex filename
|
||||
132488 3184 5363760 5499432 53ea28 calboard.elf
|
||||
'Finished building: calboard.elf.size'
|
||||
' '
|
||||
10:56:14 **** Auto Build of configuration Debug for project calboard ****
|
||||
make pre-build main-build
|
||||
a9-linaro-pre-build-step
|
||||
' '
|
||||
'Building file: ../src/cal_meas.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/cal_meas.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/cal_meas.d" -MT"src/cal_meas.o" -o "src/cal_meas.o" "../src/cal_meas.c"
|
||||
../src/cal_meas.c: In function 'sw_config':
|
||||
../src/cal_meas.c:20:10: warning: unused variable 'memt_areal' [-Wunused-variable]
|
||||
char memt_areal = *(slot_start+6);
|
||||
^~~~~~~~~~
|
||||
../src/cal_meas.c:19:10: warning: unused variable 'load' [-Wunused-variable]
|
||||
char load = *(slot_start+5);
|
||||
^~~~
|
||||
../src/cal_meas.c:18:10: warning: unused variable 'volt_cur' [-Wunused-variable]
|
||||
char volt_cur = *(slot_start+4);
|
||||
^~~~~~~~
|
||||
../src/cal_meas.c:15:10: warning: unused variable 'm_fun' [-Wunused-variable]
|
||||
char m_fun = *(slot_start+1);
|
||||
^~~~~
|
||||
'Finished building: ../src/cal_meas.c'
|
||||
' '
|
||||
'Building target: calboard.elf'
|
||||
'Invoking: ARM v7 gcc linker'
|
||||
arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../calboard_bsp/ps7_cortexa9_0/lib -o "calboard.elf" ./src/GPIO_Driv.o ./src/SPI_Driv.o ./src/cal_meas.o ./src/crc16.o ./src/dna_read.o ./src/echo.o ./src/i2c_access.o ./src/iic_phyreset.o ./src/main.o ./src/platform.o ./src/platform_mb.o ./src/platform_ppc.o ./src/platform_zynq.o ./src/platform_zynqmp.o ./src/sfp.o ./src/si5324.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group
|
||||
'Finished building target: calboard.elf'
|
||||
' '
|
||||
'Invoking: ARM v7 Print Size'
|
||||
arm-none-eabi-size calboard.elf |tee "calboard.elf.size"
|
||||
text data bss dec hex filename
|
||||
132552 3184 5363760 5499496 53ea68 calboard.elf
|
||||
'Finished building: calboard.elf.size'
|
||||
' '
|
||||
10:56:55 **** Auto Build of configuration Debug for project calboard ****
|
||||
make pre-build main-build
|
||||
a9-linaro-pre-build-step
|
||||
' '
|
||||
'Building file: ../src/cal_meas.c'
|
||||
'Invoking: ARM v7 gcc compiler'
|
||||
arm-none-eabi-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/cal_meas.o" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -I../../calboard_bsp/ps7_cortexa9_0/include -MMD -MP -MF"src/cal_meas.d" -MT"src/cal_meas.o" -o "src/cal_meas.o" "../src/cal_meas.c"
|
||||
../src/cal_meas.c: In function 'sw_config':
|
||||
../src/cal_meas.c:20:10: warning: unused variable 'memt_areal' [-Wunused-variable]
|
||||
char memt_areal = *(slot_start+6);
|
||||
^~~~~~~~~~
|
||||
../src/cal_meas.c:19:10: warning: unused variable 'load' [-Wunused-variable]
|
||||
char load = *(slot_start+5);
|
||||
^~~~
|
||||
../src/cal_meas.c:18:10: warning: unused variable 'volt_cur' [-Wunused-variable]
|
||||
char volt_cur = *(slot_start+4);
|
||||
^~~~~~~~
|
||||
../src/cal_meas.c:15:10: warning: unused variable 'm_fun' [-Wunused-variable]
|
||||
char m_fun = *(slot_start+1);
|
||||
^~~~~
|
||||
'Finished building: ../src/cal_meas.c'
|
||||
' '
|
||||
'Building target: calboard.elf'
|
||||
'Invoking: ARM v7 gcc linker'
|
||||
arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -L../../calboard_bsp/ps7_cortexa9_0/lib -o "calboard.elf" ./src/GPIO_Driv.o ./src/SPI_Driv.o ./src/cal_meas.o ./src/crc16.o ./src/dna_read.o ./src/echo.o ./src/i2c_access.o ./src/iic_phyreset.o ./src/main.o ./src/platform.o ./src/platform_mb.o ./src/platform_ppc.o ./src/platform_zynq.o ./src/platform_zynqmp.o ./src/sfp.o ./src/si5324.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group
|
||||
'Finished building target: calboard.elf'
|
||||
' '
|
||||
'Invoking: ARM v7 Print Size'
|
||||
arm-none-eabi-size calboard.elf |tee "calboard.elf.size"
|
||||
text data bss dec hex filename
|
||||
132680 3184 5363760 5499624 53eae8 calboard.elf
|
||||
'Finished building: calboard.elf.size'
|
||||
' '
|
||||
+227
@@ -0,0 +1,227 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start, u32 CPLD_UU[11])
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
sw_config_data[0] = (u8)(cpld_dat>>16);
|
||||
sw_config_data[1] = (u8)(cpld_dat>>8);
|
||||
sw_config_data[2] = (u8)cpld_dat;
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
}
|
||||
|
||||
|
||||
|
||||
+217
@@ -0,0 +1,217 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//---sdio3
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//---sdio4
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//---sdio5
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//---sdio6
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//---sdio7
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//62---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//63---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//64---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//65---rst
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
}
|
||||
+237
@@ -0,0 +1,237 @@
|
||||
/*
|
||||
* Copyright (C) 2009 - 2019 Xilinx, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include "dna_read.h"
|
||||
#include "crc16.h"
|
||||
#include "GPIO_Driv.h"
|
||||
#include "SPI_Driv.h"
|
||||
#include "cal_meas.h"
|
||||
|
||||
#include "lwip/err.h"
|
||||
#include "lwip/tcp.h"
|
||||
#if defined (__arm__) || defined (__aarch64__)
|
||||
#include "xil_printf.h"
|
||||
#endif
|
||||
|
||||
char *recv_data;
|
||||
char dna_data[10];
|
||||
unsigned short recv_len;
|
||||
|
||||
unsigned read_dat = 0;
|
||||
char dat_0[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
|
||||
unsigned crc_read_dat = 0;
|
||||
|
||||
char crc_alg_dat[2] = {0,0};
|
||||
|
||||
char send_data_cpld1[2] = {0xAA,0x56};
|
||||
|
||||
int transfer_data() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
void print_app_header()
|
||||
{
|
||||
#if (LWIP_IPV6==0)
|
||||
xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
|
||||
#else
|
||||
xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
|
||||
#endif
|
||||
xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
|
||||
}
|
||||
|
||||
err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
|
||||
struct pbuf *p, err_t err)
|
||||
{
|
||||
/* do not read the packet if we are not in ESTABLISHED state */
|
||||
if (!p) {
|
||||
tcp_close(tpcb);
|
||||
tcp_recv(tpcb, NULL);
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
/* indicate that the packet has been received */
|
||||
tcp_recved(tpcb, p->len);
|
||||
|
||||
/* echo back the payload */
|
||||
/* in this case, we assume that the payload is < TCP_SND_BUF */
|
||||
if (tcp_sndbuf(tpcb) > p->len) {
|
||||
|
||||
recv_len = p->len;
|
||||
recv_data = (char*)malloc(sizeof(char)*recv_len);
|
||||
memcpy(recv_data,p->payload,recv_len);
|
||||
|
||||
if(recv_data[6] == 0x0E)
|
||||
{
|
||||
crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
|
||||
|
||||
crc_alg_dat[0] = (u8)crc_read_dat;
|
||||
crc_alg_dat[1] = (u8)(crc_read_dat>>8);
|
||||
dat_0[0]= 0x00;
|
||||
|
||||
switch(recv_data[7])
|
||||
{
|
||||
|
||||
case 0xA2://SLOT
|
||||
{
|
||||
dat_0[1]= 0x06;
|
||||
dat_0[2]= recv_data[2];
|
||||
dat_0[3]= recv_data[3];
|
||||
dat_0[4]= recv_data[4];
|
||||
dat_0[5]= recv_data[5];
|
||||
dat_0[6]= recv_data[6];
|
||||
dat_0[7]= recv_data[7];
|
||||
if(recv_data[15]==crc_alg_dat[1]&&recv_data[16]==crc_alg_dat[0])
|
||||
{
|
||||
dat_0[8]= 0x01;
|
||||
dat_0[9]= 0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
dat_0[8]= 0xff;
|
||||
dat_0[9]= 0xff;
|
||||
}
|
||||
dat_0[10]= recv_data[15];
|
||||
dat_0[11]= recv_data[16];
|
||||
|
||||
char slot_start[7] = {recv_data[8],recv_data[9],recv_data[10],recv_data[11],recv_data[12],recv_data[13],recv_data[14]};
|
||||
//xil_printf("slot_start[0]:%x, slot_start[1]:%x,slot_start[2]:%x,slot_start[3]:%x,slot_start[4]:%x,slot_start[5]:%x,slot_start[6]:%x\n\r", slot_start[0],slot_start[1],slot_start[2],slot_start[3],slot_start[4],slot_start[5],slot_start[6]);
|
||||
rst_CPLD(CPLD_U1,4);
|
||||
rst_CPLD(CPLD_U2,4);
|
||||
rst_CPLD(CPLD_U3,4);
|
||||
sw_config(slot_start);
|
||||
|
||||
tcp_write(tpcb, dat_0, 12, 1);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case 0xA3://dna_port_read
|
||||
{
|
||||
dna_port_read(dna_data);
|
||||
dat_0[1]=0x0e;
|
||||
dat_0[2]=recv_data[2];
|
||||
dat_0[3]=recv_data[3];
|
||||
dat_0[4]=recv_data[4];
|
||||
dat_0[5]=recv_data[5];
|
||||
dat_0[6]=recv_data[6];
|
||||
dat_0[7]=recv_data[7];
|
||||
if(recv_data[8]==crc_alg_dat[1]&&recv_data[9]==crc_alg_dat[0])
|
||||
{
|
||||
dat_0[8]= 0x01;
|
||||
dat_0[9]= 0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
dat_0[8]= 0xff;
|
||||
dat_0[9]= 0xff;
|
||||
}
|
||||
dat_0[10]= dna_data[0];
|
||||
dat_0[11]= dna_data[1];
|
||||
dat_0[12]= dna_data[2];
|
||||
dat_0[13]= dna_data[3];
|
||||
dat_0[14]= dna_data[4];
|
||||
dat_0[15]= dna_data[5];
|
||||
dat_0[16]= dna_data[6];
|
||||
dat_0[17]= dna_data[7];
|
||||
|
||||
dat_0[18]= recv_data[8];
|
||||
dat_0[19]= recv_data[9];
|
||||
|
||||
tcp_write(tpcb, dat_0, 20, 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else
|
||||
xil_printf("no space in tcp_sndbuf\n\r");
|
||||
|
||||
|
||||
|
||||
/* free the received pbuf */
|
||||
pbuf_free(p);
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
|
||||
{
|
||||
static int connection = 1;
|
||||
|
||||
/* set the receive callback for this connection */
|
||||
tcp_recv(newpcb, recv_callback);
|
||||
|
||||
/* just use an integer number indicating the connection id as the
|
||||
callback argument */
|
||||
tcp_arg(newpcb, (void*)(UINTPTR)connection);
|
||||
|
||||
/* increment for subsequent accepted connections */
|
||||
connection++;
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
|
||||
int start_application()
|
||||
{
|
||||
struct tcp_pcb *pcb;
|
||||
err_t err;
|
||||
unsigned port = 200;
|
||||
|
||||
/* create new TCP PCB structure */
|
||||
pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
|
||||
if (!pcb) {
|
||||
xil_printf("Error creating PCB. Out of Memory\n\r");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* bind to specified @port */
|
||||
err = tcp_bind(pcb, IP_ANY_TYPE, port);
|
||||
if (err != ERR_OK) {
|
||||
xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
|
||||
return -2;
|
||||
}
|
||||
|
||||
/* we do not need any arguments to callback functions */
|
||||
tcp_arg(pcb, NULL);
|
||||
|
||||
/* listen for connections */
|
||||
pcb = tcp_listen(pcb);
|
||||
if (!pcb) {
|
||||
xil_printf("Out of memory while tcp_listen\n\r");
|
||||
return -3;
|
||||
}
|
||||
|
||||
/* specify callback to use for incoming connections */
|
||||
tcp_accept(pcb, accept_callback);
|
||||
|
||||
xil_printf("TCP echo server started @ port %d\n\r", port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
+242
@@ -0,0 +1,242 @@
|
||||
/*
|
||||
* Copyright (C) 2009 - 2019 Xilinx, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include "dna_read.h"
|
||||
#include "crc16.h"
|
||||
#include "GPIO_Driv.h"
|
||||
#include "SPI_Driv.h"
|
||||
#include "cal_meas.h"
|
||||
|
||||
#include "lwip/err.h"
|
||||
#include "lwip/tcp.h"
|
||||
#if defined (__arm__) || defined (__aarch64__)
|
||||
#include "xil_printf.h"
|
||||
#endif
|
||||
|
||||
char *recv_data;
|
||||
char dna_data[10];
|
||||
unsigned short recv_len;
|
||||
|
||||
unsigned read_dat = 0;
|
||||
char dat_0[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
|
||||
unsigned crc_read_dat = 0;
|
||||
|
||||
char crc_alg_dat[2] = {0,0};
|
||||
|
||||
char send_data_cpld1[2] = {0xAA,0x56};
|
||||
|
||||
int transfer_data() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
void print_app_header()
|
||||
{
|
||||
#if (LWIP_IPV6==0)
|
||||
xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
|
||||
#else
|
||||
xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
|
||||
#endif
|
||||
xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
|
||||
}
|
||||
|
||||
err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
|
||||
struct pbuf *p, err_t err)
|
||||
{
|
||||
/* do not read the packet if we are not in ESTABLISHED state */
|
||||
if (!p) {
|
||||
tcp_close(tpcb);
|
||||
tcp_recv(tpcb, NULL);
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
/* indicate that the packet has been received */
|
||||
tcp_recved(tpcb, p->len);
|
||||
|
||||
/* echo back the payload */
|
||||
/* in this case, we assume that the payload is < TCP_SND_BUF */
|
||||
if (tcp_sndbuf(tpcb) > p->len) {
|
||||
|
||||
recv_len = p->len;
|
||||
recv_data = (char*)malloc(sizeof(char)*recv_len);
|
||||
memcpy(recv_data,p->payload,recv_len);
|
||||
|
||||
if(recv_data[6] == 0x0E)
|
||||
{
|
||||
crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
|
||||
|
||||
crc_alg_dat[0] = (u8)crc_read_dat;
|
||||
crc_alg_dat[1] = (u8)(crc_read_dat>>8);
|
||||
dat_0[0]= 0x00;
|
||||
|
||||
switch(recv_data[7])
|
||||
{
|
||||
|
||||
case 0xA2://SLOT
|
||||
{
|
||||
|
||||
dat_0[1]= 0x06;
|
||||
dat_0[2]= recv_data[2];
|
||||
dat_0[3]= recv_data[3];
|
||||
dat_0[4]= recv_data[4];
|
||||
dat_0[5]= recv_data[5];
|
||||
dat_0[6]= recv_data[6];
|
||||
dat_0[7]= recv_data[7];
|
||||
if(recv_data[15]==crc_alg_dat[1]&&recv_data[16]==crc_alg_dat[0])
|
||||
{
|
||||
dat_0[8]= 0x01;
|
||||
dat_0[9]= 0x01;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
dat_0[8]= 0xff;
|
||||
dat_0[9]= 0xff;
|
||||
}
|
||||
dat_0[10]= recv_data[15];
|
||||
dat_0[11]= recv_data[16];
|
||||
|
||||
char slot_start[7] = {recv_data[8],recv_data[9],recv_data[10],recv_data[11],recv_data[12],recv_data[13],recv_data[14]};
|
||||
//xil_printf("slot_start[0]:%x, slot_start[1]:%x,slot_start[2]:%x,slot_start[3]:%x,slot_start[4]:%x,slot_start[5]:%x,slot_start[6]:%x\n\r", slot_start[0],slot_start[1],slot_start[2],slot_start[3],slot_start[4],slot_start[5],slot_start[6]);
|
||||
rst_CPLD(CPLD_U1,4);
|
||||
rst_CPLD(CPLD_U2,4);
|
||||
rst_CPLD(CPLD_U3,4);
|
||||
sw_config(slot_start);
|
||||
|
||||
tcp_write(tpcb, dat_0, 12, 1);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case 0xA3://dna_port_read
|
||||
{
|
||||
dna_port_read(dna_data);
|
||||
dat_0[1]=0x0e;
|
||||
dat_0[2]=recv_data[2];
|
||||
dat_0[3]=recv_data[3];
|
||||
dat_0[4]=recv_data[4];
|
||||
dat_0[5]=recv_data[5];
|
||||
dat_0[6]=recv_data[6];
|
||||
dat_0[7]=recv_data[7];
|
||||
if(recv_data[8]==crc_alg_dat[1]&&recv_data[9]==crc_alg_dat[0])
|
||||
{
|
||||
dat_0[8]= 0x01;
|
||||
dat_0[9]= 0x01;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
dat_0[8]= 0xff;
|
||||
dat_0[9]= 0xff;
|
||||
}
|
||||
|
||||
dat_0[10]= dna_data[0];
|
||||
dat_0[11]= dna_data[1];
|
||||
dat_0[12]= dna_data[2];
|
||||
dat_0[13]= dna_data[3];
|
||||
dat_0[14]= dna_data[4];
|
||||
dat_0[15]= dna_data[5];
|
||||
dat_0[16]= dna_data[6];
|
||||
dat_0[17]= dna_data[7];
|
||||
|
||||
dat_0[18]= recv_data[8];
|
||||
dat_0[19]= recv_data[9];
|
||||
|
||||
tcp_write(tpcb, dat_0, 20, 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
} else
|
||||
xil_printf("no space in tcp_sndbuf\n\r");
|
||||
|
||||
|
||||
|
||||
/* free the received pbuf */
|
||||
pbuf_free(p);
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
|
||||
{
|
||||
static int connection = 1;
|
||||
|
||||
/* set the receive callback for this connection */
|
||||
tcp_recv(newpcb, recv_callback);
|
||||
|
||||
/* just use an integer number indicating the connection id as the
|
||||
callback argument */
|
||||
tcp_arg(newpcb, (void*)(UINTPTR)connection);
|
||||
|
||||
/* increment for subsequent accepted connections */
|
||||
connection++;
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
|
||||
int start_application()
|
||||
{
|
||||
struct tcp_pcb *pcb;
|
||||
err_t err;
|
||||
unsigned port = 200;
|
||||
|
||||
/* create new TCP PCB structure */
|
||||
pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
|
||||
if (!pcb) {
|
||||
xil_printf("Error creating PCB. Out of Memory\n\r");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* bind to specified @port */
|
||||
err = tcp_bind(pcb, IP_ANY_TYPE, port);
|
||||
if (err != ERR_OK) {
|
||||
xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
|
||||
return -2;
|
||||
}
|
||||
|
||||
/* we do not need any arguments to callback functions */
|
||||
tcp_arg(pcb, NULL);
|
||||
|
||||
/* listen for connections */
|
||||
pcb = tcp_listen(pcb);
|
||||
if (!pcb) {
|
||||
xil_printf("Out of memory while tcp_listen\n\r");
|
||||
return -3;
|
||||
}
|
||||
|
||||
/* specify callback to use for incoming connections */
|
||||
tcp_accept(pcb, accept_callback);
|
||||
|
||||
xil_printf("TCP echo server started @ port %d\n\r", port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
+29
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* cal_meas.h
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#ifndef SRC_CAL_MEAS_H_
|
||||
#define SRC_CAL_MEAS_H_
|
||||
|
||||
#include "sleep.h"
|
||||
#include "stdio.h"
|
||||
#include "xgpiops.h"
|
||||
#include "SPI_Driv.h"
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
|
||||
#define U1_SW_FC_DV0 1
|
||||
#define dat_width 3
|
||||
|
||||
void sw_init( void );
|
||||
void sw_config(char *slot_start);
|
||||
void fsmc_mmc_config(char slot,char m_fun);
|
||||
void dmm_config(char slot, u16 ch_num);
|
||||
void rc_config(char m_fun);
|
||||
void fsc_oc_config(char slot,char m_fun, u16 ch_num);
|
||||
void rl_config(char load);
|
||||
|
||||
#endif /* SRC_CAL_MEAS_H_ */
|
||||
+81
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//---sdio3
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//---sdio4
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//---sdio5
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//---sdio6
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//---sdio7
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
}
|
||||
+157
@@ -0,0 +1,157 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+285
@@ -0,0 +1,285 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0xFF,0xFF,0xFF};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 u1_io_rc_dat = 0;
|
||||
u16 u1_rc_dat = 0;
|
||||
u16 u1_lofs_vpk_dat = 0;
|
||||
u16 u1_lofs_apk_dat = 0;
|
||||
u16 u1_lofs_vpk_apk_dat = 0;
|
||||
|
||||
u16 ch_num = 0;
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
//xil_printf("slot: %d\n\r", slot);
|
||||
//xil_printf("m_fun: %d\n\r", m_fun);
|
||||
//xil_printf("ch_num: %d\n\r", ch_num);
|
||||
fsc_oc_config(slot,m_fun,ch_num);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
dmm_config(slot,ch_num);
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dmm_config(char slot, u16 ch_num)
|
||||
{
|
||||
u16 sw_oc_dmm_dat = 0;
|
||||
if(ch_num>=1&&ch_num<=64)
|
||||
{
|
||||
sw_oc_dmm_dat = (0x0001<<((slot-1)*4));
|
||||
sw_oc_dmm_dat = ~sw_oc_dmm_dat;
|
||||
}
|
||||
else if(ch_num>=65&&ch_num<=128)
|
||||
{
|
||||
sw_oc_dmm_dat = (0x0001<<((slot-1)*4+1));
|
||||
sw_oc_dmm_dat = ~sw_oc_dmm_dat;
|
||||
}
|
||||
else if(ch_num>=129&&ch_num<=192)
|
||||
{
|
||||
sw_oc_dmm_dat = (0x0001<<((slot-1)*4+2));
|
||||
sw_oc_dmm_dat = ~sw_oc_dmm_dat;
|
||||
}
|
||||
else
|
||||
{
|
||||
sw_oc_dmm_dat = (0x0001<<((slot-1)*4+3));
|
||||
sw_oc_dmm_dat = ~sw_oc_dmm_dat;
|
||||
}
|
||||
//xil_printf("oc_dmm_dat: %x\n\r", sw_oc_dmm_dat);
|
||||
sw_config_data[0] = (u8)(sw_oc_dmm_dat>>8);
|
||||
sw_config_data[1] = (u8)(sw_oc_dmm_dat);
|
||||
spi_write_onewire(U1_SW_OC_DMM, sw_config_data, dat_width, CPLD_U1);
|
||||
|
||||
}
|
||||
|
||||
void rc_config(char m_fun)
|
||||
{
|
||||
u16 rc_dat = 0;
|
||||
switch(m_fun)
|
||||
{
|
||||
case 0x01:
|
||||
{
|
||||
rc_dat = 0xFFFD;
|
||||
break;
|
||||
}
|
||||
case 0x02:
|
||||
{
|
||||
rc_dat = 0xFFFB;
|
||||
break;
|
||||
}
|
||||
case 0x03:
|
||||
{
|
||||
rc_dat = 0xFFF9;
|
||||
break;
|
||||
}
|
||||
}
|
||||
//xil_printf("rc_dat: %x\n\r", rc_dat);
|
||||
sw_config_data[0] = (u8)(rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
}
|
||||
|
||||
void rl_config(char load)
|
||||
{
|
||||
u16 rl_dat = 0;
|
||||
if(load>=1&&load<=9)
|
||||
{
|
||||
rl_dat = (0x0001<<(load-1));
|
||||
rl_dat = ~rl_dat;
|
||||
//xil_printf("load: %x\n\r", load);
|
||||
//xil_printf("rl_01_dat: %x\n\r", rl_dat);
|
||||
sw_config_data[0] = (u8)(rl_dat>>8);
|
||||
sw_config_data[1] = (u8)(rl_dat);
|
||||
spi_write_onewire(U1_SW_RL1, sw_config_data, dat_width, CPLD_U1);
|
||||
}
|
||||
else
|
||||
{
|
||||
rl_dat = (0x0001<<(load-10));
|
||||
rl_dat = ~rl_dat;
|
||||
//xil_printf("load: %x\n\r", load);
|
||||
//xil_printf("rl_02_dat: %x\n\r", rl_dat);
|
||||
sw_config_data[0] = (u8)(rl_dat>>8);
|
||||
sw_config_data[1] = (u8)(rl_dat);
|
||||
spi_write_onewire(U1_SW_RL2, sw_config_data, dat_width, CPLD_U1);
|
||||
}
|
||||
}
|
||||
|
||||
void fsc_oc_config(char slot,char m_fun, u16 ch_num)
|
||||
{
|
||||
u16 fc_dv0_dat = 0;
|
||||
switch(m_fun)
|
||||
{
|
||||
case 0x01:
|
||||
{
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x01,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
}
|
||||
else
|
||||
{
|
||||
//xil_printf("m_fun=0x01,ch_num=17~32 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-17));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U2_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
|
||||
//xil_printf("CPLD_U2:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U2_SW_FC_DV0+slot-1);
|
||||
}
|
||||
//xil_printf("reg_data: %x\n\r", fc_dv0_dat);
|
||||
break;
|
||||
}
|
||||
case 0x02:
|
||||
{
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x02,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
else
|
||||
{
|
||||
//xil_printf("m_fun=0x02,ch_num=17~32 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-17));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U2_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
|
||||
//xil_printf("CPLD_U2:\n\r");
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U2_SW_SC_DV0+slot-1);
|
||||
}
|
||||
//xil_printf("reg_data: %x\n\r", fc_dv0_dat);
|
||||
break;
|
||||
}
|
||||
case 0x03:
|
||||
{
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=17~32 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-17));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U2_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(U2_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
|
||||
//xil_printf("CPLD_U2:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U2_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U2_SW_SC_DV0+slot-1);
|
||||
}
|
||||
//xil_printf("reg_data: %x\n\r", fc_dv0_dat);
|
||||
break;
|
||||
}
|
||||
case 0x04:
|
||||
{
|
||||
if(ch_num>=1&&ch_num<=64)
|
||||
{
|
||||
//xil_printf("m_fun=0x04,ch_num=1~64 \n\r");
|
||||
fc_dv0_dat = (0x0001<<((ch_num-1)/8));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_OC_DV0+(slot-1)*2, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("oc_reg_addr: %d\n\r", U1_SW_OC_DV0+(slot-1)*2);
|
||||
}
|
||||
else if(ch_num>=65&&ch_num<=128)
|
||||
{
|
||||
//xil_printf("m_fun=0x04,ch_num=65~128 \n\r");
|
||||
fc_dv0_dat = (0x0001<<((ch_num-65)/8));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U2_SW_OC_DV0+(slot-1)*2, sw_config_data, dat_width, CPLD_U2);
|
||||
//xil_printf("CPLD_U2:\n\r");
|
||||
//xil_printf("oc_reg_addr: %d\n\r", U2_SW_OC_DV0+(slot-1)*2);
|
||||
}
|
||||
else if(ch_num>=129&&ch_num<=192)
|
||||
{
|
||||
//xil_printf("m_fun=0x04,ch_num=129~192 \n\r");
|
||||
fc_dv0_dat = (0x0001<<((ch_num-129)/8));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_OC_DV1+(slot-1)*2, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("oc_reg_addr: %d\n\r", U1_SW_OC_DV1+(slot-1)*2);
|
||||
}
|
||||
else if(ch_num>=193&&ch_num<=256)
|
||||
{
|
||||
//xil_printf("m_fun=0x04,ch_num=193~256 \n\r");
|
||||
fc_dv0_dat = (0x0001<<((ch_num-193)/8));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U2_SW_OC_DV1+(slot-1)*2, sw_config_data, dat_width, CPLD_U2);
|
||||
//xil_printf("CPLD_U2:\n\r");
|
||||
//xil_printf("oc_reg_addr: %d\n\r", U2_SW_OC_DV1+(slot-1)*2);
|
||||
}
|
||||
//xil_printf("reg_data: %x\n\r", fc_dv0_dat);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
+237
@@ -0,0 +1,237 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+80
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//---sdio3
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//---sdio4
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//---sdio5
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//---sdio6
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//---sdio7
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//65---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//62---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//63---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//64---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
}
|
||||
+108
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
/*-------------------------------------CPLD_U3------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//66---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//67---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//68---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//66
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//67
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//66---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//67---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//68---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);
|
||||
|
||||
}
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+87
@@ -0,0 +1,87 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0xFF,0xFF,0xFF};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+247
@@ -0,0 +1,247 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00220000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
sw_config_data[0] = (u8)(cpld_dat>>16);
|
||||
sw_config_data[1] = (u8)(cpld_dat>>8);
|
||||
sw_config_data[2] = (u8)(cpld_dat);
|
||||
|
||||
xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
|
||||
xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
|
||||
|
||||
xil_printf("cpld_addr: %d\n\r", cpld_addr);
|
||||
xil_printf("cpld_dat: %d\n\r", cpld_dat);
|
||||
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
|
||||
sw_config_data[0] = 0x00;
|
||||
sw_config_data[1] = 0x00;
|
||||
sw_config_data[2] = 0x01;
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
|
||||
|
||||
slot_en = 0x00000000;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
}
|
||||
|
||||
|
||||
|
||||
+87
@@ -0,0 +1,87 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+108
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);//68---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);//69---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
/*-------------------------------------CPLD_U3------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 0);//79---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 1);//80---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
}
|
||||
+63
@@ -0,0 +1,63 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0xFF,0xFF,0xFF};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+238
@@ -0,0 +1,238 @@
|
||||
/*
|
||||
* Copyright (C) 2009 - 2019 Xilinx, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include "dna_read.h"
|
||||
#include "crc16.h"
|
||||
#include "GPIO_Driv.h"
|
||||
#include "SPI_Driv.h"
|
||||
#include "cal_meas.h"
|
||||
|
||||
#include "lwip/err.h"
|
||||
#include "lwip/tcp.h"
|
||||
#if defined (__arm__) || defined (__aarch64__)
|
||||
#include "xil_printf.h"
|
||||
#endif
|
||||
|
||||
char *recv_data;
|
||||
char dna_data[10];
|
||||
unsigned short recv_len;
|
||||
|
||||
unsigned read_dat = 0;
|
||||
char dat_0[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
|
||||
unsigned crc_read_dat = 0;
|
||||
|
||||
char crc_alg_dat[2] = {0,0};
|
||||
|
||||
char send_data_cpld1[2] = {0xAA,0x56};
|
||||
|
||||
int transfer_data() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
void print_app_header()
|
||||
{
|
||||
#if (LWIP_IPV6==0)
|
||||
xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
|
||||
#else
|
||||
xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
|
||||
#endif
|
||||
xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
|
||||
}
|
||||
|
||||
err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
|
||||
struct pbuf *p, err_t err)
|
||||
{
|
||||
/* do not read the packet if we are not in ESTABLISHED state */
|
||||
if (!p) {
|
||||
tcp_close(tpcb);
|
||||
tcp_recv(tpcb, NULL);
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
/* indicate that the packet has been received */
|
||||
tcp_recved(tpcb, p->len);
|
||||
|
||||
/* echo back the payload */
|
||||
/* in this case, we assume that the payload is < TCP_SND_BUF */
|
||||
if (tcp_sndbuf(tpcb) > p->len) {
|
||||
|
||||
recv_len = p->len;
|
||||
recv_data = (char*)malloc(sizeof(char)*recv_len);
|
||||
memcpy(recv_data,p->payload,recv_len);
|
||||
|
||||
if(recv_data[6] == 0x0E)
|
||||
{
|
||||
crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
|
||||
|
||||
crc_alg_dat[0] = (u8)crc_read_dat;
|
||||
crc_alg_dat[1] = (u8)(crc_read_dat>>8);
|
||||
dat_0[0]= 0x00;
|
||||
|
||||
switch(recv_data[7])
|
||||
{
|
||||
|
||||
case 0xA2://SLOT
|
||||
{
|
||||
dat_0[1]= 0x06;
|
||||
dat_0[2]= recv_data[2];
|
||||
dat_0[3]= recv_data[3];
|
||||
dat_0[4]= recv_data[4];
|
||||
dat_0[5]= recv_data[5];
|
||||
dat_0[6]= recv_data[6];
|
||||
dat_0[7]= recv_data[7];
|
||||
if(recv_data[15]==crc_alg_dat[1]&&recv_data[16]==crc_alg_dat[0])
|
||||
{
|
||||
dat_0[8]= 0x01;
|
||||
dat_0[9]= 0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
dat_0[8]= 0xff;
|
||||
dat_0[9]= 0xff;
|
||||
}
|
||||
dat_0[10]= recv_data[15];
|
||||
dat_0[11]= recv_data[16];
|
||||
|
||||
char slot_start[7] = {recv_data[8],recv_data[9],recv_data[10],recv_data[11],recv_data[12],recv_data[13],recv_data[14]};
|
||||
//xil_printf("slot_start[0]:%x, slot_start[1]:%x,slot_start[2]:%x,slot_start[3]:%x,slot_start[4]:%x,slot_start[5]:%x,slot_start[6]:%x\n\r", slot_start[0],slot_start[1],slot_start[2],slot_start[3],slot_start[4],slot_start[5],slot_start[6]);
|
||||
rst_CPLD(CPLD_U1,4);
|
||||
rst_CPLD(CPLD_U2,4);
|
||||
rst_CPLD(CPLD_U3,4);
|
||||
sw_config(slot_start);
|
||||
|
||||
tcp_write(tpcb, dat_0, 12, 1);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case 0xA3://dna_port_read
|
||||
{
|
||||
dna_port_read(dna_data);
|
||||
dat_0[1]=0x0e;
|
||||
dat_0[2]=recv_data[2];
|
||||
dat_0[3]=recv_data[3];
|
||||
dat_0[4]=recv_data[4];
|
||||
dat_0[5]=recv_data[5];
|
||||
dat_0[6]=recv_data[6];
|
||||
dat_0[7]=recv_data[7];
|
||||
if(recv_data[8]==crc_alg_dat[1]&&recv_data[9]==crc_alg_dat[0])
|
||||
{
|
||||
dat_0[8]= 0x01;
|
||||
dat_0[9]= 0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
dat_0[8]= 0xff;
|
||||
dat_0[9]= 0xff;
|
||||
}
|
||||
|
||||
dat_0[10]= dna_data[0];
|
||||
dat_0[11]= dna_data[1];
|
||||
dat_0[12]= dna_data[2];
|
||||
dat_0[13]= dna_data[3];
|
||||
dat_0[14]= dna_data[4];
|
||||
dat_0[15]= dna_data[5];
|
||||
dat_0[16]= dna_data[6];
|
||||
dat_0[17]= dna_data[7];
|
||||
|
||||
dat_0[18]= recv_data[8];
|
||||
dat_0[19]= recv_data[9];
|
||||
|
||||
tcp_write(tpcb, dat_0, 20, 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else
|
||||
xil_printf("no space in tcp_sndbuf\n\r");
|
||||
|
||||
|
||||
|
||||
/* free the received pbuf */
|
||||
pbuf_free(p);
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
|
||||
{
|
||||
static int connection = 1;
|
||||
|
||||
/* set the receive callback for this connection */
|
||||
tcp_recv(newpcb, recv_callback);
|
||||
|
||||
/* just use an integer number indicating the connection id as the
|
||||
callback argument */
|
||||
tcp_arg(newpcb, (void*)(UINTPTR)connection);
|
||||
|
||||
/* increment for subsequent accepted connections */
|
||||
connection++;
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
|
||||
int start_application()
|
||||
{
|
||||
struct tcp_pcb *pcb;
|
||||
err_t err;
|
||||
unsigned port = 200;
|
||||
|
||||
/* create new TCP PCB structure */
|
||||
pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
|
||||
if (!pcb) {
|
||||
xil_printf("Error creating PCB. Out of Memory\n\r");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* bind to specified @port */
|
||||
err = tcp_bind(pcb, IP_ANY_TYPE, port);
|
||||
if (err != ERR_OK) {
|
||||
xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
|
||||
return -2;
|
||||
}
|
||||
|
||||
/* we do not need any arguments to callback functions */
|
||||
tcp_arg(pcb, NULL);
|
||||
|
||||
/* listen for connections */
|
||||
pcb = tcp_listen(pcb);
|
||||
if (!pcb) {
|
||||
xil_printf("Out of memory while tcp_listen\n\r");
|
||||
return -3;
|
||||
}
|
||||
|
||||
/* specify callback to use for incoming connections */
|
||||
tcp_accept(pcb, accept_callback);
|
||||
|
||||
xil_printf("TCP echo server started @ port %d\n\r", port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//62---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//63---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//64---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//65---rst
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
}
|
||||
+558
@@ -0,0 +1,558 @@
|
||||
/*
|
||||
* SPI_Driv.c
|
||||
*
|
||||
* Created on: 2021年4月2日
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "SPI_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
|
||||
|
||||
extern u32 K7_U0[16];
|
||||
extern u32 molex_4_bank_3[4];
|
||||
extern u32 cs_en_bank_3[4];
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void interface_initial(u32* device,u32 num_wire)
|
||||
* Description : interface initial
|
||||
* Parameter : device -- CPLD
|
||||
* num_wire -- 复位线编号
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void interface_initial(u32* device) //wire_num = cs sck sdi/o
|
||||
{
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void rst_CPLD(u32* device,u32 num_wire)
|
||||
* Description : CPLD reset
|
||||
* Parameter : device -- CPLD
|
||||
* num_wire -- 复位线编号
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
|
||||
{
|
||||
u32 rst_n = *(device+num_wire);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
|
||||
usleep(2);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_write_onewire(char addr, u32 data, char width, u32* device)
|
||||
* Description : spi onewire write
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_write_onewire(char addr, char *data, char width, u32* device)
|
||||
{
|
||||
char temp_addr = 0;
|
||||
//u32 temp_data = 0;
|
||||
u32 temp_data = 0;
|
||||
char i = 0,j=0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs= *(device+1);
|
||||
u32 sdi= *(device+2);
|
||||
|
||||
temp_addr = addr;
|
||||
///temp_data = data;
|
||||
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); // w/r标志位 1=w 0=r
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 8; i++) // 8bit地址
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_addr&0x80)
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
|
||||
}
|
||||
|
||||
for(j=0;j<width;j++)
|
||||
{
|
||||
temp_data = *(data+j);
|
||||
for(i = 0; i < 8; i++) //nbit数据
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_data&0x80) //注意数据位nbit，要从[n-1]取位
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_data <<= 1;
|
||||
}
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs , 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : u32 spi_read_onewire(char addr, char width, u32* device)
|
||||
* Description : spi onewire read
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
u32 spi_read_onewire(char addr, char width, u32* device,char* read_data)
|
||||
{
|
||||
char temp_addr=0;
|
||||
u32 temp_data=0;
|
||||
char i=0,j=0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs= *(device+1);
|
||||
u32 sdi= *(device+2);
|
||||
u32 sdo= *(device+3);
|
||||
|
||||
temp_addr = addr;
|
||||
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0); // w/r标志位 1=w 0=r
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 8; i++) // 8bit地址
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_addr&0x80)
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
|
||||
}
|
||||
|
||||
for(j=0; j<width; j++)
|
||||
{
|
||||
for(i = 0; i < 8; i++) //nbit数据
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
temp_data = temp_data << 1; //sck低电平准备数据 准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo)) //sck高电平接收数据 数据匹配到准备好的数位，等待一起传递到MCU
|
||||
temp_data = temp_data| 0x00000001;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
}
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
read_data[0] = (u8)(temp_data>>16);
|
||||
read_data[1] = (u8)(temp_data>>8);
|
||||
read_data[0] = (u8)(temp_data);
|
||||
return temp_data;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
|
||||
* Description : forwire write to reg
|
||||
* Parameter : txdata--数据
|
||||
* sdi0,sdi1,sdi2,sdi3--IO
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
|
||||
{
|
||||
switch(txdata & 0x0F)
|
||||
{
|
||||
case 0x00:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x01:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x02:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x03:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x04:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x05:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x06:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x07:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x08:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x09:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0A:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0B:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0C:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0D:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0E:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0F:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_write_fourwire(char addr, u16 data, u32* device)
|
||||
* Description : spi fourwire write
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_write_fourwire(char addr, u16 data, u32* device)
|
||||
{
|
||||
u8 temp_addr = 0;
|
||||
u16 temp_data = 0;
|
||||
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
|
||||
u8 split_data[4] = {0}; //16bit数据拆成4个4bit
|
||||
u8 i;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
u32 sdi0 = *(device+2);
|
||||
u32 sdi1 = *(device+3);
|
||||
u32 sdi2 = *(device+4);
|
||||
u32 sdi3 = *(device+5);
|
||||
|
||||
temp_addr = addr;
|
||||
temp_data = data;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 2;i++) // 8bit地址 四根线分两次传输
|
||||
{
|
||||
split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F; //sck高电平准备数据 数据从MCU到中间变量上
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
for(i = 0; i < 4;i++) //16bit数据 4根线分四次传输
|
||||
{
|
||||
split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
|
||||
//usleep(20);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
|
||||
* Description : forwire read from reg
|
||||
* Parameter : sdo0,sdo1,sdo2,sdo3--IO
|
||||
* Return : rxdata--数据
|
||||
******************************************************************************/
|
||||
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
|
||||
{
|
||||
u32 GPIO_PIN[4];
|
||||
u16 rdata[4];
|
||||
u16 rxdata = 0;
|
||||
|
||||
GPIO_PIN[0] = sdo0;
|
||||
GPIO_PIN[1] = sdo1;
|
||||
GPIO_PIN[2] = sdo2;
|
||||
GPIO_PIN[3] = sdo3;
|
||||
|
||||
for(u8 i = 0; i < 4 ; i++)
|
||||
{
|
||||
rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
|
||||
//xil_printf("rdata[i] = %x\r\n",rdata[i]);
|
||||
rxdata = ((rdata[i])<<i) + rxdata ;
|
||||
}
|
||||
return rxdata;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_read_fourwire(char addr, u16* rxdata, u32* device)
|
||||
* Description : spi fourwire read
|
||||
* Parameter : addr -- 地址
|
||||
* rxdata -- 数据
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_read_fourwire(char addr, u16* rxdata, u32* device) //接收数据使用指针传递，方便接收多个
|
||||
{
|
||||
u8 temp_addr = 0;
|
||||
u16 temp_data = 0;
|
||||
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
|
||||
u16 split_data[4] = {0}; //16bit数据拆成4个4bit
|
||||
u8 i = 0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
u32 sdio0 = *(device+2);
|
||||
u32 sdio1 = *(device+3);
|
||||
u32 sdio2 = *(device+4);
|
||||
u32 sdio3 = *(device+5);
|
||||
|
||||
temp_addr = addr;
|
||||
|
||||
split_addr[0] = (temp_addr >> 4)&0x0F;
|
||||
split_addr[1] = (temp_addr)&0x0F;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 2; i++) // 8bit地址 四根线分两次传输
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++)
|
||||
{
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0); //input
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++) //16bit数据 4根线分四次接收
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3); //sck低电平准备数据 数据从通信线到中间变量上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
temp_data = temp_data<<4;
|
||||
temp_data = temp_data + split_data[i];
|
||||
//temp_data = (split_data[i]<<(4*(3-i))) + temp_data; //sck高电平接收数据 数据从中间变量到MCU上
|
||||
// xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
|
||||
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++)
|
||||
{
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1); //output
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
|
||||
*rxdata = temp_data;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
|
||||
//usleep(20);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void GPIO_dir_set(u32* device,char dir)
|
||||
* Description : change GPIO direction
|
||||
* Parameter : device -- CPLD
|
||||
* dir -- GPIO_OUT/GPIO_IN
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void GPIO_dir_set_16(u32* device,char dir)
|
||||
{
|
||||
u32 sdio[16] = {0};
|
||||
u8 i;
|
||||
|
||||
for(i = 0; i < 16;i++)
|
||||
{
|
||||
sdio[i] = *(device+i);
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void GPIO_dir_set_cs_enable(u32* device,u8 dir)
|
||||
{
|
||||
u32 sdio[4] = {0};
|
||||
u8 i;
|
||||
u8 dir_temp = 0;
|
||||
|
||||
for(i = 0; i < 4;i++)
|
||||
{
|
||||
sdio[i] = *(device+i);
|
||||
dir_temp = (((dir >> (3-i))) & 0x01);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void rst(char *d)
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
|
||||
usleep(20);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
|
||||
}
|
||||
|
||||
|
||||
void func_test(void)
|
||||
{
|
||||
|
||||
XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
|
||||
}
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+87
@@ -0,0 +1,87 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+244
@@ -0,0 +1,244 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00220000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
sw_config_data[0] = (u8)(cpld_dat>>16);
|
||||
sw_config_data[1] = (u8)(cpld_dat>>8);
|
||||
sw_config_data[2] = (u8)(cpld_dat);
|
||||
|
||||
xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
|
||||
xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
|
||||
|
||||
xil_printf("cpld_addr: %d\n\r", cpld_addr);
|
||||
xil_printf("cpld_dat: %d\n\r", cpld_dat);
|
||||
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
|
||||
sw_config_data[0] = 0x00;
|
||||
sw_config_data[1] = 0x00;
|
||||
sw_config_data[2] = 0x01;
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
|
||||
}
|
||||
|
||||
|
||||
|
||||
+241
@@ -0,0 +1,241 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00220000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
|
||||
xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
sw_config_data[0] = (u8)(cpld_dat>>16);
|
||||
sw_config_data[1] = (u8)(cpld_dat>>8);
|
||||
sw_config_data[2] = (u8)(cpld_dat);
|
||||
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
|
||||
|
||||
sw_config_data[0] = 0x00;
|
||||
sw_config_data[1] = 0x00;
|
||||
sw_config_data[2] = 0x01;
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
|
||||
}
|
||||
|
||||
|
||||
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+108
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
/*-------------------------------------CPLD_U3------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
}
|
||||
+84
@@ -0,0 +1,84 @@
|
||||
/*
|
||||
* cal_meas.h
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#ifndef SRC_CAL_MEAS_H_
|
||||
#define SRC_CAL_MEAS_H_
|
||||
|
||||
#include "sleep.h"
|
||||
#include "stdio.h"
|
||||
#include "xgpiops.h"
|
||||
#include "SPI_Driv.h"
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
//reg addr(CPLD_U1)
|
||||
#define U1_SW_FC_DV0 1
|
||||
#define U1_SW_FC_DV1 2
|
||||
#define U1_SW_FC_DV2 3
|
||||
#define U1_SW_FC_DV3 4
|
||||
|
||||
#define U1_SW_SC_DV0 5
|
||||
#define U1_SW_SC_DV1 6
|
||||
#define U1_SW_SC_DV2 7
|
||||
#define U1_SW_SC_DV3 8
|
||||
|
||||
#define U1_SW_OC_DV0 9
|
||||
#define U1_SW_OC_DV1 10
|
||||
|
||||
#define U1_SW_OC_DV2 11
|
||||
#define U1_SW_OC_DV3 12
|
||||
|
||||
#define U1_SW_OC_DV4 13
|
||||
#define U1_SW_OC_DV5 14
|
||||
|
||||
#define U1_SW_OC_DV6 15
|
||||
#define U1_SW_OC_DV7 16
|
||||
|
||||
#define U1_SW_FMC_SMC 17
|
||||
#define U1_SW_OC_DMM 18
|
||||
#define U1_SW_MMC 19
|
||||
#define U1_SW_RC 20
|
||||
#define U1_SW_IO_RC 21
|
||||
#define U1_SW_RL1 22
|
||||
#define U1_SW_RL2 23
|
||||
#define U1_SW_LOFS_VPK 24
|
||||
#define U1_SW_LOFS_APK 25
|
||||
|
||||
|
||||
//reg addr(CPLD_U2)
|
||||
#define U2_SW_FC_DV0 1
|
||||
#define U2_SW_FC_DV1 2
|
||||
#define U2_SW_FC_DV2 3
|
||||
#define U2_SW_FC_DV3 4
|
||||
|
||||
#define U2_SW_SC_DV0 5
|
||||
#define U2_SW_SC_DV1 6
|
||||
#define U2_SW_SC_DV2 7
|
||||
#define U2_SW_SC_DV3 8
|
||||
|
||||
#define U2_SW_OC_DV0 9
|
||||
#define U2_SW_OC_DV1 10
|
||||
|
||||
#define U2_SW_OC_DV2 11
|
||||
#define U2_SW_OC_DV3 12
|
||||
|
||||
#define U2_SW_OC_DV4 13
|
||||
#define U2_SW_OC_DV5 14
|
||||
|
||||
#define U2_SW_OC_DV6 15
|
||||
#define U2_SW_OC_DV7 16
|
||||
|
||||
#define dat_width 3
|
||||
|
||||
void sw_init( void );
|
||||
void sw_config(char *slot_start);
|
||||
void fsmc_mmc_config(char slot,char m_fun);
|
||||
void dmm_config(char slot, u16 ch_num);
|
||||
void rc_config(char m_fun);
|
||||
void fsc_oc_config(char slot,char m_fun, u16 ch_num);
|
||||
void rl_config(char load);
|
||||
|
||||
#endif /* SRC_CAL_MEAS_H_ */
|
||||
+97
@@ -0,0 +1,97 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+219
@@ -0,0 +1,219 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
+286
@@ -0,0 +1,286 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0xFF,0xFF,0xFF};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 u1_io_rc_dat = 0;
|
||||
u16 u1_rc_dat = 0;
|
||||
u16 u1_lofs_vpk_dat = 0;
|
||||
u16 u1_lofs_apk_dat = 0;
|
||||
u16 u1_lofs_vpk_apk_dat = 0;
|
||||
|
||||
u16 ch_num = 0;
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
//xil_printf("slot: %d\n\r", slot);
|
||||
//xil_printf("m_fun: %d\n\r", m_fun);
|
||||
//xil_printf("ch_num: %d\n\r", ch_num);
|
||||
fsc_oc_config(slot,m_fun,ch_num);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
dmm_config(slot,ch_num);
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
void dmm_config(char slot, u16 ch_num)
|
||||
{
|
||||
u16 sw_oc_dmm_dat = 0;
|
||||
if(ch_num>=1&&ch_num<=64)
|
||||
{
|
||||
sw_oc_dmm_dat = (0x0001<<((slot-1)*4));
|
||||
sw_oc_dmm_dat = ~sw_oc_dmm_dat;
|
||||
}
|
||||
else if(ch_num>=65&&ch_num<=128)
|
||||
{
|
||||
sw_oc_dmm_dat = (0x0001<<((slot-1)*4+1));
|
||||
sw_oc_dmm_dat = ~sw_oc_dmm_dat;
|
||||
}
|
||||
else if(ch_num>=129&&ch_num<=192)
|
||||
{
|
||||
sw_oc_dmm_dat = (0x0001<<((slot-1)*4+2));
|
||||
sw_oc_dmm_dat = ~sw_oc_dmm_dat;
|
||||
}
|
||||
else
|
||||
{
|
||||
sw_oc_dmm_dat = (0x0001<<((slot-1)*4+3));
|
||||
sw_oc_dmm_dat = ~sw_oc_dmm_dat;
|
||||
}
|
||||
//xil_printf("oc_dmm_dat: %x\n\r", sw_oc_dmm_dat);
|
||||
sw_config_data[0] = (u8)(sw_oc_dmm_dat>>8);
|
||||
sw_config_data[1] = (u8)(sw_oc_dmm_dat);
|
||||
spi_write_onewire(U1_SW_OC_DMM, sw_config_data, dat_width, CPLD_U1);
|
||||
|
||||
}
|
||||
|
||||
void rc_config(char m_fun)
|
||||
{
|
||||
u16 rc_dat = 0;
|
||||
switch(m_fun)
|
||||
{
|
||||
case 0x01:
|
||||
{
|
||||
rc_dat = 0xFFFD;
|
||||
break;
|
||||
}
|
||||
case 0x02:
|
||||
{
|
||||
rc_dat = 0xFFFB;
|
||||
break;
|
||||
}
|
||||
case 0x03:
|
||||
{
|
||||
rc_dat = 0xFFF9;
|
||||
break;
|
||||
}
|
||||
}
|
||||
//xil_printf("rc_dat: %x\n\r", rc_dat);
|
||||
sw_config_data[0] = (u8)(rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
}
|
||||
|
||||
void rl_config(char load)
|
||||
{
|
||||
u16 rl_dat = 0;
|
||||
if(load>=1&&load<=9)
|
||||
{
|
||||
rl_dat = (0x0001<<(load-1));
|
||||
rl_dat = ~rl_dat;
|
||||
//xil_printf("load: %x\n\r", load);
|
||||
//xil_printf("rl_01_dat: %x\n\r", rl_dat);
|
||||
sw_config_data[0] = (u8)(rl_dat>>8);
|
||||
sw_config_data[1] = (u8)(rl_dat);
|
||||
spi_write_onewire(U1_SW_RL1, sw_config_data, dat_width, CPLD_U1);
|
||||
}
|
||||
else
|
||||
{
|
||||
rl_dat = (0x0001<<(load-10));
|
||||
rl_dat = ~rl_dat;
|
||||
//xil_printf("load: %x\n\r", load);
|
||||
//xil_printf("rl_02_dat: %x\n\r", rl_dat);
|
||||
sw_config_data[0] = (u8)(rl_dat>>8);
|
||||
sw_config_data[1] = (u8)(rl_dat);
|
||||
spi_write_onewire(U1_SW_RL2, sw_config_data, dat_width, CPLD_U1);
|
||||
}
|
||||
}
|
||||
|
||||
void fsc_oc_config(char slot,char m_fun, u16 ch_num)
|
||||
{
|
||||
u16 fc_dv0_dat = 0;
|
||||
switch(m_fun)
|
||||
{
|
||||
case 0x01:
|
||||
{
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x01,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
}
|
||||
else
|
||||
{
|
||||
//xil_printf("m_fun=0x01,ch_num=17~32 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-17));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U2_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
|
||||
//xil_printf("CPLD_U2:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U2_SW_FC_DV0+slot-1);
|
||||
}
|
||||
//xil_printf("reg_data: %x\n\r", fc_dv0_dat);
|
||||
break;
|
||||
}
|
||||
case 0x02:
|
||||
{
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x02,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
else
|
||||
{
|
||||
//xil_printf("m_fun=0x02,ch_num=17~32 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-17));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U2_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
|
||||
//xil_printf("CPLD_U2:\n\r");
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U2_SW_SC_DV0+slot-1);
|
||||
}
|
||||
//xil_printf("reg_data: %x\n\r", fc_dv0_dat);
|
||||
break;
|
||||
}
|
||||
case 0x03:
|
||||
{
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=17~32 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-17));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U2_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(U2_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U2);
|
||||
//xil_printf("CPLD_U2:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U2_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U2_SW_SC_DV0+slot-1);
|
||||
}
|
||||
//xil_printf("reg_data: %x\n\r", fc_dv0_dat);
|
||||
break;
|
||||
}
|
||||
case 0x04:
|
||||
{
|
||||
if(ch_num>=1&&ch_num<=64)
|
||||
{
|
||||
//xil_printf("m_fun=0x04,ch_num=1~64 \n\r");
|
||||
fc_dv0_dat = (0x0001<<((ch_num-1)/8));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_OC_DV0+(slot-1)*2, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("oc_reg_addr: %d\n\r", U1_SW_OC_DV0+(slot-1)*2);
|
||||
}
|
||||
else if(ch_num>=65&&ch_num<=128)
|
||||
{
|
||||
//xil_printf("m_fun=0x04,ch_num=65~128 \n\r");
|
||||
fc_dv0_dat = (0x0001<<((ch_num-65)/8));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U2_SW_OC_DV0+(slot-1)*2, sw_config_data, dat_width, CPLD_U2);
|
||||
//xil_printf("CPLD_U2:\n\r");
|
||||
//xil_printf("oc_reg_addr: %d\n\r", U2_SW_OC_DV0+(slot-1)*2);
|
||||
}
|
||||
else if(ch_num>=129&&ch_num<=192)
|
||||
{
|
||||
//xil_printf("m_fun=0x04,ch_num=129~192 \n\r");
|
||||
fc_dv0_dat = (0x0001<<((ch_num-129)/8));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_OC_DV1+(slot-1)*2, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("oc_reg_addr: %d\n\r", U1_SW_OC_DV1+(slot-1)*2);
|
||||
}
|
||||
else if(ch_num>=193&&ch_num<=256)
|
||||
{
|
||||
//xil_printf("m_fun=0x04,ch_num=193~256 \n\r");
|
||||
fc_dv0_dat = (0x0001<<((ch_num-193)/8));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U2_SW_OC_DV1+(slot-1)*2, sw_config_data, dat_width, CPLD_U2);
|
||||
//xil_printf("CPLD_U2:\n\r");
|
||||
//xil_printf("oc_reg_addr: %d\n\r", U2_SW_OC_DV1+(slot-1)*2);
|
||||
}
|
||||
//xil_printf("reg_data: %x\n\r", fc_dv0_dat);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+108
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);//68---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);//69---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
/*-------------------------------------CPLD_U3------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//78---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//79---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 0);//80---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 1);//77---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
}
|
||||
+108
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
/*-------------------------------------CPLD_U3------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
}
|
||||
+66
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32
|
||||
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+221
@@ -0,0 +1,221 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start, u32 CPLD_UU[11])
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0xFF,0xFF,0xFF};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0xFF,0xFF,0xFF};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+555
@@ -0,0 +1,555 @@
|
||||
/*
|
||||
* SPI_Driv.c
|
||||
*
|
||||
* Created on: 2021年4月2日
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "SPI_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
|
||||
|
||||
extern u32 K7_U0[16];
|
||||
extern u32 molex_4_bank_3[4];
|
||||
extern u32 cs_en_bank_3[4];
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void interface_initial(u32* device,u32 num_wire)
|
||||
* Description : interface initial
|
||||
* Parameter : device -- CPLD
|
||||
* num_wire -- 复位线编号
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void interface_initial(u32* device) //wire_num = cs sck sdi/o
|
||||
{
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void rst_CPLD(u32* device,u32 num_wire)
|
||||
* Description : CPLD reset
|
||||
* Parameter : device -- CPLD
|
||||
* num_wire -- 复位线编号
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
|
||||
{
|
||||
u32 rst_n = *(device+num_wire);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
|
||||
usleep(2);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_write_onewire(char addr, u32 data, char width, u32* device)
|
||||
* Description : spi onewire write
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_write_onewire(char addr, char *data, char width, u32* device)
|
||||
{
|
||||
char temp_addr = 0;
|
||||
//u32 temp_data = 0;
|
||||
u32 temp_data = 0;
|
||||
char i = 0,j=0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs= *(device+1);
|
||||
u32 sdi= *(device+2);
|
||||
|
||||
temp_addr = addr;
|
||||
///temp_data = data;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 8; i++) // 8bit地址
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_addr&0x80)
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
|
||||
}
|
||||
|
||||
for(j=0;j<width;j++)
|
||||
{
|
||||
temp_data = *(data+j);
|
||||
for(i = 0; i < 8; i++) //nbit数据
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_data&0x80) //注意数据位nbit，要从[n-1]取位
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_data <<= 1;
|
||||
}
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs , 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : u32 spi_read_onewire(char addr, char width, u32* device)
|
||||
* Description : spi onewire read
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
u32 spi_read_onewire(char addr, char width, u32* device)
|
||||
{
|
||||
char temp_addr=0;
|
||||
u32 temp_data=0;
|
||||
char i=0,j=0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs= *(device+1);
|
||||
u32 sdi= *(device+2);
|
||||
u32 sdo= *(device+3);
|
||||
|
||||
temp_addr = addr;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 8; i++) // 8bit地址
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_addr&0x80)
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
|
||||
}
|
||||
|
||||
for(j=0; j<width; j++)
|
||||
{
|
||||
for(i = 0; i < 8; i++) //nbit数据
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
temp_data = temp_data << 1; //sck低电平准备数据 准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo)) //sck高电平接收数据 数据匹配到准备好的数位，等待一起传递到MCU
|
||||
temp_data = temp_data| 0x00000001;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
}
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
return temp_data;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
|
||||
* Description : forwire write to reg
|
||||
* Parameter : txdata--数据
|
||||
* sdi0,sdi1,sdi2,sdi3--IO
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
|
||||
{
|
||||
switch(txdata & 0x0F)
|
||||
{
|
||||
case 0x00:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x01:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x02:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x03:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x04:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x05:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x06:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x07:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x08:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x09:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0A:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0B:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0C:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0D:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0E:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0F:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_write_fourwire(char addr, u16 data, u32* device)
|
||||
* Description : spi fourwire write
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_write_fourwire(char addr, u16 data, u32* device)
|
||||
{
|
||||
u8 temp_addr = 0;
|
||||
u16 temp_data = 0;
|
||||
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
|
||||
u8 split_data[4] = {0}; //16bit数据拆成4个4bit
|
||||
u8 i;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
u32 sdi0 = *(device+2);
|
||||
u32 sdi1 = *(device+3);
|
||||
u32 sdi2 = *(device+4);
|
||||
u32 sdi3 = *(device+5);
|
||||
|
||||
temp_addr = addr;
|
||||
temp_data = data;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 2;i++) // 8bit地址 四根线分两次传输
|
||||
{
|
||||
split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F; //sck高电平准备数据 数据从MCU到中间变量上
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
for(i = 0; i < 4;i++) //16bit数据 4根线分四次传输
|
||||
{
|
||||
split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
|
||||
//usleep(20);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
|
||||
* Description : forwire read from reg
|
||||
* Parameter : sdo0,sdo1,sdo2,sdo3--IO
|
||||
* Return : rxdata--数据
|
||||
******************************************************************************/
|
||||
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
|
||||
{
|
||||
u32 GPIO_PIN[4];
|
||||
u16 rdata[4];
|
||||
u16 rxdata = 0;
|
||||
|
||||
GPIO_PIN[0] = sdo0;
|
||||
GPIO_PIN[1] = sdo1;
|
||||
GPIO_PIN[2] = sdo2;
|
||||
GPIO_PIN[3] = sdo3;
|
||||
|
||||
for(u8 i = 0; i < 4 ; i++)
|
||||
{
|
||||
rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
|
||||
//xil_printf("rdata[i] = %x\r\n",rdata[i]);
|
||||
rxdata = ((rdata[i])<<i) + rxdata ;
|
||||
}
|
||||
return rxdata;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_read_fourwire(char addr, u16* rxdata, u32* device)
|
||||
* Description : spi fourwire read
|
||||
* Parameter : addr -- 地址
|
||||
* rxdata -- 数据
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_read_fourwire(char addr, u16* rxdata, u32* device) //接收数据使用指针传递，方便接收多个
|
||||
{
|
||||
u8 temp_addr = 0;
|
||||
u16 temp_data = 0;
|
||||
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
|
||||
u16 split_data[4] = {0}; //16bit数据拆成4个4bit
|
||||
u8 i = 0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
u32 sdio0 = *(device+2);
|
||||
u32 sdio1 = *(device+3);
|
||||
u32 sdio2 = *(device+4);
|
||||
u32 sdio3 = *(device+5);
|
||||
|
||||
temp_addr = addr;
|
||||
|
||||
split_addr[0] = (temp_addr >> 4)&0x0F;
|
||||
split_addr[1] = (temp_addr)&0x0F;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 2; i++) // 8bit地址 四根线分两次传输
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++)
|
||||
{
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0); //input
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++) //16bit数据 4根线分四次接收
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3); //sck低电平准备数据 数据从通信线到中间变量上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
temp_data = temp_data<<4;
|
||||
temp_data = temp_data + split_data[i];
|
||||
//temp_data = (split_data[i]<<(4*(3-i))) + temp_data; //sck高电平接收数据 数据从中间变量到MCU上
|
||||
// xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
|
||||
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++)
|
||||
{
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1); //output
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
|
||||
*rxdata = temp_data;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
|
||||
//usleep(20);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void GPIO_dir_set(u32* device,char dir)
|
||||
* Description : change GPIO direction
|
||||
* Parameter : device -- CPLD
|
||||
* dir -- GPIO_OUT/GPIO_IN
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void GPIO_dir_set_16(u32* device,char dir)
|
||||
{
|
||||
u32 sdio[16] = {0};
|
||||
u8 i;
|
||||
|
||||
for(i = 0; i < 16;i++)
|
||||
{
|
||||
sdio[i] = *(device+i);
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void GPIO_dir_set_cs_enable(u32* device,u8 dir)
|
||||
{
|
||||
u32 sdio[4] = {0};
|
||||
u8 i;
|
||||
u8 dir_temp = 0;
|
||||
|
||||
for(i = 0; i < 4;i++)
|
||||
{
|
||||
sdio[i] = *(device+i);
|
||||
dir_temp = (((dir >> (3-i))) & 0x01);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void rst(char *d)
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
|
||||
usleep(20);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
|
||||
}
|
||||
|
||||
|
||||
void func_test(void)
|
||||
{
|
||||
|
||||
XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
|
||||
}
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{ cpld_addr = 0x82;}
|
||||
else if(slot==2)
|
||||
{ cpld_addr = 0x83;}
|
||||
else if(slot==3)
|
||||
{ cpld_addr = 0x84;}
|
||||
else
|
||||
{ cpld_addr = 0x85;}
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{ cpld_addr = 0x82;}
|
||||
else if(slot==2)
|
||||
{ cpld_addr = 0x83;}
|
||||
else if(slot==3)
|
||||
{ cpld_addr = 0x84;}
|
||||
else
|
||||
{ cpld_addr = 0x85;}
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+108
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
/*-------------------------------------CPLD_U3------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
}
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//58---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//55---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//56---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//57---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//60---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//60---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//60---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//62---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//63---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//64---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//65---rst
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
}
|
||||
+558
@@ -0,0 +1,558 @@
|
||||
/*
|
||||
* SPI_Driv.c
|
||||
*
|
||||
* Created on: 2021年4月2日
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "SPI_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
|
||||
|
||||
extern u32 K7_U0[16];
|
||||
extern u32 molex_4_bank_3[4];
|
||||
extern u32 cs_en_bank_3[4];
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void interface_initial(u32* device,u32 num_wire)
|
||||
* Description : interface initial
|
||||
* Parameter : device -- CPLD
|
||||
* num_wire -- 复位线编号
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void interface_initial(u32* device) //wire_num = cs sck sdi/o
|
||||
{
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void rst_CPLD(u32* device,u32 num_wire)
|
||||
* Description : CPLD reset
|
||||
* Parameter : device -- CPLD
|
||||
* num_wire -- 复位线编号
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
|
||||
{
|
||||
u32 rst_n = *(device+num_wire);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
|
||||
usleep(2);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_write_onewire(char addr, u32 data, char width, u32* device)
|
||||
* Description : spi onewire write
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_write_onewire(char addr, char *data, char width, u32* device)
|
||||
{
|
||||
char temp_addr = 0;
|
||||
//u32 temp_data = 0;
|
||||
u32 temp_data = 0;
|
||||
char i = 0,j=0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs= *(device+1);
|
||||
u32 sdi= *(device+2);
|
||||
|
||||
temp_addr = addr;
|
||||
///temp_data = data;
|
||||
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); // w/r标志位 1=w 0=r
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 8; i++) // 8bit地址
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_addr&0x80)
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
|
||||
}
|
||||
|
||||
for(j=0;j<width;j++)
|
||||
{
|
||||
temp_data = *(data+j);
|
||||
for(i = 0; i < 8; i++) //nbit数据
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_data&0x80) //注意数据位nbit，要从[n-1]取位
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_data <<= 1;
|
||||
}
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs , 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : u32 spi_read_onewire(char addr, char width, u32* device)
|
||||
* Description : spi onewire read
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
u32 spi_read_onewire(char addr, char width, u32* device,char* read_data)
|
||||
{
|
||||
char temp_addr=0;
|
||||
u32 temp_data=0;
|
||||
char i=0,j=0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs= *(device+1);
|
||||
u32 sdi= *(device+2);
|
||||
u32 sdo= *(device+3);
|
||||
|
||||
temp_addr = addr;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 8; i++) // 8bit地址
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_addr&0x80)
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
|
||||
}
|
||||
|
||||
for(j=0; j<width; j++)
|
||||
{
|
||||
for(i = 0; i < 8; i++) //nbit数据
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
temp_data = temp_data << 1; //sck低电平准备数据 准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo)) //sck高电平接收数据 数据匹配到准备好的数位，等待一起传递到MCU
|
||||
temp_data = temp_data| 0x00000001;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
}
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
read_data[0] = (u8)(temp_data>>16);
|
||||
read_data[1] = (u8)(temp_data>>8);
|
||||
read_data[0] = (u8)(temp_data);
|
||||
return temp_data;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
|
||||
* Description : forwire write to reg
|
||||
* Parameter : txdata--数据
|
||||
* sdi0,sdi1,sdi2,sdi3--IO
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
|
||||
{
|
||||
switch(txdata & 0x0F)
|
||||
{
|
||||
case 0x00:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x01:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x02:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x03:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x04:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x05:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x06:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x07:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x08:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x09:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0A:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0B:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0C:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0D:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0E:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0F:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_write_fourwire(char addr, u16 data, u32* device)
|
||||
* Description : spi fourwire write
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_write_fourwire(char addr, u16 data, u32* device)
|
||||
{
|
||||
u8 temp_addr = 0;
|
||||
u16 temp_data = 0;
|
||||
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
|
||||
u8 split_data[4] = {0}; //16bit数据拆成4个4bit
|
||||
u8 i;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
u32 sdi0 = *(device+2);
|
||||
u32 sdi1 = *(device+3);
|
||||
u32 sdi2 = *(device+4);
|
||||
u32 sdi3 = *(device+5);
|
||||
|
||||
temp_addr = addr;
|
||||
temp_data = data;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 2;i++) // 8bit地址 四根线分两次传输
|
||||
{
|
||||
split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F; //sck高电平准备数据 数据从MCU到中间变量上
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
for(i = 0; i < 4;i++) //16bit数据 4根线分四次传输
|
||||
{
|
||||
split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
|
||||
//usleep(20);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
|
||||
* Description : forwire read from reg
|
||||
* Parameter : sdo0,sdo1,sdo2,sdo3--IO
|
||||
* Return : rxdata--数据
|
||||
******************************************************************************/
|
||||
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
|
||||
{
|
||||
u32 GPIO_PIN[4];
|
||||
u16 rdata[4];
|
||||
u16 rxdata = 0;
|
||||
|
||||
GPIO_PIN[0] = sdo0;
|
||||
GPIO_PIN[1] = sdo1;
|
||||
GPIO_PIN[2] = sdo2;
|
||||
GPIO_PIN[3] = sdo3;
|
||||
|
||||
for(u8 i = 0; i < 4 ; i++)
|
||||
{
|
||||
rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
|
||||
//xil_printf("rdata[i] = %x\r\n",rdata[i]);
|
||||
rxdata = ((rdata[i])<<i) + rxdata ;
|
||||
}
|
||||
return rxdata;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_read_fourwire(char addr, u16* rxdata, u32* device)
|
||||
* Description : spi fourwire read
|
||||
* Parameter : addr -- 地址
|
||||
* rxdata -- 数据
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_read_fourwire(char addr, u16* rxdata, u32* device) //接收数据使用指针传递，方便接收多个
|
||||
{
|
||||
u8 temp_addr = 0;
|
||||
u16 temp_data = 0;
|
||||
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
|
||||
u16 split_data[4] = {0}; //16bit数据拆成4个4bit
|
||||
u8 i = 0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
u32 sdio0 = *(device+2);
|
||||
u32 sdio1 = *(device+3);
|
||||
u32 sdio2 = *(device+4);
|
||||
u32 sdio3 = *(device+5);
|
||||
|
||||
temp_addr = addr;
|
||||
|
||||
split_addr[0] = (temp_addr >> 4)&0x0F;
|
||||
split_addr[1] = (temp_addr)&0x0F;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 2; i++) // 8bit地址 四根线分两次传输
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++)
|
||||
{
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0); //input
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++) //16bit数据 4根线分四次接收
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3); //sck低电平准备数据 数据从通信线到中间变量上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
temp_data = temp_data<<4;
|
||||
temp_data = temp_data + split_data[i];
|
||||
//temp_data = (split_data[i]<<(4*(3-i))) + temp_data; //sck高电平接收数据 数据从中间变量到MCU上
|
||||
// xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
|
||||
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++)
|
||||
{
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1); //output
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
|
||||
*rxdata = temp_data;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
|
||||
//usleep(20);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void GPIO_dir_set(u32* device,char dir)
|
||||
* Description : change GPIO direction
|
||||
* Parameter : device -- CPLD
|
||||
* dir -- GPIO_OUT/GPIO_IN
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void GPIO_dir_set_16(u32* device,char dir)
|
||||
{
|
||||
u32 sdio[16] = {0};
|
||||
u8 i;
|
||||
|
||||
for(i = 0; i < 16;i++)
|
||||
{
|
||||
sdio[i] = *(device+i);
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void GPIO_dir_set_cs_enable(u32* device,u8 dir)
|
||||
{
|
||||
u32 sdio[4] = {0};
|
||||
u8 i;
|
||||
u8 dir_temp = 0;
|
||||
|
||||
for(i = 0; i < 4;i++)
|
||||
{
|
||||
sdio[i] = *(device+i);
|
||||
dir_temp = (((dir >> (3-i))) & 0x01);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void rst(char *d)
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
|
||||
usleep(20);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
|
||||
}
|
||||
|
||||
|
||||
void func_test(void)
|
||||
{
|
||||
|
||||
XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
|
||||
}
|
||||
+80
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//---sdio3
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//---sdio4
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//---sdio5
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//---sdio6
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//---sdio7
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
}
|
||||
+242
@@ -0,0 +1,242 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00220000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
sw_config_data[0] = (u8)(cpld_dat>>16);
|
||||
sw_config_data[1] = (u8)(cpld_dat>>8);
|
||||
sw_config_data[2] = (u8)(cpld_dat);
|
||||
|
||||
xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
|
||||
xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
|
||||
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
|
||||
xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
|
||||
|
||||
sw_config_data[0] = 0x00;
|
||||
sw_config_data[1] = 0x00;
|
||||
sw_config_data[2] = 0x01;
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
|
||||
}
|
||||
|
||||
|
||||
|
||||
+108
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
/*-------------------------------------CPLD_U3------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
}
|
||||
+108
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
/*-------------------------------------CPLD_U3------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//66---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//67---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//68---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//66
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//67
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
}
|
||||
+223
@@ -0,0 +1,223 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start, u32 CPLD_UU[11])
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
}
|
||||
|
||||
|
||||
|
||||
+235
@@ -0,0 +1,235 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
sw_config_data[0] = (u8)(cpld_dat>>16);
|
||||
sw_config_data[1] = (u8)(cpld_dat>>8);
|
||||
sw_config_data[2] = (u8)(cpld_dat);
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
|
||||
|
||||
sw_config_data[0] = 0x00;
|
||||
sw_config_data[1] = 0x00;
|
||||
sw_config_data[2] = 0x01;
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
|
||||
}
|
||||
|
||||
|
||||
|
||||
+558
@@ -0,0 +1,558 @@
|
||||
/*
|
||||
* SPI_Driv.c
|
||||
*
|
||||
* Created on: 2021年4月2日
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "SPI_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
|
||||
|
||||
extern u32 K7_U0[16];
|
||||
extern u32 molex_4_bank_3[4];
|
||||
extern u32 cs_en_bank_3[4];
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void interface_initial(u32* device,u32 num_wire)
|
||||
* Description : interface initial
|
||||
* Parameter : device -- CPLD
|
||||
* num_wire -- 复位线编号
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void interface_initial(u32* device) //wire_num = cs sck sdi/o
|
||||
{
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void rst_CPLD(u32* device,u32 num_wire)
|
||||
* Description : CPLD reset
|
||||
* Parameter : device -- CPLD
|
||||
* num_wire -- 复位线编号
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void rst_CPLD(u32* device,u32 num_wire) //wire_num = cs sck sdi/o
|
||||
{
|
||||
u32 rst_n = *(device+num_wire);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 1);
|
||||
usleep(2);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, rst_n, 0);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_write_onewire(char addr, u32 data, char width, u32* device)
|
||||
* Description : spi onewire write
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_write_onewire(char addr, char *data, char width, u32* device)
|
||||
{
|
||||
char temp_addr = 0;
|
||||
//u32 temp_data = 0;
|
||||
u32 temp_data = 0;
|
||||
char i = 0,j=0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs= *(device+1);
|
||||
u32 sdi= *(device+2);
|
||||
|
||||
temp_addr = addr;
|
||||
///temp_data = data;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 8; i++) // 8bit地址
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_addr&0x80)
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
|
||||
}
|
||||
|
||||
for(j=0;j<width;j++)
|
||||
{
|
||||
temp_data = *(data+j);
|
||||
for(i = 0; i < 8; i++) //nbit数据
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_data&0x80) //注意数据位nbit，要从[n-1]取位
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1);
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_data <<= 1;
|
||||
}
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs , 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : u32 spi_read_onewire(char addr, char width, u32* device)
|
||||
* Description : spi onewire read
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
u32 spi_read_onewire(char addr, char width, u32* device,char* read_data)
|
||||
{
|
||||
char temp_addr=0;
|
||||
u32 temp_data=0;
|
||||
char i=0,j=0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs= *(device+1);
|
||||
u32 sdi= *(device+2);
|
||||
u32 sdo= *(device+3);
|
||||
|
||||
temp_addr = addr;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 8; i++) // 8bit地址
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
if(temp_addr&0x80)
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
else
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
|
||||
}
|
||||
|
||||
for(j=0; j<width; j++)
|
||||
{
|
||||
for(i = 0; i < 8; i++) //nbit数据
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
temp_data = temp_data << 1; //sck低电平准备数据 准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo)) //sck高电平接收数据 数据匹配到准备好的数位，等待一起传递到MCU
|
||||
temp_data = temp_data| 0x00000001;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
}
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
|
||||
read_data[0] = (u8)(temp_data>>16);
|
||||
read_data[1] = (u8)(temp_data>>8);
|
||||
read_data[0] = (u8)(temp_data);
|
||||
return temp_data;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
|
||||
* Description : forwire write to reg
|
||||
* Parameter : txdata--数据
|
||||
* sdi0,sdi1,sdi2,sdi3--IO
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
|
||||
{
|
||||
switch(txdata & 0x0F)
|
||||
{
|
||||
case 0x00:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x01:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x02:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x03:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x04:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x05:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x06:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x07:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 0);
|
||||
break;
|
||||
}
|
||||
case 0x08:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x09:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0A:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0B:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0C:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0D:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0E:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
case 0x0F:
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi0, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi1, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi2, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sdi3, 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_write_fourwire(char addr, u16 data, u32* device)
|
||||
* Description : spi fourwire write
|
||||
* Parameter : addr -- 地址
|
||||
* data -- 数据
|
||||
* width -- 数据长度
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_write_fourwire(char addr, u16 data, u32* device)
|
||||
{
|
||||
u8 temp_addr = 0;
|
||||
u16 temp_data = 0;
|
||||
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
|
||||
u8 split_data[4] = {0}; //16bit数据拆成4个4bit
|
||||
u8 i;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
u32 sdi0 = *(device+2);
|
||||
u32 sdi1 = *(device+3);
|
||||
u32 sdi2 = *(device+4);
|
||||
u32 sdi3 = *(device+5);
|
||||
|
||||
temp_addr = addr;
|
||||
temp_data = data;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
fourwire_write(0x01,sdi0,sdi1,sdi2,sdi3); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 2;i++) // 8bit地址 四根线分两次传输
|
||||
{
|
||||
split_addr[i] = (temp_addr>>(4*(1-i)))&0x0F; //sck高电平准备数据 数据从MCU到中间变量上
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_addr[i],sdi0,sdi1,sdi2,sdi3); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
for(i = 0; i < 4;i++) //16bit数据 4根线分四次传输
|
||||
{
|
||||
split_data[i] = (temp_data>>(4*(3-i)))&0x0F;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_data[i],sdi0,sdi1,sdi2,sdi3);
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
fourwire_write(0x00,sdi0,sdi1,sdi2,sdi3);
|
||||
//usleep(20);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
|
||||
* Description : forwire read from reg
|
||||
* Parameter : sdo0,sdo1,sdo2,sdo3--IO
|
||||
* Return : rxdata--数据
|
||||
******************************************************************************/
|
||||
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3)
|
||||
{
|
||||
u32 GPIO_PIN[4];
|
||||
u16 rdata[4];
|
||||
u16 rxdata = 0;
|
||||
|
||||
GPIO_PIN[0] = sdo0;
|
||||
GPIO_PIN[1] = sdo1;
|
||||
GPIO_PIN[2] = sdo2;
|
||||
GPIO_PIN[3] = sdo3;
|
||||
|
||||
for(u8 i = 0; i < 4 ; i++)
|
||||
{
|
||||
rdata[i] = XGpioPs_ReadPin(&psGpioInstancePtr,GPIO_PIN[i]);
|
||||
//xil_printf("rdata[i] = %x\r\n",rdata[i]);
|
||||
rxdata = ((rdata[i])<<i) + rxdata ;
|
||||
}
|
||||
return rxdata;
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void spi_read_fourwire(char addr, u16* rxdata, u32* device)
|
||||
* Description : spi fourwire read
|
||||
* Parameter : addr -- 地址
|
||||
* rxdata -- 数据
|
||||
* device -- CPLD
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void spi_read_fourwire(char addr, u16* rxdata, u32* device) //接收数据使用指针传递，方便接收多个
|
||||
{
|
||||
u8 temp_addr = 0;
|
||||
u16 temp_data = 0;
|
||||
u8 split_addr[2] = {0}; //将8bit地址拆分，分别给4线传输，
|
||||
u16 split_data[4] = {0}; //16bit数据拆成4个4bit
|
||||
u8 i = 0;
|
||||
u32 sck = *(device+0);
|
||||
u32 cs = *(device+1);
|
||||
u32 sdio0 = *(device+2);
|
||||
u32 sdio1 = *(device+3);
|
||||
u32 sdio2 = *(device+4);
|
||||
u32 sdio3 = *(device+5);
|
||||
|
||||
temp_addr = addr;
|
||||
|
||||
split_addr[0] = (temp_addr >> 4)&0x0F;
|
||||
split_addr[1] = (temp_addr)&0x0F;
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
|
||||
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3); // w/r标志位 1=w 0=r
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
for(i = 0; i < 2; i++) // 8bit地址 四根线分两次传输
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
fourwire_write(split_addr[i],sdio0,sdio1,sdio2,sdio3); //sck低电平传输数据 数据从中间变量到通信线上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++)
|
||||
{
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),0); //input
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++) //16bit数据 4根线分四次接收
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
|
||||
split_data[i] = fourwire_read(sdio0,sdio1,sdio2,sdio3); //sck低电平准备数据 数据从通信线到中间变量上
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
|
||||
|
||||
temp_data = temp_data<<4;
|
||||
temp_data = temp_data + split_data[i];
|
||||
//temp_data = (split_data[i]<<(4*(3-i))) + temp_data; //sck高电平接收数据 数据从中间变量到MCU上
|
||||
// xil_printf("split_data[i],temp_data = %x,%x\r\n",split_data[i],temp_data);
|
||||
|
||||
}
|
||||
|
||||
for(i = 0; i < 4; i++)
|
||||
{
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, *(device+2+i),1); //output
|
||||
}
|
||||
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
|
||||
fourwire_write(0x00,sdio0,sdio1,sdio2,sdio3);
|
||||
*rxdata = temp_data;
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);//add 2 lines
|
||||
//usleep(20);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
* Function : void GPIO_dir_set(u32* device,char dir)
|
||||
* Description : change GPIO direction
|
||||
* Parameter : device -- CPLD
|
||||
* dir -- GPIO_OUT/GPIO_IN
|
||||
* Return : void
|
||||
******************************************************************************/
|
||||
void GPIO_dir_set_16(u32* device,char dir)
|
||||
{
|
||||
u32 sdio[16] = {0};
|
||||
u8 i;
|
||||
|
||||
for(i = 0; i < 16;i++)
|
||||
{
|
||||
sdio[i] = *(device+i);
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, sdio[i],1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void GPIO_dir_set_cs_enable(u32* device,u8 dir)
|
||||
{
|
||||
u32 sdio[4] = {0};
|
||||
u8 i;
|
||||
u8 dir_temp = 0;
|
||||
|
||||
for(i = 0; i < 4;i++)
|
||||
{
|
||||
sdio[i] = *(device+i);
|
||||
dir_temp = (((dir >> (3-i))) & 0x01);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, sdio[i],dir_temp);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void rst(char *d)
|
||||
{
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 1);
|
||||
usleep(20);
|
||||
XGpioPs_WritePin(&psGpioInstancePtr, *d, 0);
|
||||
}
|
||||
|
||||
|
||||
void func_test(void)
|
||||
{
|
||||
|
||||
XGpioPs_Write(&psGpioInstancePtr, 0x03, 0x12345678);
|
||||
}
|
||||
+108
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//67---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//68---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);//69---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);//66---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
/*-------------------------------------CPLD_U3------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
}
|
||||
+77
@@ -0,0 +1,77 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//60---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//60---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//60---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//62---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//63---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//64---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//65---rst
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
}
|
||||
+241
@@ -0,0 +1,241 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00220000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
//xil_printf("relay_ctrl: %d\n\r", relay_ctrl);
|
||||
//xil_printf("ch_num_dat: %d\n\r", ch_num_dat);
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
sw_config_data[0] = (u8)(cpld_dat>>16);
|
||||
sw_config_data[1] = (u8)(cpld_dat>>8);
|
||||
sw_config_data[2] = (u8)(cpld_dat);
|
||||
|
||||
//xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[0]);
|
||||
//xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[1]);
|
||||
//xil_printf("sw_config_data[0]: %d\n\r", sw_config_data[2]);
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
|
||||
|
||||
sw_config_data[0] = 0x00;
|
||||
sw_config_data[1] = 0x00;
|
||||
sw_config_data[2] = 0x01;
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
|
||||
}
|
||||
|
||||
|
||||
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//62---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//63---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//64---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//65---rst
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
}
|
||||
+258
@@ -0,0 +1,258 @@
|
||||
/*
|
||||
* Copyright (C) 2009 - 2019 Xilinx, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "xparameters.h"
|
||||
#include "netif/xadapter.h"
|
||||
#include "platform.h"
|
||||
#include "platform_config.h"
|
||||
#if defined (__arm__) || defined(__aarch64__)
|
||||
#include "xil_printf.h"
|
||||
#endif
|
||||
|
||||
#include "lwip/tcp.h"
|
||||
#include "xil_cache.h"
|
||||
|
||||
#include "GPIO_Driv.h"
|
||||
#include "SPI_Driv.h"
|
||||
#include "cal_meas.h"
|
||||
|
||||
#if LWIP_IPV6==1
|
||||
#include "lwip/ip.h"
|
||||
#else
|
||||
#if LWIP_DHCP==1
|
||||
#include "lwip/dhcp.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* defined by each RAW mode application */
|
||||
void print_app_header();
|
||||
int start_application();
|
||||
int transfer_data();
|
||||
void tcp_fasttmr(void);
|
||||
void tcp_slowtmr(void);
|
||||
|
||||
/* missing declaration in lwIP */
|
||||
void lwip_init();
|
||||
|
||||
#if LWIP_IPV6==0
|
||||
#if LWIP_DHCP==1
|
||||
extern volatile int dhcp_timoutcntr;
|
||||
err_t dhcp_start(struct netif *netif);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
extern volatile int TcpFastTmrFlag;
|
||||
extern volatile int TcpSlowTmrFlag;
|
||||
static struct netif server_netif;
|
||||
struct netif *echo_netif;
|
||||
|
||||
#if LWIP_IPV6==1
|
||||
void print_ip6(char *msg, ip_addr_t *ip)
|
||||
{
|
||||
print(msg);
|
||||
xil_printf(" %x:%x:%x:%x:%x:%x:%x:%x\n\r",
|
||||
IP6_ADDR_BLOCK1(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK2(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK3(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK4(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK5(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK6(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK7(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK8(&ip->u_addr.ip6));
|
||||
|
||||
}
|
||||
#else
|
||||
void
|
||||
print_ip(char *msg, ip_addr_t *ip)
|
||||
{
|
||||
print(msg);
|
||||
xil_printf("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip),
|
||||
ip4_addr3(ip), ip4_addr4(ip));
|
||||
}
|
||||
|
||||
void
|
||||
print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
|
||||
{
|
||||
|
||||
print_ip("Board IP: ", ip);
|
||||
print_ip("Netmask : ", mask);
|
||||
print_ip("Gateway : ", gw);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (__arm__) && !defined (ARMR5)
|
||||
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
|
||||
int ProgramSi5324(void);
|
||||
int ProgramSfpPhy(void);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef XPS_BOARD_ZCU102
|
||||
#ifdef XPAR_XIICPS_0_DEVICE_ID
|
||||
int IicPhyReset(void);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int main()
|
||||
{
|
||||
#if LWIP_IPV6==0
|
||||
ip_addr_t ipaddr, netmask, gw;
|
||||
|
||||
#endif
|
||||
/* the mac address of the board. this should be unique per board */
|
||||
unsigned char mac_ethernet_address[] =
|
||||
{ 0x00, 0x0a, 0x35, 0x00, 0x01, 0x01 };
|
||||
|
||||
echo_netif = &server_netif;
|
||||
#if defined (__arm__) && !defined (ARMR5)
|
||||
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
|
||||
ProgramSi5324();
|
||||
ProgramSfpPhy();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Define this board specific macro in order perform PHY reset on ZCU102 */
|
||||
#ifdef XPS_BOARD_ZCU102
|
||||
if(IicPhyReset()) {
|
||||
xil_printf("Error performing PHY reset \n\r");
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
init_platform();
|
||||
|
||||
#if LWIP_IPV6==0
|
||||
#if LWIP_DHCP==1
|
||||
ipaddr.addr = 0;
|
||||
gw.addr = 0;
|
||||
netmask.addr = 0;
|
||||
#else
|
||||
/* initialize IP addresses to be used */
|
||||
IP4_ADDR(&ipaddr, 192, 168, 100, 110);
|
||||
IP4_ADDR(&netmask, 255, 255, 255, 0);
|
||||
IP4_ADDR(&gw, 192, 168, 100, 1);
|
||||
#endif
|
||||
#endif
|
||||
print_app_header();
|
||||
|
||||
lwip_init();
|
||||
|
||||
#if (LWIP_IPV6 == 0)
|
||||
/* Add network interface to the netif_list, and set it as default */
|
||||
if (!xemac_add(echo_netif, &ipaddr, &netmask,
|
||||
&gw, mac_ethernet_address,
|
||||
PLATFORM_EMAC_BASEADDR)) {
|
||||
xil_printf("Error adding N/W interface\n\r");
|
||||
return -1;
|
||||
}
|
||||
#else
|
||||
/* Add network interface to the netif_list, and set it as default */
|
||||
if (!xemac_add(echo_netif, NULL, NULL, NULL, mac_ethernet_address,
|
||||
PLATFORM_EMAC_BASEADDR)) {
|
||||
xil_printf("Error adding N/W interface\n\r");
|
||||
return -1;
|
||||
}
|
||||
echo_netif->ip6_autoconfig_enabled = 1;
|
||||
|
||||
netif_create_ip6_linklocal_address(echo_netif, 1);
|
||||
netif_ip6_addr_set_state(echo_netif, 0, IP6_ADDR_VALID);
|
||||
|
||||
print_ip6("\n\rBoard IPv6 address ", &echo_netif->ip6_addr[0].u_addr.ip6);
|
||||
|
||||
#endif
|
||||
netif_set_default(echo_netif);
|
||||
|
||||
/* now enable interrupts */
|
||||
platform_enable_interrupts();
|
||||
|
||||
/* specify that the network if is up */
|
||||
netif_set_up(echo_netif);
|
||||
|
||||
#if (LWIP_IPV6 == 0)
|
||||
#if (LWIP_DHCP==1)
|
||||
/* Create a new DHCP client for this interface.
|
||||
* Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
|
||||
* the predefined regular intervals after starting the client.
|
||||
*/
|
||||
dhcp_start(echo_netif);
|
||||
dhcp_timoutcntr = 24;
|
||||
|
||||
while(((echo_netif->ip_addr.addr) == 0) && (dhcp_timoutcntr > 0))
|
||||
xemacif_input(echo_netif);
|
||||
|
||||
if (dhcp_timoutcntr <= 0) {
|
||||
if ((echo_netif->ip_addr.addr) == 0) {
|
||||
xil_printf("DHCP Timeout\r\n");
|
||||
xil_printf("Configuring default IP of 192.168.100.110\r\n");
|
||||
IP4_ADDR(&(echo_netif->ip_addr), 192, 168, 100, 110);
|
||||
IP4_ADDR(&(echo_netif->netmask), 255, 255, 255, 0);
|
||||
IP4_ADDR(&(echo_netif->gw), 192, 168, 100, 1);
|
||||
}
|
||||
}
|
||||
|
||||
ipaddr.addr = echo_netif->ip_addr.addr;
|
||||
gw.addr = echo_netif->gw.addr;
|
||||
netmask.addr = echo_netif->netmask.addr;
|
||||
#endif
|
||||
|
||||
print_ip_settings(&ipaddr, &netmask, &gw);
|
||||
|
||||
#endif
|
||||
|
||||
EMIO_config();
|
||||
|
||||
interface_initial(CPLD_U1);
|
||||
interface_initial(CPLD_U2);
|
||||
interface_initial(CPLD_U3);
|
||||
rst_CPLD(CPLD_U1,4);
|
||||
rst_CPLD(CPLD_U2,4);
|
||||
|
||||
/* start the application (web server, rxtest, txtest, etc..) */
|
||||
start_application();
|
||||
|
||||
|
||||
/* receive and process packets */
|
||||
while (1) {
|
||||
if (TcpFastTmrFlag) {
|
||||
tcp_fasttmr();
|
||||
TcpFastTmrFlag = 0;
|
||||
}
|
||||
if (TcpSlowTmrFlag) {
|
||||
tcp_slowtmr();
|
||||
TcpSlowTmrFlag = 0;
|
||||
}
|
||||
xemacif_input(echo_netif);
|
||||
transfer_data();
|
||||
}
|
||||
|
||||
/* never reached */
|
||||
cleanup_platform();
|
||||
|
||||
return 0;
|
||||
}
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//60---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//60---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//60---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//61---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//62---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//63---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//64---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//65---rst
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66---sdio3
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67---sdio4
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67---sdio5
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67---sdio6
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67---sdio7
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
}
|
||||
+240
@@ -0,0 +1,240 @@
|
||||
/*
|
||||
* Copyright (C) 2009 - 2019 Xilinx, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include "dna_read.h"
|
||||
#include "crc16.h"
|
||||
#include "GPIO_Driv.h"
|
||||
#include "SPI_Driv.h"
|
||||
#include "cal_meas.h"
|
||||
|
||||
#include "lwip/err.h"
|
||||
#include "lwip/tcp.h"
|
||||
#if defined (__arm__) || defined (__aarch64__)
|
||||
#include "xil_printf.h"
|
||||
#endif
|
||||
|
||||
char *recv_data;
|
||||
char dna_data[10];
|
||||
unsigned short recv_len;
|
||||
|
||||
unsigned read_dat = 0;
|
||||
char dat_0[20] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
|
||||
unsigned crc_read_dat = 0;
|
||||
|
||||
char crc_alg_dat[2] = {0,0};
|
||||
|
||||
char send_data_cpld1[2] = {0xAA,0x56};
|
||||
|
||||
int transfer_data() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
void print_app_header()
|
||||
{
|
||||
#if (LWIP_IPV6==0)
|
||||
xil_printf("\n\r\n\r-----lwIP TCP echo server ------\n\r");
|
||||
#else
|
||||
xil_printf("\n\r\n\r-----lwIPv6 TCP echo server ------\n\r");
|
||||
#endif
|
||||
xil_printf("TCP packets sent to port 6001 will be echoed back\n\r");
|
||||
}
|
||||
|
||||
err_t recv_callback(void *arg, struct tcp_pcb *tpcb,
|
||||
struct pbuf *p, err_t err)
|
||||
{
|
||||
/* do not read the packet if we are not in ESTABLISHED state */
|
||||
if (!p) {
|
||||
tcp_close(tpcb);
|
||||
tcp_recv(tpcb, NULL);
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
/* indicate that the packet has been received */
|
||||
tcp_recved(tpcb, p->len);
|
||||
|
||||
/* echo back the payload */
|
||||
/* in this case, we assume that the payload is < TCP_SND_BUF */
|
||||
if (tcp_sndbuf(tpcb) > p->len) {
|
||||
|
||||
recv_len = p->len;
|
||||
recv_data = (char*)malloc(sizeof(char)*recv_len);
|
||||
memcpy(recv_data,p->payload,recv_len);
|
||||
|
||||
if(recv_data[6] == 0x0E)
|
||||
{
|
||||
crc_read_dat = do_crc_table(recv_data+6, recv_len-8);
|
||||
|
||||
crc_alg_dat[0] = (u8)crc_read_dat;
|
||||
crc_alg_dat[1] = (u8)(crc_read_dat>>8);
|
||||
dat_0[0]= 0x00;
|
||||
|
||||
switch(recv_data[7])
|
||||
{
|
||||
|
||||
case 0xA2://SLOT
|
||||
{
|
||||
|
||||
dat_0[1]= 0x06;
|
||||
dat_0[2]= recv_data[2];
|
||||
dat_0[3]= recv_data[3];
|
||||
dat_0[4]= recv_data[4];
|
||||
dat_0[5]= recv_data[5];
|
||||
dat_0[6]= recv_data[6];
|
||||
dat_0[7]= recv_data[7];
|
||||
if(recv_data[15]==crc_alg_dat[1]&&recv_data[16]==crc_alg_dat[0])
|
||||
{
|
||||
dat_0[8]= 0x01;
|
||||
dat_0[9]= 0x01;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
dat_0[8]= 0xff;
|
||||
dat_0[9]= 0xff;
|
||||
}
|
||||
dat_0[10]= recv_data[15];
|
||||
dat_0[11]= recv_data[16];
|
||||
|
||||
char slot_start[7] = {recv_data[8],recv_data[9],recv_data[10],recv_data[11],recv_data[12],recv_data[13],recv_data[14]};
|
||||
//xil_printf("slot_start[0]:%x, slot_start[1]:%x,slot_start[2]:%x,slot_start[3]:%x,slot_start[4]:%x,slot_start[5]:%x,slot_start[6]:%x\n\r", slot_start[0],slot_start[1],slot_start[2],slot_start[3],slot_start[4],slot_start[5],slot_start[6]);
|
||||
rst_CPLD(CPLD_U1,4);
|
||||
rst_CPLD(CPLD_U2,4);
|
||||
rst_CPLD(CPLD_U3,4);
|
||||
sw_config(slot_start);
|
||||
|
||||
tcp_write(tpcb, dat_0, 12, 1);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case 0xA3://dna_port_read
|
||||
{
|
||||
dna_port_read(dna_data);
|
||||
dat_0[1]=0x0e;
|
||||
dat_0[2]=recv_data[2];
|
||||
dat_0[3]=recv_data[3];
|
||||
dat_0[4]=recv_data[4];
|
||||
dat_0[5]=recv_data[5];
|
||||
dat_0[6]=recv_data[6];
|
||||
dat_0[7]=recv_data[7];
|
||||
if(recv_data[8]==crc_alg_dat[1]&&recv_data[9]==crc_alg_dat[0])
|
||||
{
|
||||
dat_0[8]= 0x01;
|
||||
dat_0[9]= 0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
dat_0[8]= 0xff;
|
||||
dat_0[9]= 0xff;
|
||||
}
|
||||
|
||||
dat_0[10]= dna_data[0];
|
||||
dat_0[11]= dna_data[1];
|
||||
dat_0[12]= dna_data[2];
|
||||
dat_0[13]= dna_data[3];
|
||||
dat_0[14]= dna_data[4];
|
||||
dat_0[15]= dna_data[5];
|
||||
dat_0[16]= dna_data[6];
|
||||
dat_0[17]= dna_data[7];
|
||||
|
||||
dat_0[18]= recv_data[8];
|
||||
dat_0[19]= recv_data[9];
|
||||
|
||||
tcp_write(tpcb, dat_0, 20, 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else
|
||||
xil_printf("no space in tcp_sndbuf\n\r");
|
||||
|
||||
|
||||
|
||||
/* free the received pbuf */
|
||||
pbuf_free(p);
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err)
|
||||
{
|
||||
static int connection = 1;
|
||||
|
||||
/* set the receive callback for this connection */
|
||||
tcp_recv(newpcb, recv_callback);
|
||||
|
||||
/* just use an integer number indicating the connection id as the
|
||||
callback argument */
|
||||
tcp_arg(newpcb, (void*)(UINTPTR)connection);
|
||||
|
||||
/* increment for subsequent accepted connections */
|
||||
connection++;
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
|
||||
int start_application()
|
||||
{
|
||||
struct tcp_pcb *pcb;
|
||||
err_t err;
|
||||
unsigned port = 200;
|
||||
|
||||
/* create new TCP PCB structure */
|
||||
pcb = tcp_new_ip_type(IPADDR_TYPE_ANY);
|
||||
if (!pcb) {
|
||||
xil_printf("Error creating PCB. Out of Memory\n\r");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* bind to specified @port */
|
||||
err = tcp_bind(pcb, IP_ANY_TYPE, port);
|
||||
if (err != ERR_OK) {
|
||||
xil_printf("Unable to bind to port %d: err = %d\n\r", port, err);
|
||||
return -2;
|
||||
}
|
||||
|
||||
/* we do not need any arguments to callback functions */
|
||||
tcp_arg(pcb, NULL);
|
||||
|
||||
/* listen for connections */
|
||||
pcb = tcp_listen(pcb);
|
||||
if (!pcb) {
|
||||
xil_printf("Out of memory while tcp_listen\n\r");
|
||||
return -3;
|
||||
}
|
||||
|
||||
/* specify callback to use for incoming connections */
|
||||
tcp_accept(pcb, accept_callback);
|
||||
|
||||
xil_printf("TCP echo server started @ port %d\n\r", port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
+70
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+235
@@ -0,0 +1,235 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00220000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
sw_config_data[0] = (u8)(cpld_dat>>16);
|
||||
sw_config_data[1] = (u8)(cpld_dat>>8);
|
||||
sw_config_data[2] = (u8)(cpld_dat);
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
|
||||
|
||||
sw_config_data[0] = 0x00;
|
||||
sw_config_data[1] = 0x00;
|
||||
sw_config_data[2] = 0x01;
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
|
||||
}
|
||||
|
||||
|
||||
|
||||
+117
@@ -0,0 +1,117 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+129
@@ -0,0 +1,129 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
xil_printf("m_fun=1 \n\r");
|
||||
|
||||
sw_fmmc_dat = fmmc_smmc_dat;
|
||||
sw_fmmc_dat = ~sw_fmmc_dat;
|
||||
|
||||
xil_printf("reg addr: %d\n\r", SW_FMMC);
|
||||
xil_printf("reg data: %x\n\r", sw_fmmc_dat);
|
||||
Xil_Out32(AXI_BASE_ADDR+4*SW_FMMC,sw_fmmc_dat);
|
||||
|
||||
sw_rc_dat = 0x0002;
|
||||
sw_rc_dat = ~sw_rc_dat;
|
||||
|
||||
xil_printf("reg addr: %d\n\r", SW_RC);
|
||||
xil_printf("reg data: %x\n\r", sw_rc_dat);
|
||||
Xil_Out32(AXI_BASE_ADDR+4*SW_RC,sw_rc_dat);
|
||||
|
||||
if(volt_cur==0)
|
||||
{
|
||||
sw_lofs_vpk_dat = 0x0003;
|
||||
sw_lofs_vpk_dat = ~sw_lofs_vpk_dat;
|
||||
|
||||
xil_printf("reg addr: %d\n\r", SW_LOFS_VPK);
|
||||
xil_printf("reg data: %x\n\r", sw_lofs_vpk_dat);
|
||||
Xil_Out32(AXI_BASE_ADDR+4*SW_LOFS_VPK,sw_lofs_vpk_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
sw_lofs_apk_dat = 0x0003;
|
||||
sw_lofs_apk_dat = ~sw_lofs_apk_dat;
|
||||
|
||||
xil_printf("reg addr: %d\n\r", SW_LOFS_APK);
|
||||
xil_printf("reg data: %x\n\r", sw_lofs_apk_dat);
|
||||
Xil_Out32(AXI_BASE_ADDR+4*SW_LOFS_APK,sw_lofs_apk_dat);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+66
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+66
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0xFF,0xFF,0xFF};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32
|
||||
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+81
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 1);//57---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 0);//58---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//66
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//67
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//67
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 1);//68---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 0);//69---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);
|
||||
|
||||
}
|
||||
+257
@@ -0,0 +1,257 @@
|
||||
/*
|
||||
* Copyright (C) 2009 - 2019 Xilinx, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "xparameters.h"
|
||||
#include "netif/xadapter.h"
|
||||
#include "platform.h"
|
||||
#include "platform_config.h"
|
||||
#if defined (__arm__) || defined(__aarch64__)
|
||||
#include "xil_printf.h"
|
||||
#endif
|
||||
|
||||
#include "lwip/tcp.h"
|
||||
#include "xil_cache.h"
|
||||
|
||||
#include "GPIO_Driv.h"
|
||||
#include "SPI_Driv.h"
|
||||
#include "cal_meas.h"
|
||||
|
||||
#if LWIP_IPV6==1
|
||||
#include "lwip/ip.h"
|
||||
#else
|
||||
#if LWIP_DHCP==1
|
||||
#include "lwip/dhcp.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* defined by each RAW mode application */
|
||||
void print_app_header();
|
||||
int start_application();
|
||||
int transfer_data();
|
||||
void tcp_fasttmr(void);
|
||||
void tcp_slowtmr(void);
|
||||
|
||||
/* missing declaration in lwIP */
|
||||
void lwip_init();
|
||||
|
||||
#if LWIP_IPV6==0
|
||||
#if LWIP_DHCP==1
|
||||
extern volatile int dhcp_timoutcntr;
|
||||
err_t dhcp_start(struct netif *netif);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
extern volatile int TcpFastTmrFlag;
|
||||
extern volatile int TcpSlowTmrFlag;
|
||||
static struct netif server_netif;
|
||||
struct netif *echo_netif;
|
||||
|
||||
#if LWIP_IPV6==1
|
||||
void print_ip6(char *msg, ip_addr_t *ip)
|
||||
{
|
||||
print(msg);
|
||||
xil_printf(" %x:%x:%x:%x:%x:%x:%x:%x\n\r",
|
||||
IP6_ADDR_BLOCK1(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK2(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK3(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK4(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK5(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK6(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK7(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK8(&ip->u_addr.ip6));
|
||||
|
||||
}
|
||||
#else
|
||||
void
|
||||
print_ip(char *msg, ip_addr_t *ip)
|
||||
{
|
||||
print(msg);
|
||||
xil_printf("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip),
|
||||
ip4_addr3(ip), ip4_addr4(ip));
|
||||
}
|
||||
|
||||
void
|
||||
print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
|
||||
{
|
||||
|
||||
print_ip("Board IP: ", ip);
|
||||
print_ip("Netmask : ", mask);
|
||||
print_ip("Gateway : ", gw);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (__arm__) && !defined (ARMR5)
|
||||
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
|
||||
int ProgramSi5324(void);
|
||||
int ProgramSfpPhy(void);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef XPS_BOARD_ZCU102
|
||||
#ifdef XPAR_XIICPS_0_DEVICE_ID
|
||||
int IicPhyReset(void);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int main()
|
||||
{
|
||||
#if LWIP_IPV6==0
|
||||
ip_addr_t ipaddr, netmask, gw;
|
||||
|
||||
#endif
|
||||
/* the mac address of the board. this should be unique per board */
|
||||
unsigned char mac_ethernet_address[] =
|
||||
{ 0x00, 0x0a, 0x35, 0x00, 0x01, 0x01 };
|
||||
|
||||
echo_netif = &server_netif;
|
||||
#if defined (__arm__) && !defined (ARMR5)
|
||||
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
|
||||
ProgramSi5324();
|
||||
ProgramSfpPhy();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Define this board specific macro in order perform PHY reset on ZCU102 */
|
||||
#ifdef XPS_BOARD_ZCU102
|
||||
if(IicPhyReset()) {
|
||||
xil_printf("Error performing PHY reset \n\r");
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
init_platform();
|
||||
|
||||
#if LWIP_IPV6==0
|
||||
#if LWIP_DHCP==1
|
||||
ipaddr.addr = 0;
|
||||
gw.addr = 0;
|
||||
netmask.addr = 0;
|
||||
#else
|
||||
/* initialize IP addresses to be used */
|
||||
IP4_ADDR(&ipaddr, 192, 168, 100, 110);
|
||||
IP4_ADDR(&netmask, 255, 255, 255, 0);
|
||||
IP4_ADDR(&gw, 192, 168, 100, 1);
|
||||
#endif
|
||||
#endif
|
||||
print_app_header();
|
||||
|
||||
lwip_init();
|
||||
|
||||
#if (LWIP_IPV6 == 0)
|
||||
/* Add network interface to the netif_list, and set it as default */
|
||||
if (!xemac_add(echo_netif, &ipaddr, &netmask,
|
||||
&gw, mac_ethernet_address,
|
||||
PLATFORM_EMAC_BASEADDR)) {
|
||||
xil_printf("Error adding N/W interface\n\r");
|
||||
return -1;
|
||||
}
|
||||
#else
|
||||
/* Add network interface to the netif_list, and set it as default */
|
||||
if (!xemac_add(echo_netif, NULL, NULL, NULL, mac_ethernet_address,
|
||||
PLATFORM_EMAC_BASEADDR)) {
|
||||
xil_printf("Error adding N/W interface\n\r");
|
||||
return -1;
|
||||
}
|
||||
echo_netif->ip6_autoconfig_enabled = 1;
|
||||
|
||||
netif_create_ip6_linklocal_address(echo_netif, 1);
|
||||
netif_ip6_addr_set_state(echo_netif, 0, IP6_ADDR_VALID);
|
||||
|
||||
print_ip6("\n\rBoard IPv6 address ", &echo_netif->ip6_addr[0].u_addr.ip6);
|
||||
|
||||
#endif
|
||||
netif_set_default(echo_netif);
|
||||
|
||||
/* now enable interrupts */
|
||||
platform_enable_interrupts();
|
||||
|
||||
/* specify that the network if is up */
|
||||
netif_set_up(echo_netif);
|
||||
|
||||
#if (LWIP_IPV6 == 0)
|
||||
#if (LWIP_DHCP==1)
|
||||
/* Create a new DHCP client for this interface.
|
||||
* Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
|
||||
* the predefined regular intervals after starting the client.
|
||||
*/
|
||||
dhcp_start(echo_netif);
|
||||
dhcp_timoutcntr = 24;
|
||||
|
||||
while(((echo_netif->ip_addr.addr) == 0) && (dhcp_timoutcntr > 0))
|
||||
xemacif_input(echo_netif);
|
||||
|
||||
if (dhcp_timoutcntr <= 0) {
|
||||
if ((echo_netif->ip_addr.addr) == 0) {
|
||||
xil_printf("DHCP Timeout\r\n");
|
||||
xil_printf("Configuring default IP of 192.168.100.110\r\n");
|
||||
IP4_ADDR(&(echo_netif->ip_addr), 192, 168, 100, 110);
|
||||
IP4_ADDR(&(echo_netif->netmask), 255, 255, 255, 0);
|
||||
IP4_ADDR(&(echo_netif->gw), 192, 168, 100, 1);
|
||||
}
|
||||
}
|
||||
|
||||
ipaddr.addr = echo_netif->ip_addr.addr;
|
||||
gw.addr = echo_netif->gw.addr;
|
||||
netmask.addr = echo_netif->netmask.addr;
|
||||
#endif
|
||||
|
||||
print_ip_settings(&ipaddr, &netmask, &gw);
|
||||
|
||||
#endif
|
||||
|
||||
EMIO_config();
|
||||
|
||||
interface_initial(CPLD_U1);
|
||||
interface_initial(CPLD_U2);
|
||||
rst_CPLD(CPLD_U1,4);
|
||||
rst_CPLD(CPLD_U2,4);
|
||||
|
||||
/* start the application (web server, rxtest, txtest, etc..) */
|
||||
start_application();
|
||||
|
||||
|
||||
/* receive and process packets */
|
||||
while (1) {
|
||||
if (TcpFastTmrFlag) {
|
||||
tcp_fasttmr();
|
||||
TcpFastTmrFlag = 0;
|
||||
}
|
||||
if (TcpSlowTmrFlag) {
|
||||
tcp_slowtmr();
|
||||
TcpSlowTmrFlag = 0;
|
||||
}
|
||||
xemacif_input(echo_netif);
|
||||
transfer_data();
|
||||
}
|
||||
|
||||
/* never reached */
|
||||
cleanup_platform();
|
||||
|
||||
return 0;
|
||||
}
|
||||
+257
@@ -0,0 +1,257 @@
|
||||
/*
|
||||
* Copyright (C) 2009 - 2019 Xilinx, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
||||
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
|
||||
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
* OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "xparameters.h"
|
||||
#include "netif/xadapter.h"
|
||||
#include "platform.h"
|
||||
#include "platform_config.h"
|
||||
#if defined (__arm__) || defined(__aarch64__)
|
||||
#include "xil_printf.h"
|
||||
#endif
|
||||
|
||||
#include "lwip/tcp.h"
|
||||
#include "xil_cache.h"
|
||||
|
||||
#include "GPIO_Driv.h"
|
||||
#include "SPI_Driv.h"
|
||||
#include "cal_meas.h"
|
||||
|
||||
#if LWIP_IPV6==1
|
||||
#include "lwip/ip.h"
|
||||
#else
|
||||
#if LWIP_DHCP==1
|
||||
#include "lwip/dhcp.h"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* defined by each RAW mode application */
|
||||
void print_app_header();
|
||||
int start_application();
|
||||
int transfer_data();
|
||||
void tcp_fasttmr(void);
|
||||
void tcp_slowtmr(void);
|
||||
|
||||
/* missing declaration in lwIP */
|
||||
void lwip_init();
|
||||
|
||||
#if LWIP_IPV6==0
|
||||
#if LWIP_DHCP==1
|
||||
extern volatile int dhcp_timoutcntr;
|
||||
err_t dhcp_start(struct netif *netif);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
extern volatile int TcpFastTmrFlag;
|
||||
extern volatile int TcpSlowTmrFlag;
|
||||
static struct netif server_netif;
|
||||
struct netif *echo_netif;
|
||||
|
||||
#if LWIP_IPV6==1
|
||||
void print_ip6(char *msg, ip_addr_t *ip)
|
||||
{
|
||||
print(msg);
|
||||
xil_printf(" %x:%x:%x:%x:%x:%x:%x:%x\n\r",
|
||||
IP6_ADDR_BLOCK1(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK2(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK3(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK4(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK5(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK6(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK7(&ip->u_addr.ip6),
|
||||
IP6_ADDR_BLOCK8(&ip->u_addr.ip6));
|
||||
|
||||
}
|
||||
#else
|
||||
void
|
||||
print_ip(char *msg, ip_addr_t *ip)
|
||||
{
|
||||
print(msg);
|
||||
xil_printf("%d.%d.%d.%d\n\r", ip4_addr1(ip), ip4_addr2(ip),
|
||||
ip4_addr3(ip), ip4_addr4(ip));
|
||||
}
|
||||
|
||||
void
|
||||
print_ip_settings(ip_addr_t *ip, ip_addr_t *mask, ip_addr_t *gw)
|
||||
{
|
||||
|
||||
print_ip("Board IP: ", ip);
|
||||
print_ip("Netmask : ", mask);
|
||||
print_ip("Gateway : ", gw);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined (__arm__) && !defined (ARMR5)
|
||||
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
|
||||
int ProgramSi5324(void);
|
||||
int ProgramSfpPhy(void);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef XPS_BOARD_ZCU102
|
||||
#ifdef XPAR_XIICPS_0_DEVICE_ID
|
||||
int IicPhyReset(void);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int main()
|
||||
{
|
||||
#if LWIP_IPV6==0
|
||||
ip_addr_t ipaddr, netmask, gw;
|
||||
|
||||
#endif
|
||||
/* the mac address of the board. this should be unique per board */
|
||||
unsigned char mac_ethernet_address[] =
|
||||
{ 0x00, 0x0a, 0x35, 0x00, 0x01, 0x01 };
|
||||
|
||||
echo_netif = &server_netif;
|
||||
#if defined (__arm__) && !defined (ARMR5)
|
||||
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
|
||||
ProgramSi5324();
|
||||
ProgramSfpPhy();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Define this board specific macro in order perform PHY reset on ZCU102 */
|
||||
#ifdef XPS_BOARD_ZCU102
|
||||
if(IicPhyReset()) {
|
||||
xil_printf("Error performing PHY reset \n\r");
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
init_platform();
|
||||
|
||||
#if LWIP_IPV6==0
|
||||
#if LWIP_DHCP==1
|
||||
ipaddr.addr = 0;
|
||||
gw.addr = 0;
|
||||
netmask.addr = 0;
|
||||
#else
|
||||
/* initialize IP addresses to be used */
|
||||
IP4_ADDR(&ipaddr, 192, 168, 100, 110);
|
||||
IP4_ADDR(&netmask, 255, 255, 255, 0);
|
||||
IP4_ADDR(&gw, 192, 168, 100, 1);
|
||||
#endif
|
||||
#endif
|
||||
print_app_header();
|
||||
|
||||
lwip_init();
|
||||
|
||||
#if (LWIP_IPV6 == 0)
|
||||
/* Add network interface to the netif_list, and set it as default */
|
||||
if (!xemac_add(echo_netif, &ipaddr, &netmask,
|
||||
&gw, mac_ethernet_address,
|
||||
PLATFORM_EMAC_BASEADDR)) {
|
||||
xil_printf("Error adding N/W interface\n\r");
|
||||
return -1;
|
||||
}
|
||||
#else
|
||||
/* Add network interface to the netif_list, and set it as default */
|
||||
if (!xemac_add(echo_netif, NULL, NULL, NULL, mac_ethernet_address,
|
||||
PLATFORM_EMAC_BASEADDR)) {
|
||||
xil_printf("Error adding N/W interface\n\r");
|
||||
return -1;
|
||||
}
|
||||
echo_netif->ip6_autoconfig_enabled = 1;
|
||||
|
||||
netif_create_ip6_linklocal_address(echo_netif, 1);
|
||||
netif_ip6_addr_set_state(echo_netif, 0, IP6_ADDR_VALID);
|
||||
|
||||
print_ip6("\n\rBoard IPv6 address ", &echo_netif->ip6_addr[0].u_addr.ip6);
|
||||
|
||||
#endif
|
||||
netif_set_default(echo_netif);
|
||||
|
||||
/* now enable interrupts */
|
||||
platform_enable_interrupts();
|
||||
|
||||
/* specify that the network if is up */
|
||||
netif_set_up(echo_netif);
|
||||
|
||||
#if (LWIP_IPV6 == 0)
|
||||
#if (LWIP_DHCP==1)
|
||||
/* Create a new DHCP client for this interface.
|
||||
* Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
|
||||
* the predefined regular intervals after starting the client.
|
||||
*/
|
||||
dhcp_start(echo_netif);
|
||||
dhcp_timoutcntr = 24;
|
||||
|
||||
while(((echo_netif->ip_addr.addr) == 0) && (dhcp_timoutcntr > 0))
|
||||
xemacif_input(echo_netif);
|
||||
|
||||
if (dhcp_timoutcntr <= 0) {
|
||||
if ((echo_netif->ip_addr.addr) == 0) {
|
||||
xil_printf("DHCP Timeout\r\n");
|
||||
xil_printf("Configuring default IP of 192.168.100.110\r\n");
|
||||
IP4_ADDR(&(echo_netif->ip_addr), 192, 168, 100, 110);
|
||||
IP4_ADDR(&(echo_netif->netmask), 255, 255, 255, 0);
|
||||
IP4_ADDR(&(echo_netif->gw), 192, 168, 100, 1);
|
||||
}
|
||||
}
|
||||
|
||||
ipaddr.addr = echo_netif->ip_addr.addr;
|
||||
gw.addr = echo_netif->gw.addr;
|
||||
netmask.addr = echo_netif->netmask.addr;
|
||||
#endif
|
||||
|
||||
print_ip_settings(&ipaddr, &netmask, &gw);
|
||||
|
||||
#endif
|
||||
|
||||
EMIO_config( );
|
||||
|
||||
interface_initial(CPLD_U1);
|
||||
interface_initial(CPLD_U2);
|
||||
rst_CPLD(CPLD_U1,4);
|
||||
rst_CPLD(CPLD_U2,4);
|
||||
|
||||
/* start the application (web server, rxtest, txtest, etc..) */
|
||||
start_application();
|
||||
|
||||
|
||||
/* receive and process packets */
|
||||
while (1) {
|
||||
if (TcpFastTmrFlag) {
|
||||
tcp_fasttmr();
|
||||
TcpFastTmrFlag = 0;
|
||||
}
|
||||
if (TcpSlowTmrFlag) {
|
||||
tcp_slowtmr();
|
||||
TcpSlowTmrFlag = 0;
|
||||
}
|
||||
xemacif_input(echo_netif);
|
||||
transfer_data();
|
||||
}
|
||||
|
||||
/* never reached */
|
||||
cleanup_platform();
|
||||
|
||||
return 0;
|
||||
}
|
||||
+197
@@ -0,0 +1,197 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u32 ch_num = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
|
||||
ch_num = (((u32)ch_num_h)<<8) + ((u32)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+235
@@ -0,0 +1,235 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start, u32 CPLD_UU[11])
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
sw_config_data[0] = (u8)(cpld_dat>>16);
|
||||
sw_config_data[1] = (u8)(cpld_dat>>8);
|
||||
sw_config_data[2] = (u8)(cpld_dat);
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_U3);
|
||||
|
||||
|
||||
sw_config_data[0] = 0x00;
|
||||
sw_config_data[1] = 0x00;
|
||||
sw_config_data[2] = 0x01;
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U2);
|
||||
spi_write_onewire(0x81, sw_config_data, dat_width, CPLD_U3);
|
||||
}
|
||||
|
||||
|
||||
|
||||
+108
@@ -0,0 +1,108 @@
|
||||
/*
|
||||
* GPIO_Driv.c
|
||||
*
|
||||
* Created on: 2021年5月7日
|
||||
* Author: Administrator
|
||||
*/
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
XGpioPs psGpioInstancePtr; //端口
|
||||
XGpioPs_Config* GpioConfigPtr; //设备ID
|
||||
//sck,cs,sdi,sdo,rst
|
||||
u32 CPLD_U1 [11] = {54,55,56,57,58,59,60,61,62,63,64};
|
||||
u32 CPLD_U2 [11] = {65,66,67,68,69,70,71,72,73,74,75};
|
||||
u32 CPLD_U3 [11] = {76,77,78,79,80,81,82,83,84,85,86};
|
||||
|
||||
void EMIO_config(void)
|
||||
{
|
||||
int xStatus;
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
|
||||
if(GpioConfigPtr == NULL)
|
||||
return XST_FAILURE;
|
||||
|
||||
xStatus = XGpioPs_CfgInitialize(&psGpioInstancePtr,GpioConfigPtr, GpioConfigPtr->BaseAddr);
|
||||
if(XST_SUCCESS != xStatus)
|
||||
print(" PS GPIO INIT FAILED \n\r");
|
||||
|
||||
/*-------------------------------------CPLD_U1------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 54, 1);//54---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 55, 1);//55---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 56, 1);//56---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 57, 0);//57---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 58, 1);//58---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 59, 1);//59
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 60, 1);//60
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 61, 1);//61
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 62, 1);//62
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 63, 1);//63
|
||||
|
||||
/*-------------------------------------CPLD_U2------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 66, 1);//66---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 67, 1);//67---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 68, 0);//68---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 69, 1);//69---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 65, 1);//65---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 66, 1);//66---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 67, 1);//67---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 68, 0);//68---sdo
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 69, 1);//69---rst_n
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 70, 1);//70
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 71, 1);//71
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 72, 1);//72
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 73, 1);//73
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 74, 1);//74
|
||||
|
||||
/*-------------------------------------CPLD_U3------------------------------------*/
|
||||
//--设置EMIO方向
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
XGpioPs_SetDirectionPin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetDirectionPin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
//使能EMIO输出 1=output 0=input
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 76, 1);//76---sck
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 77, 1);//77---rst_n
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 78, 1);//78---cs
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 79, 1);//79---sdi
|
||||
XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 80, 0);//80---sdo
|
||||
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 81, 1);//81
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 82, 1);//82
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 83, 1);//83
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 84, 1);//84
|
||||
//XGpioPs_SetOutputEnablePin(&psGpioInstancePtr, 85, 1);//85
|
||||
|
||||
}
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u32 cpld_dat = 0;
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+167
@@ -0,0 +1,167 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
if(ch_num==1|ch_num==65|ch_num==129|ch_num==193)
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
if(slot==0x01)
|
||||
{ cpld_addr = 0x82;}
|
||||
else if()
|
||||
{ cpld_addr = 0x83;}
|
||||
else if()
|
||||
{ cpld_addr = 0x84; }
|
||||
else
|
||||
{ cpld_addr = 0x85;}
|
||||
|
||||
if(m_fun==0x04)
|
||||
{
|
||||
//xil_printf("memt_areal: %d\n\r", memt_areal);
|
||||
if(memt_areal==0x01)
|
||||
{
|
||||
u1_io_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_io_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_io_rc_dat);
|
||||
spi_write_onewire(U1_SW_IO_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("io_rc_dat: %x\n\r", u1_io_rc_dat);
|
||||
}
|
||||
else
|
||||
{
|
||||
u1_rc_dat = 0xFFFE;
|
||||
sw_config_data[0] = (u8)(u1_rc_dat>>8);
|
||||
sw_config_data[1] = (u8)(u1_rc_dat);
|
||||
spi_write_onewire(U1_SW_RC, sw_config_data, dat_width, CPLD_U1);
|
||||
// xil_printf("rc_dat: %x\n\r", u1_rc_dat);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if(ch_num>=1&&ch_num<=16)
|
||||
{
|
||||
//xil_printf("m_fun=0x03,ch_num=1~16 \n\r");
|
||||
fc_dv0_dat = (0x0001<<(ch_num-1));
|
||||
fc_dv0_dat = ~fc_dv0_dat;
|
||||
sw_config_data[0] = (u8)(fc_dv0_dat>>8);
|
||||
sw_config_data[1] = (u8)(fc_dv0_dat);
|
||||
spi_write_onewire(U1_SW_FC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
spi_write_onewire(U1_SW_SC_DV0+slot-1, sw_config_data, dat_width, CPLD_U1);
|
||||
//xil_printf("CPLD_U1:\n\r");
|
||||
//xil_printf("fc_reg_addr: %d\n\r", U1_SW_FC_DV0+slot-1);
|
||||
//xil_printf("sc_reg_addr: %d\n\r", U1_SW_SC_DV0+slot-1);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
+221
@@ -0,0 +1,221 @@
|
||||
/*
|
||||
* cal_meas.c
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#include "cal_meas.h"
|
||||
#include "SPI_Driv.h"
|
||||
char sw_config_data[3] = {0x00,0x00,0x00};
|
||||
|
||||
void sw_config(char *slot_start)
|
||||
{
|
||||
char slot = (*slot_start);
|
||||
char m_fun = *(slot_start+1);
|
||||
char ch_num_h = *(slot_start+2);
|
||||
char ch_num_l = *(slot_start+3);
|
||||
char volt_cur = *(slot_start+4);
|
||||
char load = *(slot_start+5);
|
||||
char memt_areal = *(slot_start+6);
|
||||
|
||||
u16 ch_num = 0;
|
||||
u32 ch_num_dat = 0;
|
||||
u32 relay_ctrl = 0;
|
||||
u32 slot_en = 0x00000001;
|
||||
|
||||
u8 cpld_addr = 0;
|
||||
u32 cpld_dat = 0;
|
||||
|
||||
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
|
||||
|
||||
|
||||
if(slot==1)
|
||||
{
|
||||
cpld_addr = 0x82;
|
||||
}
|
||||
else if(slot==2)
|
||||
{
|
||||
cpld_addr = 0x83;
|
||||
}
|
||||
else if(slot==3)
|
||||
{
|
||||
cpld_addr = 0x84;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpld_addr = 0x85;
|
||||
}
|
||||
|
||||
switch(ch_num)
|
||||
{
|
||||
case 0x0001:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0002:
|
||||
{
|
||||
relay_ctrl = 0x00020000;
|
||||
break;
|
||||
}
|
||||
case 0x0003:
|
||||
{
|
||||
relay_ctrl = 0x00200000;
|
||||
break;
|
||||
}
|
||||
case 0x0004:
|
||||
{
|
||||
relay_ctrl = 0x00022000;
|
||||
break;
|
||||
}
|
||||
case 0x0005:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0006:
|
||||
{
|
||||
relay_ctrl = 0x00810000;
|
||||
break;
|
||||
}
|
||||
case 0x0007:
|
||||
{
|
||||
relay_ctrl = 0x00A00000;
|
||||
break;
|
||||
}
|
||||
case 0x0008:
|
||||
{
|
||||
relay_ctrl = 0x00A10000;
|
||||
break;
|
||||
}
|
||||
case 0x0041:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0042:
|
||||
{
|
||||
relay_ctrl = 0x00008000;
|
||||
break;
|
||||
}
|
||||
case 0x0043:
|
||||
{
|
||||
relay_ctrl = 0x00100000;
|
||||
break;
|
||||
}
|
||||
case 0x0044:
|
||||
{
|
||||
relay_ctrl = 0x00108000;
|
||||
break;
|
||||
}
|
||||
case 0x0045:
|
||||
{
|
||||
relay_ctrl = 0x00800000;
|
||||
break;
|
||||
}
|
||||
case 0x0046:
|
||||
{
|
||||
relay_ctrl = 0x00804000;
|
||||
break;
|
||||
}
|
||||
case 0x0047:
|
||||
{
|
||||
relay_ctrl = 0x00900000;
|
||||
break;
|
||||
}
|
||||
case 0x0048:
|
||||
{
|
||||
relay_ctrl = 0x00904000;
|
||||
break;
|
||||
}
|
||||
case 0x0081:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x0082:
|
||||
{
|
||||
relay_ctrl = 0x00002000;
|
||||
break;
|
||||
}
|
||||
case 0x0083:
|
||||
{
|
||||
relay_ctrl = 0x00080000;
|
||||
break;
|
||||
}
|
||||
case 0x0084:
|
||||
{
|
||||
relay_ctrl = 0x00082000;
|
||||
break;
|
||||
}
|
||||
case 0x0085:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x0086:
|
||||
{
|
||||
relay_ctrl = 0x00401000;
|
||||
break;
|
||||
}
|
||||
case 0x0087:
|
||||
{
|
||||
relay_ctrl = 0x00480000;
|
||||
break;
|
||||
}
|
||||
case 0x0088:
|
||||
{
|
||||
relay_ctrl = 0x00481000;
|
||||
break;
|
||||
}
|
||||
case 0x00C1:
|
||||
{
|
||||
relay_ctrl = 0x00000000;
|
||||
break;
|
||||
}
|
||||
case 0x00C2:
|
||||
{
|
||||
relay_ctrl = 0x00000800;
|
||||
break;
|
||||
}
|
||||
case 0x00C3:
|
||||
{
|
||||
relay_ctrl = 0x00040000;
|
||||
break;
|
||||
}
|
||||
case 0x00C4:
|
||||
{
|
||||
relay_ctrl = 0x00040800;
|
||||
break;
|
||||
}
|
||||
case 0x00C5:
|
||||
{
|
||||
relay_ctrl = 0x00400000;
|
||||
break;
|
||||
}
|
||||
case 0x00C6:
|
||||
{
|
||||
relay_ctrl = 0x00400400;
|
||||
break;
|
||||
}
|
||||
case 0x00C7:
|
||||
{
|
||||
relay_ctrl = 0x00440000;
|
||||
break;
|
||||
}
|
||||
case 0x00C8:
|
||||
{
|
||||
relay_ctrl = 0x00440400;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
ch_num_dat = ((u32)ch_num)<<1;
|
||||
cpld_dat = relay_ctrl|ch_num_dat|slot_en;
|
||||
|
||||
spi_write_onewire(cpld_addr, sw_config_data, dat_width, CPLD_UU);
|
||||
}
|
||||
|
||||
|
||||
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
/*
|
||||
* cal_meas.h
|
||||
*
|
||||
* Created on: 2023Äê7ÔÂ19ÈÕ
|
||||
* Author: dell
|
||||
*/
|
||||
|
||||
#ifndef SRC_CAL_MEAS_H_
|
||||
#define SRC_CAL_MEAS_H_
|
||||
|
||||
#include "sleep.h"
|
||||
#include "stdio.h"
|
||||
#include "xgpiops.h"
|
||||
#include "SPI_Driv.h"
|
||||
#include "GPIO_Driv.h"
|
||||
|
||||
|
||||
#define U1_SW_FC_DV0 1
|
||||
#define dat_width 3
|
||||
|
||||
|
||||
|
||||
void sw_init( void );
|
||||
void sw_config(char *slot_start);
|
||||
void fsmc_mmc_config(char slot,char m_fun);
|
||||
void dmm_config(char slot, u16 ch_num);
|
||||
void rc_config(char m_fun);
|
||||
void fsc_oc_config(char slot,char m_fun, u16 ch_num);
|
||||
void rl_config(char load);
|
||||
|
||||
#endif /* SRC_CAL_MEAS_H_ */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user