Init Commit
This commit is contained in:
Jeremy Shen
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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---------------------------------------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
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| Date : Wed May 27 16:36:31 2026
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| Host : mkb running 64-bit unknown
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| Command : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb
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| Design : system_wrapper
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| Device : xc7z035ffg676-2
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| Speed File : -2
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| Design State : Synthesized
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---------------------------------------------------------------------------------------------------------------------------------------------
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Memory
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3. DSP
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4. IO and GT Specific
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5. Clocking
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6. Specific Feature
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7. Primitives
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8. Black Boxes
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9. Instantiated Netlists
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1. Slice Logic
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--------------
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+----------------------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+----------------------------+------+-------+------------+-----------+-------+
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| Slice LUTs* | 470 | 0 | 0 | 171900 | 0.27 |
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| LUT as Logic | 408 | 0 | 0 | 171900 | 0.24 |
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| LUT as Memory | 62 | 0 | 0 | 70400 | 0.09 |
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| LUT as Distributed RAM | 0 | 0 | | | |
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| LUT as Shift Register | 62 | 0 | | | |
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| Slice Registers | 648 | 0 | 0 | 343800 | 0.19 |
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| Register as Flip Flop | 591 | 0 | 0 | 343800 | 0.17 |
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| Register as Latch | 57 | 0 | 0 | 343800 | 0.02 |
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| F7 Muxes | 0 | 0 | 0 | 109300 | 0.00 |
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| F8 Muxes | 0 | 0 | 0 | 54650 | 0.00 |
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+----------------------------+------+-------+------------+-----------+-------+
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* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
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Warning! LUT value is adjusted to account for LUT combining.
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 0 | Yes | - | Set |
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| 123 | Yes | - | Reset |
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| 20 | Yes | Set | - |
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| 505 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. Memory
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---------
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+----------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+----------------+------+-------+------------+-----------+-------+
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| Block RAM Tile | 0 | 0 | 0 | 500 | 0.00 |
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| RAMB36/FIFO* | 0 | 0 | 0 | 500 | 0.00 |
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| RAMB18 | 0 | 0 | 0 | 1000 | 0.00 |
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+----------------+------+-------+------------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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3. DSP
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------
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+-----------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-----------+------+-------+------------+-----------+-------+
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| DSPs | 0 | 0 | 0 | 900 | 0.00 |
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+-----------+------+-------+------------+-----------+-------+
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4. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+------------+-----------+--------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-----------------------------+------+-------+------------+-----------+--------+
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| Bonded IOB | 33 | 0 | 0 | 250 | 13.20 |
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| Bonded IPADs | 0 | 0 | 0 | 26 | 0.00 |
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| Bonded OPADs | 0 | 0 | 0 | 16 | 0.00 |
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| Bonded IOPADs | 130 | 0 | 0 | 130 | 100.00 |
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| PHY_CONTROL | 0 | 0 | 0 | 8 | 0.00 |
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| PHASER_REF | 0 | 0 | 0 | 8 | 0.00 |
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| OUT_FIFO | 0 | 0 | 0 | 32 | 0.00 |
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| IN_FIFO | 0 | 0 | 0 | 32 | 0.00 |
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| IDELAYCTRL | 0 | 0 | 0 | 8 | 0.00 |
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| IBUFDS | 0 | 0 | 0 | 240 | 0.00 |
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| GTXE2_COMMON | 0 | 0 | 0 | 2 | 0.00 |
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| GTXE2_CHANNEL | 0 | 0 | 0 | 8 | 0.00 |
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| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 32 | 0.00 |
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| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 32 | 0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 400 | 0.00 |
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| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 150 | 0.00 |
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| IBUFDS_GTE2 | 0 | 0 | 0 | 4 | 0.00 |
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| ILOGIC | 0 | 0 | 0 | 250 | 0.00 |
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| OLOGIC | 0 | 0 | 0 | 250 | 0.00 |
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+-----------------------------+------+-------+------------+-----------+--------+
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5. Clocking
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-----------
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+------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+------------+------+-------+------------+-----------+-------+
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| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 |
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| BUFIO | 0 | 0 | 0 | 32 | 0.00 |
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| MMCME2_ADV | 0 | 0 | 0 | 8 | 0.00 |
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| PLLE2_ADV | 0 | 0 | 0 | 8 | 0.00 |
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| BUFMRCE | 0 | 0 | 0 | 16 | 0.00 |
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| BUFHCE | 0 | 0 | 0 | 168 | 0.00 |
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| BUFR | 0 | 0 | 0 | 32 | 0.00 |
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+------------+------+-------+------------+-----------+-------+
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6. Specific Feature
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-------------------
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+-------------+------+-------+------------+-----------+--------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-------------+------+-------+------------+-----------+--------+
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| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
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| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
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| DNA_PORT | 1 | 0 | 0 | 1 | 100.00 |
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| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
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| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
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| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
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| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
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| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
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| XADC | 0 | 0 | 0 | 1 | 0.00 |
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+-------------+------+-------+------------+-----------+--------+
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7. Primitives
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-------------
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+----------+------+----------------------+
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| Ref Name | Used | Functional Category |
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+----------+------+----------------------+
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| FDRE | 505 | Flop & Latch |
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| LUT3 | 169 | LUT |
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| BIBUF | 130 | IO |
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| LUT6 | 118 | LUT |
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| LUT5 | 71 | LUT |
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| LUT1 | 69 | LUT |
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| FDCE | 66 | Flop & Latch |
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| LDCE | 57 | Flop & Latch |
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| LUT4 | 52 | LUT |
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| SRLC32E | 45 | Distributed Memory |
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| OBUFT | 33 | IO |
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| IBUF | 33 | IO |
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| LUT2 | 24 | LUT |
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| FDSE | 20 | Flop & Latch |
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| SRL16E | 17 | Distributed Memory |
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| CARRY4 | 6 | CarryLogic |
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| PS7 | 1 | Specialized Resource |
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| DNA_PORT | 1 | Others |
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| BUFG | 1 | Clock |
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+----------+------+----------------------+
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8. Black Boxes
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--------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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9. Instantiated Netlists
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------------------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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