Init Commit
This commit is contained in:
Jeremy Shen
@@ -0,0 +1,143 @@
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#
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# Synthesis run script generated by Vivado
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#
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set TIME_start [clock seconds]
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namespace eval ::optrace {
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variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.tcl"
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variable category "vivado_synth"
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}
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# Try to connect to running dispatch if we haven't done so already.
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# This code assumes that the Tcl interpreter is not using threads,
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# since the ::dispatch::connected variable isn't mutex protected.
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if {![info exists ::dispatch::connected]} {
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namespace eval ::dispatch {
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variable connected false
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if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
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set result "true"
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if {[catch {
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if {[lsearch -exact [package names] DispatchTcl] < 0} {
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set result [load librdi_cd_clienttcl[info sharedlibextension]]
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}
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if {$result eq "false"} {
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puts "WARNING: Could not load dispatch client library"
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}
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set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
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if { $connect_id eq "" } {
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puts "WARNING: Could not initialize dispatch client"
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} else {
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puts "INFO: Dispatch client connection id - $connect_id"
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set connected true
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}
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} catch_res]} {
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puts "WARNING: failed to connect to dispatch server - $catch_res"
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}
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}
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}
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}
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if {$::dispatch::connected} {
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# Remove the dummy proc if it exists.
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if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
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rename ::OPTRACE ""
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}
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proc ::OPTRACE { task action {tags {} } } {
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::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
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}
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# dispatch is generic. We specifically want to attach logging.
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::vitis_log::connect_client
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} else {
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# Add dummy proc if it doesn't exist.
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if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
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proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
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# Do nothing
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}
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}
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}
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proc create_report { reportName command } {
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set status "."
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append status $reportName ".fail"
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if { [file exists $status] } {
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eval file delete [glob $status]
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}
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send_msg_id runtcl-4 info "Executing : $command"
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set retval [eval catch { $command } msg]
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if { $retval != 0 } {
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set fp [open $status w]
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close $fp
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send_msg_id runtcl-5 warning "$msg"
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}
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}
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OPTRACE "synth_1" START { ROLLUP_AUTO }
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set_param chipscope.maxJobs 8
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set_msg_config -id {HDL-1065} -limit 10000
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OPTRACE "Creating in-memory project" START { }
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create_project -in_memory -part xc7z035ffg676-2
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set_param project.singleFileAddWarning.threshold 0
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set_param project.compositeFile.enableAutoGeneration 0
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set_param synth.vivado.isSynthRun true
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set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
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set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.cache/wt [current_project]
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set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.xpr [current_project]
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set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
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set_property default_lib xil_defaultlib [current_project]
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set_property target_language Verilog [current_project]
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set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.cache/ip [current_project]
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set_property ip_cache_permissions {read write} [current_project]
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OPTRACE "Creating in-memory project" END { }
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OPTRACE "Adding files" START { }
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read_verilog -library xil_defaultlib {
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/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v
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/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v
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/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v
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/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v
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}
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add_files /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/bd/system/system.bd
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set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]
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set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc]
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set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc]
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set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc]
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set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_ooc.xdc]
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set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/system_ooc.xdc]
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OPTRACE "Adding files" END { }
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# Mark all dcp files as not used in implementation to prevent them from being
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# stitched into the results of this synthesis run. Any black boxes in the
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# design are intentionally left as such for best results. Dcp files will be
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# stitched into the design at a later time, either when this synthesis run is
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# opened, or when it is stitched into a dependent implementation run.
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foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
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set_property used_in_implementation false $dcp
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}
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read_xdc /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc
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set_property used_in_implementation false [get_files /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
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read_xdc /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc
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set_property used_in_implementation false [get_files /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
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read_xdc dont_touch.xdc
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set_property used_in_implementation false [get_files dont_touch.xdc]
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set_param ips.enableIPCacheLiteLoad 1
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close [open __synthesis_is_running__ w]
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OPTRACE "synth_design" START { }
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synth_design -top system_wrapper -part xc7z035ffg676-2
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OPTRACE "synth_design" END { }
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if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
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send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
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}
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OPTRACE "write_checkpoint" START { CHECKPOINT }
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# disable binary constraint mode for synth run checkpoints
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set_param constraints.enableBinaryConstraints false
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write_checkpoint -force -noxdef system_wrapper.dcp
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OPTRACE "write_checkpoint" END { }
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OPTRACE "synth reports" START { REPORT }
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create_report "synth_1_synth_report_utilization_0" "report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb"
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OPTRACE "synth reports" END { }
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file delete __synthesis_is_running__
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close [open __synthesis_is_complete__ w]
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OPTRACE "synth_1" END { }
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