yuysh/NewInstrCalBoard_Zynq
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Jeremy Shen
2026-05-27 09:56:09 +00:00
commit ee3ede1152
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Debug_FW.runs/synth_1/.Vivado_Synthesis.queue.rst
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Debug_FW.runs/synth_1/.Xil/system_wrapper_propImpl.xdc
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set_property SRC_FILE_INFO {cfile:/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc rfile:../../../Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc id:1 order:EARLY scoped_inst:system_i/processing_system7_0/inst} [current_design]
set_property SRC_FILE_INFO {cfile:/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc rfile:../../../Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc id:2 order:EARLY scoped_inst:system_i/rst_ps7_0_100M/U0} [current_design]
set_property SRC_FILE_INFO {cfile:/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc rfile:../../../Debug_FW.srcs/constrs_1/new/pin_cons.xdc id:3} [current_design]
set_property SRC_FILE_INFO {cfile:/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc rfile:../../../Debug_FW.srcs/constrs_1/new/pin_debug.xdc id:4} [current_design]
current_instance system_i/processing_system7_0/inst
set_property src_info {type:SCOPED_XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
set_input_jitter clk_fpga_0 0.3
set_property src_info {type:SCOPED_XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "A19" [get_ports "MIO[53]"]
set_property src_info {type:SCOPED_XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "A20" [get_ports "MIO[52]"]
set_property src_info {type:SCOPED_XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "A18" [get_ports "MIO[49]"]
set_property src_info {type:SCOPED_XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "B21" [get_ports "MIO[48]"]
set_property src_info {type:SCOPED_XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "B19" [get_ports "MIO[47]"]
set_property src_info {type:SCOPED_XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "E17" [get_ports "MIO[46]"]
set_property src_info {type:SCOPED_XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "C18" [get_ports "MIO[45]"]
set_property src_info {type:SCOPED_XDC file:1 line:80 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "E18" [get_ports "MIO[44]"]
set_property src_info {type:SCOPED_XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "D18" [get_ports "MIO[43]"]
set_property src_info {type:SCOPED_XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "F17" [get_ports "MIO[42]"]
set_property src_info {type:SCOPED_XDC file:1 line:101 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "C19" [get_ports "MIO[41]"]
set_property src_info {type:SCOPED_XDC file:1 line:108 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "C22" [get_ports "MIO[40]"]
set_property src_info {type:SCOPED_XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "F18" [get_ports "MIO[27]"]
set_property src_info {type:SCOPED_XDC file:1 line:122 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "H17" [get_ports "MIO[26]"]
set_property src_info {type:SCOPED_XDC file:1 line:129 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "F19" [get_ports "MIO[25]"]
set_property src_info {type:SCOPED_XDC file:1 line:136 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "J19" [get_ports "MIO[24]"]
set_property src_info {type:SCOPED_XDC file:1 line:143 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "F20" [get_ports "MIO[23]"]
set_property src_info {type:SCOPED_XDC file:1 line:150 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "G22" [get_ports "MIO[22]"]
set_property src_info {type:SCOPED_XDC file:1 line:157 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "F22" [get_ports "MIO[21]"]
set_property src_info {type:SCOPED_XDC file:1 line:164 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "H19" [get_ports "MIO[20]"]
set_property src_info {type:SCOPED_XDC file:1 line:171 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "G19" [get_ports "MIO[19]"]
set_property src_info {type:SCOPED_XDC file:1 line:178 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "G20" [get_ports "MIO[18]"]
set_property src_info {type:SCOPED_XDC file:1 line:185 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "G17" [get_ports "MIO[17]"]
set_property src_info {type:SCOPED_XDC file:1 line:192 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "G21" [get_ports "MIO[16]"]
set_property src_info {type:SCOPED_XDC file:1 line:199 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "A24" [get_ports "MIO[8]"]
set_property src_info {type:SCOPED_XDC file:1 line:205 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "F23" [get_ports "MIO[6]"]
set_property src_info {type:SCOPED_XDC file:1 line:211 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "C26" [get_ports "MIO[5]"]
set_property src_info {type:SCOPED_XDC file:1 line:217 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "F24" [get_ports "MIO[4]"]
set_property src_info {type:SCOPED_XDC file:1 line:223 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "D25" [get_ports "MIO[3]"]
set_property src_info {type:SCOPED_XDC file:1 line:229 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "E25" [get_ports "MIO[2]"]
set_property src_info {type:SCOPED_XDC file:1 line:235 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "D26" [get_ports "MIO[1]"]
set_property src_info {type:SCOPED_XDC file:1 line:241 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "W21" [get_ports "DDR_VRP"]
set_property src_info {type:SCOPED_XDC file:1 line:245 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "V21" [get_ports "DDR_VRN"]
set_property src_info {type:SCOPED_XDC file:1 line:249 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "V22" [get_ports "DDR_WEB"]
set_property src_info {type:SCOPED_XDC file:1 line:253 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "V23" [get_ports "DDR_RAS_n"]
set_property src_info {type:SCOPED_XDC file:1 line:257 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "Y22" [get_ports "DDR_ODT"]
set_property src_info {type:SCOPED_XDC file:1 line:261 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "H22" [get_ports "DDR_DRSTB"]
set_property src_info {type:SCOPED_XDC file:1 line:265 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "W24" [get_ports "DDR_DQS[3]"]
set_property src_info {type:SCOPED_XDC file:1 line:269 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "P25" [get_ports "DDR_DQS[2]"]
set_property src_info {type:SCOPED_XDC file:1 line:273 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "L24" [get_ports "DDR_DQS[1]"]
set_property src_info {type:SCOPED_XDC file:1 line:277 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "H24" [get_ports "DDR_DQS[0]"]
set_property src_info {type:SCOPED_XDC file:1 line:281 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "W25" [get_ports "DDR_DQS_n[3]"]
set_property src_info {type:SCOPED_XDC file:1 line:285 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "R25" [get_ports "DDR_DQS_n[2]"]
set_property src_info {type:SCOPED_XDC file:1 line:289 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "L25" [get_ports "DDR_DQS_n[1]"]
set_property src_info {type:SCOPED_XDC file:1 line:293 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "G25" [get_ports "DDR_DQS_n[0]"]
set_property src_info {type:SCOPED_XDC file:1 line:297 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "L23" [get_ports "DDR_DQ[9]"]
set_property src_info {type:SCOPED_XDC file:1 line:301 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "K26" [get_ports "DDR_DQ[8]"]
set_property src_info {type:SCOPED_XDC file:1 line:305 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "J23" [get_ports "DDR_DQ[7]"]
set_property src_info {type:SCOPED_XDC file:1 line:309 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "J24" [get_ports "DDR_DQ[6]"]
set_property src_info {type:SCOPED_XDC file:1 line:313 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "H23" [get_ports "DDR_DQ[5]"]
set_property src_info {type:SCOPED_XDC file:1 line:317 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "H26" [get_ports "DDR_DQ[4]"]
set_property src_info {type:SCOPED_XDC file:1 line:321 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "G26" [get_ports "DDR_DQ[3]"]
set_property src_info {type:SCOPED_XDC file:1 line:325 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "W23" [get_ports "DDR_DQ[31]"]
set_property src_info {type:SCOPED_XDC file:1 line:329 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "Y26" [get_ports "DDR_DQ[30]"]
set_property src_info {type:SCOPED_XDC file:1 line:333 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "J25" [get_ports "DDR_DQ[2]"]
set_property src_info {type:SCOPED_XDC file:1 line:337 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "Y25" [get_ports "DDR_DQ[29]"]
set_property src_info {type:SCOPED_XDC file:1 line:341 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "W26" [get_ports "DDR_DQ[28]"]
set_property src_info {type:SCOPED_XDC file:1 line:345 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "U25" [get_ports "DDR_DQ[27]"]
set_property src_info {type:SCOPED_XDC file:1 line:349 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "U24" [get_ports "DDR_DQ[26]"]
set_property src_info {type:SCOPED_XDC file:1 line:353 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "U26" [get_ports "DDR_DQ[25]"]
set_property src_info {type:SCOPED_XDC file:1 line:357 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "V24" [get_ports "DDR_DQ[24]"]
set_property src_info {type:SCOPED_XDC file:1 line:361 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "R23" [get_ports "DDR_DQ[23]"]
set_property src_info {type:SCOPED_XDC file:1 line:365 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "T23" [get_ports "DDR_DQ[22]"]
set_property src_info {type:SCOPED_XDC file:1 line:369 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "T25" [get_ports "DDR_DQ[21]"]
set_property src_info {type:SCOPED_XDC file:1 line:373 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "T24" [get_ports "DDR_DQ[20]"]
set_property src_info {type:SCOPED_XDC file:1 line:377 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "F25" [get_ports "DDR_DQ[1]"]
set_property src_info {type:SCOPED_XDC file:1 line:381 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "P23" [get_ports "DDR_DQ[19]"]
set_property src_info {type:SCOPED_XDC file:1 line:385 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "N26" [get_ports "DDR_DQ[18]"]
set_property src_info {type:SCOPED_XDC file:1 line:389 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "P24" [get_ports "DDR_DQ[17]"]
set_property src_info {type:SCOPED_XDC file:1 line:393 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "R26" [get_ports "DDR_DQ[16]"]
set_property src_info {type:SCOPED_XDC file:1 line:397 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "N23" [get_ports "DDR_DQ[15]"]
set_property src_info {type:SCOPED_XDC file:1 line:401 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "M24" [get_ports "DDR_DQ[14]"]
set_property src_info {type:SCOPED_XDC file:1 line:405 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "N24" [get_ports "DDR_DQ[13]"]
set_property src_info {type:SCOPED_XDC file:1 line:409 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "M25" [get_ports "DDR_DQ[12]"]
set_property src_info {type:SCOPED_XDC file:1 line:413 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "K23" [get_ports "DDR_DQ[11]"]
set_property src_info {type:SCOPED_XDC file:1 line:417 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "M26" [get_ports "DDR_DQ[10]"]
set_property src_info {type:SCOPED_XDC file:1 line:421 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "J26" [get_ports "DDR_DQ[0]"]
set_property src_info {type:SCOPED_XDC file:1 line:425 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "V26" [get_ports "DDR_DM[3]"]
set_property src_info {type:SCOPED_XDC file:1 line:429 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "P26" [get_ports "DDR_DM[2]"]
set_property src_info {type:SCOPED_XDC file:1 line:433 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "K25" [get_ports "DDR_DM[1]"]
set_property src_info {type:SCOPED_XDC file:1 line:437 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "G24" [get_ports "DDR_DM[0]"]
set_property src_info {type:SCOPED_XDC file:1 line:441 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "Y21" [get_ports "DDR_CS_n"]
set_property src_info {type:SCOPED_XDC file:1 line:445 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "U21" [get_ports "DDR_CKE"]
set_property src_info {type:SCOPED_XDC file:1 line:449 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "R21" [get_ports "DDR_Clk"]
set_property src_info {type:SCOPED_XDC file:1 line:453 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "P21" [get_ports "DDR_Clk_n"]
set_property src_info {type:SCOPED_XDC file:1 line:457 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "Y23" [get_ports "DDR_CAS_n"]
set_property src_info {type:SCOPED_XDC file:1 line:461 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "R22" [get_ports "DDR_BankAddr[2]"]
set_property src_info {type:SCOPED_XDC file:1 line:465 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "T22" [get_ports "DDR_BankAddr[1]"]
set_property src_info {type:SCOPED_XDC file:1 line:469 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "U22" [get_ports "DDR_BankAddr[0]"]
set_property src_info {type:SCOPED_XDC file:1 line:473 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "U20" [get_ports "DDR_Addr[9]"]
set_property src_info {type:SCOPED_XDC file:1 line:477 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "T20" [get_ports "DDR_Addr[8]"]
set_property src_info {type:SCOPED_XDC file:1 line:481 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "J21" [get_ports "DDR_Addr[7]"]
set_property src_info {type:SCOPED_XDC file:1 line:485 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "L20" [get_ports "DDR_Addr[6]"]
set_property src_info {type:SCOPED_XDC file:1 line:489 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "N22" [get_ports "DDR_Addr[5]"]
set_property src_info {type:SCOPED_XDC file:1 line:493 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "M20" [get_ports "DDR_Addr[4]"]
set_property src_info {type:SCOPED_XDC file:1 line:497 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "L22" [get_ports "DDR_Addr[3]"]
set_property src_info {type:SCOPED_XDC file:1 line:501 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "N21" [get_ports "DDR_Addr[2]"]
set_property src_info {type:SCOPED_XDC file:1 line:505 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "K20" [get_ports "DDR_Addr[1]"]
set_property src_info {type:SCOPED_XDC file:1 line:509 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "R20" [get_ports "DDR_Addr[14]"]
set_property src_info {type:SCOPED_XDC file:1 line:513 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "J20" [get_ports "DDR_Addr[13]"]
set_property src_info {type:SCOPED_XDC file:1 line:517 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "P20" [get_ports "DDR_Addr[12]"]
set_property src_info {type:SCOPED_XDC file:1 line:521 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "H21" [get_ports "DDR_Addr[11]"]
set_property src_info {type:SCOPED_XDC file:1 line:525 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "M22" [get_ports "DDR_Addr[10]"]
set_property src_info {type:SCOPED_XDC file:1 line:529 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "K22" [get_ports "DDR_Addr[0]"]
set_property src_info {type:SCOPED_XDC file:1 line:533 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "C23" [get_ports "PS_PORB"]
set_property src_info {type:SCOPED_XDC file:1 line:536 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "A22" [get_ports "PS_SRSTB"]
set_property src_info {type:SCOPED_XDC file:1 line:539 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN "B24" [get_ports "PS_CLK"]
current_instance
current_instance system_i/rst_ps7_0_100M/U0
set_property src_info {type:SCOPED_XDC file:2 line:50 export:INPUT save:INPUT read:READ} [current_design]
create_waiver -type CDC -id {CDC-11} -user "proc_sys_reset" -desc "Timing uncritical paths" -tags "1171415" -scope -internal -to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to}]]
current_instance
set_property src_info {type:XDC file:3 line:35 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB21 [get_ports {EMIO_0_tri_io[0]}]
set_property src_info {type:XDC file:3 line:36 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN W20 [get_ports {EMIO_0_tri_io[1]}]
set_property src_info {type:XDC file:3 line:37 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN Y20 [get_ports {EMIO_0_tri_io[2]}]
set_property src_info {type:XDC file:3 line:38 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE18 [get_ports {EMIO_0_tri_io[3]}]
set_property src_info {type:XDC file:3 line:39 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF18 [get_ports {EMIO_0_tri_io[4]}]
set_property src_info {type:XDC file:3 line:40 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF19 [get_ports {EMIO_0_tri_io[5]}]
set_property src_info {type:XDC file:3 line:41 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE21 [get_ports {EMIO_0_tri_io[6]}]
set_property src_info {type:XDC file:3 line:42 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE20 [get_ports {EMIO_0_tri_io[7]}]
set_property src_info {type:XDC file:3 line:43 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD18 [get_ports {EMIO_0_tri_io[8]}]
set_property src_info {type:XDC file:3 line:44 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD19 [get_ports {EMIO_0_tri_io[9]}]
set_property src_info {type:XDC file:3 line:45 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA22 [get_ports {EMIO_0_tri_io[10]}]
set_property src_info {type:XDC file:3 line:47 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AB25 [get_ports {EMIO_0_tri_io[11]}]
set_property src_info {type:XDC file:3 line:48 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD23 [get_ports {EMIO_0_tri_io[12]}]
set_property src_info {type:XDC file:3 line:49 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD20 [get_ports {EMIO_0_tri_io[13]}]
set_property src_info {type:XDC file:3 line:50 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD21 [get_ports {EMIO_0_tri_io[14]}]
set_property src_info {type:XDC file:3 line:51 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC23 [get_ports {EMIO_0_tri_io[15]}]
set_property src_info {type:XDC file:3 line:52 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA25 [get_ports {EMIO_0_tri_io[16]}]
set_property src_info {type:XDC file:3 line:53 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD24 [get_ports {EMIO_0_tri_io[17]}]
set_property src_info {type:XDC file:3 line:54 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC24 [get_ports {EMIO_0_tri_io[18]}]
set_property src_info {type:XDC file:3 line:55 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC21 [get_ports {EMIO_0_tri_io[19]}]
set_property src_info {type:XDC file:3 line:56 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AC22 [get_ports {EMIO_0_tri_io[20]}]
set_property src_info {type:XDC file:3 line:57 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF20 [get_ports {EMIO_0_tri_io[21]}]
set_property src_info {type:XDC file:3 line:59 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AD10 [get_ports {EMIO_0_tri_io[22]}]
set_property src_info {type:XDC file:3 line:60 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA12 [get_ports {EMIO_0_tri_io[23]}]
set_property src_info {type:XDC file:3 line:61 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF12 [get_ports {EMIO_0_tri_io[24]}]
set_property src_info {type:XDC file:3 line:62 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AA13 [get_ports {EMIO_0_tri_io[25]}]
set_property src_info {type:XDC file:3 line:63 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE12 [get_ports {EMIO_0_tri_io[26]}]
set_property src_info {type:XDC file:3 line:64 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE13 [get_ports {EMIO_0_tri_io[27]}]
set_property src_info {type:XDC file:3 line:65 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF13 [get_ports {EMIO_0_tri_io[28]}]
set_property src_info {type:XDC file:3 line:66 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE11 [get_ports {EMIO_0_tri_io[29]}]
set_property src_info {type:XDC file:3 line:67 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AF10 [get_ports {EMIO_0_tri_io[30]}]
set_property src_info {type:XDC file:3 line:68 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN AE10 [get_ports {EMIO_0_tri_io[31]}]
set_property src_info {type:XDC file:3 line:69 export:INPUT save:INPUT read:READ} [current_design]
set_property PACKAGE_PIN W13 [get_ports {EMIO_0_tri_io[32]}]
set_property src_info {type:XDC file:4 line:79 export:INPUT save:INPUT read:READ} [current_design]
create_debug_core u_ila_0 ila
set_property src_info {type:XDC file:4 line:80 export:INPUT save:INPUT read:READ} [current_design]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:4 line:81 export:INPUT save:INPUT read:READ} [current_design]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:4 line:82 export:INPUT save:INPUT read:READ} [current_design]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:4 line:83 export:INPUT save:INPUT read:READ} [current_design]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:4 line:84 export:INPUT save:INPUT read:READ} [current_design]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:4 line:85 export:INPUT save:INPUT read:READ} [current_design]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:4 line:86 export:INPUT save:INPUT read:READ} [current_design]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:4 line:87 export:INPUT save:INPUT read:READ} [current_design]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property src_info {type:XDC file:4 line:88 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
set_property src_info {type:XDC file:4 line:89 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/clk [get_nets [list system_i/processing_system7_0/inst/FCLK_CLK0]]
set_property src_info {type:XDC file:4 line:90 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property src_info {type:XDC file:4 line:91 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe0]
set_property src_info {type:XDC file:4 line:92 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe0 [get_nets [list EMIO_0_tri_i_0]]
set_property src_info {type:XDC file:4 line:93 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:94 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property src_info {type:XDC file:4 line:95 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
set_property src_info {type:XDC file:4 line:96 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe1 [get_nets [list EMIO_0_tri_i_1]]
set_property src_info {type:XDC file:4 line:97 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:98 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property src_info {type:XDC file:4 line:99 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
set_property src_info {type:XDC file:4 line:100 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe2 [get_nets [list EMIO_0_tri_i_2]]
set_property src_info {type:XDC file:4 line:101 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:102 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
set_property src_info {type:XDC file:4 line:103 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
set_property src_info {type:XDC file:4 line:104 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe3 [get_nets [list EMIO_0_tri_i_3]]
set_property src_info {type:XDC file:4 line:105 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:106 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
set_property src_info {type:XDC file:4 line:107 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
set_property src_info {type:XDC file:4 line:108 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe4 [get_nets [list EMIO_0_tri_i_4]]
set_property src_info {type:XDC file:4 line:109 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:110 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
set_property src_info {type:XDC file:4 line:111 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
set_property src_info {type:XDC file:4 line:112 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe5 [get_nets [list EMIO_0_tri_i_5]]
set_property src_info {type:XDC file:4 line:113 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:114 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
set_property src_info {type:XDC file:4 line:115 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
set_property src_info {type:XDC file:4 line:116 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe6 [get_nets [list EMIO_0_tri_i_6]]
set_property src_info {type:XDC file:4 line:117 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:118 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
set_property src_info {type:XDC file:4 line:119 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
set_property src_info {type:XDC file:4 line:120 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe7 [get_nets [list EMIO_0_tri_i_7]]
set_property src_info {type:XDC file:4 line:121 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:122 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
set_property src_info {type:XDC file:4 line:123 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
set_property src_info {type:XDC file:4 line:124 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe8 [get_nets [list EMIO_0_tri_i_8]]
set_property src_info {type:XDC file:4 line:125 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:126 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
set_property src_info {type:XDC file:4 line:127 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
set_property src_info {type:XDC file:4 line:128 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe9 [get_nets [list EMIO_0_tri_i_9]]
set_property src_info {type:XDC file:4 line:129 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:130 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
set_property src_info {type:XDC file:4 line:131 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
set_property src_info {type:XDC file:4 line:132 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe10 [get_nets [list EMIO_0_tri_i_10]]
set_property src_info {type:XDC file:4 line:133 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:134 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
set_property src_info {type:XDC file:4 line:135 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
set_property src_info {type:XDC file:4 line:136 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe11 [get_nets [list EMIO_0_tri_i_11]]
set_property src_info {type:XDC file:4 line:137 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:138 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
set_property src_info {type:XDC file:4 line:139 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
set_property src_info {type:XDC file:4 line:140 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe12 [get_nets [list EMIO_0_tri_i_12]]
set_property src_info {type:XDC file:4 line:141 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:142 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
set_property src_info {type:XDC file:4 line:143 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
set_property src_info {type:XDC file:4 line:144 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe13 [get_nets [list EMIO_0_tri_i_13]]
set_property src_info {type:XDC file:4 line:145 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:146 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
set_property src_info {type:XDC file:4 line:147 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
set_property src_info {type:XDC file:4 line:148 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe14 [get_nets [list EMIO_0_tri_i_14]]
set_property src_info {type:XDC file:4 line:149 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:150 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
set_property src_info {type:XDC file:4 line:151 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
set_property src_info {type:XDC file:4 line:152 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe15 [get_nets [list EMIO_0_tri_i_15]]
set_property src_info {type:XDC file:4 line:153 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:154 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
set_property src_info {type:XDC file:4 line:155 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
set_property src_info {type:XDC file:4 line:156 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe16 [get_nets [list EMIO_0_tri_i_16]]
set_property src_info {type:XDC file:4 line:157 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:158 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
set_property src_info {type:XDC file:4 line:159 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
set_property src_info {type:XDC file:4 line:160 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe17 [get_nets [list EMIO_0_tri_i_17]]
set_property src_info {type:XDC file:4 line:161 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:162 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
set_property src_info {type:XDC file:4 line:163 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
set_property src_info {type:XDC file:4 line:164 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe18 [get_nets [list EMIO_0_tri_i_18]]
set_property src_info {type:XDC file:4 line:165 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:166 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
set_property src_info {type:XDC file:4 line:167 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
set_property src_info {type:XDC file:4 line:168 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe19 [get_nets [list EMIO_0_tri_i_19]]
set_property src_info {type:XDC file:4 line:169 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:170 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
set_property src_info {type:XDC file:4 line:171 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
set_property src_info {type:XDC file:4 line:172 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe20 [get_nets [list EMIO_0_tri_i_20]]
set_property src_info {type:XDC file:4 line:173 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:174 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
set_property src_info {type:XDC file:4 line:175 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
set_property src_info {type:XDC file:4 line:176 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe21 [get_nets [list EMIO_0_tri_i_21]]
set_property src_info {type:XDC file:4 line:177 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:178 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
set_property src_info {type:XDC file:4 line:179 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
set_property src_info {type:XDC file:4 line:180 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe22 [get_nets [list EMIO_0_tri_i_22]]
set_property src_info {type:XDC file:4 line:181 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:182 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
set_property src_info {type:XDC file:4 line:183 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
set_property src_info {type:XDC file:4 line:184 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe23 [get_nets [list EMIO_0_tri_i_23]]
set_property src_info {type:XDC file:4 line:185 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:186 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
set_property src_info {type:XDC file:4 line:187 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
set_property src_info {type:XDC file:4 line:188 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe24 [get_nets [list EMIO_0_tri_i_24]]
set_property src_info {type:XDC file:4 line:189 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:190 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
set_property src_info {type:XDC file:4 line:191 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
set_property src_info {type:XDC file:4 line:192 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe25 [get_nets [list EMIO_0_tri_i_25]]
set_property src_info {type:XDC file:4 line:193 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:194 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
set_property src_info {type:XDC file:4 line:195 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
set_property src_info {type:XDC file:4 line:196 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe26 [get_nets [list EMIO_0_tri_i_26]]
set_property src_info {type:XDC file:4 line:197 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:198 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
set_property src_info {type:XDC file:4 line:199 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
set_property src_info {type:XDC file:4 line:200 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe27 [get_nets [list EMIO_0_tri_i_27]]
set_property src_info {type:XDC file:4 line:201 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:202 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
set_property src_info {type:XDC file:4 line:203 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
set_property src_info {type:XDC file:4 line:204 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe28 [get_nets [list EMIO_0_tri_i_28]]
set_property src_info {type:XDC file:4 line:205 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:206 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
set_property src_info {type:XDC file:4 line:207 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
set_property src_info {type:XDC file:4 line:208 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe29 [get_nets [list EMIO_0_tri_i_29]]
set_property src_info {type:XDC file:4 line:209 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:210 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
set_property src_info {type:XDC file:4 line:211 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
set_property src_info {type:XDC file:4 line:212 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe30 [get_nets [list EMIO_0_tri_i_30]]
set_property src_info {type:XDC file:4 line:213 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:214 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
set_property src_info {type:XDC file:4 line:215 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
set_property src_info {type:XDC file:4 line:216 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe31 [get_nets [list EMIO_0_tri_i_31]]
set_property src_info {type:XDC file:4 line:217 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:218 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
set_property src_info {type:XDC file:4 line:219 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
set_property src_info {type:XDC file:4 line:220 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe32 [get_nets [list EMIO_0_tri_i_32]]
set_property src_info {type:XDC file:4 line:221 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:222 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
set_property src_info {type:XDC file:4 line:223 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
set_property src_info {type:XDC file:4 line:224 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe33 [get_nets [list EMIO_0_tri_o_0]]
set_property src_info {type:XDC file:4 line:225 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:226 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
set_property src_info {type:XDC file:4 line:227 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
set_property src_info {type:XDC file:4 line:228 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe34 [get_nets [list EMIO_0_tri_o_1]]
set_property src_info {type:XDC file:4 line:229 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:230 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
set_property src_info {type:XDC file:4 line:231 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
set_property src_info {type:XDC file:4 line:232 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe35 [get_nets [list EMIO_0_tri_o_2]]
set_property src_info {type:XDC file:4 line:233 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:234 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
set_property src_info {type:XDC file:4 line:235 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
set_property src_info {type:XDC file:4 line:236 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe36 [get_nets [list EMIO_0_tri_o_3]]
set_property src_info {type:XDC file:4 line:237 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:238 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
set_property src_info {type:XDC file:4 line:239 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
set_property src_info {type:XDC file:4 line:240 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe37 [get_nets [list EMIO_0_tri_o_4]]
set_property src_info {type:XDC file:4 line:241 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:242 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
set_property src_info {type:XDC file:4 line:243 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
set_property src_info {type:XDC file:4 line:244 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe38 [get_nets [list EMIO_0_tri_o_5]]
set_property src_info {type:XDC file:4 line:245 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:246 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
set_property src_info {type:XDC file:4 line:247 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
set_property src_info {type:XDC file:4 line:248 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe39 [get_nets [list EMIO_0_tri_o_6]]
set_property src_info {type:XDC file:4 line:249 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:250 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
set_property src_info {type:XDC file:4 line:251 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
set_property src_info {type:XDC file:4 line:252 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe40 [get_nets [list EMIO_0_tri_o_7]]
set_property src_info {type:XDC file:4 line:253 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:254 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
set_property src_info {type:XDC file:4 line:255 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
set_property src_info {type:XDC file:4 line:256 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe41 [get_nets [list EMIO_0_tri_o_8]]
set_property src_info {type:XDC file:4 line:257 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:258 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
set_property src_info {type:XDC file:4 line:259 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
set_property src_info {type:XDC file:4 line:260 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe42 [get_nets [list EMIO_0_tri_o_9]]
set_property src_info {type:XDC file:4 line:261 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:262 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
set_property src_info {type:XDC file:4 line:263 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
set_property src_info {type:XDC file:4 line:264 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe43 [get_nets [list EMIO_0_tri_o_10]]
set_property src_info {type:XDC file:4 line:265 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:266 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
set_property src_info {type:XDC file:4 line:267 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
set_property src_info {type:XDC file:4 line:268 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe44 [get_nets [list EMIO_0_tri_o_11]]
set_property src_info {type:XDC file:4 line:269 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:270 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
set_property src_info {type:XDC file:4 line:271 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
set_property src_info {type:XDC file:4 line:272 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe45 [get_nets [list EMIO_0_tri_o_12]]
set_property src_info {type:XDC file:4 line:273 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:274 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
set_property src_info {type:XDC file:4 line:275 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
set_property src_info {type:XDC file:4 line:276 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe46 [get_nets [list EMIO_0_tri_o_13]]
set_property src_info {type:XDC file:4 line:277 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:278 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
set_property src_info {type:XDC file:4 line:279 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
set_property src_info {type:XDC file:4 line:280 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe47 [get_nets [list EMIO_0_tri_o_14]]
set_property src_info {type:XDC file:4 line:281 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:282 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
set_property src_info {type:XDC file:4 line:283 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
set_property src_info {type:XDC file:4 line:284 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe48 [get_nets [list EMIO_0_tri_o_15]]
set_property src_info {type:XDC file:4 line:285 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:286 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
set_property src_info {type:XDC file:4 line:287 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
set_property src_info {type:XDC file:4 line:288 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe49 [get_nets [list EMIO_0_tri_o_16]]
set_property src_info {type:XDC file:4 line:289 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:290 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
set_property src_info {type:XDC file:4 line:291 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
set_property src_info {type:XDC file:4 line:292 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe50 [get_nets [list EMIO_0_tri_o_17]]
set_property src_info {type:XDC file:4 line:293 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:294 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
set_property src_info {type:XDC file:4 line:295 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
set_property src_info {type:XDC file:4 line:296 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe51 [get_nets [list EMIO_0_tri_o_18]]
set_property src_info {type:XDC file:4 line:297 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:298 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
set_property src_info {type:XDC file:4 line:299 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
set_property src_info {type:XDC file:4 line:300 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe52 [get_nets [list EMIO_0_tri_o_19]]
set_property src_info {type:XDC file:4 line:301 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:302 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
set_property src_info {type:XDC file:4 line:303 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
set_property src_info {type:XDC file:4 line:304 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe53 [get_nets [list EMIO_0_tri_o_20]]
set_property src_info {type:XDC file:4 line:305 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:306 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
set_property src_info {type:XDC file:4 line:307 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
set_property src_info {type:XDC file:4 line:308 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe54 [get_nets [list EMIO_0_tri_o_21]]
set_property src_info {type:XDC file:4 line:309 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:310 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
set_property src_info {type:XDC file:4 line:311 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
set_property src_info {type:XDC file:4 line:312 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe55 [get_nets [list EMIO_0_tri_o_22]]
set_property src_info {type:XDC file:4 line:313 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:314 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
set_property src_info {type:XDC file:4 line:315 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
set_property src_info {type:XDC file:4 line:316 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe56 [get_nets [list EMIO_0_tri_o_23]]
set_property src_info {type:XDC file:4 line:317 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:318 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
set_property src_info {type:XDC file:4 line:319 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
set_property src_info {type:XDC file:4 line:320 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe57 [get_nets [list EMIO_0_tri_o_24]]
set_property src_info {type:XDC file:4 line:321 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:322 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
set_property src_info {type:XDC file:4 line:323 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
set_property src_info {type:XDC file:4 line:324 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe58 [get_nets [list EMIO_0_tri_o_25]]
set_property src_info {type:XDC file:4 line:325 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:326 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
set_property src_info {type:XDC file:4 line:327 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
set_property src_info {type:XDC file:4 line:328 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe59 [get_nets [list EMIO_0_tri_o_26]]
set_property src_info {type:XDC file:4 line:329 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:330 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
set_property src_info {type:XDC file:4 line:331 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
set_property src_info {type:XDC file:4 line:332 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe60 [get_nets [list EMIO_0_tri_o_27]]
set_property src_info {type:XDC file:4 line:333 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:334 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
set_property src_info {type:XDC file:4 line:335 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
set_property src_info {type:XDC file:4 line:336 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe61 [get_nets [list EMIO_0_tri_o_28]]
set_property src_info {type:XDC file:4 line:337 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:338 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
set_property src_info {type:XDC file:4 line:339 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
set_property src_info {type:XDC file:4 line:340 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe62 [get_nets [list EMIO_0_tri_o_29]]
set_property src_info {type:XDC file:4 line:341 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:342 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
set_property src_info {type:XDC file:4 line:343 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
set_property src_info {type:XDC file:4 line:344 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe63 [get_nets [list EMIO_0_tri_o_30]]
set_property src_info {type:XDC file:4 line:345 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:346 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
set_property src_info {type:XDC file:4 line:347 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
set_property src_info {type:XDC file:4 line:348 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe64 [get_nets [list EMIO_0_tri_o_31]]
set_property src_info {type:XDC file:4 line:349 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:350 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
set_property src_info {type:XDC file:4 line:351 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe65]
set_property src_info {type:XDC file:4 line:352 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe65 [get_nets [list EMIO_0_tri_o_32]]
set_property src_info {type:XDC file:4 line:353 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:354 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
set_property src_info {type:XDC file:4 line:355 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe66]
set_property src_info {type:XDC file:4 line:356 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe66 [get_nets [list EMIO_0_tri_t_0]]
set_property src_info {type:XDC file:4 line:357 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:358 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
set_property src_info {type:XDC file:4 line:359 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe67]
set_property src_info {type:XDC file:4 line:360 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe67 [get_nets [list EMIO_0_tri_t_1]]
set_property src_info {type:XDC file:4 line:361 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:362 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
set_property src_info {type:XDC file:4 line:363 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe68]
set_property src_info {type:XDC file:4 line:364 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe68 [get_nets [list EMIO_0_tri_t_2]]
set_property src_info {type:XDC file:4 line:365 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:366 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
set_property src_info {type:XDC file:4 line:367 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe69]
set_property src_info {type:XDC file:4 line:368 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe69 [get_nets [list EMIO_0_tri_t_3]]
set_property src_info {type:XDC file:4 line:369 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:370 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
set_property src_info {type:XDC file:4 line:371 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe70]
set_property src_info {type:XDC file:4 line:372 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe70 [get_nets [list EMIO_0_tri_t_4]]
set_property src_info {type:XDC file:4 line:373 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:374 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
set_property src_info {type:XDC file:4 line:375 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe71]
set_property src_info {type:XDC file:4 line:376 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe71 [get_nets [list EMIO_0_tri_t_5]]
set_property src_info {type:XDC file:4 line:377 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:378 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72]
set_property src_info {type:XDC file:4 line:379 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe72]
set_property src_info {type:XDC file:4 line:380 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe72 [get_nets [list EMIO_0_tri_t_6]]
set_property src_info {type:XDC file:4 line:381 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:382 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
set_property src_info {type:XDC file:4 line:383 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe73]
set_property src_info {type:XDC file:4 line:384 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe73 [get_nets [list EMIO_0_tri_t_7]]
set_property src_info {type:XDC file:4 line:385 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:386 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74]
set_property src_info {type:XDC file:4 line:387 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe74]
set_property src_info {type:XDC file:4 line:388 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe74 [get_nets [list EMIO_0_tri_t_8]]
set_property src_info {type:XDC file:4 line:389 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:390 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75]
set_property src_info {type:XDC file:4 line:391 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe75]
set_property src_info {type:XDC file:4 line:392 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe75 [get_nets [list EMIO_0_tri_t_9]]
set_property src_info {type:XDC file:4 line:393 export:INPUT save:INPUT read:READ} [current_design]
create_debug_port u_ila_0 probe
set_property src_info {type:XDC file:4 line:394 export:INPUT save:INPUT read:READ} [current_design]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76]
set_property src_info {type:XDC file:4 line:395 export:INPUT save:INPUT read:READ} [current_design]
set_property port_width 1 [get_debug_ports u_ila_0/probe76]
set_property src_info {type:XDC file:4 line:396 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port u_ila_0/probe76 [get_nets [list EMIO_0_tri_t_10]]
set_property src_info {type:XDC file:4 line:397 export:INPUT save:INPUT read:READ} [current_design]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property src_info {type:XDC file:4 line:398 export:INPUT save:INPUT read:READ} [current_design]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property src_info {type:XDC file:4 line:399 export:INPUT save:INPUT read:READ} [current_design]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
set_property src_info {type:XDC file:4 line:400 export:INPUT save:INPUT read:READ} [current_design]
connect_debug_port dbg_hub/clk [get_nets u_ila_0_FCLK_CLK0]
Debug_FW.runs/synth_1/.vivado.begin.rst
+5
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@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="ly0kos" Host="mkb" Pid="958816" HostCore="32" HostMemory="131002412">
</Process>
</ProcessHandle>
Debug_FW.runs/synth_1/.vivado.end.rst
View File
Debug_FW.runs/synth_1/ISEWrap.js
Executable
+270
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@@ -0,0 +1,270 @@
//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var wbemFlagReturnImmediately = 0x10;
var wbemFlagForwardOnly = 0x20;
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
var NOC = 0;
var NOLP = 0;
var TPM = 0;
var cpuInfos = new Enumerator(processor);
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
var cpuInfo = cpuInfos.item();
NOC += cpuInfo.NumberOfCores;
NOLP += cpuInfo.NumberOfLogicalProcessors;
}
var csInfos = new Enumerator(computerSystem);
for(;!csInfos.atEnd(); csInfos.moveNext()) {
var csInfo = csInfos.item();
TPM += csInfo.TotalPhysicalMemory;
}
var ISEHOSTCORE = NOLP
var ISEMEMTOTAL = TPM
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\" HostCore=\"" + ISEHOSTCORE +
"\" HostMemory=\"" + ISEMEMTOTAL +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}
Debug_FW.runs/synth_1/ISEWrap.sh
Executable
+85
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@@ -0,0 +1,85 @@
#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
#
cmd_exists()
{
command -v "$1" >/dev/null 2>&1
}
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
HostNameFile=/proc/sys/kernel/hostname
if cmd_exists hostname
then
ISE_HOST=$(hostname)
elif cmd_exists uname
then
ISE_HOST=$(uname -n)
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
then
ISE_HOST=$(cat $HostNameFile)
elif [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL
Debug_FW.runs/synth_1/__synthesis_is_complete__
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Debug_FW.runs/synth_1/dont_touch.xdc
+42
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@@ -0,0 +1,42 @@
# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.
# XDC: new/pin_cons.xdc
# XDC: new/pin_debug.xdc
# Block Designs: bd/system/system.bd
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system || ORIG_REF_NAME==system} -quiet] -quiet
# IP: bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system_processing_system7_0_0 || ORIG_REF_NAME==system_processing_system7_0_0} -quiet] -quiet
# IP: bd/system/ip/system_dna_port_read_0_0/system_dna_port_read_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system_dna_port_read_0_0 || ORIG_REF_NAME==system_dna_port_read_0_0} -quiet] -quiet
# IP: bd/system/ip/system_mydna_read_v1_0_0_0/system_mydna_read_v1_0_0_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system_mydna_read_v1_0_0_0 || ORIG_REF_NAME==system_mydna_read_v1_0_0_0} -quiet] -quiet
# IP: bd/system/ip/system_auto_pc_0/system_auto_pc_0.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system_auto_pc_0 || ORIG_REF_NAME==system_auto_pc_0} -quiet] -quiet
# IP: bd/system/ip/system_ps7_0_axi_periph_1/system_ps7_0_axi_periph_1.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system_ps7_0_axi_periph_1 || ORIG_REF_NAME==system_ps7_0_axi_periph_1} -quiet] -quiet
# IP: bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xci
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system_rst_ps7_0_100M_1 || ORIG_REF_NAME==system_rst_ps7_0_100M_1} -quiet] -quiet
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc
set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filter {REF_NAME==system_processing_system7_0_0 || ORIG_REF_NAME==system_processing_system7_0_0} -quiet] {/inst } ]/inst ] -quiet] -quiet
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc
set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filter {REF_NAME==system_rst_ps7_0_100M_1 || ORIG_REF_NAME==system_rst_ps7_0_100M_1} -quiet] {/U0 } ]/U0 ] -quiet] -quiet
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc
#dup# set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filter {REF_NAME==system_rst_ps7_0_100M_1 || ORIG_REF_NAME==system_rst_ps7_0_100M_1} -quiet] {/U0 } ]/U0 ] -quiet] -quiet
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_ooc.xdc
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/system_ooc.xdc
Debug_FW.runs/synth_1/gen_run.xml
+98
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@@ -0,0 +1,98 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7z035ffg676-2" LaunchTime="1779870965">
<File Type="VDS-TIMINGSUMMARY" Name="system_wrapper_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="system_wrapper.dcp"/>
<File Type="RDS-UTIL-PB" Name="system_wrapper_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="system_wrapper_utilization_synth.rpt"/>
<File Type="RDS-PROPCONSTRS" Name="system_wrapper_drc_synth.rpt"/>
<File Type="RDS-RDS" Name="system_wrapper.vds"/>
<File Type="REPORTS-TCL" Name="system_wrapper_reports.tcl"/>
<File Type="VDS-TIMING-PB" Name="system_wrapper_timing_summary_synth.pb"/>
<File Type="PA-TCL" Name="system_wrapper.tcl"/>
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/src/dna_port_read.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/sources_1/src/dna_port_read.v"/>
<Attr Name="ImportTime" Val="1779770889"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/src/mydna_read_v1_0_S00_AXI.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v"/>
<Attr Name="ImportTime" Val="1779770889"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/src/mydna_read_v1_0.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/sources_1/src/mydna_read_v1_0.v"/>
<Attr Name="ImportTime" Val="1779770889"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/system/system.bd">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/sources_1/bd/system/system.bd"/>
<Attr Name="ImportTime" Val="1779870939"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PGENDIR/sources_1/bd/system/hdl/system_wrapper.v">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.gen/sources_1/bd/system/hdl/system_wrapper.v"/>
<Attr Name="ImportTime" Val="1779691907"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="system_wrapper"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/pin_cons.xdc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/constrs_1/new/pin_cons.xdc"/>
<Attr Name="ImportTime" Val="1779869379"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/constrs_1/new/pin_debug.xdc">
<FileInfo>
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/constrs_1/new/pin_debug.xdc"/>
<Attr Name="ImportTime" Val="1779869379"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/pin_debug.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
Debug_FW.runs/synth_1/htr.txt
+10
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@@ -0,0 +1,10 @@
#
# Vivado(TM)
# htr.txt: a Vivado-generated description of how-to-repeat the
# the basic steps of a run. Note that runme.bat/sh needs
# to be invoked for Vivado to track run status.
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
#
vivado -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
Debug_FW.runs/synth_1/rundef.js
+41
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@@ -0,0 +1,41 @@
//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
//
echo "This script was generated under a different operating system."
echo "Please update the PATH variable below, before executing this script"
exit
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;";
} else {
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
ISEStep( "vivado",
"-log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}
Debug_FW.runs/synth_1/runme.bat
+12
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@@ -0,0 +1,12 @@
@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
set PATH=%SYSTEMROOT%\system32;%PATH%
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
Debug_FW.runs/synth_1/runme.log
+696
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@@ -0,0 +1,696 @@
*** Running vivado
with args -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
****** Vivado v2023.2 (64-bit)
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source system_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
Command: synth_design -top system_wrapper -part xc7z035ffg676-2
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
INFO: [Device 21-403] Loading part xc7z035ffg676-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 958941
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2149.453 ; gain = 411.629 ; free physical = 845 ; free virtual = 70077
---------------------------------------------------------------------------------
WARNING: [Synth 8-11121] redeclaration of ANSI port 'read_vld' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:33]
WARNING: [Synth 8-11121] redeclaration of ANSI port 'dna_port' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:34]
INFO: [Synth 8-6157] synthesizing module 'system_wrapper' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13]
INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
INFO: [Synth 8-6157] synthesizing module 'system' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318]
INFO: [Synth 8-6157] synthesizing module 'system_dna_port_read_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'dna_port_read' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23]
INFO: [Synth 8-6157] synthesizing module 'DNA_PORT' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264]
Parameter SIM_DNA_VALUE bound to: 57'b000000000000000000000000000000000000000000000000000000000
INFO: [Synth 8-6155] done synthesizing module 'DNA_PORT' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264]
INFO: [Synth 8-6155] done synthesizing module 'dna_port_read' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23]
INFO: [Synth 8-6155] done synthesizing module 'system_dna_port_read_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'system_mydna_read_v1_0_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4]
Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4]
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:235]
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:379]
INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4]
INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4]
INFO: [Synth 8-6155] done synthesizing module 'system_mydna_read_v1_0_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'system_processing_system7_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
INFO: [Synth 8-6157] synthesizing module 'BIBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
INFO: [Synth 8-6157] synthesizing module 'PS7' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
INFO: [Synth 8-6155] done synthesizing module 'PS7' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
INFO: [Synth 8-6155] done synthesizing module 'system_processing_system7_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'system_ps7_0_axi_periph_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632]
INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_11SE3QO' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13]
INFO: [Synth 8-6157] synthesizing module 'system_auto_pc_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392]
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3446]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546]
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3608]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'SI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871]
WARNING: [Synth 8-7023] instance 'SI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'MI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126]
WARNING: [Synth 8-7023] instance 'MI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285]
INFO: [Synth 8-6155] done synthesizing module 'system_auto_pc_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53]
INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_11SE3QO' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13]
INFO: [Synth 8-6155] done synthesizing module 'system_ps7_0_axi_periph_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632]
INFO: [Synth 8-638] synthesizing module 'system_rst_ps7_0_100M_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
Parameter C_EXT_RESET_HIGH bound to: 1'b0
Parameter C_AUX_RESET_HIGH bound to: 1'b0
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:129]
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488]
INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873]
INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
INFO: [Synth 8-256] done synthesizing module 'system_rst_ps7_0_100M_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74]
WARNING: [Synth 8-7071] port 'mb_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
WARNING: [Synth 8-7023] instance 'rst_ps7_0_100M' of module 'system_rst_ps7_0_100M_1' has 10 connections declared, but only 7 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
INFO: [Synth 8-6155] done synthesizing module 'system' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318]
INFO: [Synth 8-6155] done synthesizing module 'system_wrapper' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13]
WARNING: [Synth 8-6014] Unused sequential element slv_reg1_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:228]
WARNING: [Synth 8-6014] Unused sequential element slv_reg2_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:229]
WARNING: [Synth 8-6014] Unused sequential element state_r1_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3596]
WARNING: [Synth 8-6014] Unused sequential element s_arlen_r_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3597]
WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_bid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_rid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_rlast in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wlast in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_arlen[7] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_arlen[6] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_arlen[5] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_arlen[4] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_arlen[3] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_arlen[2] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 767 ; free virtual = 69885
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891
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Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2359.391 ; gain = 0.000 ; free physical = 749 ; free virtual = 69874
INFO: [Netlist 29-17] Analyzing 46 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2518.867 ; gain = 0.000 ; free physical = 714 ; free virtual = 69858
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 46 instances were transformed.
FDR => FDRE: 12 instances
IOBUF => IOBUF (IBUF, OBUFT): 33 instances
SRL16 => SRL16E: 1 instance
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 872 ; free virtual = 69870
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Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 946 ; free virtual = 69833
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Start Loading Part and Timing Information
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Loading part: xc7z035ffg676-2
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 945 ; free virtual = 69833
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Start Applying 'set_property' XDC Constraints
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Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 1).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_1. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 2).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_2. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 3).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_3. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 4).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_4. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 5).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_5. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 6).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_6. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 7).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_7. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 8).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_8. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 9).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_9. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 10).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_10. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 11).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_11. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 12).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_12. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 13).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_13. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 14).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_14. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 15).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_15. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 16).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_16. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 17).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_17. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 18).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_18. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 19).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_19. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 20).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_20. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 21).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_21. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 22).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_22. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 23).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_23. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 24).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_24. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 25).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_25. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 26).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_28. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 27).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_29. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 28).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_30. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 29).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_26. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 30).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_27. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 31).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_31. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 32).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_32. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 33).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_o_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 34).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_t_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 67).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0/inst. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 30).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M/U0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 35).
Applied set_property KEEP_HIERARCHY = SOFT for system_i. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/dna_port_read_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/mydna_read_v1_0_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph/s00_couplers/auto_pc. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M. (constraint file auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 940 ; free virtual = 69830
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm'
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_0'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:213]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_1'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:218]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_2'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:273]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_3'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:328]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_4'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:348]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_5'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:353]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_6'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:358]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_7'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:363]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_8'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:368]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_9'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:373]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_10'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:223]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_11'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:228]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_12'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:233]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_13'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:238]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_14'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:243]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_15'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:248]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_16'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:253]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_17'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:258]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_18'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:263]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_19'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:268]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_20'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:278]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_21'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:283]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_22'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:288]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_23'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:293]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_24'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:298]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_25'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:303]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_28'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:318]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_29'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:323]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_30'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:333]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_26'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:308]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_27'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:313]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_31'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:338]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_32'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:343]
WARNING: [Synth 8-327] inferring latch for variable 'dna_port_reg_reg' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:413]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
SM_IDLE | 01 | 00
SM_CMD_EN | 11 | 01
SM_CMD_ACCEPTED | 10 | 10
SM_DONE_WAIT | 00 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
SM_IDLE | 01 | 00
SM_CMD_EN | 11 | 01
SM_CMD_ACCEPTED | 10 | 10
SM_DONE | 00 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 929 ; free virtual = 69825
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 8
2 Input 9 Bit Adders := 2
2 Input 8 Bit Adders := 2
2 Input 6 Bit Adders := 1
2 Input 5 Bit Adders := 4
2 Input 4 Bit Adders := 4
2 Input 2 Bit Adders := 2
+---Registers :
66 Bit Registers := 4
57 Bit Registers := 1
47 Bit Registers := 2
32 Bit Registers := 3
14 Bit Registers := 2
12 Bit Registers := 9
9 Bit Registers := 2
8 Bit Registers := 3
6 Bit Registers := 1
5 Bit Registers := 4
4 Bit Registers := 8
3 Bit Registers := 3
2 Bit Registers := 9
1 Bit Registers := 43
+---Muxes :
2 Input 66 Bit Muxes := 4
2 Input 47 Bit Muxes := 2
4 Input 32 Bit Muxes := 3
2 Input 32 Bit Muxes := 9
2 Input 14 Bit Muxes := 2
2 Input 12 Bit Muxes := 6
2 Input 9 Bit Muxes := 4
2 Input 8 Bit Muxes := 1
2 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 4
2 Input 4 Bit Muxes := 18
2 Input 2 Bit Muxes := 17
4 Input 2 Bit Muxes := 4
2 Input 1 Bit Muxes := 37
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 900 (col length:140)
BRAMs: 1000 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (FDRE_inst) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (BSR_OUT_DFF[0].FDRE_BSR) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (PR_OUT_DFF[0].FDRE_PER) is unused and will be removed from module proc_sys_reset.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1838 ; free virtual = 70743
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1815 ; free virtual = 70747
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1781 ; free virtual = 70713
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1765 ; free virtual = 70711
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
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Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
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Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
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Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Dynamic Shift Register Report:
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|dsrl | memory_reg[3] | 20 | 20 | 20 | 0 | 0 | 0 | 0 |
|dsrl__1 | memory_reg[3] | 2 | 2 | 2 | 0 | 0 | 0 | 0 |
|dsrl__2 | memory_reg[31] | 34 | 34 | 0 | 34 | 0 | 0 | 0 |
|dsrl__3 | memory_reg[31] | 13 | 13 | 0 | 13 | 0 | 0 | 0 |
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+---------+------+
| |Cell |Count |
+------+---------+------+
|1 |BIBUF | 130|
|2 |BUFG | 1|
|3 |CARRY4 | 6|
|4 |DNA_PORT | 1|
|5 |LUT1 | 69|
|6 |LUT2 | 24|
|7 |LUT3 | 169|
|8 |LUT4 | 52|
|9 |LUT5 | 71|
|10 |LUT6 | 118|
|11 |PS7 | 1|
|12 |SRL16 | 1|
|13 |SRL16E | 16|
|14 |SRLC32E | 45|
|15 |FDCE | 66|
|16 |FDR | 4|
|17 |FDRE | 501|
|18 |FDSE | 20|
|19 |LD | 57|
|20 |IOBUF | 33|
+------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 136 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 618.598 ; free physical = 1531 ; free virtual = 70510
Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1531 ; free virtual = 70509
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 1748 ; free virtual = 70732
INFO: [Netlist 29-17] Analyzing 101 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2563.766 ; gain = 0.000 ; free physical = 1757 ; free virtual = 70743
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 95 instances were transformed.
FDR => FDRE: 4 instances
IOBUF => IOBUF (IBUF, OBUFT): 33 instances
LD => LDCE: 57 instances
SRL16 => SRL16E: 1 instance
Synth Design complete | Checksum: 8993d7c
INFO: [Common 17-83] Releasing license: Synthesis
187 Infos, 142 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2563.801 ; gain = 1259.379 ; free physical = 1759 ; free virtual = 70746
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1991.605; main = 1727.861; forked = 379.983
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3465.613; main = 2563.770; forked = 1042.766
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2611.777 ; gain = 0.000 ; free physical = 1758 ; free virtual = 70746
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:36:31 2026...
Debug_FW.runs/synth_1/runme.sh
Executable
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@@ -0,0 +1,40 @@
#!/bin/sh
#
# Vivado(TM)
# runme.sh: a Vivado-generated Runs Script for UNIX
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
#
if [ -z "$PATH" ]; then
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin
else
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH
fi
export PATH
if [ -z "$LD_LIBRARY_PATH" ]; then
LD_LIBRARY_PATH=
else
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
fi
export LD_LIBRARY_PATH
HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1'
cd "$HD_PWD"
HD_LOG=runme.log
/bin/touch $HD_LOG
ISEStep="./ISEWrap.sh"
EAStep()
{
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
if [ $? -ne 0 ]
then
exit
fi
}
EAStep vivado -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
Debug_FW.runs/synth_1/system_wrapper.dcp
BIN
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Debug_FW.runs/synth_1/system_wrapper.tcl
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#
# Synthesis run script generated by Vivado
#
set TIME_start [clock seconds]
namespace eval ::optrace {
variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.tcl"
variable category "vivado_synth"
}
# Try to connect to running dispatch if we haven't done so already.
# This code assumes that the Tcl interpreter is not using threads,
# since the ::dispatch::connected variable isn't mutex protected.
if {![info exists ::dispatch::connected]} {
namespace eval ::dispatch {
variable connected false
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
set result "true"
if {[catch {
if {[lsearch -exact [package names] DispatchTcl] < 0} {
set result [load librdi_cd_clienttcl[info sharedlibextension]]
}
if {$result eq "false"} {
puts "WARNING: Could not load dispatch client library"
}
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
if { $connect_id eq "" } {
puts "WARNING: Could not initialize dispatch client"
} else {
puts "INFO: Dispatch client connection id - $connect_id"
set connected true
}
} catch_res]} {
puts "WARNING: failed to connect to dispatch server - $catch_res"
}
}
}
}
if {$::dispatch::connected} {
# Remove the dummy proc if it exists.
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
rename ::OPTRACE ""
}
proc ::OPTRACE { task action {tags {} } } {
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
}
# dispatch is generic. We specifically want to attach logging.
::vitis_log::connect_client
} else {
# Add dummy proc if it doesn't exist.
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
# Do nothing
}
}
}
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
OPTRACE "synth_1" START { ROLLUP_AUTO }
set_param chipscope.maxJobs 8
set_msg_config -id {HDL-1065} -limit 10000
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7z035ffg676-2
set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.cache/wt [current_project]
set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.xpr [current_project]
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
OPTRACE "Creating in-memory project" END { }
OPTRACE "Adding files" START { }
read_verilog -library xil_defaultlib {
/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v
/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v
/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v
/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v
}
add_files /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/bd/system/system.bd
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc]
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc]
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_ooc.xdc]
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/system_ooc.xdc]
OPTRACE "Adding files" END { }
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
set_property used_in_implementation false $dcp
}
read_xdc /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc
set_property used_in_implementation false [get_files /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
read_xdc /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc
set_property used_in_implementation false [get_files /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
read_xdc dont_touch.xdc
set_property used_in_implementation false [get_files dont_touch.xdc]
set_param ips.enableIPCacheLiteLoad 1
close [open __synthesis_is_running__ w]
OPTRACE "synth_design" START { }
synth_design -top system_wrapper -part xc7z035ffg676-2
OPTRACE "synth_design" END { }
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
}
OPTRACE "write_checkpoint" START { CHECKPOINT }
# disable binary constraint mode for synth run checkpoints
set_param constraints.enableBinaryConstraints false
write_checkpoint -force -noxdef system_wrapper.dcp
OPTRACE "write_checkpoint" END { }
OPTRACE "synth reports" START { REPORT }
create_report "synth_1_synth_report_utilization_0" "report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb"
OPTRACE "synth reports" END { }
file delete __synthesis_is_running__
close [open __synthesis_is_complete__ w]
OPTRACE "synth_1" END { }
Debug_FW.runs/synth_1/system_wrapper.vds
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#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Wed May 27 16:36:06 2026
# Process ID: 958858
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1
# Command line: vivado -log system_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.vds
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/vivado.jou
# Running On: mkb, OS: Linux, CPU Frequency: 4933.113 MHz, CPU Physical cores: 32, Host memory: 134146 MB
#-----------------------------------------------------------
source system_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
Command: synth_design -top system_wrapper -part xc7z035ffg676-2
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
INFO: [Device 21-403] Loading part xc7z035ffg676-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 958941
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2149.453 ; gain = 411.629 ; free physical = 845 ; free virtual = 70077
---------------------------------------------------------------------------------
WARNING: [Synth 8-11121] redeclaration of ANSI port 'read_vld' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:33]
WARNING: [Synth 8-11121] redeclaration of ANSI port 'dna_port' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:34]
INFO: [Synth 8-6157] synthesizing module 'system_wrapper' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13]
INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
INFO: [Synth 8-6157] synthesizing module 'system' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318]
INFO: [Synth 8-6157] synthesizing module 'system_dna_port_read_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'dna_port_read' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23]
INFO: [Synth 8-6157] synthesizing module 'DNA_PORT' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264]
Parameter SIM_DNA_VALUE bound to: 57'b000000000000000000000000000000000000000000000000000000000
INFO: [Synth 8-6155] done synthesizing module 'DNA_PORT' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264]
INFO: [Synth 8-6155] done synthesizing module 'dna_port_read' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23]
INFO: [Synth 8-6155] done synthesizing module 'system_dna_port_read_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'system_mydna_read_v1_0_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4]
Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4]
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:235]
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:379]
INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4]
INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4]
INFO: [Synth 8-6155] done synthesizing module 'system_mydna_read_v1_0_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'system_processing_system7_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
INFO: [Synth 8-6157] synthesizing module 'BIBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
INFO: [Synth 8-6157] synthesizing module 'PS7' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
INFO: [Synth 8-6155] done synthesizing module 'PS7' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
INFO: [Synth 8-6155] done synthesizing module 'system_processing_system7_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'system_ps7_0_axi_periph_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632]
INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_11SE3QO' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13]
INFO: [Synth 8-6157] synthesizing module 'system_auto_pc_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392]
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3446]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546]
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3608]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'SI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871]
WARNING: [Synth 8-7023] instance 'SI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'MI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126]
WARNING: [Synth 8-7023] instance 'MI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704]
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285]
INFO: [Synth 8-6155] done synthesizing module 'system_auto_pc_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53]
INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_11SE3QO' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13]
INFO: [Synth 8-6155] done synthesizing module 'system_ps7_0_axi_periph_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632]
INFO: [Synth 8-638] synthesizing module 'system_rst_ps7_0_100M_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74]
Parameter C_FAMILY bound to: zynq - type: string
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
Parameter C_EXT_RESET_HIGH bound to: 1'b0
Parameter C_AUX_RESET_HIGH bound to: 1'b0
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:129]
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441]
Parameter INIT bound to: 1'b1
INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488]
INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873]
INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
Parameter INIT bound to: 1'b0
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
INFO: [Synth 8-256] done synthesizing module 'system_rst_ps7_0_100M_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74]
WARNING: [Synth 8-7071] port 'mb_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
WARNING: [Synth 8-7023] instance 'rst_ps7_0_100M' of module 'system_rst_ps7_0_100M_1' has 10 connections declared, but only 7 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
INFO: [Synth 8-6155] done synthesizing module 'system' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318]
INFO: [Synth 8-6155] done synthesizing module 'system_wrapper' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13]
WARNING: [Synth 8-6014] Unused sequential element slv_reg1_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:228]
WARNING: [Synth 8-6014] Unused sequential element slv_reg2_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:229]
WARNING: [Synth 8-6014] Unused sequential element state_r1_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3596]
WARNING: [Synth 8-6014] Unused sequential element s_arlen_r_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3597]
WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_bid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_rid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_rlast in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wlast in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_arlen[7] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_arlen[6] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_arlen[5] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_arlen[4] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_arlen[3] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
WARNING: [Synth 8-7129] Port s_arlen[2] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 767 ; free virtual = 69885
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891
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Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2359.391 ; gain = 0.000 ; free physical = 749 ; free virtual = 69874
INFO: [Netlist 29-17] Analyzing 46 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2518.867 ; gain = 0.000 ; free physical = 714 ; free virtual = 69858
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 46 instances were transformed.
FDR => FDRE: 12 instances
IOBUF => IOBUF (IBUF, OBUFT): 33 instances
SRL16 => SRL16E: 1 instance
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 872 ; free virtual = 69870
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Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 946 ; free virtual = 69833
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Start Loading Part and Timing Information
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Loading part: xc7z035ffg676-2
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 945 ; free virtual = 69833
---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
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Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 1).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_1. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 2).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_2. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 3).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_3. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 4).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_4. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 5).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_5. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 6).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_6. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 7).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_7. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 8).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_8. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 9).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_9. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 10).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_10. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 11).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_11. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 12).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_12. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 13).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_13. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 14).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_14. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 15).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_15. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 16).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_16. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 17).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_17. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 18).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_18. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 19).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_19. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 20).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_20. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 21).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_21. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 22).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_22. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 23).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_23. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 24).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_24. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 25).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_25. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 26).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_28. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 27).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_29. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 28).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_30. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 29).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_26. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 30).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_27. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 31).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_31. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 32).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_32. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 33).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_o_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 34).
Applied set_property MARK_DEBUG = true for EMIO_0_tri_t_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 67).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0/inst. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 30).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M/U0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 35).
Applied set_property KEEP_HIERARCHY = SOFT for system_i. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/dna_port_read_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/mydna_read_v1_0_0. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph/s00_couplers/auto_pc. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph. (constraint file auto generated constraint).
Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M. (constraint file auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 940 ; free virtual = 69830
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm'
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_0'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:213]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_1'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:218]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_2'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:273]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_3'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:328]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_4'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:348]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_5'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:353]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_6'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:358]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_7'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:363]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_8'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:368]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_9'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:373]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_10'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:223]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_11'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:228]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_12'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:233]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_13'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:238]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_14'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:243]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_15'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:248]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_16'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:253]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_17'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:258]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_18'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:263]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_19'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:268]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_20'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:278]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_21'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:283]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_22'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:288]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_23'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:293]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_24'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:298]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_25'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:303]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_28'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:318]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_29'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:323]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_30'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:333]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_26'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:308]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_27'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:313]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_31'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:338]
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_32'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:343]
WARNING: [Synth 8-327] inferring latch for variable 'dna_port_reg_reg' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:413]
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
SM_IDLE | 01 | 00
SM_CMD_EN | 11 | 01
SM_CMD_ACCEPTED | 10 | 10
SM_DONE_WAIT | 00 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm'
---------------------------------------------------------------------------------------------------
State | New Encoding | Previous Encoding
---------------------------------------------------------------------------------------------------
SM_IDLE | 01 | 00
SM_CMD_EN | 11 | 01
SM_CMD_ACCEPTED | 10 | 10
SM_DONE | 00 | 11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 929 ; free virtual = 69825
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 12 Bit Adders := 8
2 Input 9 Bit Adders := 2
2 Input 8 Bit Adders := 2
2 Input 6 Bit Adders := 1
2 Input 5 Bit Adders := 4
2 Input 4 Bit Adders := 4
2 Input 2 Bit Adders := 2
+---Registers :
66 Bit Registers := 4
57 Bit Registers := 1
47 Bit Registers := 2
32 Bit Registers := 3
14 Bit Registers := 2
12 Bit Registers := 9
9 Bit Registers := 2
8 Bit Registers := 3
6 Bit Registers := 1
5 Bit Registers := 4
4 Bit Registers := 8
3 Bit Registers := 3
2 Bit Registers := 9
1 Bit Registers := 43
+---Muxes :
2 Input 66 Bit Muxes := 4
2 Input 47 Bit Muxes := 2
4 Input 32 Bit Muxes := 3
2 Input 32 Bit Muxes := 9
2 Input 14 Bit Muxes := 2
2 Input 12 Bit Muxes := 6
2 Input 9 Bit Muxes := 4
2 Input 8 Bit Muxes := 1
2 Input 6 Bit Muxes := 1
2 Input 5 Bit Muxes := 4
2 Input 4 Bit Muxes := 18
2 Input 2 Bit Muxes := 17
4 Input 2 Bit Muxes := 4
2 Input 1 Bit Muxes := 37
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 900 (col length:140)
BRAMs: 1000 (col length: RAMB18 140 RAMB36 70)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (FDRE_inst) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (BSR_OUT_DFF[0].FDRE_BSR) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N) is unused and will be removed from module proc_sys_reset.
WARNING: [Synth 8-3332] Sequential element (PR_OUT_DFF[0].FDRE_PER) is unused and will be removed from module proc_sys_reset.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1838 ; free virtual = 70743
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1815 ; free virtual = 70747
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1781 ; free virtual = 70713
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1765 ; free virtual = 70711
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
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Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
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Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Dynamic Shift Register Report:
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|dsrl | memory_reg[3] | 20 | 20 | 20 | 0 | 0 | 0 | 0 |
|dsrl__1 | memory_reg[3] | 2 | 2 | 2 | 0 | 0 | 0 | 0 |
|dsrl__2 | memory_reg[31] | 34 | 34 | 0 | 34 | 0 | 0 | 0 |
|dsrl__3 | memory_reg[31] | 13 | 13 | 0 | 13 | 0 | 0 | 0 |
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+---------+------+
| |Cell |Count |
+------+---------+------+
|1 |BIBUF | 130|
|2 |BUFG | 1|
|3 |CARRY4 | 6|
|4 |DNA_PORT | 1|
|5 |LUT1 | 69|
|6 |LUT2 | 24|
|7 |LUT3 | 169|
|8 |LUT4 | 52|
|9 |LUT5 | 71|
|10 |LUT6 | 118|
|11 |PS7 | 1|
|12 |SRL16 | 1|
|13 |SRL16E | 16|
|14 |SRLC32E | 45|
|15 |FDCE | 66|
|16 |FDR | 4|
|17 |FDRE | 501|
|18 |FDSE | 20|
|19 |LD | 57|
|20 |IOBUF | 33|
+------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 136 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 618.598 ; free physical = 1531 ; free virtual = 70510
Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1531 ; free virtual = 70509
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 1748 ; free virtual = 70732
INFO: [Netlist 29-17] Analyzing 101 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2563.766 ; gain = 0.000 ; free physical = 1757 ; free virtual = 70743
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 95 instances were transformed.
FDR => FDRE: 4 instances
IOBUF => IOBUF (IBUF, OBUFT): 33 instances
LD => LDCE: 57 instances
SRL16 => SRL16E: 1 instance
Synth Design complete | Checksum: 8993d7c
INFO: [Common 17-83] Releasing license: Synthesis
187 Infos, 142 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2563.801 ; gain = 1259.379 ; free physical = 1759 ; free virtual = 70746
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1991.605; main = 1727.861; forked = 379.983
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3465.613; main = 2563.770; forked = 1042.766
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2611.777 ; gain = 0.000 ; free physical = 1758 ; free virtual = 70746
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:36:31 2026...
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date : Wed May 27 16:36:31 2026
| Host : mkb running 64-bit unknown
| Command : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb
| Design : system_wrapper
| Device : xc7z035ffg676-2
| Speed File : -2
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 470 | 0 | 0 | 171900 | 0.27 |
| LUT as Logic | 408 | 0 | 0 | 171900 | 0.24 |
| LUT as Memory | 62 | 0 | 0 | 70400 | 0.09 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 62 | 0 | | | |
| Slice Registers | 648 | 0 | 0 | 343800 | 0.19 |
| Register as Flip Flop | 591 | 0 | 0 | 343800 | 0.17 |
| Register as Latch | 57 | 0 | 0 | 343800 | 0.02 |
| F7 Muxes | 0 | 0 | 0 | 109300 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 54650 | 0.00 |
+----------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 123 | Yes | - | Reset |
| 20 | Yes | Set | - |
| 505 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Memory
---------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 500 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 500 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 1000 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
3. DSP
------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 900 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. IO and GT Specific
---------------------
+-----------------------------+------+-------+------------+-----------+--------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------------------+------+-------+------------+-----------+--------+
| Bonded IOB | 33 | 0 | 0 | 250 | 13.20 |
| Bonded IPADs | 0 | 0 | 0 | 26 | 0.00 |
| Bonded OPADs | 0 | 0 | 0 | 16 | 0.00 |
| Bonded IOPADs | 130 | 0 | 0 | 130 | 100.00 |
| PHY_CONTROL | 0 | 0 | 0 | 8 | 0.00 |
| PHASER_REF | 0 | 0 | 0 | 8 | 0.00 |
| OUT_FIFO | 0 | 0 | 0 | 32 | 0.00 |
| IN_FIFO | 0 | 0 | 0 | 32 | 0.00 |
| IDELAYCTRL | 0 | 0 | 0 | 8 | 0.00 |
| IBUFDS | 0 | 0 | 0 | 240 | 0.00 |
| GTXE2_COMMON | 0 | 0 | 0 | 2 | 0.00 |
| GTXE2_CHANNEL | 0 | 0 | 0 | 8 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 32 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 32 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 400 | 0.00 |
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 150 | 0.00 |
| IBUFDS_GTE2 | 0 | 0 | 0 | 4 | 0.00 |
| ILOGIC | 0 | 0 | 0 | 250 | 0.00 |
| OLOGIC | 0 | 0 | 0 | 250 | 0.00 |
+-----------------------------+------+-------+------------+-----------+--------+
5. Clocking
-----------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 0 | 32 | 0.00 |
| MMCME2_ADV | 0 | 0 | 0 | 8 | 0.00 |
| PLLE2_ADV | 0 | 0 | 0 | 8 | 0.00 |
| BUFMRCE | 0 | 0 | 0 | 16 | 0.00 |
| BUFHCE | 0 | 0 | 0 | 168 | 0.00 |
| BUFR | 0 | 0 | 0 | 32 | 0.00 |
+------------+------+-------+------------+-----------+-------+
6. Specific Feature
-------------------
+-------------+------+-------+------------+-----------+--------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+--------+
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 1 | 0 | 0 | 1 | 100.00 |
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+------------+-----------+--------+
7. Primitives
-------------
+----------+------+----------------------+
| Ref Name | Used | Functional Category |
+----------+------+----------------------+
| FDRE | 505 | Flop & Latch |
| LUT3 | 169 | LUT |
| BIBUF | 130 | IO |
| LUT6 | 118 | LUT |
| LUT5 | 71 | LUT |
| LUT1 | 69 | LUT |
| FDCE | 66 | Flop & Latch |
| LDCE | 57 | Flop & Latch |
| LUT4 | 52 | LUT |
| SRLC32E | 45 | Distributed Memory |
| OBUFT | 33 | IO |
| IBUF | 33 | IO |
| LUT2 | 24 | LUT |
| FDSE | 20 | Flop & Latch |
| SRL16E | 17 | Distributed Memory |
| CARRY4 | 6 | CarryLogic |
| PS7 | 1 | Specialized Resource |
| DNA_PORT | 1 | Others |
| BUFG | 1 | Clock |
+----------+------+----------------------+
8. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
9. Instantiated Netlists
------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
Debug_FW.runs/synth_1/vivado.jou
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#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Wed May 27 16:36:06 2026
# Process ID: 958858
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1
# Command line: vivado -log system_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.vds
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/vivado.jou
# Running On: mkb, OS: Linux, CPU Frequency: 4933.113 MHz, CPU Physical cores: 32, Host memory: 134146 MB
#-----------------------------------------------------------
source system_wrapper.tcl -notrace
Debug_FW.runs/synth_1/vivado.pb
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