Init Commit
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Jeremy Shen
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
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| Date : Wed May 27 16:42:41 2026
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| Host : mkb running 64-bit unknown
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| Command : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
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| Design : system_wrapper
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| Device : xc7z035ffg676-2
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| Design State : routed
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| Grade : commercial
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| Process : typical
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| Characterization : Production
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----------------------------------------------------------------------------------------------------------------------------------------------------------------
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Power Report
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Table of Contents
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-----------------
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1. Summary
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1.1 On-Chip Components
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1.2 Power Supply Summary
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1.3 Confidence Level
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2. Settings
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2.1 Environment
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2.2 Clock Constraints
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3. Detailed Reports
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3.1 By Hierarchy
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1. Summary
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----------
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+--------------------------+--------------+
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| Total On-Chip Power (W) | 1.909 |
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| Design Power Budget (W) | Unspecified* |
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| Power Budget Margin (W) | NA |
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| Dynamic (W) | 1.688 |
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| Device Static (W) | 0.221 |
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| Effective TJA (C/W) | 1.9 |
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| Max Ambient (C) | 81.4 |
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| Junction Temperature (C) | 28.6 |
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| Confidence Level | Low |
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| Setting File | --- |
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| Simulation Activity File | --- |
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| Design Nets Matched | NA |
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+--------------------------+--------------+
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* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
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1.1 On-Chip Components
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----------------------
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+--------------------------+-----------+----------+-----------+-----------------+
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| On-Chip | Power (W) | Used | Available | Utilization (%) |
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+--------------------------+-----------+----------+-----------+-----------------+
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| Clocks | 0.097 | 4 | --- | --- |
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| Slice Logic | 0.012 | 67930 | --- | --- |
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| LUT as Logic | 0.011 | 13657 | 171900 | 7.94 |
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| Register | <0.001 | 29180 | 343800 | 8.49 |
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| LUT as Shift Register | <0.001 | 6873 | 70400 | 9.76 |
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| LUT as Distributed RAM | <0.001 | 152 | 70400 | 0.22 |
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| CARRY4 | <0.001 | 1979 | 54650 | 3.62 |
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| BUFG | <0.001 | 1 | 32 | 3.13 |
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| F7/F8 Muxes | <0.001 | 1059 | 218600 | 0.48 |
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| Others | 0.000 | 6317 | --- | --- |
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| Signals | 0.025 | 38363 | --- | --- |
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| Block RAM | 0.002 | 2.5 | 500 | 0.50 |
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| I/O | 0.024 | 33 | 250 | 13.20 |
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| PS7 | 1.528 | 1 | --- | --- |
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| Static Power | 0.221 | | | |
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| Total | 1.909 | | | |
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+--------------------------+-----------+----------+-----------+-----------------+
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1.2 Power Supply Summary
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------------------------
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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| Vccint | 1.000 | 0.194 | 0.136 | 0.059 | NA | Unspecified | NA |
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| Vccaux | 1.800 | 0.041 | 0.001 | 0.040 | NA | Unspecified | NA |
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| Vcco33 | 3.300 | 0.008 | 0.007 | 0.001 | NA | Unspecified | NA |
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| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccbram | 1.000 | 0.002 | 0.000 | 0.002 | NA | Unspecified | NA |
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| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
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| Vccpint | 1.000 | 0.736 | 0.718 | 0.018 | NA | Unspecified | NA |
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| Vccpaux | 1.800 | 0.061 | 0.051 | 0.010 | NA | Unspecified | NA |
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| Vccpll | 1.800 | 0.017 | 0.014 | 0.003 | NA | Unspecified | NA |
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| Vcco_ddr | 1.500 | 0.459 | 0.457 | 0.002 | NA | Unspecified | NA |
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| Vcco_mio0 | 1.800 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
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| Vcco_mio1 | 1.800 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
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| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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1.3 Confidence Level
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--------------------
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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| User Input Data | Confidence | Details | Action |
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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| Design implementation state | High | Design is routed | |
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| Clock nodes activity | High | User specified more than 95% of clocks | |
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| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
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| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
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| Device models | High | Device models are Production | |
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| | | | |
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| Overall confidence level | Low | | |
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+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
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2. Settings
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-----------
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2.1 Environment
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---------------
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+-----------------------+--------------------------+
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| Ambient Temp (C) | 25.0 |
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| ThetaJA (C/W) | 1.9 |
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| Airflow (LFM) | 250 |
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| Heat Sink | medium (Medium Profile) |
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| ThetaSA (C/W) | 3.4 |
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| Board Selection | medium (10"x10") |
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| # of Board Layers | 12to15 (12 to 15 Layers) |
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| Board Temperature (C) | 25.0 |
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+-----------------------+--------------------------+
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2.2 Clock Constraints
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---------------------
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+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------+-----------------+
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| Clock | Domain | Constraint (ns) |
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+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------+-----------------+
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| clk_fpga_0 | system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | 10.0 |
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| dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TCK | 33.0 |
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+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------+-----------------+
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3. Detailed Reports
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-------------------
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3.1 By Hierarchy
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----------------
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+--------------------------+-----------+
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| Name | Power (W) |
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+--------------------------+-----------+
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| system_wrapper | 1.688 |
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| dbg_hub | 0.003 |
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| inst | 0.003 |
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| BSCANID.u_xsdbm_id | 0.003 |
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| system_i | 1.535 |
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| processing_system7_0 | 1.530 |
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| inst | 1.530 |
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| ps7_0_axi_periph | 0.003 |
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| s00_couplers | 0.003 |
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| u_ila_0 | 0.125 |
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| inst | 0.125 |
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| ila_core_inst | 0.125 |
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+--------------------------+-----------+
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