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This commit is contained in:
Jeremy Shen
2026-05-27 09:56:09 +00:00
commit ee3ede1152
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Debug_FW.runs/impl_1/runme.log
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*** Running vivado
with args -log system_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
****** Vivado v2023.2 (64-bit)
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source system_wrapper.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
Command: link_design -top system_wrapper -part xc7z035ffg676-2
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7z035ffg676-2
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1722.395 ; gain = 0.000 ; free physical = 1995 ; free virtual = 71203
INFO: [Netlist 29-17] Analyzing 39 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc:50]
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-1687] 1 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2307.883 ; gain = 0.000 ; free physical = 1722 ; free virtual = 70993
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 33 instances were transformed.
IOBUF => IOBUF (IBUF, OBUFT): 33 instances
11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2307.883 ; gain = 962.004 ; free physical = 1730 ; free virtual = 71000
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
Running DRC as a precondition to command opt_design
Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2307.883 ; gain = 0.000 ; free physical = 1727 ; free virtual = 71012
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 2382775f8
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2762.520 ; gain = 454.637 ; free physical = 1293 ; free virtual = 70618
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1.1 Generate And Synthesize Debug Cores
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
INFO: [Chipscope 16-329] Generating Script for core instance : u_ila_0
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:ila:6.2 for cell u_ila_0_CV.
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3095.020 ; gain = 0.000 ; free physical = 9128 ; free virtual = 68708
Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3201.777 ; gain = 0.000 ; free physical = 8923 ; free virtual = 68563
Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3378.160 ; gain = 0.000 ; free physical = 8306 ; free virtual = 68085
Phase 1.1.1 Generate And Synthesize Debug Cores | Checksum: 1a85f7bbe
Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68085
Phase 1.1 Core Generation And Design Setup | Checksum: 1a85f7bbe
Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68085
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1a85f7bbe
Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68086
Phase 1 Initialization | Checksum: 1a85f7bbe
Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8300 ; free virtual = 68083
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1a85f7bbe
Time (s): cpu = 00:03:06 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8296 ; free virtual = 68078
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1a85f7bbe
Time (s): cpu = 00:03:06 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8279 ; free virtual = 68065
Phase 2 Timer Update And Timing Data Collection | Checksum: 1a85f7bbe
Time (s): cpu = 00:03:06 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8279 ; free virtual = 68065
Phase 3 Retarget
INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 20e292eaa
Time (s): cpu = 00:03:07 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8270 ; free virtual = 68062
Retarget | Checksum: 20e292eaa
INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 35 cells
INFO: [Opt 31-1021] In phase Retarget, 99 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 1fb9c5663
Time (s): cpu = 00:03:07 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8271 ; free virtual = 68063
Constant propagation | Checksum: 1fb9c5663
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 16 cells
INFO: [Opt 31-1021] In phase Constant propagation, 49 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Phase 5 Sweep
Phase 5 Sweep | Checksum: 1dd19d44b
Time (s): cpu = 00:03:08 ; elapsed = 00:03:18 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8274 ; free virtual = 68074
Sweep | Checksum: 1dd19d44b
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 46 cells
INFO: [Opt 31-1021] In phase Sweep, 956 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Phase 6 BUFG optimization
INFO: [Opt 31-194] Inserted BUFG system_i/dna_port_read_0/inst/read_vld_BUFG_inst to drive 57 load(s) on clock net system_i/dna_port_read_0/inst/read_vld_BUFG
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
Phase 6 BUFG optimization | Checksum: 202feca59
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8266 ; free virtual = 68070
BUFG optimization | Checksum: 202feca59
INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_A due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_B due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 due to none static srl address bits
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 due to none static srl address bits
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 202feca59
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8263 ; free virtual = 68069
Shift Register Optimization | Checksum: 202feca59
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 202feca59
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8260 ; free virtual = 68067
Post Processing Netlist | Checksum: 202feca59
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
INFO: [Opt 31-1021] In phase Post Processing Netlist, 57 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2572a104c
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8258 ; free virtual = 68070
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3442.176 ; gain = 0.000 ; free physical = 8255 ; free virtual = 68068
Phase 9.2 Verifying Netlist Connectivity | Checksum: 2572a104c
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8255 ; free virtual = 68068
Phase 9 Finalization | Checksum: 2572a104c
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8255 ; free virtual = 68068
Opt_design Change Summary
=========================
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 4 | 35 | 99 |
| Constant propagation | 0 | 16 | 49 |
| Sweep | 0 | 46 | 956 |
| BUFG optimization | 1 | 0 | 0 |
| Shift Register Optimization | 0 | 0 | 0 |
| Post Processing Netlist | 0 | 0 | 57 |
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 2572a104c
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8254 ; free virtual = 68068
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3442.176 ; gain = 0.000 ; free physical = 8253 ; free virtual = 68067
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Power 33-23] Power model is not available for DNA_PORT_inst
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 3 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 3 newly gated: 0 Total Ports: 6
Ending PowerOpt Patch Enables Task | Checksum: 1c6a995af
Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7922 ; free virtual = 67775
Ending Power Optimization Task | Checksum: 1c6a995af
Time (s): cpu = 00:00:11 ; elapsed = 00:00:04 . Memory (MB): peak = 3998.043 ; gain = 555.867 ; free physical = 7922 ; free virtual = 67775
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 1c6a995af
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7922 ; free virtual = 67774
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7921 ; free virtual = 67776
Ending Netlist Obfuscation Task | Checksum: 1b06a1b26
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7921 ; free virtual = 67776
INFO: [Common 17-83] Releasing license: Implementation
54 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:03:26 ; elapsed = 00:03:28 . Memory (MB): peak = 3998.043 ; gain = 1690.160 ; free physical = 7921 ; free virtual = 67776
INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx
Command: report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_drc_opted.rpt.
report_drc completed successfully
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
Wrote PlaceDB: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7766 ; free virtual = 67648
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7766 ; free virtual = 67648
Writing XDEF routing.
Writing XDEF routing logical nets.
Write ShapeDB Complete: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67652
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67653
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67653
Wrote Device Cache: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67654
Write Physdb Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67654
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_opt.dcp' has been generated.
INFO: [Chipscope 16-240] Debug cores have already been implemented
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7612 ; free virtual = 67560
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 19758bd7a
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7612 ; free virtual = 67559
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7611 ; free virtual = 67559
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8751fbf6
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7587 ; free virtual = 67558
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: dd0b0e99
Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7431 ; free virtual = 67481
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: dd0b0e99
Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7428 ; free virtual = 67479
Phase 1 Placer Initialization | Checksum: dd0b0e99
Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7428 ; free virtual = 67479
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: eecb6848
Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7404 ; free virtual = 67474
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: db55687b
Time (s): cpu = 00:00:23 ; elapsed = 00:00:12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7407 ; free virtual = 67493
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: db55687b
Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7401 ; free virtual = 67488
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1e9ca9de9
Time (s): cpu = 00:00:54 ; elapsed = 00:00:25 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7017 ; free virtual = 67264
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 1172 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 565 nets or LUTs. Breaked 0 LUT, combined 565 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7022 ; free virtual = 67279
Summary of Physical Synthesis Optimizations
============================================
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 565 | 565 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 565 | 565 | 0 | 4 | 00:00:01 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2be40b2db
Time (s): cpu = 00:00:59 ; elapsed = 00:00:28 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7014 ; free virtual = 67290
Phase 2.4 Global Placement Core | Checksum: 2859c5ffd
Time (s): cpu = 00:01:01 ; elapsed = 00:00:29 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7011 ; free virtual = 67293
Phase 2 Global Placement | Checksum: 2859c5ffd
Time (s): cpu = 00:01:01 ; elapsed = 00:00:29 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7011 ; free virtual = 67293
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1ea091a8d
Time (s): cpu = 00:01:05 ; elapsed = 00:00:30 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7007 ; free virtual = 67305
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 29969cf51
Time (s): cpu = 00:01:13 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6986 ; free virtual = 67345
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 2b62d77e5
Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6984 ; free virtual = 67343
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1ed299be3
Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6982 ; free virtual = 67342
Phase 3.5 Small Shape Detail Placement
Phase 3.5.1 Place Remaining
Phase 3.5.1 Place Remaining | Checksum: 21b5bb37c
Time (s): cpu = 00:01:20 ; elapsed = 00:00:41 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6918 ; free virtual = 67346
Phase 3.5 Small Shape Detail Placement | Checksum: 21b5bb37c
Time (s): cpu = 00:01:20 ; elapsed = 00:00:41 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6849 ; free virtual = 67281
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1a6b845f5
Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6838 ; free virtual = 67277
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1a81ce610
Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6834 ; free virtual = 67277
Phase 3 Detail Placement | Checksum: 1a81ce610
Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6828 ; free virtual = 67276
Phase 4 Post Placement Optimization and Clean-Up
Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1472dfedc
Phase 4.1.1.1 BUFG Insertion
Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.626 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: a925bbef
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6782 ; free virtual = 67315
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: a925bbef
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6769 ; free virtual = 67309
Phase 4.1.1.1 BUFG Insertion | Checksum: 1472dfedc
Time (s): cpu = 00:01:38 ; elapsed = 00:00:50 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6768 ; free virtual = 67314
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=2.626. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 14f55351a
Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
Phase 4.1 Post Commit Optimization | Checksum: 14f55351a
Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 14f55351a
Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6750 ; free virtual = 67308
Phase 4.3 Placer Reporting
Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion
____________________________________________________
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 2x2| 2x2|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
| East| 1x1| 1x1|
|___________|___________________|___________________|
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 14f55351a
Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6748 ; free virtual = 67312
Phase 4.3 Placer Reporting | Checksum: 14f55351a
Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19c30fa75
Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6741 ; free virtual = 67314
Ending Placer Task | Checksum: dcf0239e
Time (s): cpu = 00:01:41 ; elapsed = 00:00:53 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6725 ; free virtual = 67298
90 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:44 ; elapsed = 00:00:54 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6725 ; free virtual = 67298
INFO: [runtcl-4] Executing : report_io -file system_wrapper_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6722 ; free virtual = 67295
INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_placed.rpt -pb system_wrapper_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6708 ; free virtual = 67293
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6731 ; free virtual = 67329
Wrote PlaceDB: Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67235
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67235
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67236
Wrote Netlist Cache: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6582 ; free virtual = 67237
Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6582 ; free virtual = 67238
Write Physdb Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6581 ; free virtual = 67237
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_placed.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 76da8209 ConstDB: 0 ShapeSum: 6615a195 RouteDB: 0
Post Restoration Checksum: NetGraph: 4a144a14 | NumContArr: af14b29e | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 27e7af1ec
Time (s): cpu = 00:00:49 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5905 ; free virtual = 66985
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 27e7af1ec
Time (s): cpu = 00:00:50 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5899 ; free virtual = 66984
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 27e7af1ec
Time (s): cpu = 00:00:50 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5899 ; free virtual = 66984
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 32928bcd2
Time (s): cpu = 00:01:06 ; elapsed = 00:00:40 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5635 ; free virtual = 66801
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.632 | TNS=0.000 | WHS=-0.263 | THS=-1616.164|
Phase 2.4 Update Timing for Bus Skew
Phase 2.4.1 Update Timing
Phase 2.4.1 Update Timing | Checksum: 2864114c5
Time (s): cpu = 00:01:19 ; elapsed = 00:00:43 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5449 ; free virtual = 66672
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.632 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 2.4 Update Timing for Bus Skew | Checksum: 291576a87
Time (s): cpu = 00:01:19 ; elapsed = 00:00:44 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5447 ; free virtual = 66671
Router Utilization Summary
Global Vertical Routing Utilization = 0.0211705 %
Global Horizontal Routing Utilization = 0.00488761 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 38492
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 38484
Number of Partially Routed Nets = 8
Number of Node Overlaps = 6
Phase 2 Router Initialization | Checksum: 2a426d310
Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5405 ; free virtual = 66633
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 2a426d310
Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5405 ; free virtual = 66633
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 22defbe6f
Time (s): cpu = 00:01:27 ; elapsed = 00:00:46 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5394 ; free virtual = 66641
Phase 3 Initial Routing | Checksum: 22defbe6f
Time (s): cpu = 00:01:27 ; elapsed = 00:00:46 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5394 ; free virtual = 66641
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 2836
Number of Nodes with overlaps = 86
Number of Nodes with overlaps = 3
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.177 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 23a222cd5
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5385 ; free virtual = 66739
Phase 4 Rip-up And Reroute | Checksum: 23a222cd5
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5385 ; free virtual = 66739
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 23a222cd5
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 23a222cd5
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
Phase 5 Delay and Skew Optimization | Checksum: 23a222cd5
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 2a8514d39
Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5382 ; free virtual = 66749
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.189 | TNS=0.000 | WHS=0.028 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 253fa4620
Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
Phase 6 Post Hold Fix | Checksum: 253fa4620
Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 2.42898 %
Global Horizontal Routing Utilization = 2.87613 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 0
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 0
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 253fa4620
Time (s): cpu = 00:01:48 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 253fa4620
Time (s): cpu = 00:01:48 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 24ae08112
Time (s): cpu = 00:01:50 ; elapsed = 00:00:57 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5378 ; free virtual = 66754
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.189 | TNS=0.000 | WHS=0.028 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 24ae08112
Time (s): cpu = 00:01:53 ; elapsed = 00:00:58 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5367 ; free virtual = 66762
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 10a817867
Time (s): cpu = 00:01:54 ; elapsed = 00:00:59 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5358 ; free virtual = 66761
Ending Routing Task | Checksum: 10a817867
Time (s): cpu = 00:01:55 ; elapsed = 00:01:00 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5334 ; free virtual = 66752
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
108 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:59 ; elapsed = 00:01:02 . Memory (MB): peak = 4083.043 ; gain = 85.000 ; free physical = 5335 ; free virtual = 66757
INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx
Command: report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx
Command: report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 8 threads
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5233 ; free virtual = 66738
INFO: [runtcl-4] Executing : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
Command: report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
INFO: [Power 33-23] Power model is not available for DNA_PORT_inst
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
119 Infos, 83 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5140 ; free virtual = 66731
INFO: [runtcl-4] Executing : report_route_status -file system_wrapper_route_status.rpt -pb system_wrapper_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file system_wrapper_timing_summary_routed.rpt -pb system_wrapper_timing_summary_routed.pb -rpx system_wrapper_timing_summary_routed.rpx -warn_on_violation
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
INFO: [runtcl-4] Executing : report_incremental_reuse -file system_wrapper_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file system_wrapper_bus_skew_routed.rpt -pb system_wrapper_bus_skew_routed.pb -rpx system_wrapper_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5090 ; free virtual = 66740
Wrote PlaceDB: Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5008 ; free virtual = 66718
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5008 ; free virtual = 66718
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.29 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66717
Wrote Netlist Cache: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66719
Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66720
Write Physdb Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66721
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_routed.dcp' has been generated.
Command: write_bitstream -force system_wrapper.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I0) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1/I0) is not included in the LUT equation: 'O6=(A6+~A6)*((A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A5' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I1) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
WARNING: [DRC RTSTAT-10] No routable loads: 21 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TMS, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i... and (the first 15 of 19 listed).
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 4 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./system_wrapper.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Common 17-83] Releasing license: Implementation
13 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 4599.906 ; gain = 300.855 ; free physical = 4256 ; free virtual = 66217
INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:43:10 2026...