Init Commit
This commit is contained in:
Jeremy Shen
@@ -0,0 +1,15 @@
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||||
<?xml version="1.0"?>
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||||
<Runs Version="1" Minor="0">
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||||
<Run Id="synth_1" LaunchDir="/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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||||
<Run Id="impl_1" LaunchDir="/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
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||||
<Parent Id="synth_1"/>
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||||
</Run>
|
||||
<Parameters>
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||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
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||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
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||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
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||||
</Parameters>
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||||
<ProductInfo Name="vivado"/>
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||||
</Runs>
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||||
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||||
@@ -0,0 +1,5 @@
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<?xml version="1.0"?>
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||||
<ProcessHandle Version="1" Minor="0">
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||||
<Process Command=".planAhead." Owner="ly0kos" Host="mkb" Pid="959246">
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||||
</Process>
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||||
</ProcessHandle>
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||||
@@ -0,0 +1,5 @@
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||||
<?xml version="1.0"?>
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||||
<ProcessHandle Version="1" Minor="0">
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||||
<Process Command=".planAhead." Owner="ly0kos" Host="mkb" Pid="959246">
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</Process>
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||||
</ProcessHandle>
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||||
@@ -0,0 +1,5 @@
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||||
<?xml version="1.0"?>
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||||
<ProcessHandle Version="1" Minor="0">
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||||
<Process Command=".planAhead." Owner="ly0kos" Host="mkb" Pid="959246">
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||||
</Process>
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||||
</ProcessHandle>
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||||
@@ -0,0 +1,5 @@
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<?xml version="1.0"?>
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||||
<ProcessHandle Version="1" Minor="0">
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||||
<Process Command=".planAhead." Owner="ly0kos" Host="mkb" Pid="959246">
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</Process>
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</ProcessHandle>
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@@ -0,0 +1,5 @@
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<?xml version="1.0"?>
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<ProcessHandle Version="1" Minor="0">
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||||
<Process Command="vivado" Owner="ly0kos" Host="mkb" Pid="959204" HostCore="32" HostMemory="131002412">
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</Process>
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||||
</ProcessHandle>
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||||
@@ -0,0 +1,5 @@
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<?xml version="1.0"?>
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||||
<ProcessHandle Version="1" Minor="0">
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||||
<Process Command=".planAhead." Owner="ly0kos" Host="mkb" Pid="959246">
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||||
</Process>
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||||
</ProcessHandle>
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||||
Executable
+270
@@ -0,0 +1,270 @@
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//
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||||
// Vivado(TM)
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||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
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||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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||||
//
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||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
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||||
var ISELogFileStr = null;
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||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
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||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
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||||
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||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
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||||
//
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||||
function ISEInit() {
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||||
|
||||
// 1. RUN DIR setup
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||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
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||||
ISERunDir =
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||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
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||||
|
||||
// 2. LOG file setup
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||||
ISELogFileStr = ISEOpenFile( ISELogFile );
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||||
|
||||
// 3. LOG echo?
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||||
var ISEScriptArgs = WScript.Arguments;
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||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
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||||
ISELogEcho = false;
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||||
break;
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||||
}
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||||
}
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||||
|
||||
// 4. WSH version check
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||||
var ISEOptimalVersionWSH = 5.6;
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||||
var ISECurrentVersionWSH = WScript.Version;
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||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
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||||
|
||||
ISEStdErr( "" );
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||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
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||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
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||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
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||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
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||||
ISEStdOut( "" );
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||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
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||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
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||||
ISEProg += ".bat";
|
||||
}
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||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
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||||
var ISEExitCode = 1;
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||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
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||||
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||||
// BEGIN file creation
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||||
ISETouchFile( ISEStep, "begin" );
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||||
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||||
// LAUNCH!
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||||
ISELogFileStr.Close();
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||||
ISECmdLine =
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||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
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||||
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||||
} else { // WSH 5.6
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||||
|
||||
// LAUNCH!
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||||
ISEShell.CurrentDirectory = ISERunDir;
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||||
|
||||
// Redirect STDERR to STDOUT
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||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
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||||
var wbemFlagReturnImmediately = 0x10;
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||||
var wbemFlagForwardOnly = 0x20;
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||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
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||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
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||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
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||||
var cpuInfo = cpuInfos.item();
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||||
NOC += cpuInfo.NumberOfCores;
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||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
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||||
}
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||||
var csInfos = new Enumerator(computerSystem);
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||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
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||||
var csInfo = csInfos.item();
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||||
TPM += csInfo.TotalPhysicalMemory;
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||||
}
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||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
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||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
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||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
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||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
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||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
Executable
+85
@@ -0,0 +1,85 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
-------------------------------------
|
||||
| Tool Version : Vivado v.2023.2
|
||||
| Date : Wed May 27 16:40:37 2026
|
||||
| Host : mkb
|
||||
| Design : design_1
|
||||
| Device : xc7z035-ffg676-2--
|
||||
-------------------------------------
|
||||
|
||||
For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,181 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="impl_1" LaunchPart="xc7z035ffg676-2" LaunchTime="1779870965">
|
||||
<File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-RQS" Name="system_wrapper_postroute_physopted.rqs"/>
|
||||
<File Type="ROUTE-RQS" Name="system_wrapper_routed.rqs"/>
|
||||
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
|
||||
<File Type="BG-BGN" Name="system_wrapper.bgn"/>
|
||||
<File Type="BITSTR-SYSDEF" Name="system_wrapper.sysdef"/>
|
||||
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
|
||||
<File Type="BITSTR-LTX" Name="system_wrapper.ltx"/>
|
||||
<File Type="RBD_FILE" Name="system_wrapper.rbd"/>
|
||||
<File Type="NPI_FILE" Name="system_wrapper.npi"/>
|
||||
<File Type="RNPI_FILE" Name="system_wrapper.rnpi"/>
|
||||
<File Type="CFI_FILE" Name="system_wrapper.cfi"/>
|
||||
<File Type="RCFI_FILE" Name="system_wrapper.rcfi"/>
|
||||
<File Type="PL-PDI-FILE" Name="system_wrapper_pld.pdi"/>
|
||||
<File Type="BOOT-PDI-FILE" Name="system_wrapper_boot.pdi"/>
|
||||
<File Type="RDI-RDI" Name="system_wrapper.vdi"/>
|
||||
<File Type="PDI-FILE" Name="system_wrapper.pdi"/>
|
||||
<File Type="BITSTR-MMI" Name="system_wrapper.mmi"/>
|
||||
<File Type="BITSTR-BMM" Name="system_wrapper_bd.bmm"/>
|
||||
<File Type="BITSTR-NKY" Name="system_wrapper.nky"/>
|
||||
<File Type="BITSTR-RBT" Name="system_wrapper.rbt"/>
|
||||
<File Type="BITSTR-MSK" Name="system_wrapper.msk"/>
|
||||
<File Type="BG-BIN" Name="system_wrapper.bin"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
|
||||
<File Type="BG-BIT" Name="system_wrapper.bit"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="system_wrapper_bus_skew_postroute_physopted.rpx"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="system_wrapper_bus_skew_postroute_physopted.pb"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="system_wrapper_bus_skew_postroute_physopted.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="system_wrapper_timing_summary_postroute_physopted.rpx"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="system_wrapper_timing_summary_postroute_physopted.pb"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="system_wrapper_timing_summary_postroute_physopted.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="system_wrapper_postroute_physopt_bb.dcp"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-DCP" Name="system_wrapper_postroute_physopt.dcp"/>
|
||||
<File Type="BG-DRC" Name="system_wrapper.drc"/>
|
||||
<File Type="ROUTE-RQS-PB" Name="system_wrapper_rqs_routed.pb"/>
|
||||
<File Type="ROUTE-BUS-SKEW-RPX" Name="system_wrapper_bus_skew_routed.rpx"/>
|
||||
<File Type="ROUTE-BUS-SKEW-PB" Name="system_wrapper_bus_skew_routed.pb"/>
|
||||
<File Type="ROUTE-BUS-SKEW" Name="system_wrapper_bus_skew_routed.rpt"/>
|
||||
<File Type="PA-TCL" Name="system_wrapper.tcl"/>
|
||||
<File Type="INIT-TIMING" Name="system_wrapper_timing_summary_init.rpt"/>
|
||||
<File Type="OPT-DCP" Name="system_wrapper_opt.dcp"/>
|
||||
<File Type="OPT-RQA-PB" Name="system_wrapper_rqa_opted.pb"/>
|
||||
<File Type="OPT-DRC" Name="system_wrapper_drc_opted.rpt"/>
|
||||
<File Type="PLACE-TIMING" Name="system_wrapper_timing_summary_placed.rpt"/>
|
||||
<File Type="OPT-METHODOLOGY-DRC" Name="system_wrapper_methodology_drc_opted.rpt"/>
|
||||
<File Type="PLACE-UTIL-PB" Name="system_wrapper_utilization_placed.pb"/>
|
||||
<File Type="OPT-HWDEF" Name="system_wrapper.hwdef"/>
|
||||
<File Type="POSTPLACE-PWROPT-TIMING" Name="system_wrapper_timing_summary_postplace_pwropted.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="system_wrapper_reports.tcl"/>
|
||||
<File Type="OPT-TIMING" Name="system_wrapper_timing_summary_opted.rpt"/>
|
||||
<File Type="PWROPT-DCP" Name="system_wrapper_pwropt.dcp"/>
|
||||
<File Type="PWROPT-DRC" Name="system_wrapper_drc_pwropted.rpt"/>
|
||||
<File Type="PWROPT-TIMING" Name="system_wrapper_timing_summary_pwropted.rpt"/>
|
||||
<File Type="PLACE-DCP" Name="system_wrapper_placed.dcp"/>
|
||||
<File Type="PLACE-RQA-PB" Name="system_wrapper_rqa_placed.pb"/>
|
||||
<File Type="PLACE-IO" Name="system_wrapper_io_placed.rpt"/>
|
||||
<File Type="PHYSOPT-TIMING" Name="system_wrapper_timing_summary_physopted.rpt"/>
|
||||
<File Type="PLACE-CLK" Name="system_wrapper_clock_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-UTIL" Name="system_wrapper_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-CTRL" Name="system_wrapper_control_sets_placed.rpt"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC" Name="system_wrapper_methodology_drc_routed.rpt"/>
|
||||
<File Type="PLACE-SIMILARITY" Name="system_wrapper_incremental_reuse_placed.rpt"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="system_wrapper_methodology_drc_routed.pb"/>
|
||||
<File Type="PLACE-PRE-SIMILARITY" Name="system_wrapper_incremental_reuse_pre_placed.rpt"/>
|
||||
<File Type="ROUTE-DRC-RPX" Name="system_wrapper_drc_routed.rpx"/>
|
||||
<File Type="POSTPLACE-PWROPT-DCP" Name="system_wrapper_postplace_pwropt.dcp"/>
|
||||
<File Type="PHYSOPT-DCP" Name="system_wrapper_physopt.dcp"/>
|
||||
<File Type="PHYSOPT-DRC" Name="system_wrapper_drc_physopted.rpt"/>
|
||||
<File Type="ROUTE-ERROR-DCP" Name="system_wrapper_routed_error.dcp"/>
|
||||
<File Type="ROUTE-DCP" Name="system_wrapper_routed.dcp"/>
|
||||
<File Type="ROUTE-BLACKBOX-DCP" Name="system_wrapper_routed_bb.dcp"/>
|
||||
<File Type="ROUTE-DRC" Name="system_wrapper_drc_routed.rpt"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="system_wrapper_methodology_drc_routed.rpx"/>
|
||||
<File Type="ROUTE-DRC-PB" Name="system_wrapper_drc_routed.pb"/>
|
||||
<File Type="ROUTE-PWR" Name="system_wrapper_power_routed.rpt"/>
|
||||
<File Type="ROUTE-PWR-SUM" Name="system_wrapper_power_summary_routed.pb"/>
|
||||
<File Type="ROUTE-PWR-RPX" Name="system_wrapper_power_routed.rpx"/>
|
||||
<File Type="ROUTE-STATUS" Name="system_wrapper_route_status.rpt"/>
|
||||
<File Type="ROUTE-STATUS-PB" Name="system_wrapper_route_status.pb"/>
|
||||
<File Type="ROUTE-TIMINGSUMMARY" Name="system_wrapper_timing_summary_routed.rpt"/>
|
||||
<File Type="ROUTE-TIMING-PB" Name="system_wrapper_timing_summary_routed.pb"/>
|
||||
<File Type="ROUTE-TIMING-RPX" Name="system_wrapper_timing_summary_routed.rpx"/>
|
||||
<File Type="ROUTE-SIMILARITY" Name="system_wrapper_incremental_reuse_routed.rpt"/>
|
||||
<File Type="ROUTE-CLK" Name="system_wrapper_clock_utilization_routed.rpt"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/src/dna_port_read.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/sources_1/src/dna_port_read.v"/>
|
||||
<Attr Name="ImportTime" Val="1779770889"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/src/mydna_read_v1_0_S00_AXI.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v"/>
|
||||
<Attr Name="ImportTime" Val="1779770889"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/src/mydna_read_v1_0.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/sources_1/src/mydna_read_v1_0.v"/>
|
||||
<Attr Name="ImportTime" Val="1779770889"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/system/system.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/sources_1/bd/system/system.bd"/>
|
||||
<Attr Name="ImportTime" Val="1779870939"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/system/hdl/system_wrapper.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.gen/sources_1/bd/system/hdl/system_wrapper.v"/>
|
||||
<Attr Name="ImportTime" Val="1779691907"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="system_wrapper"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/pin_cons.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/constrs_1/new/pin_cons.xdc"/>
|
||||
<Attr Name="ImportTime" Val="1779869379"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/constrs_1/new/pin_debug.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/constrs_1/new/pin_debug.xdc"/>
|
||||
<Attr Name="ImportTime" Val="1779869379"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/pin_debug.xdc"/>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
@@ -0,0 +1,10 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log system_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,37 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6178695f70726f746f636f6c5f636f6e7665727465725f76325f315f32395c73797374656d5f6175746f5f70635f30:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c646e615f706f72745f726561645f76315f305f315c73797374656d5f646e615f706f72745f726561645f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6d79646e615f726561645f76315f305f76315f305f315c73797374656d5f6d79646e615f726561645f76315f305f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c70726f63657373696e675f73797374656d375f76355f355f365c73797374656d5f70726f63657373696e675f73797374656d375f305f30:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6178695f696e746572636f6e6e6563745f76325f315f33305c73797374656d5f7073375f305f6178695f7065726970685f31:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c70726f635f7379735f72657365745f76355f305f31345c73797374656d5f7273745f7073375f305f3130304d5f31:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:37:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3766333431353462636535633438353438666465373135373064316531336265:506172656e742050412070726f6a656374204944:00
|
||||
eof:882976205
|
||||
Binary file not shown.
@@ -0,0 +1,45 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;";
|
||||
} else {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
// pre-commands:
|
||||
ISETouchFile( "init_design", "begin" );
|
||||
ISEStep( "vivado",
|
||||
"-log system_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace" );
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
@@ -0,0 +1,845 @@
|
||||
|
||||
*** Running vivado
|
||||
with args -log system_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
|
||||
|
||||
|
||||
****** Vivado v2023.2 (64-bit)
|
||||
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
source system_wrapper.tcl -notrace
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
|
||||
Command: link_design -top system_wrapper -part xc7z035ffg676-2
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1722.395 ; gain = 0.000 ; free physical = 1995 ; free virtual = 71203
|
||||
INFO: [Netlist 29-17] Analyzing 39 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc:50]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-1687] 1 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2307.883 ; gain = 0.000 ; free physical = 1722 ; free virtual = 70993
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 33 instances were transformed.
|
||||
IOBUF => IOBUF (IBUF, OBUFT): 33 instances
|
||||
|
||||
11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2307.883 ; gain = 962.004 ; free physical = 1730 ; free virtual = 71000
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2307.883 ; gain = 0.000 ; free physical = 1727 ; free virtual = 71012
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Ending Cache Timing Information Task | Checksum: 2382775f8
|
||||
|
||||
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2762.520 ; gain = 454.637 ; free physical = 1293 ; free virtual = 70618
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Initialization
|
||||
|
||||
Phase 1.1 Core Generation And Design Setup
|
||||
|
||||
Phase 1.1.1 Generate And Synthesize Debug Cores
|
||||
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub
|
||||
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
|
||||
INFO: [Chipscope 16-329] Generating Script for core instance : u_ila_0
|
||||
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:ila:6.2 for cell u_ila_0_CV.
|
||||
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3095.020 ; gain = 0.000 ; free physical = 9128 ; free virtual = 68708
|
||||
Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3201.777 ; gain = 0.000 ; free physical = 8923 ; free virtual = 68563
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3378.160 ; gain = 0.000 ; free physical = 8306 ; free virtual = 68085
|
||||
Phase 1.1.1 Generate And Synthesize Debug Cores | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68085
|
||||
Phase 1.1 Core Generation And Design Setup | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68085
|
||||
|
||||
Phase 1.2 Setup Constraints And Sort Netlist
|
||||
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68086
|
||||
Phase 1 Initialization | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8300 ; free virtual = 68083
|
||||
|
||||
Phase 2 Timer Update And Timing Data Collection
|
||||
|
||||
Phase 2.1 Timer Update
|
||||
Phase 2.1 Timer Update | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:06 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8296 ; free virtual = 68078
|
||||
|
||||
Phase 2.2 Timing Data Collection
|
||||
Phase 2.2 Timing Data Collection | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:06 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8279 ; free virtual = 68065
|
||||
Phase 2 Timer Update And Timing Data Collection | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:06 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8279 ; free virtual = 68065
|
||||
|
||||
Phase 3 Retarget
|
||||
INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 3 Retarget | Checksum: 20e292eaa
|
||||
|
||||
Time (s): cpu = 00:03:07 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8270 ; free virtual = 68062
|
||||
Retarget | Checksum: 20e292eaa
|
||||
INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 35 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 99 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 4 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 4 Constant propagation | Checksum: 1fb9c5663
|
||||
|
||||
Time (s): cpu = 00:03:07 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8271 ; free virtual = 68063
|
||||
Constant propagation | Checksum: 1fb9c5663
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 16 cells
|
||||
INFO: [Opt 31-1021] In phase Constant propagation, 49 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 5 Sweep
|
||||
Phase 5 Sweep | Checksum: 1dd19d44b
|
||||
|
||||
Time (s): cpu = 00:03:08 ; elapsed = 00:03:18 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8274 ; free virtual = 68074
|
||||
Sweep | Checksum: 1dd19d44b
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 46 cells
|
||||
INFO: [Opt 31-1021] In phase Sweep, 956 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 6 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG system_i/dna_port_read_0/inst/read_vld_BUFG_inst to drive 57 load(s) on clock net system_i/dna_port_read_0/inst/read_vld_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 6 BUFG optimization | Checksum: 202feca59
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8266 ; free virtual = 68070
|
||||
BUFG optimization | Checksum: 202feca59
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 7 Shift Register Optimization
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_A due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_B due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 due to none static srl address bits
|
||||
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
|
||||
Phase 7 Shift Register Optimization | Checksum: 202feca59
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8263 ; free virtual = 68069
|
||||
Shift Register Optimization | Checksum: 202feca59
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 8 Post Processing Netlist
|
||||
Phase 8 Post Processing Netlist | Checksum: 202feca59
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8260 ; free virtual = 68067
|
||||
Post Processing Netlist | Checksum: 202feca59
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Post Processing Netlist, 57 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 9 Finalization
|
||||
|
||||
Phase 9.1 Finalizing Design Cores and Updating Shapes
|
||||
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2572a104c
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8258 ; free virtual = 68070
|
||||
|
||||
Phase 9.2 Verifying Netlist Connectivity
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3442.176 ; gain = 0.000 ; free physical = 8255 ; free virtual = 68068
|
||||
Phase 9.2 Verifying Netlist Connectivity | Checksum: 2572a104c
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8255 ; free virtual = 68068
|
||||
Phase 9 Finalization | Checksum: 2572a104c
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8255 ; free virtual = 68068
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 4 | 35 | 99 |
|
||||
| Constant propagation | 0 | 16 | 49 |
|
||||
| Sweep | 0 | 46 | 956 |
|
||||
| BUFG optimization | 1 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 57 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Ending Logic Optimization Task | Checksum: 2572a104c
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8254 ; free virtual = 68068
|
||||
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
|
||||
Done building netlist checker database: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3442.176 ; gain = 0.000 ; free physical = 8253 ; free virtual = 68067
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
INFO: [Power 33-23] Power model is not available for DNA_PORT_inst
|
||||
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
||||
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
|
||||
|
||||
Starting PowerOpt Patch Enables Task
|
||||
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 3 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
||||
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
|
||||
Number of BRAM Ports augmented: 3 newly gated: 0 Total Ports: 6
|
||||
Ending PowerOpt Patch Enables Task | Checksum: 1c6a995af
|
||||
|
||||
Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7922 ; free virtual = 67775
|
||||
Ending Power Optimization Task | Checksum: 1c6a995af
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:04 . Memory (MB): peak = 3998.043 ; gain = 555.867 ; free physical = 7922 ; free virtual = 67775
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 1c6a995af
|
||||
|
||||
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7922 ; free virtual = 67774
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7921 ; free virtual = 67776
|
||||
Ending Netlist Obfuscation Task | Checksum: 1b06a1b26
|
||||
|
||||
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7921 ; free virtual = 67776
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
54 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
opt_design: Time (s): cpu = 00:03:26 ; elapsed = 00:03:28 . Memory (MB): peak = 3998.043 ; gain = 1690.160 ; free physical = 7921 ; free virtual = 67776
|
||||
INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx
|
||||
Command: report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Wrote PlaceDB: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7766 ; free virtual = 67648
|
||||
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7766 ; free virtual = 67648
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67652
|
||||
Writing XDEF routing special nets.
|
||||
Wrote RouteStorage: Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67653
|
||||
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67653
|
||||
Wrote Device Cache: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67654
|
||||
Write Physdb Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67654
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_opt.dcp' has been generated.
|
||||
INFO: [Chipscope 16-240] Debug cores have already been implemented
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
|
||||
|
||||
Starting Placer Task
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7612 ; free virtual = 67560
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 19758bd7a
|
||||
|
||||
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7612 ; free virtual = 67559
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7611 ; free virtual = 67559
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8751fbf6
|
||||
|
||||
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7587 ; free virtual = 67558
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: dd0b0e99
|
||||
|
||||
Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7431 ; free virtual = 67481
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: dd0b0e99
|
||||
|
||||
Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7428 ; free virtual = 67479
|
||||
Phase 1 Placer Initialization | Checksum: dd0b0e99
|
||||
|
||||
Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7428 ; free virtual = 67479
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: eecb6848
|
||||
|
||||
Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7404 ; free virtual = 67474
|
||||
|
||||
Phase 2.2 Update Timing before SLR Path Opt
|
||||
Phase 2.2 Update Timing before SLR Path Opt | Checksum: db55687b
|
||||
|
||||
Time (s): cpu = 00:00:23 ; elapsed = 00:00:12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7407 ; free virtual = 67493
|
||||
|
||||
Phase 2.3 Post-Processing in Floorplanning
|
||||
Phase 2.3 Post-Processing in Floorplanning | Checksum: db55687b
|
||||
|
||||
Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7401 ; free virtual = 67488
|
||||
|
||||
Phase 2.4 Global Placement Core
|
||||
|
||||
Phase 2.4.1 UpdateTiming Before Physical Synthesis
|
||||
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1e9ca9de9
|
||||
|
||||
Time (s): cpu = 00:00:54 ; elapsed = 00:00:25 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7017 ; free virtual = 67264
|
||||
|
||||
Phase 2.4.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 1172 LUT instances to create LUTNM shape
|
||||
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
|
||||
INFO: [Physopt 32-1138] End 1 Pass. Optimized 565 nets or LUTs. Breaked 0 LUT, combined 565 existing LUTs and moved 0 existing LUT
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7022 ; free virtual = 67279
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| LUT Combining | 0 | 565 | 565 | 0 | 1 | 00:00:00 |
|
||||
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 565 | 565 | 0 | 4 | 00:00:01 |
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2be40b2db
|
||||
|
||||
Time (s): cpu = 00:00:59 ; elapsed = 00:00:28 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7014 ; free virtual = 67290
|
||||
Phase 2.4 Global Placement Core | Checksum: 2859c5ffd
|
||||
|
||||
Time (s): cpu = 00:01:01 ; elapsed = 00:00:29 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7011 ; free virtual = 67293
|
||||
Phase 2 Global Placement | Checksum: 2859c5ffd
|
||||
|
||||
Time (s): cpu = 00:01:01 ; elapsed = 00:00:29 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7011 ; free virtual = 67293
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 1ea091a8d
|
||||
|
||||
Time (s): cpu = 00:01:05 ; elapsed = 00:00:30 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7007 ; free virtual = 67305
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 29969cf51
|
||||
|
||||
Time (s): cpu = 00:01:13 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6986 ; free virtual = 67345
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 2b62d77e5
|
||||
|
||||
Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6984 ; free virtual = 67343
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 1ed299be3
|
||||
|
||||
Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6982 ; free virtual = 67342
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
|
||||
Phase 3.5.1 Place Remaining
|
||||
Phase 3.5.1 Place Remaining | Checksum: 21b5bb37c
|
||||
|
||||
Time (s): cpu = 00:01:20 ; elapsed = 00:00:41 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6918 ; free virtual = 67346
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 21b5bb37c
|
||||
|
||||
Time (s): cpu = 00:01:20 ; elapsed = 00:00:41 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6849 ; free virtual = 67281
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1a6b845f5
|
||||
|
||||
Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6838 ; free virtual = 67277
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1a81ce610
|
||||
|
||||
Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6834 ; free virtual = 67277
|
||||
Phase 3 Detail Placement | Checksum: 1a81ce610
|
||||
|
||||
Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6828 ; free virtual = 67276
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 1472dfedc
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
|
||||
Starting Physical Synthesis Task
|
||||
|
||||
Phase 1 Physical Synthesis Initialization
|
||||
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
|
||||
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.626 | TNS=0.000 |
|
||||
Phase 1 Physical Synthesis Initialization | Checksum: a925bbef
|
||||
|
||||
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6782 ; free virtual = 67315
|
||||
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
|
||||
Ending Physical Synthesis Task | Checksum: a925bbef
|
||||
|
||||
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6769 ; free virtual = 67309
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 1472dfedc
|
||||
|
||||
Time (s): cpu = 00:01:38 ; elapsed = 00:00:50 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6768 ; free virtual = 67314
|
||||
|
||||
Phase 4.1.1.2 Post Placement Timing Optimization
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=2.626. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 14f55351a
|
||||
|
||||
Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
|
||||
|
||||
Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 14f55351a
|
||||
|
||||
Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 14f55351a
|
||||
|
||||
Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6750 ; free virtual = 67308
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
|
||||
Phase 4.3.1 Print Estimated Congestion
|
||||
INFO: [Place 30-612] Post-Placement Estimated Congestion
|
||||
____________________________________________________
|
||||
| | Global Congestion | Short Congestion |
|
||||
| Direction | Region Size | Region Size |
|
||||
|___________|___________________|___________________|
|
||||
| North| 2x2| 2x2|
|
||||
|___________|___________________|___________________|
|
||||
| South| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
| East| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
| West| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
|
||||
Phase 4.3.1 Print Estimated Congestion | Checksum: 14f55351a
|
||||
|
||||
Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6748 ; free virtual = 67312
|
||||
Phase 4.3 Placer Reporting | Checksum: 14f55351a
|
||||
|
||||
Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
|
||||
|
||||
Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19c30fa75
|
||||
|
||||
Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6741 ; free virtual = 67314
|
||||
Ending Placer Task | Checksum: dcf0239e
|
||||
|
||||
Time (s): cpu = 00:01:41 ; elapsed = 00:00:53 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6725 ; free virtual = 67298
|
||||
90 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
place_design: Time (s): cpu = 00:01:44 ; elapsed = 00:00:54 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6725 ; free virtual = 67298
|
||||
INFO: [runtcl-4] Executing : report_io -file system_wrapper_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6722 ; free virtual = 67295
|
||||
INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_placed.rpt -pb system_wrapper_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6708 ; free virtual = 67293
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6731 ; free virtual = 67329
|
||||
Wrote PlaceDB: Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67235
|
||||
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67235
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Wrote RouteStorage: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67236
|
||||
Wrote Netlist Cache: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6582 ; free virtual = 67237
|
||||
Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6582 ; free virtual = 67238
|
||||
Write Physdb Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6581 ; free virtual = 67237
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_placed.dcp' has been generated.
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Checksum: PlaceDB: 76da8209 ConstDB: 0 ShapeSum: 6615a195 RouteDB: 0
|
||||
Post Restoration Checksum: NetGraph: 4a144a14 | NumContArr: af14b29e | Constraints: c2a8fa9d | Timing: c2a8fa9d
|
||||
Phase 1 Build RT Design | Checksum: 27e7af1ec
|
||||
|
||||
Time (s): cpu = 00:00:49 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5905 ; free virtual = 66985
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Fix Topology Constraints
|
||||
Phase 2.1 Fix Topology Constraints | Checksum: 27e7af1ec
|
||||
|
||||
Time (s): cpu = 00:00:50 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5899 ; free virtual = 66984
|
||||
|
||||
Phase 2.2 Pre Route Cleanup
|
||||
Phase 2.2 Pre Route Cleanup | Checksum: 27e7af1ec
|
||||
|
||||
Time (s): cpu = 00:00:50 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5899 ; free virtual = 66984
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.3 Update Timing
|
||||
Phase 2.3 Update Timing | Checksum: 32928bcd2
|
||||
|
||||
Time (s): cpu = 00:01:06 ; elapsed = 00:00:40 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5635 ; free virtual = 66801
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.632 | TNS=0.000 | WHS=-0.263 | THS=-1616.164|
|
||||
|
||||
|
||||
Phase 2.4 Update Timing for Bus Skew
|
||||
|
||||
Phase 2.4.1 Update Timing
|
||||
Phase 2.4.1 Update Timing | Checksum: 2864114c5
|
||||
|
||||
Time (s): cpu = 00:01:19 ; elapsed = 00:00:43 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5449 ; free virtual = 66672
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.632 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 2.4 Update Timing for Bus Skew | Checksum: 291576a87
|
||||
|
||||
Time (s): cpu = 00:01:19 ; elapsed = 00:00:44 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5447 ; free virtual = 66671
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0211705 %
|
||||
Global Horizontal Routing Utilization = 0.00488761 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 38492
|
||||
(Failed Nets is the sum of unrouted and partially routed nets)
|
||||
Number of Unrouted Nets = 38484
|
||||
Number of Partially Routed Nets = 8
|
||||
Number of Node Overlaps = 6
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 2a426d310
|
||||
|
||||
Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5405 ; free virtual = 66633
|
||||
|
||||
Phase 3 Initial Routing
|
||||
|
||||
Phase 3.1 Global Routing
|
||||
Phase 3.1 Global Routing | Checksum: 2a426d310
|
||||
|
||||
Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5405 ; free virtual = 66633
|
||||
|
||||
Phase 3.2 Initial Net Routing
|
||||
Phase 3.2 Initial Net Routing | Checksum: 22defbe6f
|
||||
|
||||
Time (s): cpu = 00:01:27 ; elapsed = 00:00:46 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5394 ; free virtual = 66641
|
||||
Phase 3 Initial Routing | Checksum: 22defbe6f
|
||||
|
||||
Time (s): cpu = 00:01:27 ; elapsed = 00:00:46 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5394 ; free virtual = 66641
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 2836
|
||||
Number of Nodes with overlaps = 86
|
||||
Number of Nodes with overlaps = 3
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.177 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 23a222cd5
|
||||
|
||||
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5385 ; free virtual = 66739
|
||||
Phase 4 Rip-up And Reroute | Checksum: 23a222cd5
|
||||
|
||||
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5385 ; free virtual = 66739
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 23a222cd5
|
||||
|
||||
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 23a222cd5
|
||||
|
||||
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 23a222cd5
|
||||
|
||||
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 2a8514d39
|
||||
|
||||
Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5382 ; free virtual = 66749
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.189 | TNS=0.000 | WHS=0.028 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 253fa4620
|
||||
|
||||
Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
|
||||
Phase 6 Post Hold Fix | Checksum: 253fa4620
|
||||
|
||||
Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 2.42898 %
|
||||
Global Horizontal Routing Utilization = 2.87613 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
(Failed Nets is the sum of unrouted and partially routed nets)
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 253fa4620
|
||||
|
||||
Time (s): cpu = 00:01:48 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 253fa4620
|
||||
|
||||
Time (s): cpu = 00:01:48 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 24ae08112
|
||||
|
||||
Time (s): cpu = 00:01:50 ; elapsed = 00:00:57 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5378 ; free virtual = 66754
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.189 | TNS=0.000 | WHS=0.028 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 24ae08112
|
||||
|
||||
Time (s): cpu = 00:01:53 ; elapsed = 00:00:58 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5367 ; free virtual = 66762
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Phase 11 Post-Route Event Processing
|
||||
Phase 11 Post-Route Event Processing | Checksum: 10a817867
|
||||
|
||||
Time (s): cpu = 00:01:54 ; elapsed = 00:00:59 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5358 ; free virtual = 66761
|
||||
Ending Routing Task | Checksum: 10a817867
|
||||
|
||||
Time (s): cpu = 00:01:55 ; elapsed = 00:01:00 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5334 ; free virtual = 66752
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
108 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:01:59 ; elapsed = 00:01:02 . Memory (MB): peak = 4083.043 ; gain = 85.000 ; free physical = 5335 ; free virtual = 66757
|
||||
INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx
|
||||
Command: report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 8 threads
|
||||
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
report_methodology: Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5233 ; free virtual = 66738
|
||||
INFO: [runtcl-4] Executing : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
|
||||
Command: report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
|
||||
INFO: [Power 33-23] Power model is not available for DNA_PORT_inst
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
|
||||
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
|
||||
119 Infos, 83 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
report_power: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5140 ; free virtual = 66731
|
||||
INFO: [runtcl-4] Executing : report_route_status -file system_wrapper_route_status.rpt -pb system_wrapper_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file system_wrapper_timing_summary_routed.rpt -pb system_wrapper_timing_summary_routed.pb -rpx system_wrapper_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
|
||||
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file system_wrapper_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file system_wrapper_bus_skew_routed.rpt -pb system_wrapper_bus_skew_routed.pb -rpx system_wrapper_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5090 ; free virtual = 66740
|
||||
Wrote PlaceDB: Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5008 ; free virtual = 66718
|
||||
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5008 ; free virtual = 66718
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Wrote RouteStorage: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.29 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66717
|
||||
Wrote Netlist Cache: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66719
|
||||
Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66720
|
||||
Write Physdb Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66721
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_routed.dcp' has been generated.
|
||||
Command: write_bitstream -force system_wrapper.bit
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
|
||||
Running DRC as a precondition to command write_bitstream
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I0) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
||||
WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1/I0) is not included in the LUT equation: 'O6=(A6+~A6)*((A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
||||
WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A5' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I1) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
||||
WARNING: [DRC RTSTAT-10] No routable loads: 21 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TMS, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i... and (the first 15 of 19 listed).
|
||||
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 4 Warnings
|
||||
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
|
||||
Loading data files...
|
||||
Loading site data...
|
||||
Loading route data...
|
||||
Processing options...
|
||||
Creating bitmap...
|
||||
Creating bitstream...
|
||||
Writing bitstream ./system_wrapper.bit...
|
||||
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
13 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
write_bitstream completed successfully
|
||||
write_bitstream: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 4599.906 ; gain = 300.855 ; free physical = 4256 ; free virtual = 66217
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:43:10 2026...
|
||||
Executable
+44
@@ -0,0 +1,44 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin
|
||||
else
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
# pre-commands:
|
||||
/bin/touch .init_design.begin.rst
|
||||
EAStep vivado -log system_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
|
||||
|
||||
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,312 @@
|
||||
#
|
||||
# Report generation script generated by Vivado
|
||||
#
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
namespace eval ::optrace {
|
||||
variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper.tcl"
|
||||
variable category "vivado_impl"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc start_step { step } {
|
||||
set stopFile ".stop.rst"
|
||||
if {[file isfile .stop.rst]} {
|
||||
puts ""
|
||||
puts "*** Halting run - EA reset detected ***"
|
||||
puts ""
|
||||
puts ""
|
||||
return -code error
|
||||
}
|
||||
set beginFile ".$step.begin.rst"
|
||||
set platform "$::tcl_platform(platform)"
|
||||
set user "$::tcl_platform(user)"
|
||||
set pid [pid]
|
||||
set host ""
|
||||
if { [string equal $platform unix] } {
|
||||
if { [info exist ::env(HOSTNAME)] } {
|
||||
set host $::env(HOSTNAME)
|
||||
} elseif { [info exist ::env(HOST)] } {
|
||||
set host $::env(HOST)
|
||||
}
|
||||
} else {
|
||||
if { [info exist ::env(COMPUTERNAME)] } {
|
||||
set host $::env(COMPUTERNAME)
|
||||
}
|
||||
}
|
||||
set ch [open $beginFile w]
|
||||
puts $ch "<?xml version=\"1.0\"?>"
|
||||
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
|
||||
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
|
||||
puts $ch " </Process>"
|
||||
puts $ch "</ProcessHandle>"
|
||||
close $ch
|
||||
}
|
||||
|
||||
proc end_step { step } {
|
||||
set endFile ".$step.end.rst"
|
||||
set ch [open $endFile w]
|
||||
close $ch
|
||||
}
|
||||
|
||||
proc step_failed { step } {
|
||||
set endFile ".$step.error.rst"
|
||||
set ch [open $endFile w]
|
||||
close $ch
|
||||
OPTRACE "impl_1" END { }
|
||||
}
|
||||
|
||||
set_msg_config -id {HDL-1065} -limit 10000
|
||||
|
||||
OPTRACE "impl_1" START { ROLLUP_1 }
|
||||
OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
|
||||
start_step init_design
|
||||
set ACTIVE_STEP init_design
|
||||
set rc [catch {
|
||||
create_msg_db init_design.pb
|
||||
set_param chipscope.maxJobs 8
|
||||
set_param runs.launchOptions { -jobs 32 }
|
||||
OPTRACE "create in-memory project" START { }
|
||||
create_project -in_memory -part xc7z035ffg676-2
|
||||
set_property design_mode GateLvl [current_fileset]
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
OPTRACE "create in-memory project" END { }
|
||||
OPTRACE "set parameters" START { }
|
||||
set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.cache/wt [current_project]
|
||||
set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.xpr [current_project]
|
||||
set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
OPTRACE "set parameters" END { }
|
||||
OPTRACE "add files" START { }
|
||||
add_files -quiet /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.dcp
|
||||
set_msg_config -source 4 -id {BD 41-1661} -limit 0
|
||||
set_param project.isImplRun true
|
||||
add_files /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/bd/system/system.bd
|
||||
set_param project.isImplRun false
|
||||
OPTRACE "read constraints: implementation" START { }
|
||||
read_xdc /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc
|
||||
read_xdc /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc
|
||||
OPTRACE "read constraints: implementation" END { }
|
||||
OPTRACE "read constraints: implementation_pre" START { }
|
||||
OPTRACE "read constraints: implementation_pre" END { }
|
||||
OPTRACE "add files" END { }
|
||||
OPTRACE "link_design" START { }
|
||||
set_param project.isImplRun true
|
||||
link_design -top system_wrapper -part xc7z035ffg676-2
|
||||
OPTRACE "link_design" END { }
|
||||
set_param project.isImplRun false
|
||||
OPTRACE "gray box cells" START { }
|
||||
OPTRACE "gray box cells" END { }
|
||||
OPTRACE "init_design_reports" START { REPORT }
|
||||
OPTRACE "init_design_reports" END { }
|
||||
OPTRACE "init_design_write_hwdef" START { }
|
||||
OPTRACE "init_design_write_hwdef" END { }
|
||||
close_msg_db -file init_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed init_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step init_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Init Design" END { }
|
||||
OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
|
||||
start_step opt_design
|
||||
set ACTIVE_STEP opt_design
|
||||
set rc [catch {
|
||||
create_msg_db opt_design.pb
|
||||
OPTRACE "read constraints: opt_design" START { }
|
||||
OPTRACE "read constraints: opt_design" END { }
|
||||
OPTRACE "opt_design" START { }
|
||||
opt_design
|
||||
OPTRACE "opt_design" END { }
|
||||
OPTRACE "read constraints: opt_design_post" START { }
|
||||
OPTRACE "read constraints: opt_design_post" END { }
|
||||
OPTRACE "opt_design reports" START { REPORT }
|
||||
create_report "impl_1_opt_report_drc_0" "report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx"
|
||||
OPTRACE "opt_design reports" END { }
|
||||
OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force system_wrapper_opt.dcp
|
||||
OPTRACE "Opt Design: write_checkpoint" END { }
|
||||
close_msg_db -file opt_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed opt_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step opt_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Opt Design" END { }
|
||||
OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
|
||||
start_step place_design
|
||||
set ACTIVE_STEP place_design
|
||||
set rc [catch {
|
||||
create_msg_db place_design.pb
|
||||
OPTRACE "read constraints: place_design" START { }
|
||||
OPTRACE "read constraints: place_design" END { }
|
||||
if { [llength [get_debug_cores -quiet] ] > 0 } {
|
||||
OPTRACE "implement_debug_core" START { }
|
||||
implement_debug_core
|
||||
OPTRACE "implement_debug_core" END { }
|
||||
}
|
||||
OPTRACE "place_design" START { }
|
||||
place_design
|
||||
OPTRACE "place_design" END { }
|
||||
OPTRACE "read constraints: place_design_post" START { }
|
||||
OPTRACE "read constraints: place_design_post" END { }
|
||||
OPTRACE "place_design reports" START { REPORT }
|
||||
create_report "impl_1_place_report_io_0" "report_io -file system_wrapper_io_placed.rpt"
|
||||
create_report "impl_1_place_report_utilization_0" "report_utilization -file system_wrapper_utilization_placed.rpt -pb system_wrapper_utilization_placed.pb"
|
||||
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt"
|
||||
OPTRACE "place_design reports" END { }
|
||||
OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force system_wrapper_placed.dcp
|
||||
OPTRACE "Place Design: write_checkpoint" END { }
|
||||
close_msg_db -file place_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed place_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step place_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Place Design" END { }
|
||||
OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
|
||||
start_step route_design
|
||||
set ACTIVE_STEP route_design
|
||||
set rc [catch {
|
||||
create_msg_db route_design.pb
|
||||
OPTRACE "read constraints: route_design" START { }
|
||||
OPTRACE "read constraints: route_design" END { }
|
||||
OPTRACE "route_design" START { }
|
||||
route_design
|
||||
OPTRACE "route_design" END { }
|
||||
OPTRACE "read constraints: route_design_post" START { }
|
||||
OPTRACE "read constraints: route_design_post" END { }
|
||||
OPTRACE "route_design reports" START { REPORT }
|
||||
create_report "impl_1_route_report_drc_0" "report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_methodology_0" "report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_power_0" "report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx"
|
||||
create_report "impl_1_route_report_route_status_0" "report_route_status -file system_wrapper_route_status.rpt -pb system_wrapper_route_status.pb"
|
||||
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file system_wrapper_timing_summary_routed.rpt -pb system_wrapper_timing_summary_routed.pb -rpx system_wrapper_timing_summary_routed.rpx -warn_on_violation "
|
||||
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file system_wrapper_incremental_reuse_routed.rpt"
|
||||
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt"
|
||||
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file system_wrapper_bus_skew_routed.rpt -pb system_wrapper_bus_skew_routed.pb -rpx system_wrapper_bus_skew_routed.rpx"
|
||||
OPTRACE "route_design reports" END { }
|
||||
OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force system_wrapper_routed.dcp
|
||||
OPTRACE "Route Design: write_checkpoint" END { }
|
||||
OPTRACE "route_design misc" START { }
|
||||
close_msg_db -file route_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
|
||||
OPTRACE "route_design write_checkpoint" END { }
|
||||
write_checkpoint -force system_wrapper_routed_error.dcp
|
||||
step_failed route_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step route_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "route_design misc" END { }
|
||||
OPTRACE "Phase: Route Design" END { }
|
||||
OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
|
||||
OPTRACE "write_bitstream setup" START { }
|
||||
start_step write_bitstream
|
||||
set ACTIVE_STEP write_bitstream
|
||||
set rc [catch {
|
||||
create_msg_db write_bitstream.pb
|
||||
OPTRACE "read constraints: write_bitstream" START { }
|
||||
OPTRACE "read constraints: write_bitstream" END { }
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
catch { write_mem_info -force -no_partial_mmi system_wrapper.mmi }
|
||||
OPTRACE "write_bitstream setup" END { }
|
||||
OPTRACE "write_bitstream" START { }
|
||||
write_bitstream -force system_wrapper.bit
|
||||
OPTRACE "write_bitstream" END { }
|
||||
OPTRACE "write_bitstream misc" START { }
|
||||
OPTRACE "read constraints: write_bitstream_post" START { }
|
||||
OPTRACE "read constraints: write_bitstream_post" END { }
|
||||
catch {write_debug_probes -quiet -force system_wrapper}
|
||||
catch {file copy -force system_wrapper.ltx debug_nets.ltx}
|
||||
close_msg_db -file write_bitstream.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed write_bitstream
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step write_bitstream
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "write_bitstream misc" END { }
|
||||
OPTRACE "Phase: Write Bitstream" END { }
|
||||
OPTRACE "impl_1" END { }
|
||||
@@ -0,0 +1,846 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Wed May 27 16:36:42 2026
|
||||
# Process ID: 959246
|
||||
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1
|
||||
# Command line: vivado -log system_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
|
||||
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper.vdi
|
||||
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/vivado.jou
|
||||
# Running On: mkb, OS: Linux, CPU Frequency: 4911.606 MHz, CPU Physical cores: 32, Host memory: 134146 MB
|
||||
#-----------------------------------------------------------
|
||||
source system_wrapper.tcl -notrace
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
|
||||
Command: link_design -top system_wrapper -part xc7z035ffg676-2
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1722.395 ; gain = 0.000 ; free physical = 1995 ; free virtual = 71203
|
||||
INFO: [Netlist 29-17] Analyzing 39 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc:50]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Project 1-1687] 1 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2307.883 ; gain = 0.000 ; free physical = 1722 ; free virtual = 70993
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 33 instances were transformed.
|
||||
IOBUF => IOBUF (IBUF, OBUFT): 33 instances
|
||||
|
||||
11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2307.883 ; gain = 962.004 ; free physical = 1730 ; free virtual = 71000
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2307.883 ; gain = 0.000 ; free physical = 1727 ; free virtual = 71012
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Ending Cache Timing Information Task | Checksum: 2382775f8
|
||||
|
||||
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2762.520 ; gain = 454.637 ; free physical = 1293 ; free virtual = 70618
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Initialization
|
||||
|
||||
Phase 1.1 Core Generation And Design Setup
|
||||
|
||||
Phase 1.1.1 Generate And Synthesize Debug Cores
|
||||
INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub
|
||||
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.
|
||||
INFO: [Chipscope 16-329] Generating Script for core instance : u_ila_0
|
||||
INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:ila:6.2 for cell u_ila_0_CV.
|
||||
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3095.020 ; gain = 0.000 ; free physical = 9128 ; free virtual = 68708
|
||||
Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3201.777 ; gain = 0.000 ; free physical = 8923 ; free virtual = 68563
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3378.160 ; gain = 0.000 ; free physical = 8306 ; free virtual = 68085
|
||||
Phase 1.1.1 Generate And Synthesize Debug Cores | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68085
|
||||
Phase 1.1 Core Generation And Design Setup | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68085
|
||||
|
||||
Phase 1.2 Setup Constraints And Sort Netlist
|
||||
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68086
|
||||
Phase 1 Initialization | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8300 ; free virtual = 68083
|
||||
|
||||
Phase 2 Timer Update And Timing Data Collection
|
||||
|
||||
Phase 2.1 Timer Update
|
||||
Phase 2.1 Timer Update | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:06 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8296 ; free virtual = 68078
|
||||
|
||||
Phase 2.2 Timing Data Collection
|
||||
Phase 2.2 Timing Data Collection | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:06 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8279 ; free virtual = 68065
|
||||
Phase 2 Timer Update And Timing Data Collection | Checksum: 1a85f7bbe
|
||||
|
||||
Time (s): cpu = 00:03:06 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8279 ; free virtual = 68065
|
||||
|
||||
Phase 3 Retarget
|
||||
INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 3 Retarget | Checksum: 20e292eaa
|
||||
|
||||
Time (s): cpu = 00:03:07 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8270 ; free virtual = 68062
|
||||
Retarget | Checksum: 20e292eaa
|
||||
INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 35 cells
|
||||
INFO: [Opt 31-1021] In phase Retarget, 99 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 4 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 4 Constant propagation | Checksum: 1fb9c5663
|
||||
|
||||
Time (s): cpu = 00:03:07 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8271 ; free virtual = 68063
|
||||
Constant propagation | Checksum: 1fb9c5663
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 16 cells
|
||||
INFO: [Opt 31-1021] In phase Constant propagation, 49 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 5 Sweep
|
||||
Phase 5 Sweep | Checksum: 1dd19d44b
|
||||
|
||||
Time (s): cpu = 00:03:08 ; elapsed = 00:03:18 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8274 ; free virtual = 68074
|
||||
Sweep | Checksum: 1dd19d44b
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 46 cells
|
||||
INFO: [Opt 31-1021] In phase Sweep, 956 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 6 BUFG optimization
|
||||
INFO: [Opt 31-194] Inserted BUFG system_i/dna_port_read_0/inst/read_vld_BUFG_inst to drive 57 load(s) on clock net system_i/dna_port_read_0/inst/read_vld_BUFG
|
||||
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
|
||||
Phase 6 BUFG optimization | Checksum: 202feca59
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8266 ; free virtual = 68070
|
||||
BUFG optimization | Checksum: 202feca59
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 7 Shift Register Optimization
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_A due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_B due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 due to none static srl address bits
|
||||
WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 due to none static srl address bits
|
||||
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
|
||||
Phase 7 Shift Register Optimization | Checksum: 202feca59
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8263 ; free virtual = 68069
|
||||
Shift Register Optimization | Checksum: 202feca59
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 8 Post Processing Netlist
|
||||
Phase 8 Post Processing Netlist | Checksum: 202feca59
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8260 ; free virtual = 68067
|
||||
Post Processing Netlist | Checksum: 202feca59
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
INFO: [Opt 31-1021] In phase Post Processing Netlist, 57 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
||||
|
||||
Phase 9 Finalization
|
||||
|
||||
Phase 9.1 Finalizing Design Cores and Updating Shapes
|
||||
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2572a104c
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8258 ; free virtual = 68070
|
||||
|
||||
Phase 9.2 Verifying Netlist Connectivity
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3442.176 ; gain = 0.000 ; free physical = 8255 ; free virtual = 68068
|
||||
Phase 9.2 Verifying Netlist Connectivity | Checksum: 2572a104c
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8255 ; free virtual = 68068
|
||||
Phase 9 Finalization | Checksum: 2572a104c
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8255 ; free virtual = 68068
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 4 | 35 | 99 |
|
||||
| Constant propagation | 0 | 16 | 49 |
|
||||
| Sweep | 0 | 46 | 956 |
|
||||
| BUFG optimization | 1 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 57 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Ending Logic Optimization Task | Checksum: 2572a104c
|
||||
|
||||
Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8254 ; free virtual = 68068
|
||||
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
|
||||
Done building netlist checker database: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3442.176 ; gain = 0.000 ; free physical = 8253 ; free virtual = 68067
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
INFO: [Power 33-23] Power model is not available for DNA_PORT_inst
|
||||
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
||||
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
|
||||
|
||||
Starting PowerOpt Patch Enables Task
|
||||
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 3 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
||||
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
|
||||
Number of BRAM Ports augmented: 3 newly gated: 0 Total Ports: 6
|
||||
Ending PowerOpt Patch Enables Task | Checksum: 1c6a995af
|
||||
|
||||
Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7922 ; free virtual = 67775
|
||||
Ending Power Optimization Task | Checksum: 1c6a995af
|
||||
|
||||
Time (s): cpu = 00:00:11 ; elapsed = 00:00:04 . Memory (MB): peak = 3998.043 ; gain = 555.867 ; free physical = 7922 ; free virtual = 67775
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 1c6a995af
|
||||
|
||||
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7922 ; free virtual = 67774
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7921 ; free virtual = 67776
|
||||
Ending Netlist Obfuscation Task | Checksum: 1b06a1b26
|
||||
|
||||
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7921 ; free virtual = 67776
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
54 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
opt_design: Time (s): cpu = 00:03:26 ; elapsed = 00:03:28 . Memory (MB): peak = 3998.043 ; gain = 1690.160 ; free physical = 7921 ; free virtual = 67776
|
||||
INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx
|
||||
Command: report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Wrote PlaceDB: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7766 ; free virtual = 67648
|
||||
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7766 ; free virtual = 67648
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67652
|
||||
Writing XDEF routing special nets.
|
||||
Wrote RouteStorage: Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67653
|
||||
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67653
|
||||
Wrote Device Cache: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67654
|
||||
Write Physdb Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67654
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_opt.dcp' has been generated.
|
||||
INFO: [Chipscope 16-240] Debug cores have already been implemented
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
|
||||
|
||||
Starting Placer Task
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7612 ; free virtual = 67560
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 19758bd7a
|
||||
|
||||
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7612 ; free virtual = 67559
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7611 ; free virtual = 67559
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8751fbf6
|
||||
|
||||
Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7587 ; free virtual = 67558
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: dd0b0e99
|
||||
|
||||
Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7431 ; free virtual = 67481
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: dd0b0e99
|
||||
|
||||
Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7428 ; free virtual = 67479
|
||||
Phase 1 Placer Initialization | Checksum: dd0b0e99
|
||||
|
||||
Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7428 ; free virtual = 67479
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: eecb6848
|
||||
|
||||
Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7404 ; free virtual = 67474
|
||||
|
||||
Phase 2.2 Update Timing before SLR Path Opt
|
||||
Phase 2.2 Update Timing before SLR Path Opt | Checksum: db55687b
|
||||
|
||||
Time (s): cpu = 00:00:23 ; elapsed = 00:00:12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7407 ; free virtual = 67493
|
||||
|
||||
Phase 2.3 Post-Processing in Floorplanning
|
||||
Phase 2.3 Post-Processing in Floorplanning | Checksum: db55687b
|
||||
|
||||
Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7401 ; free virtual = 67488
|
||||
|
||||
Phase 2.4 Global Placement Core
|
||||
|
||||
Phase 2.4.1 UpdateTiming Before Physical Synthesis
|
||||
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1e9ca9de9
|
||||
|
||||
Time (s): cpu = 00:00:54 ; elapsed = 00:00:25 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7017 ; free virtual = 67264
|
||||
|
||||
Phase 2.4.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 1172 LUT instances to create LUTNM shape
|
||||
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
|
||||
INFO: [Physopt 32-1138] End 1 Pass. Optimized 565 nets or LUTs. Breaked 0 LUT, combined 565 existing LUTs and moved 0 existing LUT
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
|
||||
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7022 ; free virtual = 67279
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| LUT Combining | 0 | 565 | 565 | 0 | 1 | 00:00:00 |
|
||||
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
|
||||
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 0 | 565 | 565 | 0 | 4 | 00:00:01 |
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2be40b2db
|
||||
|
||||
Time (s): cpu = 00:00:59 ; elapsed = 00:00:28 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7014 ; free virtual = 67290
|
||||
Phase 2.4 Global Placement Core | Checksum: 2859c5ffd
|
||||
|
||||
Time (s): cpu = 00:01:01 ; elapsed = 00:00:29 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7011 ; free virtual = 67293
|
||||
Phase 2 Global Placement | Checksum: 2859c5ffd
|
||||
|
||||
Time (s): cpu = 00:01:01 ; elapsed = 00:00:29 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7011 ; free virtual = 67293
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 1ea091a8d
|
||||
|
||||
Time (s): cpu = 00:01:05 ; elapsed = 00:00:30 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7007 ; free virtual = 67305
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 29969cf51
|
||||
|
||||
Time (s): cpu = 00:01:13 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6986 ; free virtual = 67345
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 2b62d77e5
|
||||
|
||||
Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6984 ; free virtual = 67343
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 1ed299be3
|
||||
|
||||
Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6982 ; free virtual = 67342
|
||||
|
||||
Phase 3.5 Small Shape Detail Placement
|
||||
|
||||
Phase 3.5.1 Place Remaining
|
||||
Phase 3.5.1 Place Remaining | Checksum: 21b5bb37c
|
||||
|
||||
Time (s): cpu = 00:01:20 ; elapsed = 00:00:41 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6918 ; free virtual = 67346
|
||||
Phase 3.5 Small Shape Detail Placement | Checksum: 21b5bb37c
|
||||
|
||||
Time (s): cpu = 00:01:20 ; elapsed = 00:00:41 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6849 ; free virtual = 67281
|
||||
|
||||
Phase 3.6 Re-assign LUT pins
|
||||
Phase 3.6 Re-assign LUT pins | Checksum: 1a6b845f5
|
||||
|
||||
Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6838 ; free virtual = 67277
|
||||
|
||||
Phase 3.7 Pipeline Register Optimization
|
||||
Phase 3.7 Pipeline Register Optimization | Checksum: 1a81ce610
|
||||
|
||||
Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6834 ; free virtual = 67277
|
||||
Phase 3 Detail Placement | Checksum: 1a81ce610
|
||||
|
||||
Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6828 ; free virtual = 67276
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 1472dfedc
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
|
||||
Starting Physical Synthesis Task
|
||||
|
||||
Phase 1 Physical Synthesis Initialization
|
||||
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
|
||||
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.626 | TNS=0.000 |
|
||||
Phase 1 Physical Synthesis Initialization | Checksum: a925bbef
|
||||
|
||||
Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6782 ; free virtual = 67315
|
||||
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
|
||||
Ending Physical Synthesis Task | Checksum: a925bbef
|
||||
|
||||
Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6769 ; free virtual = 67309
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 1472dfedc
|
||||
|
||||
Time (s): cpu = 00:01:38 ; elapsed = 00:00:50 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6768 ; free virtual = 67314
|
||||
|
||||
Phase 4.1.1.2 Post Placement Timing Optimization
|
||||
INFO: [Place 30-746] Post Placement Timing Summary WNS=2.626. For the most accurate timing information please run report_timing.
|
||||
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 14f55351a
|
||||
|
||||
Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
|
||||
|
||||
Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 14f55351a
|
||||
|
||||
Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307
|
||||
|
||||
Phase 4.2 Post Placement Cleanup
|
||||
Phase 4.2 Post Placement Cleanup | Checksum: 14f55351a
|
||||
|
||||
Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6750 ; free virtual = 67308
|
||||
|
||||
Phase 4.3 Placer Reporting
|
||||
|
||||
Phase 4.3.1 Print Estimated Congestion
|
||||
INFO: [Place 30-612] Post-Placement Estimated Congestion
|
||||
____________________________________________________
|
||||
| | Global Congestion | Short Congestion |
|
||||
| Direction | Region Size | Region Size |
|
||||
|___________|___________________|___________________|
|
||||
| North| 2x2| 2x2|
|
||||
|___________|___________________|___________________|
|
||||
| South| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
| East| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
| West| 1x1| 1x1|
|
||||
|___________|___________________|___________________|
|
||||
|
||||
Phase 4.3.1 Print Estimated Congestion | Checksum: 14f55351a
|
||||
|
||||
Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6748 ; free virtual = 67312
|
||||
Phase 4.3 Placer Reporting | Checksum: 14f55351a
|
||||
|
||||
Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
|
||||
|
||||
Phase 4.4 Final Placement Cleanup
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
|
||||
|
||||
Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19c30fa75
|
||||
|
||||
Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6741 ; free virtual = 67314
|
||||
Ending Placer Task | Checksum: dcf0239e
|
||||
|
||||
Time (s): cpu = 00:01:41 ; elapsed = 00:00:53 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6725 ; free virtual = 67298
|
||||
90 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
place_design completed successfully
|
||||
place_design: Time (s): cpu = 00:01:44 ; elapsed = 00:00:54 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6725 ; free virtual = 67298
|
||||
INFO: [runtcl-4] Executing : report_io -file system_wrapper_io_placed.rpt
|
||||
report_io: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6722 ; free virtual = 67295
|
||||
INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_placed.rpt -pb system_wrapper_utilization_placed.pb
|
||||
INFO: [runtcl-4] Executing : report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt
|
||||
report_control_sets: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6708 ; free virtual = 67293
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6731 ; free virtual = 67329
|
||||
Wrote PlaceDB: Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67235
|
||||
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67235
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Wrote RouteStorage: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67236
|
||||
Wrote Netlist Cache: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6582 ; free virtual = 67237
|
||||
Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6582 ; free virtual = 67238
|
||||
Write Physdb Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6581 ; free virtual = 67237
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_placed.dcp' has been generated.
|
||||
Command: route_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
|
||||
Running DRC as a precondition to command route_design
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
|
||||
Starting Routing Task
|
||||
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
|
||||
|
||||
Phase 1 Build RT Design
|
||||
Checksum: PlaceDB: 76da8209 ConstDB: 0 ShapeSum: 6615a195 RouteDB: 0
|
||||
Post Restoration Checksum: NetGraph: 4a144a14 | NumContArr: af14b29e | Constraints: c2a8fa9d | Timing: c2a8fa9d
|
||||
Phase 1 Build RT Design | Checksum: 27e7af1ec
|
||||
|
||||
Time (s): cpu = 00:00:49 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5905 ; free virtual = 66985
|
||||
|
||||
Phase 2 Router Initialization
|
||||
|
||||
Phase 2.1 Fix Topology Constraints
|
||||
Phase 2.1 Fix Topology Constraints | Checksum: 27e7af1ec
|
||||
|
||||
Time (s): cpu = 00:00:50 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5899 ; free virtual = 66984
|
||||
|
||||
Phase 2.2 Pre Route Cleanup
|
||||
Phase 2.2 Pre Route Cleanup | Checksum: 27e7af1ec
|
||||
|
||||
Time (s): cpu = 00:00:50 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5899 ; free virtual = 66984
|
||||
Number of Nodes with overlaps = 0
|
||||
|
||||
Phase 2.3 Update Timing
|
||||
Phase 2.3 Update Timing | Checksum: 32928bcd2
|
||||
|
||||
Time (s): cpu = 00:01:06 ; elapsed = 00:00:40 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5635 ; free virtual = 66801
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.632 | TNS=0.000 | WHS=-0.263 | THS=-1616.164|
|
||||
|
||||
|
||||
Phase 2.4 Update Timing for Bus Skew
|
||||
|
||||
Phase 2.4.1 Update Timing
|
||||
Phase 2.4.1 Update Timing | Checksum: 2864114c5
|
||||
|
||||
Time (s): cpu = 00:01:19 ; elapsed = 00:00:43 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5449 ; free virtual = 66672
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.632 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 2.4 Update Timing for Bus Skew | Checksum: 291576a87
|
||||
|
||||
Time (s): cpu = 00:01:19 ; elapsed = 00:00:44 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5447 ; free virtual = 66671
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 0.0211705 %
|
||||
Global Horizontal Routing Utilization = 0.00488761 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 38492
|
||||
(Failed Nets is the sum of unrouted and partially routed nets)
|
||||
Number of Unrouted Nets = 38484
|
||||
Number of Partially Routed Nets = 8
|
||||
Number of Node Overlaps = 6
|
||||
|
||||
Phase 2 Router Initialization | Checksum: 2a426d310
|
||||
|
||||
Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5405 ; free virtual = 66633
|
||||
|
||||
Phase 3 Initial Routing
|
||||
|
||||
Phase 3.1 Global Routing
|
||||
Phase 3.1 Global Routing | Checksum: 2a426d310
|
||||
|
||||
Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5405 ; free virtual = 66633
|
||||
|
||||
Phase 3.2 Initial Net Routing
|
||||
Phase 3.2 Initial Net Routing | Checksum: 22defbe6f
|
||||
|
||||
Time (s): cpu = 00:01:27 ; elapsed = 00:00:46 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5394 ; free virtual = 66641
|
||||
Phase 3 Initial Routing | Checksum: 22defbe6f
|
||||
|
||||
Time (s): cpu = 00:01:27 ; elapsed = 00:00:46 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5394 ; free virtual = 66641
|
||||
|
||||
Phase 4 Rip-up And Reroute
|
||||
|
||||
Phase 4.1 Global Iteration 0
|
||||
Number of Nodes with overlaps = 2836
|
||||
Number of Nodes with overlaps = 86
|
||||
Number of Nodes with overlaps = 3
|
||||
Number of Nodes with overlaps = 0
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.177 | TNS=0.000 | WHS=N/A | THS=N/A |
|
||||
|
||||
Phase 4.1 Global Iteration 0 | Checksum: 23a222cd5
|
||||
|
||||
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5385 ; free virtual = 66739
|
||||
Phase 4 Rip-up And Reroute | Checksum: 23a222cd5
|
||||
|
||||
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5385 ; free virtual = 66739
|
||||
|
||||
Phase 5 Delay and Skew Optimization
|
||||
|
||||
Phase 5.1 Delay CleanUp
|
||||
Phase 5.1 Delay CleanUp | Checksum: 23a222cd5
|
||||
|
||||
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
|
||||
|
||||
Phase 5.2 Clock Skew Optimization
|
||||
Phase 5.2 Clock Skew Optimization | Checksum: 23a222cd5
|
||||
|
||||
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
|
||||
Phase 5 Delay and Skew Optimization | Checksum: 23a222cd5
|
||||
|
||||
Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738
|
||||
|
||||
Phase 6 Post Hold Fix
|
||||
|
||||
Phase 6.1 Hold Fix Iter
|
||||
|
||||
Phase 6.1.1 Update Timing
|
||||
Phase 6.1.1 Update Timing | Checksum: 2a8514d39
|
||||
|
||||
Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5382 ; free virtual = 66749
|
||||
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.189 | TNS=0.000 | WHS=0.028 | THS=0.000 |
|
||||
|
||||
Phase 6.1 Hold Fix Iter | Checksum: 253fa4620
|
||||
|
||||
Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
|
||||
Phase 6 Post Hold Fix | Checksum: 253fa4620
|
||||
|
||||
Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
|
||||
|
||||
Phase 7 Route finalize
|
||||
|
||||
Router Utilization Summary
|
||||
Global Vertical Routing Utilization = 2.42898 %
|
||||
Global Horizontal Routing Utilization = 2.87613 %
|
||||
Routable Net Status*
|
||||
*Does not include unroutable nets such as driverless and loadless.
|
||||
Run report_route_status for detailed report.
|
||||
Number of Failed Nets = 0
|
||||
(Failed Nets is the sum of unrouted and partially routed nets)
|
||||
Number of Unrouted Nets = 0
|
||||
Number of Partially Routed Nets = 0
|
||||
Number of Node Overlaps = 0
|
||||
|
||||
Phase 7 Route finalize | Checksum: 253fa4620
|
||||
|
||||
Time (s): cpu = 00:01:48 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
|
||||
|
||||
Phase 8 Verifying routed nets
|
||||
|
||||
Verification completed successfully
|
||||
Phase 8 Verifying routed nets | Checksum: 253fa4620
|
||||
|
||||
Time (s): cpu = 00:01:48 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748
|
||||
|
||||
Phase 9 Depositing Routes
|
||||
Phase 9 Depositing Routes | Checksum: 24ae08112
|
||||
|
||||
Time (s): cpu = 00:01:50 ; elapsed = 00:00:57 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5378 ; free virtual = 66754
|
||||
|
||||
Phase 10 Post Router Timing
|
||||
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.189 | TNS=0.000 | WHS=0.028 | THS=0.000 |
|
||||
|
||||
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
|
||||
Phase 10 Post Router Timing | Checksum: 24ae08112
|
||||
|
||||
Time (s): cpu = 00:01:53 ; elapsed = 00:00:58 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5367 ; free virtual = 66762
|
||||
INFO: [Route 35-16] Router Completed Successfully
|
||||
|
||||
Phase 11 Post-Route Event Processing
|
||||
Phase 11 Post-Route Event Processing | Checksum: 10a817867
|
||||
|
||||
Time (s): cpu = 00:01:54 ; elapsed = 00:00:59 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5358 ; free virtual = 66761
|
||||
Ending Routing Task | Checksum: 10a817867
|
||||
|
||||
Time (s): cpu = 00:01:55 ; elapsed = 00:01:00 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5334 ; free virtual = 66752
|
||||
|
||||
Routing Is Done.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
108 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
route_design completed successfully
|
||||
route_design: Time (s): cpu = 00:01:59 ; elapsed = 00:01:02 . Memory (MB): peak = 4083.043 ; gain = 85.000 ; free physical = 5335 ; free virtual = 66757
|
||||
INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx
|
||||
Command: report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_drc_routed.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx
|
||||
Command: report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [DRC 23-133] Running Methodology with 8 threads
|
||||
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_methodology_drc_routed.rpt.
|
||||
report_methodology completed successfully
|
||||
report_methodology: Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5233 ; free virtual = 66738
|
||||
INFO: [runtcl-4] Executing : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
|
||||
Command: report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
|
||||
INFO: [Power 33-23] Power model is not available for DNA_PORT_inst
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
|
||||
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
|
||||
119 Infos, 83 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
report_power completed successfully
|
||||
report_power: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5140 ; free virtual = 66731
|
||||
INFO: [runtcl-4] Executing : report_route_status -file system_wrapper_route_status.rpt -pb system_wrapper_route_status.pb
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file system_wrapper_timing_summary_routed.rpt -pb system_wrapper_timing_summary_routed.pb -rpx system_wrapper_timing_summary_routed.rpx -warn_on_violation
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
|
||||
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
|
||||
INFO: [runtcl-4] Executing : report_incremental_reuse -file system_wrapper_incremental_reuse_routed.rpt
|
||||
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
|
||||
INFO: [runtcl-4] Executing : report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt
|
||||
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file system_wrapper_bus_skew_routed.rpt -pb system_wrapper_bus_skew_routed.pb -rpx system_wrapper_bus_skew_routed.rpx
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5090 ; free virtual = 66740
|
||||
Wrote PlaceDB: Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5008 ; free virtual = 66718
|
||||
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5008 ; free virtual = 66718
|
||||
Writing XDEF routing.
|
||||
Writing XDEF routing logical nets.
|
||||
Writing XDEF routing special nets.
|
||||
Wrote RouteStorage: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.29 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66717
|
||||
Wrote Netlist Cache: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66719
|
||||
Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66720
|
||||
Write Physdb Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66721
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_routed.dcp' has been generated.
|
||||
Command: write_bitstream -force system_wrapper.bit
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035'
|
||||
Running DRC as a precondition to command write_bitstream
|
||||
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
|
||||
INFO: [DRC 23-27] Running DRC with 8 threads
|
||||
WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I0) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
||||
WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1/I0) is not included in the LUT equation: 'O6=(A6+~A6)*((A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
||||
WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A5' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I1) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
||||
WARNING: [DRC RTSTAT-10] No routable loads: 21 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TMS, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i... and (the first 15 of 19 listed).
|
||||
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 4 Warnings
|
||||
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
|
||||
Loading data files...
|
||||
Loading site data...
|
||||
Loading route data...
|
||||
Processing options...
|
||||
Creating bitmap...
|
||||
Creating bitstream...
|
||||
Writing bitstream ./system_wrapper.bit...
|
||||
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
13 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
write_bitstream completed successfully
|
||||
write_bitstream: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 4599.906 ; gain = 300.855 ; free physical = 4256 ; free virtual = 66217
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:43:10 2026...
|
||||
@@ -0,0 +1,2 @@
|
||||
|
||||
2018.1’Bus skew results˜¥[¶A
|
||||
@@ -0,0 +1,413 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Wed May 27 16:42:45 2026
|
||||
| Host : mkb running 64-bit unknown
|
||||
| Command : report_bus_skew -warn_on_violation -file system_wrapper_bus_skew_routed.rpt -pb system_wrapper_bus_skew_routed.pb -rpx system_wrapper_bus_skew_routed.rpx
|
||||
| Design : system_wrapper
|
||||
| Device : 7z035-ffg676
|
||||
| Speed File : -2 PRODUCTION 1.12 2019-11-22
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Bus Skew Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Bus Skew Report Summary
|
||||
2. Bus Skew Report Per Constraint
|
||||
|
||||
1. Bus Skew Report Summary
|
||||
--------------------------
|
||||
|
||||
Id Position From To Corner Requirement(ns) Actual(ns) Slack(ns)
|
||||
-- -------- ------------------------------ ------------------------------ ------ --------------- ---------- ---------
|
||||
1 79 [get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]}]]
|
||||
[get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]}]]
|
||||
Slow 10.000 0.518 9.482
|
||||
2 81 [get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]}]]
|
||||
[get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]}]]
|
||||
Slow 10.000 0.458 9.542
|
||||
3 84 [get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]}]]
|
||||
[get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]}]]
|
||||
Slow 10.000 0.387 9.613
|
||||
4 86 [get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]}]]
|
||||
[get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]}]]
|
||||
Slow 10.000 0.324 9.676
|
||||
|
||||
|
||||
2. Bus Skew Report Per Constraint
|
||||
---------------------------------
|
||||
|
||||
Id: 1
|
||||
set_bus_skew -from [get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]}]] -to [get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]}]] 10.000
|
||||
Requirement: 10.000ns
|
||||
Endpoints: 4
|
||||
|
||||
From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns)
|
||||
-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- ---------
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
||||
clk_fpga_0 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
|
||||
Slow 0.518 9.482
|
||||
|
||||
|
||||
Slack (MET) : 9.482ns (requirement - actual skew)
|
||||
Endpoint Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
|
||||
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK)
|
||||
Endpoint Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
|
||||
(rising edge-triggered cell FDCE clocked by clk_fpga_0)
|
||||
Reference Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
|
||||
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK)
|
||||
Reference Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
|
||||
(rising edge-triggered cell FDCE clocked by clk_fpga_0)
|
||||
Path Type: Bus Skew (Max at Slow Process Corner)
|
||||
Requirement: 10.000ns
|
||||
Endpoint Relative Delay: 3.670ns
|
||||
Reference Relative Delay: 2.219ns
|
||||
Relative CRPR: 0.933ns
|
||||
Actual Bus Skew: 0.518ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR)
|
||||
|
||||
Endpoint path:
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
||||
0.000 0.000 r
|
||||
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
||||
net (fo=1, routed) 3.978 3.978 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
||||
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 4.071 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
||||
net (fo=482, routed) 1.234 5.305 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
|
||||
SLICE_X39Y177 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X39Y177 FDCE (Prop_fdce_C_Q) 0.223 5.528 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
|
||||
net (fo=1, routed) 0.559 6.087 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
|
||||
SLICE_X40Y185 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock clk_fpga_0 rise edge)
|
||||
0.000 0.000 r
|
||||
PS7_X0Y0 PS7 0.000 0.000 r system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
||||
net (fo=1, routed) 1.241 1.241 system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
||||
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.083 1.324 r system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
||||
net (fo=42143, routed) 1.101 2.425 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
|
||||
SLICE_X40Y185 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/C
|
||||
clock pessimism 0.000 2.425
|
||||
SLICE_X40Y185 FDCE (Setup_fdce_C_D) -0.008 2.417 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
|
||||
-------------------------------------------------------------------
|
||||
data arrival 6.087
|
||||
clock arrival 2.417
|
||||
-------------------------------------------------------------------
|
||||
relative delay 3.670
|
||||
|
||||
Reference path:
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
||||
0.000 0.000 r
|
||||
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
||||
net (fo=1, routed) 3.372 3.372 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
||||
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 3.455 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
||||
net (fo=482, routed) 1.095 4.550 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
|
||||
SLICE_X38Y176 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X38Y176 FDCE (Prop_fdce_C_Q) 0.206 4.756 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
|
||||
net (fo=1, routed) 0.243 4.999 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
|
||||
SLICE_X39Y176 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock clk_fpga_0 rise edge)
|
||||
0.000 0.000 r
|
||||
PS7_X0Y0 PS7 0.000 0.000 r system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
||||
net (fo=1, routed) 1.339 1.339 system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
||||
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.093 1.432 r system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
||||
net (fo=42143, routed) 1.230 2.662 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
|
||||
SLICE_X39Y176 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/C
|
||||
clock pessimism 0.000 2.662
|
||||
SLICE_X39Y176 FDCE (Hold_fdce_C_D) 0.118 2.780 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
|
||||
-------------------------------------------------------------------
|
||||
data arrival 4.999
|
||||
clock arrival 2.780
|
||||
-------------------------------------------------------------------
|
||||
relative delay 2.219
|
||||
|
||||
|
||||
|
||||
Id: 2
|
||||
set_bus_skew -from [get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]}]] -to [get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]}]] 10.000
|
||||
Requirement: 10.000ns
|
||||
Endpoints: 4
|
||||
|
||||
From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns)
|
||||
-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- ---------
|
||||
clk_fpga_0 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
|
||||
Slow 0.458 9.542
|
||||
|
||||
|
||||
Slack (MET) : 9.542ns (requirement - actual skew)
|
||||
Endpoint Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
|
||||
(rising edge-triggered cell FDCE clocked by clk_fpga_0)
|
||||
Endpoint Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
|
||||
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK)
|
||||
Reference Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
|
||||
(rising edge-triggered cell FDCE clocked by clk_fpga_0)
|
||||
Reference Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
|
||||
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK)
|
||||
Path Type: Bus Skew (Max at Slow Process Corner)
|
||||
Requirement: 10.000ns
|
||||
Endpoint Relative Delay: -1.130ns
|
||||
Reference Relative Delay: -2.586ns
|
||||
Relative CRPR: 0.998ns
|
||||
Actual Bus Skew: 0.458ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR)
|
||||
|
||||
Endpoint path:
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock clk_fpga_0 rise edge)
|
||||
0.000 0.000 r
|
||||
PS7_X0Y0 PS7 0.000 0.000 r system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
||||
net (fo=1, routed) 1.339 1.339 system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
||||
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.093 1.432 r system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
||||
net (fo=42143, routed) 1.230 2.662 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
|
||||
SLICE_X39Y176 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X39Y176 FDCE (Prop_fdce_C_Q) 0.223 2.885 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
|
||||
net (fo=1, routed) 0.556 3.441 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
|
||||
SLICE_X38Y176 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
||||
0.000 0.000 r
|
||||
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
||||
net (fo=1, routed) 3.372 3.372 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
||||
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 3.455 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
||||
net (fo=482, routed) 1.095 4.550 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
|
||||
SLICE_X38Y176 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/C
|
||||
clock pessimism 0.000 4.550
|
||||
SLICE_X38Y176 FDCE (Setup_fdce_C_D) 0.022 4.572 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
|
||||
-------------------------------------------------------------------
|
||||
data arrival 3.441
|
||||
clock arrival 4.572
|
||||
-------------------------------------------------------------------
|
||||
relative delay -1.130
|
||||
|
||||
Reference path:
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock clk_fpga_0 rise edge)
|
||||
0.000 0.000 r
|
||||
PS7_X0Y0 PS7 0.000 0.000 r system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
||||
net (fo=1, routed) 1.241 1.241 system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
||||
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.083 1.324 r system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
||||
net (fo=42143, routed) 1.093 2.417 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
|
||||
SLICE_X39Y176 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X39Y176 FDCE (Prop_fdce_C_Q) 0.178 2.595 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
|
||||
net (fo=1, routed) 0.273 2.868 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
|
||||
SLICE_X38Y176 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
||||
0.000 0.000 r
|
||||
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
||||
net (fo=1, routed) 3.978 3.978 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
||||
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 4.071 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
||||
net (fo=482, routed) 1.232 5.303 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
|
||||
SLICE_X38Y176 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/C
|
||||
clock pessimism 0.000 5.303
|
||||
SLICE_X38Y176 FDCE (Hold_fdce_C_D) 0.152 5.455 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
|
||||
-------------------------------------------------------------------
|
||||
data arrival 2.868
|
||||
clock arrival 5.455
|
||||
-------------------------------------------------------------------
|
||||
relative delay -2.586
|
||||
|
||||
|
||||
|
||||
Id: 3
|
||||
set_bus_skew -from [get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]}]] -to [get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]}]] 10.000
|
||||
Requirement: 10.000ns
|
||||
Endpoints: 4
|
||||
|
||||
From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns)
|
||||
-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- ---------
|
||||
clk_fpga_0 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
|
||||
Slow 0.387 9.613
|
||||
|
||||
|
||||
Slack (MET) : 9.613ns (requirement - actual skew)
|
||||
Endpoint Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
|
||||
(rising edge-triggered cell FDCE clocked by clk_fpga_0)
|
||||
Endpoint Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
|
||||
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK)
|
||||
Reference Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
|
||||
(rising edge-triggered cell FDCE clocked by clk_fpga_0)
|
||||
Reference Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
|
||||
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK)
|
||||
Path Type: Bus Skew (Max at Slow Process Corner)
|
||||
Requirement: 10.000ns
|
||||
Endpoint Relative Delay: -1.277ns
|
||||
Reference Relative Delay: -2.597ns
|
||||
Relative CRPR: 0.933ns
|
||||
Actual Bus Skew: 0.387ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR)
|
||||
|
||||
Endpoint path:
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock clk_fpga_0 rise edge)
|
||||
0.000 0.000 r
|
||||
PS7_X0Y0 PS7 0.000 0.000 r system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
||||
net (fo=1, routed) 1.339 1.339 system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
||||
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.093 1.432 r system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
||||
net (fo=42143, routed) 1.232 2.664 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
|
||||
SLICE_X32Y172 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X32Y172 FDCE (Prop_fdce_C_Q) 0.259 2.923 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
|
||||
net (fo=1, routed) 0.369 3.292 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
|
||||
SLICE_X34Y174 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
||||
0.000 0.000 r
|
||||
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
||||
net (fo=1, routed) 3.372 3.372 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
||||
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 3.455 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
||||
net (fo=482, routed) 1.094 4.549 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
|
||||
SLICE_X34Y174 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/C
|
||||
clock pessimism 0.000 4.549
|
||||
SLICE_X34Y174 FDCE (Setup_fdce_C_D) 0.021 4.570 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
|
||||
-------------------------------------------------------------------
|
||||
data arrival 3.292
|
||||
clock arrival 4.570
|
||||
-------------------------------------------------------------------
|
||||
relative delay -1.277
|
||||
|
||||
Reference path:
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock clk_fpga_0 rise edge)
|
||||
0.000 0.000 r
|
||||
PS7_X0Y0 PS7 0.000 0.000 r system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
||||
net (fo=1, routed) 1.241 1.241 system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
||||
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.083 1.324 r system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
||||
net (fo=42143, routed) 1.097 2.421 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
|
||||
SLICE_X34Y170 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X34Y170 FDCE (Prop_fdce_C_Q) 0.206 2.627 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
|
||||
net (fo=1, routed) 0.237 2.864 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
|
||||
SLICE_X34Y168 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
||||
0.000 0.000 r
|
||||
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
||||
net (fo=1, routed) 3.978 3.978 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
||||
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 4.071 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
||||
net (fo=482, routed) 1.239 5.310 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
|
||||
SLICE_X34Y168 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/C
|
||||
clock pessimism 0.000 5.310
|
||||
SLICE_X34Y168 FDCE (Hold_fdce_C_D) 0.152 5.462 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
|
||||
-------------------------------------------------------------------
|
||||
data arrival 2.864
|
||||
clock arrival 5.462
|
||||
-------------------------------------------------------------------
|
||||
relative delay -2.597
|
||||
|
||||
|
||||
|
||||
Id: 4
|
||||
set_bus_skew -from [get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]}]] -to [get_cells [list {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]} {dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]}]] 10.000
|
||||
Requirement: 10.000ns
|
||||
Endpoints: 4
|
||||
|
||||
From Clock To Clock Endpoint Pin Reference Pin Corner Actual(ns) Slack(ns)
|
||||
-------------------- -------------------- ------------------------------ ------------------------------ ------ ---------- ---------
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
||||
clk_fpga_0 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
|
||||
Slow 0.324 9.676
|
||||
|
||||
|
||||
Slack (MET) : 9.676ns (requirement - actual skew)
|
||||
Endpoint Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
|
||||
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK)
|
||||
Endpoint Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
|
||||
(rising edge-triggered cell FDCE clocked by clk_fpga_0)
|
||||
Reference Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
|
||||
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK)
|
||||
Reference Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
|
||||
(rising edge-triggered cell FDCE clocked by clk_fpga_0)
|
||||
Path Type: Bus Skew (Max at Slow Process Corner)
|
||||
Requirement: 10.000ns
|
||||
Endpoint Relative Delay: 3.492ns
|
||||
Reference Relative Delay: 2.211ns
|
||||
Relative CRPR: 0.956ns
|
||||
Actual Bus Skew: 0.324ns (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR)
|
||||
|
||||
Endpoint path:
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
||||
0.000 0.000 r
|
||||
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
||||
net (fo=1, routed) 3.978 3.978 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
||||
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 4.071 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
||||
net (fo=482, routed) 1.239 5.310 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
|
||||
SLICE_X34Y168 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X34Y168 FDCE (Prop_fdce_C_Q) 0.236 5.546 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
|
||||
net (fo=1, routed) 0.306 5.852 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
|
||||
SLICE_X34Y169 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock clk_fpga_0 rise edge)
|
||||
0.000 0.000 r
|
||||
PS7_X0Y0 PS7 0.000 0.000 r system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
||||
net (fo=1, routed) 1.241 1.241 system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
||||
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.083 1.324 r system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
||||
net (fo=42143, routed) 1.098 2.422 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
|
||||
SLICE_X34Y169 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/C
|
||||
clock pessimism 0.000 2.422
|
||||
SLICE_X34Y169 FDCE (Setup_fdce_C_D) -0.062 2.360 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
|
||||
-------------------------------------------------------------------
|
||||
data arrival 5.852
|
||||
clock arrival 2.360
|
||||
-------------------------------------------------------------------
|
||||
relative delay 3.492
|
||||
|
||||
Reference path:
|
||||
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
||||
------------------------------------------------------------------- -------------------
|
||||
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
||||
0.000 0.000 r
|
||||
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
||||
net (fo=1, routed) 3.372 3.372 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
||||
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 3.455 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
||||
net (fo=482, routed) 1.100 4.555 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
|
||||
SLICE_X35Y169 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
|
||||
------------------------------------------------------------------- -------------------
|
||||
SLICE_X35Y169 FDCE (Prop_fdce_C_Q) 0.178 4.733 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
|
||||
net (fo=1, routed) 0.298 5.030 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
|
||||
SLICE_X34Y170 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
|
||||
------------------------------------------------------------------- -------------------
|
||||
|
||||
(clock clk_fpga_0 rise edge)
|
||||
0.000 0.000 r
|
||||
PS7_X0Y0 PS7 0.000 0.000 r system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
||||
net (fo=1, routed) 1.339 1.339 system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
||||
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.093 1.432 r system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
||||
net (fo=42143, routed) 1.235 2.667 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
|
||||
SLICE_X34Y170 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/C
|
||||
clock pessimism 0.000 2.667
|
||||
SLICE_X34Y170 FDCE (Hold_fdce_C_D) 0.152 2.819 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
|
||||
-------------------------------------------------------------------
|
||||
data arrival 5.030
|
||||
clock arrival 2.819
|
||||
-------------------------------------------------------------------
|
||||
relative delay 2.211
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,339 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Wed May 27 16:42:44 2026
|
||||
| Host : mkb running 64-bit unknown
|
||||
| Command : report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt
|
||||
| Design : system_wrapper
|
||||
| Device : 7z035-ffg676
|
||||
| Speed File : -2 PRODUCTION 1.12 2019-11-22
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Utilization Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Clock Primitive Utilization
|
||||
2. Global Clock Resources
|
||||
3. Global Clock Source Details
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
5. Clock Regions : Global Clock Summary
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
7. Device Cell Placement Summary for Global Clock g1
|
||||
8. Device Cell Placement Summary for Global Clock g2
|
||||
9. Clock Region Cell Placement per Global Clock: Region X0Y2
|
||||
10. Clock Region Cell Placement per Global Clock: Region X0Y3
|
||||
11. Clock Region Cell Placement per Global Clock: Region X1Y3
|
||||
12. Clock Region Cell Placement per Global Clock: Region X0Y4
|
||||
13. Clock Region Cell Placement per Global Clock: Region X1Y4
|
||||
14. Clock Region Cell Placement per Global Clock: Region X0Y5
|
||||
15. Clock Region Cell Placement per Global Clock: Region X1Y5
|
||||
16. Clock Region Cell Placement per Global Clock: Region X0Y6
|
||||
|
||||
1. Clock Primitive Utilization
|
||||
------------------------------
|
||||
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| Type | Used | Available | LOC | Clock Region | Pblock |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| BUFGCTRL | 3 | 32 | 0 | 0 | 0 |
|
||||
| BUFH | 0 | 168 | 0 | 0 | 0 |
|
||||
| BUFIO | 0 | 32 | 0 | 0 | 0 |
|
||||
| BUFMR | 0 | 16 | 0 | 0 | 0 |
|
||||
| BUFR | 0 | 32 | 0 | 0 | 0 |
|
||||
| MMCM | 0 | 8 | 0 | 0 | 0 |
|
||||
| PLL | 0 | 8 | 0 | 0 | 0 |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
|
||||
|
||||
2. Global Clock Resources
|
||||
-------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------------------------+
|
||||
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------------------------+
|
||||
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 8 | 35619 | 0 | 10.000 | clk_fpga_0 | system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O | system_i/processing_system7_0/inst/FCLK_CLK0 |
|
||||
| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 2 | 461 | 0 | 33.000 | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O | dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i |
|
||||
| g2 | src2 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 2 | 57 | 0 | | | system_i/dna_port_read_0/inst/read_vld_BUFG_inst/O | system_i/dna_port_read_0/inst/read_vld_BUFG |
|
||||
+-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------------------------------------------------------------------------------+------------------------------------------------------------------------+----------------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
|
||||
|
||||
3. Global Clock Source Details
|
||||
------------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+---------------+--------------+-------------+-----------------+---------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|
||||
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+---------------+--------------+-------------+-----------------+---------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|
||||
| src0 | g0 | PS7/FCLKCLK[0] | PS7_X0Y0 | PS7_X0Y0 | X0Y6 | 1 | 0 | 10.000 | clk_fpga_0 | system_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] | system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] |
|
||||
| src1 | g1 | BSCANE2/TCK | None | BSCAN_X0Y0 | X1Y5 | 1 | 0 | 33.000 | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TCK |
|
||||
| src2 | g2 | LUT6/O | None | SLICE_X90Y146 | X1Y2 | 1 | 0 | | | system_i/dna_port_read_0/inst/read_vld_INST_0/O | system_i/dna_port_read_0/inst/read_vld |
|
||||
+-----------+-----------+-----------------+------------+---------------+--------------+-------------+-----------------+---------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
|
||||
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
------------------------------------------
|
||||
|
||||
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+---------------+--------------+--------------+--------------+--------------+
|
||||
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+-------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+-------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4500 | 0 | 1600 | 0 | 80 | 0 | 40 | 0 | 80 |
|
||||
| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3700 | 0 | 1050 | 0 | 80 | 0 | 40 | 0 | 60 |
|
||||
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4500 | 0 | 1600 | 0 | 80 | 0 | 40 | 0 | 80 |
|
||||
| X1Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3700 | 0 | 1050 | 0 | 80 | 0 | 40 | 0 | 60 |
|
||||
| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 812 | 4500 | 295 | 1600 | 0 | 80 | 0 | 40 | 0 | 80 |
|
||||
| X1Y2 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3700 | 0 | 1050 | 0 | 80 | 0 | 40 | 0 | 60 |
|
||||
| X0Y3 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 14573 | 4500 | 3335 | 1600 | 0 | 80 | 2 | 40 | 0 | 80 |
|
||||
| X1Y3 | 2 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 640 | 3550 | 264 | 1000 | 0 | 70 | 0 | 35 | 0 | 60 |
|
||||
| X0Y4 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 11646 | 4500 | 2311 | 1600 | 0 | 80 | 0 | 40 | 0 | 80 |
|
||||
| X1Y4 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 555 | 4100 | 226 | 1150 | 0 | 100 | 0 | 50 | 0 | 60 |
|
||||
| X0Y5 | 2 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 820 | 3200 | 364 | 1000 | 0 | 40 | 0 | 20 | 0 | 40 |
|
||||
| X1Y5 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3500 | 0 | 1150 | 0 | 100 | 0 | 50 | 0 | 60 |
|
||||
| X0Y6 | 2 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 77 | 3200 | 37 | 1000 | 0 | 40 | 0 | 20 | 0 | 40 |
|
||||
| X1Y6 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 3500 | 0 | 1150 | 0 | 100 | 0 | 50 | 0 | 60 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+-------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
* Global Clock column represents track count; while other columns represents cell counts
|
||||
|
||||
|
||||
5. Clock Regions : Global Clock Summary
|
||||
---------------------------------------
|
||||
|
||||
All Modules
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y6 | 0 | 0 |
|
||||
| Y5 | 0 | 0 |
|
||||
| Y4 | 0 | 0 |
|
||||
| Y3 | 0 | 0 |
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 0 | 0 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
6. Device Cell Placement Summary for Global Clock g0
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------------------+
|
||||
| g0 | BUFG/O | n/a | clk_fpga_0 | 10.000 | {0.000 5.000} | 29180 | 0 | 0 | 0 | system_i/processing_system7_0/inst/FCLK_CLK0 |
|
||||
+-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+--------+------+-----------------------+
|
||||
| | X0 | X1 | HORIZONTAL PROG DELAY |
|
||||
+----+--------+------+-----------------------+
|
||||
| Y6 | 91 | 0 | 0 |
|
||||
| Y5 | 869 | 1 | 0 |
|
||||
| Y4 | 11787 | 557 | 0 |
|
||||
| Y3 | 14575 | 482 | 0 |
|
||||
| Y2 | 818 | 0 | 0 |
|
||||
| Y1 | 0 | 0 | - |
|
||||
| Y0 | 0 | 0 | - |
|
||||
+----+--------+------+-----------------------+
|
||||
|
||||
|
||||
7. Device Cell Placement Summary for Global Clock g1
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+--------------------------------------------------------------------------------------------+-------------+----------------+-------------+----------+----------------+----------+----------------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+--------------------------------------------------------------------------------------------+-------------+----------------+-------------+----------+----------------+----------+----------------------------------------+
|
||||
| g1 | BUFG/O | n/a | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | 33.000 | {0.000 16.500} | 458 | 0 | 0 | 0 | dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i |
|
||||
+-----------+-----------------+-------------------+--------------------------------------------------------------------------------------------+-------------+----------------+-------------+----------+----------------+----------+----------------------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+------+------+-----------------------+
|
||||
| | X0 | X1 | HORIZONTAL PROG DELAY |
|
||||
+----+------+------+-----------------------+
|
||||
| Y6 | 0 | 0 | - |
|
||||
| Y5 | 0 | 0 | - |
|
||||
| Y4 | 0 | 0 | - |
|
||||
| Y3 | 299 | 159 | 0 |
|
||||
| Y2 | 0 | 0 | - |
|
||||
| Y1 | 0 | 0 | - |
|
||||
| Y0 | 0 | 0 | - |
|
||||
+----+------+------+-----------------------+
|
||||
|
||||
|
||||
8. Device Cell Placement Summary for Global Clock g2
|
||||
----------------------------------------------------
|
||||
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------------------------------------+
|
||||
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------------------------------------+
|
||||
| g2 | BUFG/O | n/a | | | | 57 | 0 | 0 | 0 | system_i/dna_port_read_0/inst/read_vld_BUFG |
|
||||
+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------------------------------------+
|
||||
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
|
||||
** IO Loads column represents load cell count of IO types
|
||||
*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
|
||||
**** GT Loads column represents load cell count of GT types
|
||||
|
||||
|
||||
+----+-----+----+-----------------------+
|
||||
| | X0 | X1 | HORIZONTAL PROG DELAY |
|
||||
+----+-----+----+-----------------------+
|
||||
| Y6 | 1 | 0 | 0 |
|
||||
| Y5 | 56 | 0 | 0 |
|
||||
| Y4 | 0 | 0 | - |
|
||||
| Y3 | 0 | 0 | - |
|
||||
| Y2 | 0 | 0 | - |
|
||||
| Y1 | 0 | 0 | - |
|
||||
| Y0 | 0 | 0 | - |
|
||||
+----+-----+----+-----------------------+
|
||||
|
||||
|
||||
9. Clock Region Cell Placement per Global Clock: Region X0Y2
|
||||
------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 818 | 0 | 812 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | system_i/processing_system7_0/inst/FCLK_CLK0 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
10. Clock Region Cell Placement per Global Clock: Region X0Y3
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-------+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-------+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 14575 | 0 | 14274 | 298 | 2 | 0 | 0 | 0 | 0 | 0 | system_i/processing_system7_0/inst/FCLK_CLK0 |
|
||||
| g1 | n/a | BUFG/O | None | 299 | 0 | 299 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-------+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
11. Clock Region Cell Placement per Global Clock: Region X1Y3
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 482 | 0 | 481 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | system_i/processing_system7_0/inst/FCLK_CLK0 |
|
||||
| g1 | n/a | BUFG/O | None | 159 | 0 | 159 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
12. Clock Region Cell Placement per Global Clock: Region X0Y4
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-------+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-------+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 11787 | 0 | 11646 | 141 | 0 | 0 | 0 | 0 | 0 | 0 | system_i/processing_system7_0/inst/FCLK_CLK0 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-------+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
13. Clock Region Cell Placement per Global Clock: Region X1Y4
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 557 | 0 | 555 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | system_i/processing_system7_0/inst/FCLK_CLK0 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
14. Clock Region Cell Placement per Global Clock: Region X0Y5
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 869 | 0 | 820 | 49 | 0 | 0 | 0 | 0 | 0 | 0 | system_i/processing_system7_0/inst/FCLK_CLK0 |
|
||||
| g2 | n/a | BUFG/O | None | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | system_i/dna_port_read_0/inst/read_vld_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
15. Clock Region Cell Placement per Global Clock: Region X1Y5
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | system_i/processing_system7_0/inst/FCLK_CLK0 |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
16. Clock Region Cell Placement per Global Clock: Region X0Y6
|
||||
-------------------------------------------------------------
|
||||
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
| g0 | n/a | BUFG/O | None | 91 | 0 | 77 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | system_i/processing_system7_0/inst/FCLK_CLK0 |
|
||||
| g2 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | system_i/dna_port_read_0/inst/read_vld_BUFG |
|
||||
+-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+----------------------------------------------+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
|
||||
|
||||
|
||||
|
||||
# Location of BUFG Primitives
|
||||
set_property LOC BUFGCTRL_X0Y16 [get_cells system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG]
|
||||
set_property LOC BUFGCTRL_X0Y1 [get_cells system_i/dna_port_read_0/inst/read_vld_BUFG_inst]
|
||||
set_property LOC BUFGCTRL_X0Y0 [get_cells dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck]
|
||||
|
||||
# Location of IO Primitives which is load of clock spine
|
||||
|
||||
# Location of clock ports
|
||||
|
||||
# Clock net "system_i/processing_system7_0/inst/FCLK_CLK0" driven by instance "system_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG" located at site "BUFGCTRL_X0Y16"
|
||||
#startgroup
|
||||
create_pblock {CLKAG_system_i/processing_system7_0/inst/FCLK_CLK0}
|
||||
add_cells_to_pblock [get_pblocks {CLKAG_system_i/processing_system7_0/inst/FCLK_CLK0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="system_i/processing_system7_0/inst/FCLK_CLK0"}]]]
|
||||
resize_pblock [get_pblocks {CLKAG_system_i/processing_system7_0/inst/FCLK_CLK0}] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5}
|
||||
#endgroup
|
||||
|
||||
# Clock net "system_i/dna_port_read_0/inst/read_vld_BUFG" driven by instance "system_i/dna_port_read_0/inst/read_vld_BUFG_inst" located at site "BUFGCTRL_X0Y1"
|
||||
#startgroup
|
||||
create_pblock {CLKAG_system_i/dna_port_read_0/inst/read_vld_BUFG}
|
||||
add_cells_to_pblock [get_pblocks {CLKAG_system_i/dna_port_read_0/inst/read_vld_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="system_i/dna_port_read_0/inst/read_vld_BUFG"}]]]
|
||||
resize_pblock [get_pblocks {CLKAG_system_i/dna_port_read_0/inst/read_vld_BUFG}] -add {CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6}
|
||||
#endgroup
|
||||
|
||||
# Clock net "dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i" driven by instance "dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck" located at site "BUFGCTRL_X0Y0"
|
||||
#startgroup
|
||||
create_pblock {CLKAG_dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i}
|
||||
add_cells_to_pblock [get_pblocks {CLKAG_dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i"}]]]
|
||||
resize_pblock [get_pblocks {CLKAG_dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i}] -add {CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}
|
||||
#endgroup
|
||||
@@ -0,0 +1,933 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Wed May 27 16:41:21 2026
|
||||
| Host : mkb running 64-bit unknown
|
||||
| Command : report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt
|
||||
| Design : system_wrapper
|
||||
| Device : xc7z035
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Control Set Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
2. Histogram
|
||||
3. Flip-Flop Distribution
|
||||
4. Detailed Control Set Information
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+----------------------------------------------------------+-------+
|
||||
| Status | Count |
|
||||
+----------------------------------------------------------+-------+
|
||||
| Total control sets | 855 |
|
||||
| Minimum number of control sets | 855 |
|
||||
| Addition due to synthesis replication | 0 |
|
||||
| Addition due to physical synthesis replication | 0 |
|
||||
| Unused register locations in slices containing registers | 1924 |
|
||||
+----------------------------------------------------------+-------+
|
||||
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
|
||||
** Run report_qor_suggestions for automated merging and remapping suggestions
|
||||
|
||||
|
||||
2. Histogram
|
||||
------------
|
||||
|
||||
+--------------------+-------+
|
||||
| Fanout | Count |
|
||||
+--------------------+-------+
|
||||
| Total control sets | 855 |
|
||||
| >= 0 to < 4 | 30 |
|
||||
| >= 4 to < 6 | 363 |
|
||||
| >= 6 to < 8 | 10 |
|
||||
| >= 8 to < 10 | 22 |
|
||||
| >= 10 to < 12 | 8 |
|
||||
| >= 12 to < 14 | 5 |
|
||||
| >= 14 to < 16 | 0 |
|
||||
| >= 16 | 417 |
|
||||
+--------------------+-------+
|
||||
* Control sets can be remapped at either synth_design or opt_design
|
||||
|
||||
|
||||
3. Flip-Flop Distribution
|
||||
-------------------------
|
||||
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| No | No | No | 19645 | 4064 |
|
||||
| No | No | Yes | 144 | 43 |
|
||||
| No | Yes | No | 2316 | 1091 |
|
||||
| Yes | No | No | 6474 | 1728 |
|
||||
| Yes | No | Yes | 147 | 36 |
|
||||
| Yes | Yes | No | 454 | 113 |
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
|
||||
|
||||
4. Detailed Control Set Information
|
||||
-----------------------------------
|
||||
|
||||
+-----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
|
||||
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
|
||||
+-----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 | 1 | 1 | 1.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.rst_wr_reg2 | 1 | 1 | 1.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | system_i/dna_port_read_0/inst/dna_port[56]_i_2_n_0 | 1 | 1 | 1.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.rst_wr_reg2 | 1 | 1 | 1.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[28]_i_1_n_0 | | 1 | 1 | 1.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/RESET | 1 | 1 | 1.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2 | 1 | 1 | 1.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_rd_req | 1 | 1 | 1.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/O | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/O | 1 | 1 | 1.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/O | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/O | 1 | 1 | 1.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd | 1 | 1 | 1.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/O | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/O | 1 | 1 | 1.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/id_state[1]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/RESET | 1 | 2 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] | 1 | 2 | 2.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst | 1 | 2 | 2.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst | 1 | 2 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst | 1 | 2 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst | 1 | 2 | 2.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp | | 1 | 2 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[1]_i_1_n_0 | | 1 | 2 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst/AS[0] | 1 | 3 | 3.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/icn_cmd_en_temp | | 1 | 3 | 3.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst/AS[0] | 1 | 3 | 3.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp | | 1 | 3 | 3.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/icn_cmd_en_temp | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 1 | 3 | 3.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst/AS[0] | 1 | 3 | 3.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst/AS[0] | 1 | 3 | 3.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_ld_temp_1_reg_n_0 | | 3 | 3 | 1.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_ld_temp_1_reg_n_0 | | 3 | 3 | 1.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 1 | 3 | 3.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[55].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[56].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[57].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[69].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[58].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[54].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[53].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[52].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[51].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[50].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[4].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[49].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[48].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[47].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[46].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[45].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[44].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[43].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[6].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[95].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[79].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[78].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[77].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[76].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[75].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[74].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[73].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[72].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[71].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[70].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[59].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[80].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[68].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[67].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[66].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[65].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[64].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[63].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[62].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[61].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[60].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[5].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[291].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[2].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[29].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[299].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[298].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[297].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[296].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[295].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[294].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[293].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[292].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[300].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[290].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[28].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[289].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[288].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[287].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[286].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[285].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[284].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[283].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[32].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[41].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[40].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[39].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[38].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[37].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[36].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[35].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[34].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[33].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[42].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[31].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[30].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[307].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[306].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[305].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[304].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[303].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[302].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[301].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[8].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[102].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[101].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[100].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[0].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/CNT.CNT_SRL[2].cnt_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/CNT.CNT_SRL[1].cnt_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/CNT.CNT_SRL[0].cnt_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_srl_fff/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[9].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[103].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[7].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[6].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[5].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[4].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[3].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[31].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[30].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[2].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[29].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/FSM_sequential_state_reg[1]_1[0] | | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/drdyCount[5]_i_2_n_0 | u_ila_0/inst/ila_core_inst/u_ila_regs/drdyCount[5]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_ld_temp_1 | | 4 | 4 | 1.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/SR[0] | 1 | 4 | 4.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/SYNC_reg | 1 | 4 | 4.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[17]_0[0] | 1 | 4 | 4.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/icn_cmd_en_temp | | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/FSM_sequential_state_reg[1]_1[0] | | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/E[0] | | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/E[0] | | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[28].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[111].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[110].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[10].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[109].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[108].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[107].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[106].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[105].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[104].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[90].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[9].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[99].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[98].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[97].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[96].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b.b_pipe/aresetn_d_reg[1]_inv_0 | 3 | 4 | 1.33 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[94].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[93].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[92].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[91].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/STRG_QUAL.qual_strg_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[89].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[88].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[87].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[86].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[85].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[84].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[83].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[82].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[18].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[27].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[26].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[25].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[24].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[23].tc_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[22].tc_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[21].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[20].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[1].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[19].tc_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[81].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[17].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[16].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[15].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[14].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[13].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[12].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[11].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[10].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[0].tc_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[164].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[174].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[173].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[172].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[171].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[170].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[16].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[169].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[168].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[167].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[166].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[165].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[175].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[163].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[162].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[161].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[160].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[15].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[159].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[158].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[157].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[156].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[155].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[154].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[186].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[196].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[195].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[194].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[193].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[192].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[191].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[190].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[18].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[189].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[188].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[187].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[153].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[185].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[184].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[183].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[182].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[181].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[180].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[17].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[179].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[178].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[177].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[176].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[120].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[130].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[12].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[129].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[128].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[127].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[126].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[125].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[124].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[123].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[122].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[121].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[131].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[119].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[118].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[117].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[116].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[115].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[114].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[113].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[112].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/aresetn_d_reg[0]_0 | 3 | 4 | 1.33 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | system_i/rst_ps7_0_100M/U0/EXT_LPF/lpf_int | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[142].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[152].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[151].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[150].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[14].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[149].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[148].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[147].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[146].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[145].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[144].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[143].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[281].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[141].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[140].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[13].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[139].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[138].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[137].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[136].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[135].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[134].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[133].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[132].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[248].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[259].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[258].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[257].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[256].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[255].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[254].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[253].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[252].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[251].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[250].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[24].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[249].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[25].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[247].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[246].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[245].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[244].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[243].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[242].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[241].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[240].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[23].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[239].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[238].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[237].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[271].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[282].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[280].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[27].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[279].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[197].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[278].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[277].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[276].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[275].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[274].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[273].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[272].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[198].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[270].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[26].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[269].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[268].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[267].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[266].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[265].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[264].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[263].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[262].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[261].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[260].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[214].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[221].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[220].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[19].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[1].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[21].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[236].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[219].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[200].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[218].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[217].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[216].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[201].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[215].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[235].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[213].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[212].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[202].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[203].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[204].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[211].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[210].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[205].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[20].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[209].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[208].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[207].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[206].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[223].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[232].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[231].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[230].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[22].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[229].mu_srl_reg/cnt[3]_i_1_n_0 | 1 | 4 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[228].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[227].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[233].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[226].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[225].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[224].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[234].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[222].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[199].mu_srl_reg/cnt[3]_i_1_n_0 | 2 | 4 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/cnt_read[4]_i_1_n_0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 1 | 5 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/drdy_ff9 | u_ila_0/inst/ila_core_inst/u_ila_regs/shift_reg00 | 2 | 5 | 2.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/E[0] | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 2 | 5 | 2.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/I_YESLUT6.I_YES_OREG.O_reg_reg | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/I_YESLUT6.I_YES_OREG.O_reg_reg_0 | 2 | 6 | 3.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_reset_ctrl/reset_out[5]_i_1_n_0 | 4 | 6 | 1.50 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/SR[0] | 1 | 6 | 6.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SEL | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/RESET | 2 | 6 | 3.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/rst_ps7_0_100M/U0/SEQ/seq_cnt_en | system_i/rst_ps7_0_100M/U0/SEQ/SEQ_COUNTER/clear | 1 | 6 | 6.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/ADV_TRIG.u_adv_trig/bram_addr[6]_i_1_n_0 | | 2 | 7 | 3.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/s_do_o[0] | 2 | 7 | 3.50 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_STATIC_STATUS/clear | 2 | 7 | 3.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/xsdb_rden_ffa | u_ila_0/inst/ila_core_inst/u_ila_regs/count10 | 2 | 7 | 3.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/xsdb_rden_ff9 | u_ila_0/inst/ila_core_inst/u_ila_regs/count00 | 2 | 7 | 3.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/timer_rst | 3 | 8 | 2.67 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/slv_reg3[7]_i_1_n_0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/axi_awready_i_1_n_0 | 1 | 8 | 8.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/counter[7]_i_1_n_0 | 3 | 8 | 2.67 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_SYNC/iSYNC_WORD[6]_i_1_n_0 | 1 | 8 | 8.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/ADV_TRIG_MEM_READ.u_fsm_memory_read_inst/E[0] | | 3 | 8 | 2.67 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/p_1_in[31] | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/slv_reg0[0]_i_1_n_0 | 1 | 8 | 8.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/slv_reg3[31]_i_1_n_0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/axi_awready_i_1_n_0 | 1 | 8 | 8.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/E[0] | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] | 2 | 8 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/p_1_in[15] | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/slv_reg0[0]_i_1_n_0 | 1 | 8 | 8.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/p_1_in[23] | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/slv_reg0[0]_i_1_n_0 | 1 | 8 | 8.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/slv_reg3[23]_i_1_n_0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/axi_awready_i_1_n_0 | 2 | 8 | 4.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] | 2 | 8 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/slv_reg3[15]_i_1_n_0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/axi_awready_i_1_n_0 | 1 | 8 | 8.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/ADV_TRIG_MEM_READ.u_fsm_memory_read_inst/CFG_DATA_O[15]_i_1_n_0 | 2 | 8 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/I_YESLUT6.I_YES_OREG.O_reg_reg | u_ila_0/inst/ila_core_inst/ADV_TRIG.u_adv_trig/SEQUENCER_STATE_O[7]_i_1_n_0 | 2 | 8 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/I_YESLUT6.I_YES_OREG.O_reg_reg | u_ila_0/inst/ila_core_inst/u_ila_reset_ctrl/dout_reg1_reg_0 | 1 | 8 | 8.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/mhandshake_r | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/SR[0] | 3 | 8 | 2.67 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/p_1_in[7] | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/slv_reg0[0]_i_1_n_0 | 1 | 8 | 8.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/dna_port_read_0/inst/start_flag | system_i/dna_port_read_0/inst/dna_port[56]_i_2_n_0 | 3 | 8 | 2.67 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/slaveRegDo_mux_2[15]_i_1_n_0 | 6 | 9 | 1.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/slaveRegDo_mux_0[15]_i_1_n_0 | 5 | 9 | 1.80 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/sel | u_ila_0/inst/ila_core_inst/u_ila_regs/clk_lost_cnt[7]_i_1_n_0 | 3 | 9 | 3.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[2] | 2 | 10 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/xsdb_memory_read_inst/read_addr0 | | 3 | 10 | 3.33 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/axi_awready_i_1_n_0 | 3 | 10 | 3.33 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_reset_ctrl/reset_out_reg[0]_0[0] | | 2 | 10 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 4 | 10 | 2.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/O | u_ila_0/inst/ila_core_inst/u_ila_reset_ctrl/Q[0] | 2 | 10 | 5.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_CE | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n | 2 | 10 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/O | u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/O | 2 | 10 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b.b_pipe/s_ready_i_reg_0 | | 2 | 12 | 6.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b.b_pipe/p_1_in | | 2 | 12 | 6.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[1] | 2 | 12 | 6.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[1] | 2 | 12 | 6.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/r_push_r | | 4 | 13 | 3.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_regs/slaveRegDo_mux_3[15]_i_1_n_0 | 7 | 16 | 2.29 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/ADV_TRIG_STREAM.reg_stream_ffc/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 3 | 16 | 5.33 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/E[0] | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst | 4 | 16 | 4.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_reg[6][0] | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst | 2 | 16 | 8.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 2 | 16 | 8.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0][0] | | 3 | 16 | 5.33 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/E[0] | | 4 | 16 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/cnt_read_reg[0] | | 3 | 16 | 5.33 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_82/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 3 | 16 | 5.33 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[1] | 3 | 16 | 5.33 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[1] | 3 | 16 | 5.33 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_81/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 3 | 16 | 5.33 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/adv_rb_drdy1 | | 4 | 16 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 5 | 16 | 3.20 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_85/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 6 | 16 | 2.67 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_84/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 4 | 16 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_83/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 4 | 16 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/ADV_TRIG_MEM_READ.u_fsm_memory_read_inst/BRAM_DATA[15]_i_1_n_0 | | 4 | 16 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/xsdb_memory_read_inst/EN_O | | 9 | 16 | 1.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/reg_test0 | | 2 | 16 | 8.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 6 | 16 | 2.67 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_16/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 6 | 16 | 2.67 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 6 | 16 | 2.67 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_18/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 6 | 16 | 2.67 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_19/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 4 | 16 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 5 | 16 | 3.20 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_6/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 6 | 16 | 2.67 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 7 | 16 | 2.29 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_80/I_EN_CTL_EQ1.U_CTL/xsdb_reg[15]_i_1_n_0 | | 5 | 16 | 3.20 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/COUNTER.u_count/G_COUNTER[3].U_COUNTER/counter[16]_i_1_n_0 | | 5 | 17 | 3.40 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BURST_WD_LEN_CONTROLLER/burst_wd[0]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 5 | 17 | 3.40 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/COUNTER.u_count/G_COUNTER[0].U_COUNTER/counter[16]_i_1_n_0 | | 5 | 17 | 3.40 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/COUNTER.u_count/G_COUNTER[1].U_COUNTER/counter[16]_i_1_n_0 | | 5 | 17 | 3.40 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_iport0_o[0] | 10 | 17 | 1.70 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/COUNTER.u_count/G_COUNTER[2].U_COUNTER/counter[16]_i_1_n_0 | | 5 | 17 | 3.40 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr[16]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 5 | 17 | 3.40 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/m_valid_i_reg[0] | | 7 | 18 | 2.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg[17]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 3 | 18 | 6.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/m_valid_i_reg_1[0] | | 7 | 18 | 2.57 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/icn_cmd_en_temp | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 3 | 18 | 6.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[0] | 4 | 18 | 4.50 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[0] | 3 | 18 | 6.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/drdy_ffa | u_ila_0/inst/ila_core_inst/u_ila_regs/shift_reg10 | 4 | 20 | 5.00 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 3 | 24 | 8.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 3 | 24 | 8.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[45].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[41].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[40].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[39].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[38].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[37].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[36].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[35].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[34].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[33].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[32].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[31].mu_srl_reg/shift_en_o | | 15 | 25 | 1.67 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[30].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[42].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[43].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[44].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[46].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[47].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[48].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[49].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[4].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[50].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[51].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[52].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[53].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[54].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[55].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[56].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[57].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[293].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[280].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[281].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[282].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[283].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[284].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[285].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[286].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[287].mu_srl_reg/shift_en_o | | 11 | 25 | 2.27 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[288].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[289].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[28].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[290].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[291].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[27].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[292].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[307].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[294].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[295].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[296].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[297].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[298].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[299].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[29].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[2].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[300].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[301].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[302].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[303].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[304].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[305].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[306].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[119].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[87].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[88].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[89].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[90].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[91].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[92].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[93].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[94].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[95].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[96].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[97].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[98].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[99].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[9].mu_srl_reg/shift_en_o | | 13 | 25 | 1.92 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[86].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[0].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[100].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[101].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[102].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[103].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[104].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[105].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[106].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[107].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[108].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[109].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[10].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[110].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[111].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[72].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[59].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[5].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[60].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[61].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[62].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[63].mu_srl_reg/shift_en_o | | 12 | 25 | 2.08 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[64].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[65].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[66].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[67].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[68].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[69].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[6].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[70].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[71].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[58].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[73].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[74].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[75].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[76].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[77].mu_srl_reg/shift_en_o | | 11 | 25 | 2.27 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[78].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[79].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[80].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[81].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[82].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[83].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[84].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[85].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[12].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[120].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[121].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[122].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[123].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[124].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[125].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[126].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[127].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[128].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[129].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[118].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[130].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[131].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[132].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[133].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[134].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[135].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[136].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[137].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[138].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[180].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[184].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[195].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[193].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[192].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[191].mu_srl_reg/shift_en_o | | 11 | 25 | 2.27 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[190].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[18].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[189].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[188].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[187].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[186].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[185].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[139].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[183].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[182].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[181].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[279].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[112].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[113].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[114].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[115].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[116].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[117].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[150].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[15].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[159].mu_srl_reg/shift_en_o | | 11 | 25 | 2.27 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[158].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[157].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[156].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[155].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[154].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[153].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[152].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[151].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[140].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[160].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[14].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[149].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[148].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[147].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[146].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[145].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[144].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[141].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[142].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[143].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[16].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[17].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[179].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[178].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[177].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[176].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[175].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[174].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[173].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[172].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[171].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[170].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[194].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[169].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[168].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[13].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[167].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[166].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[165].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[164].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[163].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[162].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[161].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[245].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[256].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[255].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[254].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[253].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[252].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[251].mu_srl_reg/shift_en_o | | 10 | 25 | 2.50 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[250].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[24].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[249].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[248].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[247].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[246].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[257].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[244].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[243].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[242].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[241].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[240].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[23].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[239].mu_srl_reg/shift_en_o | | 11 | 25 | 2.27 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[238].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[237].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[236].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[235].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[268].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[278].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[277].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[276].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[275].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[274].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[273].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[272].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[271].mu_srl_reg/shift_en_o | | 15 | 25 | 1.67 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[270].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[26].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[269].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[234].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[267].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[266].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[265].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[264].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[263].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[262].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[261].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[260].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[25].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[259].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[258].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[205].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[214].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[213].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[196].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[211].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[210].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[20].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[209].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[208].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[207].mu_srl_reg/shift_en_o | | 12 | 25 | 2.08 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[206].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[212].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[204].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[203].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[202].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[201].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[200].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[1].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[19].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[199].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[198].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[197].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[223].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[233].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[232].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[231].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[230].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[22].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[229].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[228].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[227].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[226].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[225].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[224].mu_srl_reg/shift_en_o | | 9 | 25 | 2.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[215].mu_srl_reg/shift_en_o | | 6 | 25 | 4.17 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[222].mu_srl_reg/shift_en_o | | 11 | 25 | 2.27 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[221].mu_srl_reg/shift_en_o | | 7 | 25 | 3.57 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[220].mu_srl_reg/shift_en_o | | 8 | 25 | 3.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[21].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[219].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[218].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[217].mu_srl_reg/shift_en_o | | 4 | 25 | 6.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[216].mu_srl_reg/shift_en_o | | 5 | 25 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/s_ready_i_reg_0 | | 4 | 27 | 6.75 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/m_valid_i_reg_2[0] | | 4 | 27 | 6.75 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/s_ready_i_reg_0 | | 4 | 27 | 6.75 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/FSM_sequential_state_reg[1]_2[0] | | 4 | 27 | 6.75 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 4 | 28 | 7.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg[27]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 7 | 28 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/ADV_TRIG.u_adv_trig/CFG_BRAM_RD_DATA[23]_i_1_n_0 | | 5 | 31 | 6.20 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[28]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1_n_0 | 7 | 31 | 4.43 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_reset_ctrl/Q[3] | 9 | 32 | 3.56 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0 | 11 | 32 | 2.91 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/wr_en0 | | 8 | 32 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/slv_reg_rden__0 | system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/axi_awready_i_1_n_0 | 10 | 32 | 3.20 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/RESET | 9 | 32 | 3.56 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/shift_en_o | | 9 | 34 | 3.78 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[1]_i_1_n_0 | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/RESET | 13 | 34 | 2.62 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/CNT.CNT_SRL[0].cnt_srl_reg/shift_en_o | | 8 | 34 | 4.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/CNT.CNT_SRL[1].cnt_srl_reg/shift_en_o | | 8 | 34 | 4.25 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/CNT.CNT_SRL[2].cnt_srl_reg/shift_en_o | | 9 | 34 | 3.78 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg[0] | 14 | 41 | 2.93 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/p_1_in | | 9 | 45 | 5.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/s_ready_i_reg_0 | | 7 | 45 | 6.43 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_den_o | | 16 | 53 | 3.31 |
|
||||
| system_i/dna_port_read_0/inst/read_vld_BUFG | | | 19 | 57 | 3.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | system_i/dna_port_read_0/inst/dna_shift | system_i/dna_port_read_0/inst/dna_port[56]_i_2_n_0 | 17 | 57 | 3.35 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | | | 20 | 63 | 3.15 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg_r1_0_63_0_2_i_1_n_0 | | 16 | 64 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg_r1_64_127_0_2_i_1_n_0 | | 16 | 64 | 4.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_reset_ctrl/Q[2] | 33 | 66 | 2.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/reg_srl_fff/shift_en_o | | 25 | 103 | 4.12 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[10].tc_srl_reg/shift_en_o | | 47 | 329 | 7.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[11].tc_srl_reg/shift_en_o | | 47 | 329 | 7.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[12].tc_srl_reg/shift_en_o | | 43 | 329 | 7.65 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/STRG_QUAL.qual_strg_srl_reg/shift_en_o | | 42 | 329 | 7.83 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[0].tc_srl_reg/shift_en_o | | 47 | 329 | 7.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[13].tc_srl_reg/shift_en_o | | 43 | 329 | 7.65 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[14].tc_srl_reg/shift_en_o | | 43 | 329 | 7.65 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[15].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[16].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[17].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[28].tc_srl_reg/shift_en_o | | 45 | 329 | 7.31 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[9].tc_srl_reg/shift_en_o | | 45 | 329 | 7.31 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[8].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[7].tc_srl_reg/shift_en_o | | 45 | 329 | 7.31 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[6].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[5].tc_srl_reg/shift_en_o | | 43 | 329 | 7.65 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[4].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[3].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[31].tc_srl_reg/shift_en_o | | 47 | 329 | 7.00 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[30].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[2].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[29].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[18].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[27].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[26].tc_srl_reg/shift_en_o | | 45 | 329 | 7.31 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[25].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[24].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[23].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[22].tc_srl_reg/shift_en_o | | 44 | 329 | 7.48 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[21].tc_srl_reg/shift_en_o | | 43 | 329 | 7.65 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[20].tc_srl_reg/shift_en_o | | 43 | 329 | 7.65 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[1].tc_srl_reg/shift_en_o | | 45 | 329 | 7.31 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | u_ila_0/inst/ila_core_inst/u_ila_regs/TC_SRL[19].tc_srl_reg/shift_en_o | | 43 | 329 | 7.65 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | u_ila_0/inst/ila_core_inst/u_ila_reset_ctrl/Q[0] | 314 | 640 | 2.04 |
|
||||
| system_i/processing_system7_0/inst/FCLK_CLK0 | | | 4026 | 19606 | 4.87 |
|
||||
+-----------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
|
||||
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,35 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Wed May 27 16:40:22 2026
|
||||
| Host : mkb running 64-bit unknown
|
||||
| Command : report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx
|
||||
| Design : system_wrapper
|
||||
| Device : xc7z035ffg676-2
|
||||
| Speed File : -2
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 0
|
||||
+------+----------+-------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+------+----------+-------------+------------+
|
||||
+------+----------+-------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,72 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Wed May 27 16:42:30 2026
|
||||
| Host : mkb running 64-bit unknown
|
||||
| Command : report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx
|
||||
| Design : system_wrapper
|
||||
| Device : xc7z035ffg676-2
|
||||
| Speed File : -2
|
||||
| Design State : Fully Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 4
|
||||
+-----------+----------+-------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+----------+-------------------------+------------+
|
||||
| PDCN-1569 | Warning | LUT equation term check | 3 |
|
||||
| RTSTAT-10 | Warning | No routable loads | 1 |
|
||||
+-----------+----------+-------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
PDCN-1569#1 Warning
|
||||
LUT equation term check
|
||||
Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I0) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
||||
Related violations: <none>
|
||||
|
||||
PDCN-1569#2 Warning
|
||||
LUT equation term check
|
||||
Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1/I0) is not included in the LUT equation: 'O6=(A6+~A6)*((A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
||||
Related violations: <none>
|
||||
|
||||
PDCN-1569#3 Warning
|
||||
LUT equation term check
|
||||
Used physical LUT pin 'A5' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I1) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue.
|
||||
Related violations: <none>
|
||||
|
||||
RTSTAT-10#1 Warning
|
||||
No routable loads
|
||||
21 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1],
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i,
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i,
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow,
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2],
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i,
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow,
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0],
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2],
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0],
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1],
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TMS,
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0],
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0],
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0]
|
||||
(the first 15 of 19 listed nets/buses).
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,718 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Wed May 27 16:41:20 2026
|
||||
| Host : mkb running 64-bit unknown
|
||||
| Command : report_io -file system_wrapper_io_placed.rpt
|
||||
| Design : system_wrapper
|
||||
| Device : xc7z035
|
||||
| Speed File : -2
|
||||
| Package : ffg676
|
||||
| Package Version : FINAL 2012-10-23
|
||||
| Package Pin Delay Version : VERS. 2.0 2012-10-23
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
IO Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
2. IO Assignments by Package Pin
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+---------------+
|
||||
| Total User IO |
|
||||
+---------------+
|
||||
| 163 |
|
||||
+---------------+
|
||||
|
||||
|
||||
2. IO Assignments by Package Pin
|
||||
--------------------------------
|
||||
|
||||
+------------+-------------------+------------------+-------------------------+---------------+-------------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
|
||||
+------------+-------------------+------------------+-------------------------+---------------+-------------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A2 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| A3 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| A4 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| A5 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| A6 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| A7 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| A8 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| A9 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| A10 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A12 | | High Performance | IO_L24N_T3_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A13 | | High Performance | IO_L24P_T3_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A14 | | High Performance | IO_L21N_T3_DQS_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A15 | | High Performance | IO_L21P_T3_DQS_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A16 | | High Performance | VCCO_35 | VCCO | | 35 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| A17 | | High Performance | IO_L18N_T2_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| A18 | FIXED_IO_mio[49] | | PS_MIO49_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| A19 | FIXED_IO_mio[53] | | PS_MIO53_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| A20 | FIXED_IO_mio[52] | | PS_MIO52_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| A21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A22 | FIXED_IO_ps_srstb | | PS_SRST_B_501 | BIDIR | LVCMOS18 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A23 | FIXED_IO_mio[12] | | PS_MIO12_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A24 | FIXED_IO_mio[8] | | PS_MIO8_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | |
|
||||
| A25 | FIXED_IO_mio[10] | | PS_MIO10_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| A26 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| AA1 | | | MGTXTXN0_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AA2 | | | MGTXTXP0_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AA3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA4 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AA5 | | | MGTREFCLK1N_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AA6 | | | MGTREFCLK1P_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AA7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AA9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA10 | | High Range | IO_L3N_T0_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AA11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA12 | EMIO_0_tri_io[23] | High Range | IO_L6N_T0_VREF_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA13 | EMIO_0_tri_io[25] | High Range | IO_L6P_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA14 | | High Range | IO_L22N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AA15 | | High Range | IO_L22P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AA16 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AA17 | | High Range | IO_L19N_T3_VREF_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AA18 | | High Range | IO_L24N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AA19 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AA20 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AA21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA22 | EMIO_0_tri_io[10] | High Range | IO_L10P_T1_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA23 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AA24 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AA25 | EMIO_0_tri_io[16] | High Range | IO_L1P_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AA26 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| AB1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AB3 | | | MGTXRXN0_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AB4 | | | MGTXRXP0_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AB5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AB7 | | | MGTAVTTRCAL_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AB8 | | | MGTRREF_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB10 | | High Range | IO_L4N_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB11 | | High Range | IO_L4P_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB12 | | High Range | IO_L2P_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB13 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AB14 | | High Range | IO_L14N_T2_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB15 | | High Range | IO_L14P_T2_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB16 | | High Range | IO_L20N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB17 | | High Range | IO_L20P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB19 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AB20 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AB21 | EMIO_0_tri_io[0] | High Range | IO_L9P_T1_DQS_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB22 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AB23 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| AB24 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AB25 | EMIO_0_tri_io[11] | High Range | IO_L1N_T0_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AB26 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AC1 | | | MGTXTXN3_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AC2 | | | MGTXTXP3_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AC3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AC5 | | | MGTXRXN2_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AC6 | | | MGTXRXP2_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AC7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AC9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC10 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AC11 | | High Range | IO_L2N_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AC12 | | High Range | IO_L11P_T1_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AC13 | | High Range | IO_L12P_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AC14 | | High Range | IO_L13P_T2_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AC15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC16 | | High Range | IO_L21N_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AC17 | | High Range | IO_L21P_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AC18 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AC19 | | High Range | IO_L21N_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AC20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| AC21 | EMIO_0_tri_io[19] | High Range | IO_L14P_T2_SRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC22 | EMIO_0_tri_io[20] | High Range | IO_L14N_T2_SRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC23 | EMIO_0_tri_io[15] | High Range | IO_L12P_T1_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC24 | EMIO_0_tri_io[18] | High Range | IO_L12N_T1_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AC25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC26 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AD1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AD3 | | | MGTXRXN3_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AD4 | | | MGTXRXP3_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AD5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AD7 | | | MGTXRXN0_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AD8 | | | MGTXRXP0_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AD9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD10 | EMIO_0_tri_io[22] | High Range | IO_L7N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD11 | | High Range | IO_L11N_T1_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AD12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD13 | | High Range | IO_L12N_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AD14 | | High Range | IO_L13N_T2_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AD15 | | High Range | IO_L15N_T2_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AD16 | | High Range | IO_L15P_T2_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AD17 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AD18 | EMIO_0_tri_io[8] | High Range | IO_L17P_T2_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD19 | EMIO_0_tri_io[9] | High Range | IO_L17N_T2_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD20 | EMIO_0_tri_io[13] | High Range | IO_L13P_T2_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD21 | EMIO_0_tri_io[14] | High Range | IO_L13N_T2_MRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD23 | EMIO_0_tri_io[12] | High Range | IO_L11P_T1_SRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD24 | EMIO_0_tri_io[17] | High Range | IO_L11N_T1_SRCC_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AD25 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AD26 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AE1 | | | MGTXTXN2_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AE2 | | | MGTXTXP2_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AE3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AE5 | | | MGTXRXN1_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AE6 | | | MGTXRXP1_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AE7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE8 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AE9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE10 | EMIO_0_tri_io[31] | High Range | IO_L7P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE11 | EMIO_0_tri_io[29] | High Range | IO_L9P_T1_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE12 | EMIO_0_tri_io[26] | High Range | IO_L8P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE13 | EMIO_0_tri_io[27] | High Range | IO_L10P_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE14 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AE15 | | High Range | IO_L17N_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AE16 | | High Range | IO_L17P_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AE17 | | High Range | IO_L18P_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AE18 | EMIO_0_tri_io[3] | High Range | IO_L18P_T2_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE20 | EMIO_0_tri_io[7] | High Range | IO_L16P_T2_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE21 | EMIO_0_tri_io[6] | High Range | IO_L16N_T2_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AE22 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AE23 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AE24 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| AE25 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AE26 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AF1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AF3 | | | MGTXTXN1_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF4 | | | MGTXTXP1_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF6 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| AF7 | | | MGTXTXN0_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF8 | | | MGTXTXP0_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| AF9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF10 | EMIO_0_tri_io[30] | High Range | IO_L9N_T1_DQS_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF11 | | High Range | VCCO_12 | VCCO | | 12 | | | | | 3.30 | | | | | | | | |
|
||||
| AF12 | EMIO_0_tri_io[24] | High Range | IO_L8N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF13 | EMIO_0_tri_io[28] | High Range | IO_L10N_T1_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF14 | | High Range | IO_L16N_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AF15 | | High Range | IO_L16P_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AF16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF17 | | High Range | IO_L18N_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AF18 | EMIO_0_tri_io[4] | High Range | IO_L18N_T2_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF19 | EMIO_0_tri_io[5] | High Range | IO_L15P_T2_DQS_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF20 | EMIO_0_tri_io[21] | High Range | IO_L15N_T2_DQS_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| AF21 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| AF22 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AF23 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AF24 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AF25 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| AF26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B1 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| B2 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| B3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| B4 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| B5 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| B6 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| B7 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| B8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B9 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| B10 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| B11 | | High Performance | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B12 | | High Performance | IO_L22N_T3_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B13 | | High Performance | VCCO_35 | VCCO | | 35 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| B14 | | High Performance | IO_L20N_T3_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B15 | | High Performance | IO_L17N_T2_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B16 | | High Performance | IO_L17P_T2_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B17 | | High Performance | IO_L18P_T2_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| B18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B19 | FIXED_IO_mio[47] | | PS_MIO47_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| B20 | FIXED_IO_mio[51] | | PS_MIO51_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B21 | FIXED_IO_mio[48] | | PS_MIO48_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| B22 | FIXED_IO_mio[50] | | PS_MIO50_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B23 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| B24 | FIXED_IO_ps_clk | | PS_CLK_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B25 | FIXED_IO_mio[13] | | PS_MIO13_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| B26 | FIXED_IO_mio[11] | | PS_MIO11_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C1 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| C2 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| C3 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| C4 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C6 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| C7 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| C8 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| C9 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| C10 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| C11 | | High Performance | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C12 | | High Performance | IO_L22P_T3_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C13 | | High Performance | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C14 | | High Performance | IO_L20P_T3_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C16 | | High Performance | IO_L15N_T2_DQS_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C17 | | High Performance | IO_L15P_T2_DQS_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| C18 | FIXED_IO_mio[45] | | PS_MIO45_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| C19 | FIXED_IO_mio[41] | | PS_MIO41_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| C20 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| C21 | FIXED_IO_mio[39] | | PS_MIO39_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C22 | FIXED_IO_mio[40] | | PS_MIO40_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| C23 | FIXED_IO_ps_porb | | PS_POR_B_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C24 | FIXED_IO_mio[15] | | PS_MIO15_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| C25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C26 | FIXED_IO_mio[5] | | PS_MIO5_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | |
|
||||
| D1 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| D2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D3 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| D4 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| D5 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| D6 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| D7 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| D8 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| D9 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| D10 | | High Performance | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D11 | | High Performance | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D13 | | High Performance | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D14 | | High Performance | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D15 | | High Performance | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D16 | | High Performance | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| D17 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| D18 | FIXED_IO_mio[43] | | PS_MIO43_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| D19 | FIXED_IO_mio[35] | | PS_MIO35_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D20 | FIXED_IO_mio[37] | | PS_MIO37_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D21 | FIXED_IO_mio[38] | | PS_MIO38_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D23 | FIXED_IO_mio[14] | | PS_MIO14_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D24 | FIXED_IO_mio[9] | | PS_MIO9_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| D25 | FIXED_IO_mio[3] | | PS_MIO3_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | |
|
||||
| D26 | FIXED_IO_mio[1] | | PS_MIO1_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| E1 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| E2 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| E3 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| E4 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| E5 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| E6 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| E7 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| E8 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E10 | | High Performance | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E11 | | High Performance | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E12 | | High Performance | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E13 | | High Performance | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E14 | | High Performance | VCCO_35 | VCCO | | 35 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| E15 | | High Performance | IO_L14N_T2_AD4N_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E16 | | High Performance | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| E17 | FIXED_IO_mio[46] | | PS_MIO46_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| E18 | FIXED_IO_mio[44] | | PS_MIO44_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| E19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E20 | FIXED_IO_mio[29] | | PS_MIO29_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E21 | FIXED_IO_mio[31] | | PS_MIO31_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E22 | FIXED_IO_mio[33] | | PS_MIO33_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E23 | FIXED_IO_mio[7] | | PS_MIO7_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| E24 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| E25 | FIXED_IO_mio[2] | | PS_MIO2_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | |
|
||||
| E26 | FIXED_IO_mio[0] | | PS_MIO0_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| F1 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| F2 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| F3 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| F4 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| F5 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| F6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F7 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| F8 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| F9 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| F10 | | High Performance | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F11 | | High Performance | VCCO_35 | VCCO | | 35 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| F12 | | High Performance | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F13 | | High Performance | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F14 | | High Performance | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F15 | | High Performance | IO_L14P_T2_AD4P_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| F16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F17 | FIXED_IO_mio[42] | | PS_MIO42_501 | INOUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| F18 | FIXED_IO_mio[27] | | PS_MIO27_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| F19 | FIXED_IO_mio[25] | | PS_MIO25_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| F20 | FIXED_IO_mio[23] | | PS_MIO23_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| F21 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| F22 | FIXED_IO_mio[21] | | PS_MIO21_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| F23 | FIXED_IO_mio[6] | | PS_MIO6_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | |
|
||||
| F24 | FIXED_IO_mio[4] | | PS_MIO4_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | |
|
||||
| F25 | DDR_dq[1] | | PS_DDR_DQ1_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| F26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G1 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| G2 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| G3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G4 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| G5 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| G6 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| G7 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| G8 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| G9 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| G10 | | High Performance | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G11 | | High Performance | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G12 | | High Performance | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G14 | | High Performance | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G15 | | High Performance | IO_L10N_T1_AD11N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G16 | | High Performance | IO_L10P_T1_AD11P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| G17 | FIXED_IO_mio[17] | | PS_MIO17_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| G18 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| G19 | FIXED_IO_mio[19] | | PS_MIO19_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| G20 | FIXED_IO_mio[18] | | PS_MIO18_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| G21 | FIXED_IO_mio[16] | | PS_MIO16_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| G22 | FIXED_IO_mio[22] | | PS_MIO22_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| G23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G24 | DDR_dm[0] | | PS_DDR_DM0_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| G25 | DDR_dqs_n[0] | | PS_DDR_DQS_N0_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| G26 | DDR_dq[3] | | PS_DDR_DQ3_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| H1 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| H2 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| H3 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| H4 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| H5 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| H6 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| H7 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| H8 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| H9 | | High Performance | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| H10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H11 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| H12 | | High Performance | IO_L7N_T1_AD2N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H13 | | High Performance | IO_L7P_T1_AD2P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H14 | | High Performance | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H15 | | High Performance | VCCO_35 | VCCO | | 35 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| H16 | | High Performance | IO_0_VRN_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| H17 | FIXED_IO_mio[26] | | PS_MIO26_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| H18 | | | PS_MIO_VREF_501 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| H19 | FIXED_IO_mio[20] | | PS_MIO20_501 | OUT | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| H20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H21 | DDR_addr[11] | | PS_DDR_A11_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| H22 | DDR_reset_n | | PS_DDR_DRST_B_502 | INOUT | SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| H23 | DDR_dq[5] | | PS_DDR_DQ5_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| H24 | DDR_dqs_p[0] | | PS_DDR_DQS_P0_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| H25 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| H26 | DDR_dq[4] | | PS_DDR_DQ4_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| J1 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| J2 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| J3 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| J4 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| J5 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| J6 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| J7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J8 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| J9 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| J10 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| J11 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| J12 | | High Performance | VCCO_35 | VCCO | | 35 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| J13 | | High Performance | IO_L8N_T1_AD10N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J14 | | High Performance | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J15 | | High Performance | IO_L9N_T1_DQS_AD3N_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| J16 | FIXED_IO_mio[34] | | PS_MIO34_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| J17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J18 | FIXED_IO_mio[28] | | PS_MIO28_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| J19 | FIXED_IO_mio[24] | | PS_MIO24_501 | IN | LVCMOS18 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | |
|
||||
| J20 | DDR_addr[13] | | PS_DDR_A13_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| J21 | DDR_addr[7] | | PS_DDR_A7_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| J22 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| J23 | DDR_dq[7] | | PS_DDR_DQ7_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| J24 | DDR_dq[6] | | PS_DDR_DQ6_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| J25 | DDR_dq[2] | | PS_DDR_DQ2_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| J26 | DDR_dq[0] | | PS_DDR_DQ0_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| K1 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| K2 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| K3 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| K4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K5 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| K6 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| K7 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| K8 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| K9 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| K10 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| K11 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| K12 | | High Performance | IO_25_VRP_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K13 | | High Performance | IO_L8P_T1_AD10P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K15 | | High Performance | IO_L9P_T1_DQS_AD3P_35 | User IO | | 35 | | | | | | | | | | | | | |
|
||||
| K16 | FIXED_IO_mio[36] | | PS_MIO36_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| K17 | FIXED_IO_mio[32] | | PS_MIO32_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| K18 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| K19 | FIXED_IO_mio[30] | | PS_MIO30_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| K20 | DDR_addr[1] | | PS_DDR_A1_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| K21 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| K22 | DDR_addr[0] | | PS_DDR_A0_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| K23 | DDR_dq[11] | | PS_DDR_DQ11_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| K24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K25 | DDR_dm[1] | | PS_DDR_DM1_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| K26 | DDR_dq[8] | | PS_DDR_DQ8_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| L1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L2 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| L3 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| L4 | | High Performance | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| L5 | | High Performance | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| L6 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| L7 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| L8 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| L9 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L17 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
|
||||
| L18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L19 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
|
||||
| L20 | DDR_addr[6] | | PS_DDR_A6_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| L21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L22 | DDR_addr[3] | | PS_DDR_A3_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| L23 | DDR_dq[9] | | PS_DDR_DQ9_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| L24 | DDR_dqs_p[1] | | PS_DDR_DQS_P1_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| L25 | DDR_dqs_n[1] | | PS_DDR_DQS_N1_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| L26 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| M1 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| M2 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| M3 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| M4 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| M5 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| M6 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| M7 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| M8 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M10 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | |
|
||||
| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| M13 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| M14 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M16 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| M17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M18 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | | | |
|
||||
| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M20 | DDR_addr[4] | | PS_DDR_A4_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M21 | | | PS_DDR_VREF1_502 | PSS IO | | | | | | | | | | | | | | | |
|
||||
| M22 | DDR_addr[10] | | PS_DDR_A10_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| M23 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| M24 | DDR_dq[14] | | PS_DDR_DQ14_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| M25 | DDR_dq[12] | | PS_DDR_DQ12_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| M26 | DDR_dq[10] | | PS_DDR_DQ10_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| N1 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| N2 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| N3 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| N4 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| N5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N6 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| N7 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| N8 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| N9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N13 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| N14 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N17 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
|
||||
| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N19 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
|
||||
| N20 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| N21 | DDR_addr[2] | | PS_DDR_A2_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N22 | DDR_addr[5] | | PS_DDR_A5_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| N23 | DDR_dq[15] | | PS_DDR_DQ15_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| N24 | DDR_dq[13] | | PS_DDR_DQ13_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| N25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N26 | DDR_dq[18] | | PS_DDR_DQ18_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P10 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | |
|
||||
| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| P13 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| P14 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P16 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P18 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
|
||||
| P19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P20 | DDR_addr[12] | | PS_DDR_A12_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P21 | DDR_ck_n | | PS_DDR_CKN_502 | IN | DIFF_SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| P22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P23 | DDR_dq[19] | | PS_DDR_DQ19_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| P24 | DDR_dq[17] | | PS_DDR_DQ17_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| P25 | DDR_dqs_p[2] | | PS_DDR_DQS_P2_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| P26 | DDR_dm[2] | | PS_DDR_DM2_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| R1 | | | MGTXTXN3_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| R2 | | | MGTXTXP3_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| R3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R4 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| R5 | | | MGTREFCLK0N_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| R6 | | | MGTREFCLK0P_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| R7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R8 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R13 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| R14 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| R16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R17 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
|
||||
| R18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R19 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
|
||||
| R20 | DDR_addr[14] | | PS_DDR_A14_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R21 | DDR_ck_p | | PS_DDR_CKP_502 | IN | DIFF_SSTL15 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R22 | DDR_ba[2] | | PS_DDR_BA2_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| R23 | DDR_dq[23] | | PS_DDR_DQ23_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| R24 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| R25 | DDR_dqs_n[2] | | PS_DDR_DQS_N2_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| R26 | DDR_dq[16] | | PS_DDR_DQ16_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| T1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| T3 | | | MGTXRXN3_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| T4 | | | MGTXRXP3_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| T5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| T7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| T8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T10 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | |
|
||||
| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| T15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T16 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T18 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
|
||||
| T19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T20 | DDR_addr[8] | | PS_DDR_A8_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T21 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| T22 | DDR_ba[1] | | PS_DDR_BA1_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| T23 | DDR_dq[22] | | PS_DDR_DQ22_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| T24 | DDR_dq[20] | | PS_DDR_DQ20_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| T25 | DDR_dq[21] | | PS_DDR_DQ21_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| T26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U1 | | | MGTXTXN2_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| U2 | | | MGTXTXP2_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| U3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U4 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| U5 | | | MGTREFCLK1N_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| U6 | | | MGTREFCLK1P_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| U7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U8 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | | | |
|
||||
| U9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| U12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| U16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U17 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
|
||||
| U18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U19 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
|
||||
| U20 | DDR_addr[9] | | PS_DDR_A9_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U21 | DDR_cke | | PS_DDR_CKE_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U22 | DDR_ba[0] | | PS_DDR_BA0_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| U23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U24 | DDR_dq[26] | | PS_DDR_DQ26_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| U25 | DDR_dq[27] | | PS_DDR_DQ27_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| U26 | DDR_dq[25] | | PS_DDR_DQ25_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| V3 | | | MGTXRXN2_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| V4 | | | MGTXRXP2_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| V5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V6 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| V7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V8 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | | | |
|
||||
| V9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| V10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| V11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| V12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
|
||||
| V13 | | | RSVDGND | GND | | | | | | | | | | | | | | | |
|
||||
| V14 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
|
||||
| V15 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| V16 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| V17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V18 | | High Range | IO_25_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| V19 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| V20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V21 | FIXED_IO_ddr_vrn | | PS_DDR_VRN_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| V22 | DDR_we_n | | PS_DDR_WE_B_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V23 | DDR_ras_n | | PS_DDR_RAS_B_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| V24 | DDR_dq[24] | | PS_DDR_DQ24_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| V25 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| V26 | DDR_dm[3] | | PS_DDR_DM3_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| W1 | | | MGTXTXN1_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| W2 | | | MGTXTXP1_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| W3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W4 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| W5 | | | MGTREFCLK0N_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| W6 | | | MGTREFCLK0P_111 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| W7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W8 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | | | |
|
||||
| W9 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| W10 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| W11 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| W12 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| W13 | EMIO_0_tri_io[32] | High Range | IO_L5P_T0_12 | BIDIR | LVCMOS33 | 12 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W14 | | High Range | IO_0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W15 | | High Range | IO_L24N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W16 | | High Range | IO_L24P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W17 | | High Range | IO_25_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W18 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| W19 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| W20 | EMIO_0_tri_io[1] | High Range | IO_L19P_T3_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| W21 | FIXED_IO_ddr_vrp | | PS_DDR_VRP_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| W22 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
|
||||
| W23 | DDR_dq[31] | | PS_DDR_DQ31_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| W24 | DDR_dqs_p[3] | | PS_DDR_DQS_P3_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| W25 | DDR_dqs_n[3] | | PS_DDR_DQS_N3_502 | INOUT | DIFF_SSTL15_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| W26 | DDR_dq[28] | | PS_DDR_DQ28_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| Y1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| Y3 | | | MGTXRXN1_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| Y4 | | | MGTXRXP1_112 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| Y7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y10 | | High Range | IO_L3P_T0_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y11 | | High Range | IO_L1N_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y12 | | High Range | IO_L1P_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y13 | | High Range | IO_L5N_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y15 | | High Range | IO_L23N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y16 | | High Range | IO_L23P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y17 | | High Range | IO_L19P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y18 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| Y19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
|
||||
| Y20 | EMIO_0_tri_io[2] | High Range | IO_L19N_T3_VREF_13 | BIDIR | LVCMOS33 | 13 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y21 | DDR_cs_n | | PS_DDR_CS_B_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y22 | DDR_odt | | PS_DDR_ODT_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y23 | DDR_cas_n | | PS_DDR_CAS_B_502 | OUT | SSTL15 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
|
||||
| Y24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y25 | DDR_dq[29] | | PS_DDR_DQ29_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
| Y26 | DDR_dq[30] | | PS_DDR_DQ30_502 | INOUT | SSTL15_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | |
|
||||
+------------+-------------------+------------------+-------------------------+---------------+-------------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
* Default value
|
||||
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,530 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Wed May 27 16:42:36 2026
|
||||
| Host : mkb running 64-bit unknown
|
||||
| Command : report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx
|
||||
| Design : system_wrapper
|
||||
| Device : xc7z035ffg676-2
|
||||
| Speed File : -2
|
||||
| Design State : Fully Routed
|
||||
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report Methodology
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Max violations: <unlimited>
|
||||
Violations found: 96
|
||||
+-----------+----------+--------------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+-----------+----------+--------------------------------+------------+
|
||||
| LUTAR-1 | Warning | LUT drives async reset alert | 4 |
|
||||
| TIMING-18 | Warning | Missing input or output delay | 33 |
|
||||
| TIMING-20 | Warning | Non-clocked latch | 57 |
|
||||
| XDCB-1 | Warning | Runtime intensive exceptions | 1 |
|
||||
| LATCH-1 | Advisory | Existing latches in the design | 1 |
|
||||
+-----------+----------+--------------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
LUTAR-1#1 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst/ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/PRE,
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/PRE
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#2 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst/ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/PRE,
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/PRE
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#3 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst/ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]/PRE,
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/PRE
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
LUTAR-1#4 Warning
|
||||
LUT drives async reset alert
|
||||
LUT cell dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst/ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/PRE,
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/PRE
|
||||
dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#1 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[0] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#2 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[10] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#3 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[11] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#4 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[12] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#5 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[13] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#6 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[14] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#7 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[15] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#8 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[16] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#9 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[17] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#10 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[18] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#11 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[19] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#12 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[1] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#13 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[20] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#14 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[21] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#15 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[22] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#16 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[23] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#17 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[24] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#18 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[25] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#19 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[26] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#20 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[27] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#21 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[28] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#22 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[29] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#23 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[2] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#24 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[30] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#25 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[31] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#26 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[32] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#27 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[3] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#28 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[4] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#29 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[5] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#30 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[6] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#31 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[7] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#32 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[8] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-18#33 Warning
|
||||
Missing input or output delay
|
||||
An input delay is missing on EMIO_0_tri_io[9] relative to the rising and/or falling clock edge(s) of clk_fpga_0.
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#1 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[0] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[0]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#2 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[10] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[10]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#3 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[11] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[11]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#4 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[12] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[12]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#5 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[13] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[13]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#6 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[14] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[14]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#7 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[15] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[15]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#8 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[16] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[16]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#9 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[17] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[17]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#10 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[18] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[18]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#11 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[19] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[19]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#12 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[1] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[1]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#13 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[20] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[20]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#14 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[21] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[21]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#15 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[22] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[22]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#16 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[23] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[23]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#17 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[24] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[24]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#18 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[25] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[25]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#19 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[26] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[26]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#20 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[27] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[27]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#21 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[28] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[28]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#22 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[29] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[29]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#23 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[2] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[2]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#24 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[30] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[30]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#25 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[31] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[31]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#26 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[32] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[32]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#27 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[33] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[33]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#28 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[34] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[34]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#29 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[35] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[35]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#30 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[36] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[36]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#31 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[37] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[37]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#32 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[38] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[38]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#33 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[39] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[39]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#34 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[3] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[3]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#35 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[40] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[40]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#36 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[41] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[41]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#37 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[42] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[42]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#38 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[43] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[43]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#39 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[44] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[44]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#40 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[45] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[45]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#41 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[46] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[46]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#42 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[47] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[47]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#43 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[48] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[48]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#44 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[49] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[49]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#45 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[4] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[4]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#46 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[50] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[50]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#47 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[51] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[51]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#48 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[52] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[52]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#49 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[53] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[53]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#50 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[54] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[54]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#51 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[55] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[55]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#52 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[56] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[56]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#53 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[5] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[5]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#54 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[6] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[6]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#55 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[7] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[7]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#56 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[8] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[8]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
TIMING-20#57 Warning
|
||||
Non-clocked latch
|
||||
The latch system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[9] cannot be properly analyzed as its control pin system_i/mydna_read_v1_0_0/inst/mydna_read_v1_0_S00_AXI_inst/dna_port_reg_reg[9]/G is not reached by a timing clock
|
||||
Related violations: <none>
|
||||
|
||||
XDCB-1#1 Warning
|
||||
Runtime intensive exceptions
|
||||
The following constraint contains more than 10000 objects. To preserve runtime and memory performance, it is recommended to include minimum number of objects. Check whether this list can be simplified.
|
||||
-from = expands to 12808 design objects.
|
||||
set_false_path -from [get_pins -filter REF_PIN_NAME=~CLK* -of_objects [get_cells -hierarchical -filter {NAME =~ "*allx_typeA_match_detection.ltlib_v1_...
|
||||
/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/.Xil/Vivado-959246-mkb/u_ila_0_CV.0/out/ila_impl_early.xdc (Line: 5)
|
||||
Related violations: <none>
|
||||
|
||||
LATCH-1#1 Advisory
|
||||
Existing latches in the design
|
||||
There are 57 latches found in the design. Inferred latches are often the result of HDL coding mistakes, such as incomplete if or case statements.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,171 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Wed May 27 16:42:41 2026
|
||||
| Host : mkb running 64-bit unknown
|
||||
| Command : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx
|
||||
| Design : system_wrapper
|
||||
| Device : xc7z035ffg676-2
|
||||
| Design State : routed
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 1.909 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 1.688 |
|
||||
| Device Static (W) | 0.221 |
|
||||
| Effective TJA (C/W) | 1.9 |
|
||||
| Max Ambient (C) | 81.4 |
|
||||
| Junction Temperature (C) | 28.6 |
|
||||
| Confidence Level | Low |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
| Clocks | 0.097 | 4 | --- | --- |
|
||||
| Slice Logic | 0.012 | 67930 | --- | --- |
|
||||
| LUT as Logic | 0.011 | 13657 | 171900 | 7.94 |
|
||||
| Register | <0.001 | 29180 | 343800 | 8.49 |
|
||||
| LUT as Shift Register | <0.001 | 6873 | 70400 | 9.76 |
|
||||
| LUT as Distributed RAM | <0.001 | 152 | 70400 | 0.22 |
|
||||
| CARRY4 | <0.001 | 1979 | 54650 | 3.62 |
|
||||
| BUFG | <0.001 | 1 | 32 | 3.13 |
|
||||
| F7/F8 Muxes | <0.001 | 1059 | 218600 | 0.48 |
|
||||
| Others | 0.000 | 6317 | --- | --- |
|
||||
| Signals | 0.025 | 38363 | --- | --- |
|
||||
| Block RAM | 0.002 | 2.5 | 500 | 0.50 |
|
||||
| I/O | 0.024 | 33 | 250 | 13.20 |
|
||||
| PS7 | 1.528 | 1 | --- | --- |
|
||||
| Static Power | 0.221 | | | |
|
||||
| Total | 1.909 | | | |
|
||||
+--------------------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.194 | 0.136 | 0.059 | NA | Unspecified | NA |
|
||||
| Vccaux | 1.800 | 0.041 | 0.001 | 0.040 | NA | Unspecified | NA |
|
||||
| Vcco33 | 3.300 | 0.008 | 0.007 | 0.001 | NA | Unspecified | NA |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccbram | 1.000 | 0.002 | 0.000 | 0.002 | NA | Unspecified | NA |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccpint | 1.000 | 0.736 | 0.718 | 0.018 | NA | Unspecified | NA |
|
||||
| Vccpaux | 1.800 | 0.061 | 0.051 | 0.010 | NA | Unspecified | NA |
|
||||
| Vccpll | 1.800 | 0.017 | 0.014 | 0.003 | NA | Unspecified | NA |
|
||||
| Vcco_ddr | 1.500 | 0.459 | 0.457 | 0.002 | NA | Unspecified | NA |
|
||||
| Vcco_mio0 | 1.800 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
|
||||
| Vcco_mio1 | 1.800 | 0.003 | 0.002 | 0.001 | NA | Unspecified | NA |
|
||||
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
|
||||
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | High | User specified more than 95% of clocks | |
|
||||
| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Low | | |
|
||||
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 1.9 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 3.4 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------+-----------------+
|
||||
| clk_fpga_0 | system_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | 10.0 |
|
||||
| dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TCK | 33.0 |
|
||||
+--------------------------------------------------------------------------------------------+-------------------------------------------------------------------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+--------------------------+-----------+
|
||||
| Name | Power (W) |
|
||||
+--------------------------+-----------+
|
||||
| system_wrapper | 1.688 |
|
||||
| dbg_hub | 0.003 |
|
||||
| inst | 0.003 |
|
||||
| BSCANID.u_xsdbm_id | 0.003 |
|
||||
| system_i | 1.535 |
|
||||
| processing_system7_0 | 1.530 |
|
||||
| inst | 1.530 |
|
||||
| ps7_0_axi_periph | 0.003 |
|
||||
| s00_couplers | 0.003 |
|
||||
| u_ila_0 | 0.125 |
|
||||
| inst | 0.125 |
|
||||
| ila_core_inst | 0.125 |
|
||||
+--------------------------+-----------+
|
||||
|
||||
|
||||
Binary file not shown.
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Binary file not shown.
@@ -0,0 +1,12 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 69072 :
|
||||
# of nets not needing routing.......... : 30573 :
|
||||
# of internally routed nets........ : 30504 :
|
||||
# of nets with no loads............ : 69 :
|
||||
# of routable nets..................... : 38499 :
|
||||
# of fully routed nets............. : 38499 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,245 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Wed May 27 16:41:20 2026
|
||||
| Host : mkb running 64-bit unknown
|
||||
| Command : report_utilization -file system_wrapper_utilization_placed.rpt -pb system_wrapper_utilization_placed.pb
|
||||
| Design : system_wrapper
|
||||
| Device : xc7z035ffg676-2
|
||||
| Speed File : -2
|
||||
| Design State : Fully Placed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Slice Logic Distribution
|
||||
3. Memory
|
||||
4. DSP
|
||||
5. IO and GT Specific
|
||||
6. Clocking
|
||||
7. Specific Feature
|
||||
8. Primitives
|
||||
9. Black Boxes
|
||||
10. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+-------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+----------------------------+-------+-------+------------+-----------+-------+
|
||||
| Slice LUTs | 20682 | 0 | 0 | 171900 | 12.03 |
|
||||
| LUT as Logic | 13657 | 0 | 0 | 171900 | 7.94 |
|
||||
| LUT as Memory | 7025 | 0 | 0 | 70400 | 9.98 |
|
||||
| LUT as Distributed RAM | 152 | 0 | | | |
|
||||
| LUT as Shift Register | 6873 | 0 | | | |
|
||||
| Slice Registers | 29180 | 0 | 0 | 343800 | 8.49 |
|
||||
| Register as Flip Flop | 29123 | 0 | 0 | 343800 | 8.47 |
|
||||
| Register as Latch | 57 | 0 | 0 | 343800 | 0.02 |
|
||||
| F7 Muxes | 753 | 0 | 0 | 109300 | 0.69 |
|
||||
| F8 Muxes | 306 | 0 | 0 | 54650 | 0.56 |
|
||||
+----------------------------+-------+-------+------------+-----------+-------+
|
||||
* Warning! LUT value is adjusted to account for LUT combining.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 41 | Yes | - | Set |
|
||||
| 307 | Yes | - | Reset |
|
||||
| 65 | Yes | Set | - |
|
||||
| 28767 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Slice Logic Distribution
|
||||
---------------------------
|
||||
|
||||
+--------------------------------------------+-------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+--------------------------------------------+-------+-------+------------+-----------+-------+
|
||||
| Slice | 8247 | 0 | 0 | 54650 | 15.09 |
|
||||
| SLICEL | 5087 | 0 | | | |
|
||||
| SLICEM | 3160 | 0 | | | |
|
||||
| LUT as Logic | 13657 | 0 | 0 | 171900 | 7.94 |
|
||||
| using O5 output only | 0 | | | | |
|
||||
| using O6 output only | 11414 | | | | |
|
||||
| using O5 and O6 | 2243 | | | | |
|
||||
| LUT as Memory | 7025 | 0 | 0 | 70400 | 9.98 |
|
||||
| LUT as Distributed RAM | 152 | 0 | | | |
|
||||
| using O5 output only | 0 | | | | |
|
||||
| using O6 output only | 128 | | | | |
|
||||
| using O5 and O6 | 24 | | | | |
|
||||
| LUT as Shift Register | 6873 | 0 | | | |
|
||||
| using O5 output only | 7 | | | | |
|
||||
| using O6 output only | 421 | | | | |
|
||||
| using O5 and O6 | 6445 | | | | |
|
||||
| Slice Registers | 29180 | 0 | 0 | 343800 | 8.49 |
|
||||
| Register driven from within the Slice | 11496 | | | | |
|
||||
| Register driven from outside the Slice | 17684 | | | | |
|
||||
| LUT in front of the register is unused | 14097 | | | | |
|
||||
| LUT in front of the register is used | 3587 | | | | |
|
||||
| Unique Control Sets | 855 | | 0 | 54650 | 1.56 |
|
||||
+--------------------------------------------+-------+-------+------------+-----------+-------+
|
||||
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
|
||||
3. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------------+------+-------+------------+-----------+-------+
|
||||
| Block RAM Tile | 2.5 | 0 | 0 | 500 | 0.50 |
|
||||
| RAMB36/FIFO* | 2 | 0 | 0 | 500 | 0.40 |
|
||||
| RAMB36E1 only | 2 | | | | |
|
||||
| RAMB18 | 1 | 0 | 0 | 1000 | 0.10 |
|
||||
| RAMB18E1 only | 1 | | | | |
|
||||
+-------------------+------+-------+------------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
4. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 0 | 900 | 0.00 |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
5. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+------------+-----------+--------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------------------------+------+-------+------------+-----------+--------+
|
||||
| Bonded IOB | 33 | 33 | 0 | 250 | 13.20 |
|
||||
| IOB Master Pads | 18 | | | | |
|
||||
| IOB Slave Pads | 15 | | | | |
|
||||
| Bonded IPADs | 0 | 0 | 0 | 26 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 0 | 16 | 0.00 |
|
||||
| Bonded IOPADs | 130 | 130 | 0 | 130 | 100.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 0 | 240 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 400 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 0 | 250 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 0 | 250 | 0.00 |
|
||||
+-----------------------------+------+-------+------------+-----------+--------+
|
||||
|
||||
|
||||
6. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| BUFGCTRL | 3 | 0 | 0 | 32 | 9.38 |
|
||||
| BUFIO | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 0 | 16 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 0 | 32 | 0.00 |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
7. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+------------+-----------+--------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------+------+-------+------------+-----------+--------+
|
||||
| BSCANE2 | 1 | 0 | 0 | 4 | 25.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 1 | 0 | 0 | 1 | 100.00 |
|
||||
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+------------+-----------+--------+
|
||||
|
||||
|
||||
8. Primitives
|
||||
-------------
|
||||
|
||||
+----------+-------+----------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+-------+----------------------+
|
||||
| FDRE | 28767 | Flop & Latch |
|
||||
| LUT6 | 8925 | LUT |
|
||||
| SRLC32E | 6810 | Distributed Memory |
|
||||
| SRL16E | 6506 | Distributed Memory |
|
||||
| LUT4 | 3385 | LUT |
|
||||
| CARRY4 | 1979 | CarryLogic |
|
||||
| LUT3 | 1462 | LUT |
|
||||
| LUT5 | 1111 | LUT |
|
||||
| MUXF7 | 753 | MuxFx |
|
||||
| LUT2 | 594 | LUT |
|
||||
| LUT1 | 423 | LUT |
|
||||
| MUXF8 | 306 | MuxFx |
|
||||
| FDCE | 250 | Flop & Latch |
|
||||
| BIBUF | 130 | IO |
|
||||
| RAMD64E | 128 | Distributed Memory |
|
||||
| FDSE | 65 | Flop & Latch |
|
||||
| LDCE | 57 | Flop & Latch |
|
||||
| FDPE | 41 | Flop & Latch |
|
||||
| RAMD32 | 36 | Distributed Memory |
|
||||
| OBUFT | 33 | IO |
|
||||
| IBUF | 33 | IO |
|
||||
| RAMS32 | 12 | Distributed Memory |
|
||||
| BUFG | 3 | Clock |
|
||||
| SRLC16E | 2 | Distributed Memory |
|
||||
| RAMB36E1 | 2 | Block Memory |
|
||||
| RAMB18E1 | 1 | Block Memory |
|
||||
| PS7 | 1 | Specialized Resource |
|
||||
| DNA_PORT | 1 | Others |
|
||||
| BSCANE2 | 1 | Others |
|
||||
+----------+-------+----------------------+
|
||||
|
||||
|
||||
9. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
10. Instantiated Netlists
|
||||
-------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
| u_ila_0 | 1 |
|
||||
| dbg_hub | 1 |
|
||||
+----------+------+
|
||||
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Wed May 27 16:36:42 2026
|
||||
# Process ID: 959246
|
||||
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1
|
||||
# Command line: vivado -log system_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace
|
||||
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper.vdi
|
||||
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/vivado.jou
|
||||
# Running On: mkb, OS: Linux, CPU Frequency: 4911.606 MHz, CPU Physical cores: 32, Host memory: 134146 MB
|
||||
#-----------------------------------------------------------
|
||||
source system_wrapper.tcl -notrace
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,936 @@
|
||||
set_property SRC_FILE_INFO {cfile:/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc rfile:../../../Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc id:1 order:EARLY scoped_inst:system_i/processing_system7_0/inst} [current_design]
|
||||
set_property SRC_FILE_INFO {cfile:/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc rfile:../../../Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc id:2 order:EARLY scoped_inst:system_i/rst_ps7_0_100M/U0} [current_design]
|
||||
set_property SRC_FILE_INFO {cfile:/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc rfile:../../../Debug_FW.srcs/constrs_1/new/pin_cons.xdc id:3} [current_design]
|
||||
set_property SRC_FILE_INFO {cfile:/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc rfile:../../../Debug_FW.srcs/constrs_1/new/pin_debug.xdc id:4} [current_design]
|
||||
current_instance system_i/processing_system7_0/inst
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_input_jitter clk_fpga_0 0.3
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "A19" [get_ports "MIO[53]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:38 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "A20" [get_ports "MIO[52]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "A18" [get_ports "MIO[49]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "B21" [get_ports "MIO[48]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:59 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "B19" [get_ports "MIO[47]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "E17" [get_ports "MIO[46]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "C18" [get_ports "MIO[45]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:80 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "E18" [get_ports "MIO[44]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "D18" [get_ports "MIO[43]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:94 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "F17" [get_ports "MIO[42]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:101 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "C19" [get_ports "MIO[41]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:108 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "C22" [get_ports "MIO[40]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:115 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "F18" [get_ports "MIO[27]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:122 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "H17" [get_ports "MIO[26]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:129 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "F19" [get_ports "MIO[25]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:136 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "J19" [get_ports "MIO[24]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:143 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "F20" [get_ports "MIO[23]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:150 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "G22" [get_ports "MIO[22]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:157 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "F22" [get_ports "MIO[21]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:164 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "H19" [get_ports "MIO[20]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:171 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "G19" [get_ports "MIO[19]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:178 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "G20" [get_ports "MIO[18]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:185 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "G17" [get_ports "MIO[17]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:192 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "G21" [get_ports "MIO[16]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:199 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "A24" [get_ports "MIO[8]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:205 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "F23" [get_ports "MIO[6]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:211 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "C26" [get_ports "MIO[5]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:217 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "F24" [get_ports "MIO[4]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:223 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "D25" [get_ports "MIO[3]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:229 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "E25" [get_ports "MIO[2]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:235 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "D26" [get_ports "MIO[1]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:241 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "W21" [get_ports "DDR_VRP"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:245 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "V21" [get_ports "DDR_VRN"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:249 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "V22" [get_ports "DDR_WEB"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:253 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "V23" [get_ports "DDR_RAS_n"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:257 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "Y22" [get_ports "DDR_ODT"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:261 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "H22" [get_ports "DDR_DRSTB"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:265 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "W24" [get_ports "DDR_DQS[3]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:269 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "P25" [get_ports "DDR_DQS[2]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:273 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "L24" [get_ports "DDR_DQS[1]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:277 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "H24" [get_ports "DDR_DQS[0]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:281 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "W25" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:285 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "R25" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:289 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "L25" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:293 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "G25" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:297 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "L23" [get_ports "DDR_DQ[9]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:301 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "K26" [get_ports "DDR_DQ[8]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:305 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "J23" [get_ports "DDR_DQ[7]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:309 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "J24" [get_ports "DDR_DQ[6]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:313 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "H23" [get_ports "DDR_DQ[5]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:317 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "H26" [get_ports "DDR_DQ[4]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:321 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "G26" [get_ports "DDR_DQ[3]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:325 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "W23" [get_ports "DDR_DQ[31]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:329 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "Y26" [get_ports "DDR_DQ[30]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:333 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "J25" [get_ports "DDR_DQ[2]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:337 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "Y25" [get_ports "DDR_DQ[29]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:341 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "W26" [get_ports "DDR_DQ[28]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:345 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "U25" [get_ports "DDR_DQ[27]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:349 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "U24" [get_ports "DDR_DQ[26]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:353 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "U26" [get_ports "DDR_DQ[25]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:357 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "V24" [get_ports "DDR_DQ[24]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:361 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "R23" [get_ports "DDR_DQ[23]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:365 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "T23" [get_ports "DDR_DQ[22]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:369 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "T25" [get_ports "DDR_DQ[21]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:373 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "T24" [get_ports "DDR_DQ[20]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:377 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "F25" [get_ports "DDR_DQ[1]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:381 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "P23" [get_ports "DDR_DQ[19]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:385 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "N26" [get_ports "DDR_DQ[18]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:389 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "P24" [get_ports "DDR_DQ[17]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:393 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "R26" [get_ports "DDR_DQ[16]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:397 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "N23" [get_ports "DDR_DQ[15]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:401 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "M24" [get_ports "DDR_DQ[14]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:405 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "N24" [get_ports "DDR_DQ[13]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:409 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "M25" [get_ports "DDR_DQ[12]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:413 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "K23" [get_ports "DDR_DQ[11]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:417 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "M26" [get_ports "DDR_DQ[10]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:421 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "J26" [get_ports "DDR_DQ[0]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:425 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "V26" [get_ports "DDR_DM[3]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:429 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "P26" [get_ports "DDR_DM[2]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:433 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "K25" [get_ports "DDR_DM[1]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:437 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "G24" [get_ports "DDR_DM[0]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:441 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "Y21" [get_ports "DDR_CS_n"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:445 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "U21" [get_ports "DDR_CKE"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:449 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "R21" [get_ports "DDR_Clk"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:453 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "P21" [get_ports "DDR_Clk_n"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:457 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "Y23" [get_ports "DDR_CAS_n"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:461 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "R22" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:465 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "T22" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:469 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "U22" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:473 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "U20" [get_ports "DDR_Addr[9]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:477 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "T20" [get_ports "DDR_Addr[8]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:481 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "J21" [get_ports "DDR_Addr[7]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:485 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "L20" [get_ports "DDR_Addr[6]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:489 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "N22" [get_ports "DDR_Addr[5]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:493 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "M20" [get_ports "DDR_Addr[4]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:497 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "L22" [get_ports "DDR_Addr[3]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:501 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "N21" [get_ports "DDR_Addr[2]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:505 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "K20" [get_ports "DDR_Addr[1]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:509 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "R20" [get_ports "DDR_Addr[14]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:513 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "J20" [get_ports "DDR_Addr[13]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:517 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "P20" [get_ports "DDR_Addr[12]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:521 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "H21" [get_ports "DDR_Addr[11]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:525 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "M22" [get_ports "DDR_Addr[10]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:529 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "K22" [get_ports "DDR_Addr[0]"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:533 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "C23" [get_ports "PS_PORB"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:536 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "A22" [get_ports "PS_SRSTB"]
|
||||
set_property src_info {type:SCOPED_XDC file:1 line:539 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN "B24" [get_ports "PS_CLK"]
|
||||
current_instance
|
||||
current_instance system_i/rst_ps7_0_100M/U0
|
||||
set_property src_info {type:SCOPED_XDC file:2 line:50 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_waiver -type CDC -id {CDC-11} -user "proc_sys_reset" -desc "Timing uncritical paths" -tags "1171415" -scope -internal -to [get_pins -quiet -filter REF_PIN_NAME=~*D -of_objects [get_cells -hierarchical -filter {NAME =~ */ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to}]]
|
||||
current_instance
|
||||
set_property src_info {type:XDC file:3 line:35 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AB21 [get_ports {EMIO_0_tri_io[0]}]
|
||||
set_property src_info {type:XDC file:3 line:36 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN W20 [get_ports {EMIO_0_tri_io[1]}]
|
||||
set_property src_info {type:XDC file:3 line:37 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN Y20 [get_ports {EMIO_0_tri_io[2]}]
|
||||
set_property src_info {type:XDC file:3 line:38 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AE18 [get_ports {EMIO_0_tri_io[3]}]
|
||||
set_property src_info {type:XDC file:3 line:39 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AF18 [get_ports {EMIO_0_tri_io[4]}]
|
||||
set_property src_info {type:XDC file:3 line:40 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AF19 [get_ports {EMIO_0_tri_io[5]}]
|
||||
set_property src_info {type:XDC file:3 line:41 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AE21 [get_ports {EMIO_0_tri_io[6]}]
|
||||
set_property src_info {type:XDC file:3 line:42 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AE20 [get_ports {EMIO_0_tri_io[7]}]
|
||||
set_property src_info {type:XDC file:3 line:43 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AD18 [get_ports {EMIO_0_tri_io[8]}]
|
||||
set_property src_info {type:XDC file:3 line:44 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AD19 [get_ports {EMIO_0_tri_io[9]}]
|
||||
set_property src_info {type:XDC file:3 line:45 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AA22 [get_ports {EMIO_0_tri_io[10]}]
|
||||
set_property src_info {type:XDC file:3 line:47 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AB25 [get_ports {EMIO_0_tri_io[11]}]
|
||||
set_property src_info {type:XDC file:3 line:48 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AD23 [get_ports {EMIO_0_tri_io[12]}]
|
||||
set_property src_info {type:XDC file:3 line:49 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AD20 [get_ports {EMIO_0_tri_io[13]}]
|
||||
set_property src_info {type:XDC file:3 line:50 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AD21 [get_ports {EMIO_0_tri_io[14]}]
|
||||
set_property src_info {type:XDC file:3 line:51 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AC23 [get_ports {EMIO_0_tri_io[15]}]
|
||||
set_property src_info {type:XDC file:3 line:52 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AA25 [get_ports {EMIO_0_tri_io[16]}]
|
||||
set_property src_info {type:XDC file:3 line:53 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AD24 [get_ports {EMIO_0_tri_io[17]}]
|
||||
set_property src_info {type:XDC file:3 line:54 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AC24 [get_ports {EMIO_0_tri_io[18]}]
|
||||
set_property src_info {type:XDC file:3 line:55 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AC21 [get_ports {EMIO_0_tri_io[19]}]
|
||||
set_property src_info {type:XDC file:3 line:56 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AC22 [get_ports {EMIO_0_tri_io[20]}]
|
||||
set_property src_info {type:XDC file:3 line:57 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AF20 [get_ports {EMIO_0_tri_io[21]}]
|
||||
set_property src_info {type:XDC file:3 line:59 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AD10 [get_ports {EMIO_0_tri_io[22]}]
|
||||
set_property src_info {type:XDC file:3 line:60 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AA12 [get_ports {EMIO_0_tri_io[23]}]
|
||||
set_property src_info {type:XDC file:3 line:61 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AF12 [get_ports {EMIO_0_tri_io[24]}]
|
||||
set_property src_info {type:XDC file:3 line:62 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AA13 [get_ports {EMIO_0_tri_io[25]}]
|
||||
set_property src_info {type:XDC file:3 line:63 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AE12 [get_ports {EMIO_0_tri_io[26]}]
|
||||
set_property src_info {type:XDC file:3 line:64 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AE13 [get_ports {EMIO_0_tri_io[27]}]
|
||||
set_property src_info {type:XDC file:3 line:65 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AF13 [get_ports {EMIO_0_tri_io[28]}]
|
||||
set_property src_info {type:XDC file:3 line:66 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AE11 [get_ports {EMIO_0_tri_io[29]}]
|
||||
set_property src_info {type:XDC file:3 line:67 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AF10 [get_ports {EMIO_0_tri_io[30]}]
|
||||
set_property src_info {type:XDC file:3 line:68 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN AE10 [get_ports {EMIO_0_tri_io[31]}]
|
||||
set_property src_info {type:XDC file:3 line:69 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PACKAGE_PIN W13 [get_ports {EMIO_0_tri_io[32]}]
|
||||
set_property src_info {type:XDC file:4 line:79 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property src_info {type:XDC file:4 line:80 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property src_info {type:XDC file:4 line:81 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
|
||||
set_property src_info {type:XDC file:4 line:82 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
|
||||
set_property src_info {type:XDC file:4 line:83 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
|
||||
set_property src_info {type:XDC file:4 line:84 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
|
||||
set_property src_info {type:XDC file:4 line:85 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property src_info {type:XDC file:4 line:86 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property src_info {type:XDC file:4 line:87 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property src_info {type:XDC file:4 line:88 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
set_property src_info {type:XDC file:4 line:89 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list system_i/processing_system7_0/inst/FCLK_CLK0]]
|
||||
set_property src_info {type:XDC file:4 line:90 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property src_info {type:XDC file:4 line:91 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe0]
|
||||
set_property src_info {type:XDC file:4 line:92 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list EMIO_0_tri_i_0]]
|
||||
set_property src_info {type:XDC file:4 line:93 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:94 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property src_info {type:XDC file:4 line:95 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe1]
|
||||
set_property src_info {type:XDC file:4 line:96 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list EMIO_0_tri_i_1]]
|
||||
set_property src_info {type:XDC file:4 line:97 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:98 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property src_info {type:XDC file:4 line:99 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe2]
|
||||
set_property src_info {type:XDC file:4 line:100 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list EMIO_0_tri_i_2]]
|
||||
set_property src_info {type:XDC file:4 line:101 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:102 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property src_info {type:XDC file:4 line:103 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe3]
|
||||
set_property src_info {type:XDC file:4 line:104 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list EMIO_0_tri_i_3]]
|
||||
set_property src_info {type:XDC file:4 line:105 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:106 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property src_info {type:XDC file:4 line:107 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe4]
|
||||
set_property src_info {type:XDC file:4 line:108 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list EMIO_0_tri_i_4]]
|
||||
set_property src_info {type:XDC file:4 line:109 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:110 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property src_info {type:XDC file:4 line:111 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe5]
|
||||
set_property src_info {type:XDC file:4 line:112 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list EMIO_0_tri_i_5]]
|
||||
set_property src_info {type:XDC file:4 line:113 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:114 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property src_info {type:XDC file:4 line:115 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe6]
|
||||
set_property src_info {type:XDC file:4 line:116 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list EMIO_0_tri_i_6]]
|
||||
set_property src_info {type:XDC file:4 line:117 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:118 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
set_property src_info {type:XDC file:4 line:119 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe7]
|
||||
set_property src_info {type:XDC file:4 line:120 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list EMIO_0_tri_i_7]]
|
||||
set_property src_info {type:XDC file:4 line:121 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:122 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
set_property src_info {type:XDC file:4 line:123 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe8]
|
||||
set_property src_info {type:XDC file:4 line:124 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list EMIO_0_tri_i_8]]
|
||||
set_property src_info {type:XDC file:4 line:125 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:126 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
set_property src_info {type:XDC file:4 line:127 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe9]
|
||||
set_property src_info {type:XDC file:4 line:128 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list EMIO_0_tri_i_9]]
|
||||
set_property src_info {type:XDC file:4 line:129 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:130 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
set_property src_info {type:XDC file:4 line:131 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe10]
|
||||
set_property src_info {type:XDC file:4 line:132 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list EMIO_0_tri_i_10]]
|
||||
set_property src_info {type:XDC file:4 line:133 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:134 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
set_property src_info {type:XDC file:4 line:135 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe11]
|
||||
set_property src_info {type:XDC file:4 line:136 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list EMIO_0_tri_i_11]]
|
||||
set_property src_info {type:XDC file:4 line:137 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:138 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
set_property src_info {type:XDC file:4 line:139 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe12]
|
||||
set_property src_info {type:XDC file:4 line:140 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list EMIO_0_tri_i_12]]
|
||||
set_property src_info {type:XDC file:4 line:141 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:142 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
set_property src_info {type:XDC file:4 line:143 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe13]
|
||||
set_property src_info {type:XDC file:4 line:144 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list EMIO_0_tri_i_13]]
|
||||
set_property src_info {type:XDC file:4 line:145 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:146 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
set_property src_info {type:XDC file:4 line:147 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe14]
|
||||
set_property src_info {type:XDC file:4 line:148 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list EMIO_0_tri_i_14]]
|
||||
set_property src_info {type:XDC file:4 line:149 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:150 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
set_property src_info {type:XDC file:4 line:151 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe15]
|
||||
set_property src_info {type:XDC file:4 line:152 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list EMIO_0_tri_i_15]]
|
||||
set_property src_info {type:XDC file:4 line:153 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:154 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
set_property src_info {type:XDC file:4 line:155 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe16]
|
||||
set_property src_info {type:XDC file:4 line:156 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list EMIO_0_tri_i_16]]
|
||||
set_property src_info {type:XDC file:4 line:157 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:158 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
set_property src_info {type:XDC file:4 line:159 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe17]
|
||||
set_property src_info {type:XDC file:4 line:160 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list EMIO_0_tri_i_17]]
|
||||
set_property src_info {type:XDC file:4 line:161 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:162 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
set_property src_info {type:XDC file:4 line:163 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe18]
|
||||
set_property src_info {type:XDC file:4 line:164 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list EMIO_0_tri_i_18]]
|
||||
set_property src_info {type:XDC file:4 line:165 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:166 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
set_property src_info {type:XDC file:4 line:167 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe19]
|
||||
set_property src_info {type:XDC file:4 line:168 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list EMIO_0_tri_i_19]]
|
||||
set_property src_info {type:XDC file:4 line:169 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:170 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
set_property src_info {type:XDC file:4 line:171 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe20]
|
||||
set_property src_info {type:XDC file:4 line:172 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list EMIO_0_tri_i_20]]
|
||||
set_property src_info {type:XDC file:4 line:173 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:174 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||
set_property src_info {type:XDC file:4 line:175 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe21]
|
||||
set_property src_info {type:XDC file:4 line:176 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list EMIO_0_tri_i_21]]
|
||||
set_property src_info {type:XDC file:4 line:177 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:178 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||
set_property src_info {type:XDC file:4 line:179 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe22]
|
||||
set_property src_info {type:XDC file:4 line:180 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list EMIO_0_tri_i_22]]
|
||||
set_property src_info {type:XDC file:4 line:181 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:182 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
||||
set_property src_info {type:XDC file:4 line:183 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe23]
|
||||
set_property src_info {type:XDC file:4 line:184 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list EMIO_0_tri_i_23]]
|
||||
set_property src_info {type:XDC file:4 line:185 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:186 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
||||
set_property src_info {type:XDC file:4 line:187 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe24]
|
||||
set_property src_info {type:XDC file:4 line:188 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe24 [get_nets [list EMIO_0_tri_i_24]]
|
||||
set_property src_info {type:XDC file:4 line:189 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:190 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
||||
set_property src_info {type:XDC file:4 line:191 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe25]
|
||||
set_property src_info {type:XDC file:4 line:192 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe25 [get_nets [list EMIO_0_tri_i_25]]
|
||||
set_property src_info {type:XDC file:4 line:193 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:194 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
||||
set_property src_info {type:XDC file:4 line:195 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe26]
|
||||
set_property src_info {type:XDC file:4 line:196 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe26 [get_nets [list EMIO_0_tri_i_26]]
|
||||
set_property src_info {type:XDC file:4 line:197 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:198 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
||||
set_property src_info {type:XDC file:4 line:199 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
|
||||
set_property src_info {type:XDC file:4 line:200 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe27 [get_nets [list EMIO_0_tri_i_27]]
|
||||
set_property src_info {type:XDC file:4 line:201 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:202 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
||||
set_property src_info {type:XDC file:4 line:203 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
|
||||
set_property src_info {type:XDC file:4 line:204 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe28 [get_nets [list EMIO_0_tri_i_28]]
|
||||
set_property src_info {type:XDC file:4 line:205 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:206 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
||||
set_property src_info {type:XDC file:4 line:207 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
||||
set_property src_info {type:XDC file:4 line:208 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe29 [get_nets [list EMIO_0_tri_i_29]]
|
||||
set_property src_info {type:XDC file:4 line:209 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:210 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
||||
set_property src_info {type:XDC file:4 line:211 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
||||
set_property src_info {type:XDC file:4 line:212 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe30 [get_nets [list EMIO_0_tri_i_30]]
|
||||
set_property src_info {type:XDC file:4 line:213 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:214 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
||||
set_property src_info {type:XDC file:4 line:215 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
||||
set_property src_info {type:XDC file:4 line:216 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe31 [get_nets [list EMIO_0_tri_i_31]]
|
||||
set_property src_info {type:XDC file:4 line:217 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:218 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
||||
set_property src_info {type:XDC file:4 line:219 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
||||
set_property src_info {type:XDC file:4 line:220 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe32 [get_nets [list EMIO_0_tri_i_32]]
|
||||
set_property src_info {type:XDC file:4 line:221 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:222 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
||||
set_property src_info {type:XDC file:4 line:223 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
||||
set_property src_info {type:XDC file:4 line:224 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe33 [get_nets [list EMIO_0_tri_o_0]]
|
||||
set_property src_info {type:XDC file:4 line:225 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:226 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
||||
set_property src_info {type:XDC file:4 line:227 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
||||
set_property src_info {type:XDC file:4 line:228 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list EMIO_0_tri_o_1]]
|
||||
set_property src_info {type:XDC file:4 line:229 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:230 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
||||
set_property src_info {type:XDC file:4 line:231 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
||||
set_property src_info {type:XDC file:4 line:232 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe35 [get_nets [list EMIO_0_tri_o_2]]
|
||||
set_property src_info {type:XDC file:4 line:233 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:234 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
||||
set_property src_info {type:XDC file:4 line:235 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
||||
set_property src_info {type:XDC file:4 line:236 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe36 [get_nets [list EMIO_0_tri_o_3]]
|
||||
set_property src_info {type:XDC file:4 line:237 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:238 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
||||
set_property src_info {type:XDC file:4 line:239 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
||||
set_property src_info {type:XDC file:4 line:240 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe37 [get_nets [list EMIO_0_tri_o_4]]
|
||||
set_property src_info {type:XDC file:4 line:241 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:242 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
||||
set_property src_info {type:XDC file:4 line:243 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
||||
set_property src_info {type:XDC file:4 line:244 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe38 [get_nets [list EMIO_0_tri_o_5]]
|
||||
set_property src_info {type:XDC file:4 line:245 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:246 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
||||
set_property src_info {type:XDC file:4 line:247 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
||||
set_property src_info {type:XDC file:4 line:248 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe39 [get_nets [list EMIO_0_tri_o_6]]
|
||||
set_property src_info {type:XDC file:4 line:249 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:250 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
||||
set_property src_info {type:XDC file:4 line:251 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
||||
set_property src_info {type:XDC file:4 line:252 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe40 [get_nets [list EMIO_0_tri_o_7]]
|
||||
set_property src_info {type:XDC file:4 line:253 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:254 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
||||
set_property src_info {type:XDC file:4 line:255 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
||||
set_property src_info {type:XDC file:4 line:256 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe41 [get_nets [list EMIO_0_tri_o_8]]
|
||||
set_property src_info {type:XDC file:4 line:257 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:258 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
||||
set_property src_info {type:XDC file:4 line:259 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
||||
set_property src_info {type:XDC file:4 line:260 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe42 [get_nets [list EMIO_0_tri_o_9]]
|
||||
set_property src_info {type:XDC file:4 line:261 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:262 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
||||
set_property src_info {type:XDC file:4 line:263 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
||||
set_property src_info {type:XDC file:4 line:264 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe43 [get_nets [list EMIO_0_tri_o_10]]
|
||||
set_property src_info {type:XDC file:4 line:265 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:266 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
||||
set_property src_info {type:XDC file:4 line:267 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
||||
set_property src_info {type:XDC file:4 line:268 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe44 [get_nets [list EMIO_0_tri_o_11]]
|
||||
set_property src_info {type:XDC file:4 line:269 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:270 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
||||
set_property src_info {type:XDC file:4 line:271 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
||||
set_property src_info {type:XDC file:4 line:272 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe45 [get_nets [list EMIO_0_tri_o_12]]
|
||||
set_property src_info {type:XDC file:4 line:273 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:274 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
||||
set_property src_info {type:XDC file:4 line:275 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
||||
set_property src_info {type:XDC file:4 line:276 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe46 [get_nets [list EMIO_0_tri_o_13]]
|
||||
set_property src_info {type:XDC file:4 line:277 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:278 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
||||
set_property src_info {type:XDC file:4 line:279 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
||||
set_property src_info {type:XDC file:4 line:280 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe47 [get_nets [list EMIO_0_tri_o_14]]
|
||||
set_property src_info {type:XDC file:4 line:281 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:282 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
||||
set_property src_info {type:XDC file:4 line:283 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
||||
set_property src_info {type:XDC file:4 line:284 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe48 [get_nets [list EMIO_0_tri_o_15]]
|
||||
set_property src_info {type:XDC file:4 line:285 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:286 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
||||
set_property src_info {type:XDC file:4 line:287 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
||||
set_property src_info {type:XDC file:4 line:288 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe49 [get_nets [list EMIO_0_tri_o_16]]
|
||||
set_property src_info {type:XDC file:4 line:289 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:290 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
||||
set_property src_info {type:XDC file:4 line:291 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
||||
set_property src_info {type:XDC file:4 line:292 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe50 [get_nets [list EMIO_0_tri_o_17]]
|
||||
set_property src_info {type:XDC file:4 line:293 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:294 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
||||
set_property src_info {type:XDC file:4 line:295 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
||||
set_property src_info {type:XDC file:4 line:296 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe51 [get_nets [list EMIO_0_tri_o_18]]
|
||||
set_property src_info {type:XDC file:4 line:297 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:298 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
|
||||
set_property src_info {type:XDC file:4 line:299 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe52]
|
||||
set_property src_info {type:XDC file:4 line:300 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe52 [get_nets [list EMIO_0_tri_o_19]]
|
||||
set_property src_info {type:XDC file:4 line:301 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:302 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
|
||||
set_property src_info {type:XDC file:4 line:303 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe53]
|
||||
set_property src_info {type:XDC file:4 line:304 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe53 [get_nets [list EMIO_0_tri_o_20]]
|
||||
set_property src_info {type:XDC file:4 line:305 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:306 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
|
||||
set_property src_info {type:XDC file:4 line:307 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe54]
|
||||
set_property src_info {type:XDC file:4 line:308 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe54 [get_nets [list EMIO_0_tri_o_21]]
|
||||
set_property src_info {type:XDC file:4 line:309 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:310 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
|
||||
set_property src_info {type:XDC file:4 line:311 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe55]
|
||||
set_property src_info {type:XDC file:4 line:312 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe55 [get_nets [list EMIO_0_tri_o_22]]
|
||||
set_property src_info {type:XDC file:4 line:313 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:314 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
|
||||
set_property src_info {type:XDC file:4 line:315 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe56]
|
||||
set_property src_info {type:XDC file:4 line:316 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe56 [get_nets [list EMIO_0_tri_o_23]]
|
||||
set_property src_info {type:XDC file:4 line:317 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:318 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
|
||||
set_property src_info {type:XDC file:4 line:319 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe57]
|
||||
set_property src_info {type:XDC file:4 line:320 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe57 [get_nets [list EMIO_0_tri_o_24]]
|
||||
set_property src_info {type:XDC file:4 line:321 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:322 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
|
||||
set_property src_info {type:XDC file:4 line:323 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe58]
|
||||
set_property src_info {type:XDC file:4 line:324 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe58 [get_nets [list EMIO_0_tri_o_25]]
|
||||
set_property src_info {type:XDC file:4 line:325 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:326 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
|
||||
set_property src_info {type:XDC file:4 line:327 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe59]
|
||||
set_property src_info {type:XDC file:4 line:328 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe59 [get_nets [list EMIO_0_tri_o_26]]
|
||||
set_property src_info {type:XDC file:4 line:329 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:330 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
|
||||
set_property src_info {type:XDC file:4 line:331 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe60]
|
||||
set_property src_info {type:XDC file:4 line:332 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe60 [get_nets [list EMIO_0_tri_o_27]]
|
||||
set_property src_info {type:XDC file:4 line:333 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:334 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
|
||||
set_property src_info {type:XDC file:4 line:335 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe61]
|
||||
set_property src_info {type:XDC file:4 line:336 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe61 [get_nets [list EMIO_0_tri_o_28]]
|
||||
set_property src_info {type:XDC file:4 line:337 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:338 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
|
||||
set_property src_info {type:XDC file:4 line:339 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe62]
|
||||
set_property src_info {type:XDC file:4 line:340 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe62 [get_nets [list EMIO_0_tri_o_29]]
|
||||
set_property src_info {type:XDC file:4 line:341 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:342 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
|
||||
set_property src_info {type:XDC file:4 line:343 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe63]
|
||||
set_property src_info {type:XDC file:4 line:344 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe63 [get_nets [list EMIO_0_tri_o_30]]
|
||||
set_property src_info {type:XDC file:4 line:345 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:346 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
|
||||
set_property src_info {type:XDC file:4 line:347 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe64]
|
||||
set_property src_info {type:XDC file:4 line:348 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe64 [get_nets [list EMIO_0_tri_o_31]]
|
||||
set_property src_info {type:XDC file:4 line:349 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:350 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
|
||||
set_property src_info {type:XDC file:4 line:351 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe65]
|
||||
set_property src_info {type:XDC file:4 line:352 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe65 [get_nets [list EMIO_0_tri_o_32]]
|
||||
set_property src_info {type:XDC file:4 line:353 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:354 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
|
||||
set_property src_info {type:XDC file:4 line:355 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe66]
|
||||
set_property src_info {type:XDC file:4 line:356 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe66 [get_nets [list EMIO_0_tri_t_0]]
|
||||
set_property src_info {type:XDC file:4 line:357 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:358 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
|
||||
set_property src_info {type:XDC file:4 line:359 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe67]
|
||||
set_property src_info {type:XDC file:4 line:360 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe67 [get_nets [list EMIO_0_tri_t_1]]
|
||||
set_property src_info {type:XDC file:4 line:361 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:362 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
|
||||
set_property src_info {type:XDC file:4 line:363 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe68]
|
||||
set_property src_info {type:XDC file:4 line:364 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe68 [get_nets [list EMIO_0_tri_t_2]]
|
||||
set_property src_info {type:XDC file:4 line:365 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:366 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
|
||||
set_property src_info {type:XDC file:4 line:367 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe69]
|
||||
set_property src_info {type:XDC file:4 line:368 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe69 [get_nets [list EMIO_0_tri_t_3]]
|
||||
set_property src_info {type:XDC file:4 line:369 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:370 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
|
||||
set_property src_info {type:XDC file:4 line:371 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe70]
|
||||
set_property src_info {type:XDC file:4 line:372 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe70 [get_nets [list EMIO_0_tri_t_4]]
|
||||
set_property src_info {type:XDC file:4 line:373 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:374 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
|
||||
set_property src_info {type:XDC file:4 line:375 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe71]
|
||||
set_property src_info {type:XDC file:4 line:376 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe71 [get_nets [list EMIO_0_tri_t_5]]
|
||||
set_property src_info {type:XDC file:4 line:377 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:378 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72]
|
||||
set_property src_info {type:XDC file:4 line:379 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe72]
|
||||
set_property src_info {type:XDC file:4 line:380 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe72 [get_nets [list EMIO_0_tri_t_6]]
|
||||
set_property src_info {type:XDC file:4 line:381 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:382 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
|
||||
set_property src_info {type:XDC file:4 line:383 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe73]
|
||||
set_property src_info {type:XDC file:4 line:384 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe73 [get_nets [list EMIO_0_tri_t_7]]
|
||||
set_property src_info {type:XDC file:4 line:385 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:386 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74]
|
||||
set_property src_info {type:XDC file:4 line:387 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe74]
|
||||
set_property src_info {type:XDC file:4 line:388 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe74 [get_nets [list EMIO_0_tri_t_8]]
|
||||
set_property src_info {type:XDC file:4 line:389 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:390 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75]
|
||||
set_property src_info {type:XDC file:4 line:391 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe75]
|
||||
set_property src_info {type:XDC file:4 line:392 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe75 [get_nets [list EMIO_0_tri_t_9]]
|
||||
set_property src_info {type:XDC file:4 line:393 export:INPUT save:INPUT read:READ} [current_design]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property src_info {type:XDC file:4 line:394 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76]
|
||||
set_property src_info {type:XDC file:4 line:395 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe76]
|
||||
set_property src_info {type:XDC file:4 line:396 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port u_ila_0/probe76 [get_nets [list EMIO_0_tri_t_10]]
|
||||
set_property src_info {type:XDC file:4 line:397 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property src_info {type:XDC file:4 line:398 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property src_info {type:XDC file:4 line:399 export:INPUT save:INPUT read:READ} [current_design]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
set_property src_info {type:XDC file:4 line:400 export:INPUT save:INPUT read:READ} [current_design]
|
||||
connect_debug_port dbg_hub/clk [get_nets u_ila_0_FCLK_CLK0]
|
||||
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="ly0kos" Host="mkb" Pid="958816" HostCore="32" HostMemory="131002412">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
Executable
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
Executable
+85
@@ -0,0 +1,85 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# XDC: new/pin_cons.xdc
|
||||
|
||||
# XDC: new/pin_debug.xdc
|
||||
|
||||
# Block Designs: bd/system/system.bd
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system || ORIG_REF_NAME==system} -quiet] -quiet
|
||||
|
||||
# IP: bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system_processing_system7_0_0 || ORIG_REF_NAME==system_processing_system7_0_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/system/ip/system_dna_port_read_0_0/system_dna_port_read_0_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system_dna_port_read_0_0 || ORIG_REF_NAME==system_dna_port_read_0_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/system/ip/system_mydna_read_v1_0_0_0/system_mydna_read_v1_0_0_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system_mydna_read_v1_0_0_0 || ORIG_REF_NAME==system_mydna_read_v1_0_0_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/system/ip/system_auto_pc_0/system_auto_pc_0.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system_auto_pc_0 || ORIG_REF_NAME==system_auto_pc_0} -quiet] -quiet
|
||||
|
||||
# IP: bd/system/ip/system_ps7_0_axi_periph_1/system_ps7_0_axi_periph_1.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system_ps7_0_axi_periph_1 || ORIG_REF_NAME==system_ps7_0_axi_periph_1} -quiet] -quiet
|
||||
|
||||
# IP: bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xci
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells -hier -filter {REF_NAME==system_rst_ps7_0_100M_1 || ORIG_REF_NAME==system_rst_ps7_0_100M_1} -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filter {REF_NAME==system_processing_system7_0_0 || ORIG_REF_NAME==system_processing_system7_0_0} -quiet] {/inst } ]/inst ] -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc
|
||||
set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filter {REF_NAME==system_rst_ps7_0_100M_1 || ORIG_REF_NAME==system_rst_ps7_0_100M_1} -quiet] {/U0 } ]/U0 ] -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc
|
||||
#dup# set_property KEEP_HIERARCHY SOFT [get_cells [split [join [get_cells -hier -filter {REF_NAME==system_rst_ps7_0_100M_1 || ORIG_REF_NAME==system_rst_ps7_0_100M_1} -quiet] {/U0 } ]/U0 ] -quiet] -quiet
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_ooc.xdc
|
||||
|
||||
# XDC: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/system_ooc.xdc
|
||||
@@ -0,0 +1,98 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="synth_1" LaunchPart="xc7z035ffg676-2" LaunchTime="1779870965">
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="system_wrapper_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="system_wrapper.dcp"/>
|
||||
<File Type="RDS-UTIL-PB" Name="system_wrapper_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="system_wrapper_utilization_synth.rpt"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="system_wrapper_drc_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="system_wrapper.vds"/>
|
||||
<File Type="REPORTS-TCL" Name="system_wrapper_reports.tcl"/>
|
||||
<File Type="VDS-TIMING-PB" Name="system_wrapper_timing_summary_synth.pb"/>
|
||||
<File Type="PA-TCL" Name="system_wrapper.tcl"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/src/dna_port_read.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/sources_1/src/dna_port_read.v"/>
|
||||
<Attr Name="ImportTime" Val="1779770889"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/src/mydna_read_v1_0_S00_AXI.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v"/>
|
||||
<Attr Name="ImportTime" Val="1779770889"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/src/mydna_read_v1_0.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/sources_1/src/mydna_read_v1_0.v"/>
|
||||
<Attr Name="ImportTime" Val="1779770889"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/bd/system/system.bd">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/sources_1/bd/system/system.bd"/>
|
||||
<Attr Name="ImportTime" Val="1779870939"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PGENDIR/sources_1/bd/system/hdl/system_wrapper.v">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.gen/sources_1/bd/system/hdl/system_wrapper.v"/>
|
||||
<Attr Name="ImportTime" Val="1779691907"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="system_wrapper"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PSRCDIR/constrs_1/new/pin_cons.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/constrs_1/new/pin_cons.xdc"/>
|
||||
<Attr Name="ImportTime" Val="1779869379"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/constrs_1/new/pin_debug.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="ImportPath" Val="$PPRDIR/../proj_cal/proj_cal.srcs/constrs_1/new/pin_debug.xdc"/>
|
||||
<Attr Name="ImportTime" Val="1779869379"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/pin_debug.xdc"/>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
@@ -0,0 +1,10 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
|
||||
@@ -0,0 +1,41 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;";
|
||||
} else {
|
||||
PathVal = "/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/data/xilinx/Vivado/2023.2/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
@@ -0,0 +1,12 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
@@ -0,0 +1,696 @@
|
||||
|
||||
*** Running vivado
|
||||
with args -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
|
||||
|
||||
|
||||
****** Vivado v2023.2 (64-bit)
|
||||
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
source system_wrapper.tcl -notrace
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
|
||||
Command: synth_design -top system_wrapper -part xc7z035ffg676-2
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 958941
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2149.453 ; gain = 411.629 ; free physical = 845 ; free virtual = 70077
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-11121] redeclaration of ANSI port 'read_vld' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:33]
|
||||
WARNING: [Synth 8-11121] redeclaration of ANSI port 'dna_port' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:34]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system_wrapper' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13]
|
||||
INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system_dna_port_read_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'dna_port_read' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23]
|
||||
INFO: [Synth 8-6157] synthesizing module 'DNA_PORT' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264]
|
||||
Parameter SIM_DNA_VALUE bound to: 57'b000000000000000000000000000000000000000000000000000000000
|
||||
INFO: [Synth 8-6155] done synthesizing module 'DNA_PORT' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'dna_port_read' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system_dna_port_read_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system_mydna_read_v1_0_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4]
|
||||
Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer
|
||||
Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer
|
||||
INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4]
|
||||
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
||||
Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:235]
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:379]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system_mydna_read_v1_0_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system_processing_system7_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BIBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
|
||||
INFO: [Synth 8-6157] synthesizing module 'PS7' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'PS7' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
|
||||
WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system_processing_system7_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system_ps7_0_axi_periph_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632]
|
||||
INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_11SE3QO' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system_auto_pc_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392]
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3446]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546]
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3608]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
|
||||
WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'SI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871]
|
||||
WARNING: [Synth 8-7023] instance 'SI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
|
||||
WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'MI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126]
|
||||
WARNING: [Synth 8-7023] instance 'MI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system_auto_pc_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53]
|
||||
INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_11SE3QO' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system_ps7_0_axi_periph_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632]
|
||||
INFO: [Synth 8-638] synthesizing module 'system_rst_ps7_0_100M_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74]
|
||||
Parameter C_FAMILY bound to: zynq - type: string
|
||||
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_EXT_RESET_HIGH bound to: 1'b0
|
||||
Parameter C_AUX_RESET_HIGH bound to: 1'b0
|
||||
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
|
||||
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
|
||||
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
|
||||
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
|
||||
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:129]
|
||||
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
|
||||
Parameter INIT bound to: 1'b1
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399]
|
||||
Parameter INIT bound to: 1'b1
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441]
|
||||
Parameter INIT bound to: 1'b1
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488]
|
||||
INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
|
||||
INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873]
|
||||
INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
|
||||
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
|
||||
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
|
||||
INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
|
||||
INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
|
||||
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
|
||||
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
|
||||
INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
|
||||
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
|
||||
INFO: [Synth 8-256] done synthesizing module 'system_rst_ps7_0_100M_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74]
|
||||
WARNING: [Synth 8-7071] port 'mb_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
|
||||
WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
|
||||
WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
|
||||
WARNING: [Synth 8-7023] instance 'rst_ps7_0_100M' of module 'system_rst_ps7_0_100M_1' has 10 connections declared, but only 7 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system_wrapper' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13]
|
||||
WARNING: [Synth 8-6014] Unused sequential element slv_reg1_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:228]
|
||||
WARNING: [Synth 8-6014] Unused sequential element slv_reg2_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:229]
|
||||
WARNING: [Synth 8-6014] Unused sequential element state_r1_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3596]
|
||||
WARNING: [Synth 8-6014] Unused sequential element s_arlen_r_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3597]
|
||||
WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_bid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_rid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_rlast in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_wid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_wlast in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_arlen[7] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_arlen[6] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_arlen[5] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_arlen[4] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_arlen[3] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_arlen[2] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
|
||||
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 767 ; free virtual = 69885
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2359.391 ; gain = 0.000 ; free physical = 749 ; free virtual = 69874
|
||||
INFO: [Netlist 29-17] Analyzing 46 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2518.867 ; gain = 0.000 ; free physical = 714 ; free virtual = 69858
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 46 instances were transformed.
|
||||
FDR => FDRE: 12 instances
|
||||
IOBUF => IOBUF (IBUF, OBUFT): 33 instances
|
||||
SRL16 => SRL16E: 1 instance
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 872 ; free virtual = 69870
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 946 ; free virtual = 69833
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z035ffg676-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 945 ; free virtual = 69833
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 1).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_1. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 2).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_2. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 3).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_3. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 4).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_4. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 5).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_5. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 6).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_6. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 7).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_7. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 8).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_8. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 9).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_9. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 10).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_10. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 11).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_11. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 12).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_12. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 13).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_13. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 14).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_14. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 15).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_15. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 16).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_16. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 17).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_17. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 18).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_18. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 19).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_19. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 20).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_20. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 21).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_21. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 22).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_22. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 23).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_23. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 24).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_24. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 25).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_25. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 26).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_28. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 27).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_29. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 28).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_30. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 29).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_26. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 30).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_27. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 31).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_31. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 32).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_32. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 33).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_o_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 34).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_t_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 67).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0/inst. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 30).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M/U0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 35).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i. (constraint file auto generated constraint).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0. (constraint file auto generated constraint).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/dna_port_read_0. (constraint file auto generated constraint).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/mydna_read_v1_0_0. (constraint file auto generated constraint).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph/s00_couplers/auto_pc. (constraint file auto generated constraint).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph. (constraint file auto generated constraint).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M. (constraint file auto generated constraint).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 940 ; free virtual = 69830
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm'
|
||||
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm'
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_0'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:213]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_1'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:218]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_2'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:273]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_3'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:328]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_4'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:348]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_5'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:353]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_6'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:358]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_7'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:363]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_8'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:368]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_9'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:373]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_10'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:223]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_11'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:228]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_12'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:233]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_13'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:238]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_14'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:243]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_15'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:248]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_16'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:253]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_17'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:258]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_18'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:263]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_19'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:268]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_20'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:278]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_21'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:283]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_22'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:288]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_23'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:293]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_24'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:298]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_25'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:303]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_28'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:318]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_29'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:323]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_30'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:333]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_26'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:308]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_27'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:313]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_31'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:338]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_32'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:343]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'dna_port_reg_reg' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:413]
|
||||
---------------------------------------------------------------------------------------------------
|
||||
State | New Encoding | Previous Encoding
|
||||
---------------------------------------------------------------------------------------------------
|
||||
SM_IDLE | 01 | 00
|
||||
SM_CMD_EN | 11 | 01
|
||||
SM_CMD_ACCEPTED | 10 | 10
|
||||
SM_DONE_WAIT | 00 | 11
|
||||
---------------------------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm'
|
||||
---------------------------------------------------------------------------------------------------
|
||||
State | New Encoding | Previous Encoding
|
||||
---------------------------------------------------------------------------------------------------
|
||||
SM_IDLE | 01 | 00
|
||||
SM_CMD_EN | 11 | 01
|
||||
SM_CMD_ACCEPTED | 10 | 10
|
||||
SM_DONE | 00 | 11
|
||||
---------------------------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm'
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 929 ; free virtual = 69825
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 12 Bit Adders := 8
|
||||
2 Input 9 Bit Adders := 2
|
||||
2 Input 8 Bit Adders := 2
|
||||
2 Input 6 Bit Adders := 1
|
||||
2 Input 5 Bit Adders := 4
|
||||
2 Input 4 Bit Adders := 4
|
||||
2 Input 2 Bit Adders := 2
|
||||
+---Registers :
|
||||
66 Bit Registers := 4
|
||||
57 Bit Registers := 1
|
||||
47 Bit Registers := 2
|
||||
32 Bit Registers := 3
|
||||
14 Bit Registers := 2
|
||||
12 Bit Registers := 9
|
||||
9 Bit Registers := 2
|
||||
8 Bit Registers := 3
|
||||
6 Bit Registers := 1
|
||||
5 Bit Registers := 4
|
||||
4 Bit Registers := 8
|
||||
3 Bit Registers := 3
|
||||
2 Bit Registers := 9
|
||||
1 Bit Registers := 43
|
||||
+---Muxes :
|
||||
2 Input 66 Bit Muxes := 4
|
||||
2 Input 47 Bit Muxes := 2
|
||||
4 Input 32 Bit Muxes := 3
|
||||
2 Input 32 Bit Muxes := 9
|
||||
2 Input 14 Bit Muxes := 2
|
||||
2 Input 12 Bit Muxes := 6
|
||||
2 Input 9 Bit Muxes := 4
|
||||
2 Input 8 Bit Muxes := 1
|
||||
2 Input 6 Bit Muxes := 1
|
||||
2 Input 5 Bit Muxes := 4
|
||||
2 Input 4 Bit Muxes := 18
|
||||
2 Input 2 Bit Muxes := 17
|
||||
4 Input 2 Bit Muxes := 4
|
||||
2 Input 1 Bit Muxes := 37
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 900 (col length:140)
|
||||
BRAMs: 1000 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
|
||||
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (FDRE_inst) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (BSR_OUT_DFF[0].FDRE_BSR) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (PR_OUT_DFF[0].FDRE_PER) is unused and will be removed from module proc_sys_reset.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1838 ; free virtual = 70743
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1815 ; free virtual = 70747
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1781 ; free virtual = 70713
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1765 ; free virtual = 70711
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Dynamic Shift Register Report:
|
||||
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|
||||
|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
|
||||
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|
||||
|dsrl | memory_reg[3] | 20 | 20 | 20 | 0 | 0 | 0 | 0 |
|
||||
|dsrl__1 | memory_reg[3] | 2 | 2 | 2 | 0 | 0 | 0 | 0 |
|
||||
|dsrl__2 | memory_reg[31] | 34 | 34 | 0 | 34 | 0 | 0 | 0 |
|
||||
|dsrl__3 | memory_reg[31] | 13 | 13 | 0 | 13 | 0 | 0 | 0 |
|
||||
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+---------+------+
|
||||
| |Cell |Count |
|
||||
+------+---------+------+
|
||||
|1 |BIBUF | 130|
|
||||
|2 |BUFG | 1|
|
||||
|3 |CARRY4 | 6|
|
||||
|4 |DNA_PORT | 1|
|
||||
|5 |LUT1 | 69|
|
||||
|6 |LUT2 | 24|
|
||||
|7 |LUT3 | 169|
|
||||
|8 |LUT4 | 52|
|
||||
|9 |LUT5 | 71|
|
||||
|10 |LUT6 | 118|
|
||||
|11 |PS7 | 1|
|
||||
|12 |SRL16 | 1|
|
||||
|13 |SRL16E | 16|
|
||||
|14 |SRLC32E | 45|
|
||||
|15 |FDCE | 66|
|
||||
|16 |FDR | 4|
|
||||
|17 |FDRE | 501|
|
||||
|18 |FDSE | 20|
|
||||
|19 |LD | 57|
|
||||
|20 |IOBUF | 33|
|
||||
+------+---------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 136 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 618.598 ; free physical = 1531 ; free virtual = 70510
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1531 ; free virtual = 70509
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 1748 ; free virtual = 70732
|
||||
INFO: [Netlist 29-17] Analyzing 101 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2563.766 ; gain = 0.000 ; free physical = 1757 ; free virtual = 70743
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 95 instances were transformed.
|
||||
FDR => FDRE: 4 instances
|
||||
IOBUF => IOBUF (IBUF, OBUFT): 33 instances
|
||||
LD => LDCE: 57 instances
|
||||
SRL16 => SRL16E: 1 instance
|
||||
|
||||
Synth Design complete | Checksum: 8993d7c
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
187 Infos, 142 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2563.801 ; gain = 1259.379 ; free physical = 1759 ; free virtual = 70746
|
||||
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1991.605; main = 1727.861; forked = 379.983
|
||||
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3465.613; main = 2563.770; forked = 1042.766
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2611.777 ; gain = 0.000 ; free physical = 1758 ; free virtual = 70746
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:36:31 2026...
|
||||
Executable
+40
@@ -0,0 +1,40 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin
|
||||
else
|
||||
PATH=/data/xilinx/Vitis/2023.2/bin:/data/xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/data/xilinx/Vivado/2023.2/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
|
||||
Binary file not shown.
@@ -0,0 +1,143 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
namespace eval ::optrace {
|
||||
variable script "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.tcl"
|
||||
variable category "vivado_synth"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
OPTRACE "synth_1" START { ROLLUP_AUTO }
|
||||
set_param chipscope.maxJobs 8
|
||||
set_msg_config -id {HDL-1065} -limit 10000
|
||||
OPTRACE "Creating in-memory project" START { }
|
||||
create_project -in_memory -part xc7z035ffg676-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.cache/wt [current_project]
|
||||
set_property parent.project_path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "Creating in-memory project" END { }
|
||||
OPTRACE "Adding files" START { }
|
||||
read_verilog -library xil_defaultlib {
|
||||
/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v
|
||||
/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v
|
||||
/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v
|
||||
/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v
|
||||
}
|
||||
add_files /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/bd/system/system.bd
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/system_auto_pc_0_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_ooc.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/system_ooc.xdc]
|
||||
|
||||
OPTRACE "Adding files" END { }
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc
|
||||
set_property used_in_implementation false [get_files /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
|
||||
|
||||
read_xdc /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc
|
||||
set_property used_in_implementation false [get_files /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
|
||||
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
OPTRACE "synth_design" START { }
|
||||
synth_design -top system_wrapper -part xc7z035ffg676-2
|
||||
OPTRACE "synth_design" END { }
|
||||
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||
}
|
||||
|
||||
|
||||
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef system_wrapper.dcp
|
||||
OPTRACE "write_checkpoint" END { }
|
||||
OPTRACE "synth reports" START { REPORT }
|
||||
create_report "synth_1_synth_report_utilization_0" "report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb"
|
||||
OPTRACE "synth reports" END { }
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
OPTRACE "synth_1" END { }
|
||||
@@ -0,0 +1,697 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Wed May 27 16:36:06 2026
|
||||
# Process ID: 958858
|
||||
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1
|
||||
# Command line: vivado -log system_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
|
||||
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.vds
|
||||
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/vivado.jou
|
||||
# Running On: mkb, OS: Linux, CPU Frequency: 4933.113 MHz, CPU Physical cores: 32, Host memory: 134146 MB
|
||||
#-----------------------------------------------------------
|
||||
source system_wrapper.tcl -notrace
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'.
|
||||
Command: synth_design -top system_wrapper -part xc7z035ffg676-2
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035'
|
||||
INFO: [Device 21-403] Loading part xc7z035ffg676-2
|
||||
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
|
||||
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||
INFO: [Synth 8-7075] Helper process launched with PID 958941
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2149.453 ; gain = 411.629 ; free physical = 845 ; free virtual = 70077
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-11121] redeclaration of ANSI port 'read_vld' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:33]
|
||||
WARNING: [Synth 8-11121] redeclaration of ANSI port 'dna_port' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:34]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system_wrapper' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13]
|
||||
INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system_dna_port_read_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'dna_port_read' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23]
|
||||
INFO: [Synth 8-6157] synthesizing module 'DNA_PORT' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264]
|
||||
Parameter SIM_DNA_VALUE bound to: 57'b000000000000000000000000000000000000000000000000000000000
|
||||
INFO: [Synth 8-6155] done synthesizing module 'DNA_PORT' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'dna_port_read' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system_dna_port_read_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system_mydna_read_v1_0_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4]
|
||||
Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer
|
||||
Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer
|
||||
INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4]
|
||||
Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer
|
||||
Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:235]
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:379]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system_mydna_read_v1_0_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system_processing_system7_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
|
||||
INFO: [Synth 8-6157] synthesizing module 'BIBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598]
|
||||
INFO: [Synth 8-6157] synthesizing module 'PS7' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'PS7' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152]
|
||||
WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system_processing_system7_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system_ps7_0_axi_periph_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632]
|
||||
INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_11SE3QO' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13]
|
||||
INFO: [Synth 8-6157] synthesizing module 'system_auto_pc_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392]
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3446]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546]
|
||||
INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3608]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
|
||||
WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'SI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871]
|
||||
WARNING: [Synth 8-7023] instance 'SI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718]
|
||||
WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'MI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126]
|
||||
WARNING: [Synth 8-7023] instance 'MI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system_auto_pc_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53]
|
||||
INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_11SE3QO' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system_ps7_0_axi_periph_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632]
|
||||
INFO: [Synth 8-638] synthesizing module 'system_rst_ps7_0_100M_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74]
|
||||
Parameter C_FAMILY bound to: zynq - type: string
|
||||
Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_EXT_RESET_HIGH bound to: 1'b0
|
||||
Parameter C_AUX_RESET_HIGH bound to: 1'b0
|
||||
Parameter C_NUM_BUS_RST bound to: 1 - type: integer
|
||||
Parameter C_NUM_PERP_RST bound to: 1 - type: integer
|
||||
Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer
|
||||
Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer
|
||||
INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:129]
|
||||
INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
|
||||
Parameter INIT bound to: 1'b1
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399]
|
||||
Parameter INIT bound to: 1'b1
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441]
|
||||
Parameter INIT bound to: 1'b1
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488]
|
||||
INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
|
||||
INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873]
|
||||
INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721]
|
||||
INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574]
|
||||
Parameter INIT bound to: 1'b0
|
||||
INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584]
|
||||
INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106]
|
||||
INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821]
|
||||
INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
|
||||
INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
|
||||
INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126]
|
||||
INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304]
|
||||
INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330]
|
||||
INFO: [Synth 8-256] done synthesizing module 'system_rst_ps7_0_100M_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74]
|
||||
WARNING: [Synth 8-7071] port 'mb_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
|
||||
WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
|
||||
WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
|
||||
WARNING: [Synth 8-7023] instance 'rst_ps7_0_100M' of module 'system_rst_ps7_0_100M_1' has 10 connections declared, but only 7 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'system_wrapper' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13]
|
||||
WARNING: [Synth 8-6014] Unused sequential element slv_reg1_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:228]
|
||||
WARNING: [Synth 8-6014] Unused sequential element slv_reg2_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:229]
|
||||
WARNING: [Synth 8-6014] Unused sequential element state_r1_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3596]
|
||||
WARNING: [Synth 8-6014] Unused sequential element s_arlen_r_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3597]
|
||||
WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_bid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_rid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_rlast in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_wid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_wlast in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_arlen[7] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_arlen[6] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_arlen[5] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_arlen[4] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_arlen[3] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
|
||||
WARNING: [Synth 8-7129] Port s_arlen[2] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load
|
||||
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 767 ; free virtual = 69885
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891
|
||||
---------------------------------------------------------------------------------
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2359.391 ; gain = 0.000 ; free physical = 749 ; free virtual = 69874
|
||||
INFO: [Netlist 29-17] Analyzing 46 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0'
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]
|
||||
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc].
|
||||
Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2518.867 ; gain = 0.000 ; free physical = 714 ; free virtual = 69858
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 46 instances were transformed.
|
||||
FDR => FDRE: 12 instances
|
||||
IOBUF => IOBUF (IBUF, OBUFT): 33 instances
|
||||
SRL16 => SRL16E: 1 instance
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 872 ; free virtual = 69870
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 946 ; free virtual = 69833
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7z035ffg676-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 945 ; free virtual = 69833
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 1).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_1. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 2).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_2. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 3).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_3. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 4).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_4. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 5).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_5. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 6).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_6. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 7).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_7. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 8).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_8. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 9).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_9. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 10).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_10. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 11).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_11. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 12).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_12. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 13).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_13. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 14).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_14. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 15).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_15. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 16).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_16. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 17).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_17. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 18).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_18. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 19).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_19. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 20).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_20. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 21).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_21. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 22).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_22. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 23).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_23. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 24).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_24. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 25).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_25. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 26).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_28. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 27).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_29. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 28).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_30. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 29).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_26. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 30).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_27. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 31).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_31. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 32).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_32. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 33).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_o_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 34).
|
||||
Applied set_property MARK_DEBUG = true for EMIO_0_tri_t_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 67).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0/inst. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 30).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M/U0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 35).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i. (constraint file auto generated constraint).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0. (constraint file auto generated constraint).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/dna_port_read_0. (constraint file auto generated constraint).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/mydna_read_v1_0_0. (constraint file auto generated constraint).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph/s00_couplers/auto_pc. (constraint file auto generated constraint).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph. (constraint file auto generated constraint).
|
||||
Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M. (constraint file auto generated constraint).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 940 ; free virtual = 69830
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm'
|
||||
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm'
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_0'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:213]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_1'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:218]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_2'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:273]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_3'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:328]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_4'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:348]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_5'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:353]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_6'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:358]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_7'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:363]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_8'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:368]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_9'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:373]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_10'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:223]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_11'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:228]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_12'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:233]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_13'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:238]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_14'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:243]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_15'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:248]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_16'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:253]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_17'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:258]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_18'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:263]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_19'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:268]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_20'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:278]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_21'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:283]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_22'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:288]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_23'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:293]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_24'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:298]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_25'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:303]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_28'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:318]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_29'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:323]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_30'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:333]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_26'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:308]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_27'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:313]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_31'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:338]
|
||||
INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_32'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:343]
|
||||
WARNING: [Synth 8-327] inferring latch for variable 'dna_port_reg_reg' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:413]
|
||||
---------------------------------------------------------------------------------------------------
|
||||
State | New Encoding | Previous Encoding
|
||||
---------------------------------------------------------------------------------------------------
|
||||
SM_IDLE | 01 | 00
|
||||
SM_CMD_EN | 11 | 01
|
||||
SM_CMD_ACCEPTED | 10 | 10
|
||||
SM_DONE_WAIT | 00 | 11
|
||||
---------------------------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm'
|
||||
---------------------------------------------------------------------------------------------------
|
||||
State | New Encoding | Previous Encoding
|
||||
---------------------------------------------------------------------------------------------------
|
||||
SM_IDLE | 01 | 00
|
||||
SM_CMD_EN | 11 | 01
|
||||
SM_CMD_ACCEPTED | 10 | 10
|
||||
SM_DONE | 00 | 11
|
||||
---------------------------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm'
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 929 ; free virtual = 69825
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 12 Bit Adders := 8
|
||||
2 Input 9 Bit Adders := 2
|
||||
2 Input 8 Bit Adders := 2
|
||||
2 Input 6 Bit Adders := 1
|
||||
2 Input 5 Bit Adders := 4
|
||||
2 Input 4 Bit Adders := 4
|
||||
2 Input 2 Bit Adders := 2
|
||||
+---Registers :
|
||||
66 Bit Registers := 4
|
||||
57 Bit Registers := 1
|
||||
47 Bit Registers := 2
|
||||
32 Bit Registers := 3
|
||||
14 Bit Registers := 2
|
||||
12 Bit Registers := 9
|
||||
9 Bit Registers := 2
|
||||
8 Bit Registers := 3
|
||||
6 Bit Registers := 1
|
||||
5 Bit Registers := 4
|
||||
4 Bit Registers := 8
|
||||
3 Bit Registers := 3
|
||||
2 Bit Registers := 9
|
||||
1 Bit Registers := 43
|
||||
+---Muxes :
|
||||
2 Input 66 Bit Muxes := 4
|
||||
2 Input 47 Bit Muxes := 2
|
||||
4 Input 32 Bit Muxes := 3
|
||||
2 Input 32 Bit Muxes := 9
|
||||
2 Input 14 Bit Muxes := 2
|
||||
2 Input 12 Bit Muxes := 6
|
||||
2 Input 9 Bit Muxes := 4
|
||||
2 Input 8 Bit Muxes := 1
|
||||
2 Input 6 Bit Muxes := 1
|
||||
2 Input 5 Bit Muxes := 4
|
||||
2 Input 4 Bit Muxes := 18
|
||||
2 Input 2 Bit Muxes := 17
|
||||
4 Input 2 Bit Muxes := 4
|
||||
2 Input 1 Bit Muxes := 37
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 900 (col length:140)
|
||||
BRAMs: 1000 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
|
||||
INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726]
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (FDRE_inst) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (BSR_OUT_DFF[0].FDRE_BSR) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N) is unused and will be removed from module proc_sys_reset.
|
||||
WARNING: [Synth 8-3332] Sequential element (PR_OUT_DFF[0].FDRE_PER) is unused and will be removed from module proc_sys_reset.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1838 ; free virtual = 70743
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1815 ; free virtual = 70747
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1781 ; free virtual = 70713
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1765 ; free virtual = 70711
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Dynamic Shift Register Report:
|
||||
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|
||||
|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 |
|
||||
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|
||||
|dsrl | memory_reg[3] | 20 | 20 | 20 | 0 | 0 | 0 | 0 |
|
||||
|dsrl__1 | memory_reg[3] | 2 | 2 | 2 | 0 | 0 | 0 | 0 |
|
||||
|dsrl__2 | memory_reg[31] | 34 | 34 | 0 | 34 | 0 | 0 | 0 |
|
||||
|dsrl__3 | memory_reg[31] | 13 | 13 | 0 | 13 | 0 | 0 | 0 |
|
||||
+------------+----------------+--------+------------+--------+---------+--------+--------+--------+
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+---------+------+
|
||||
| |Cell |Count |
|
||||
+------+---------+------+
|
||||
|1 |BIBUF | 130|
|
||||
|2 |BUFG | 1|
|
||||
|3 |CARRY4 | 6|
|
||||
|4 |DNA_PORT | 1|
|
||||
|5 |LUT1 | 69|
|
||||
|6 |LUT2 | 24|
|
||||
|7 |LUT3 | 169|
|
||||
|8 |LUT4 | 52|
|
||||
|9 |LUT5 | 71|
|
||||
|10 |LUT6 | 118|
|
||||
|11 |PS7 | 1|
|
||||
|12 |SRL16 | 1|
|
||||
|13 |SRL16E | 16|
|
||||
|14 |SRLC32E | 45|
|
||||
|15 |FDCE | 66|
|
||||
|16 |FDR | 4|
|
||||
|17 |FDRE | 501|
|
||||
|18 |FDSE | 20|
|
||||
|19 |LD | 57|
|
||||
|20 |IOBUF | 33|
|
||||
+------+---------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 136 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 618.598 ; free physical = 1531 ; free virtual = 70510
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1531 ; free virtual = 70509
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 1748 ; free virtual = 70732
|
||||
INFO: [Netlist 29-17] Analyzing 101 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2563.766 ; gain = 0.000 ; free physical = 1757 ; free virtual = 70743
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 95 instances were transformed.
|
||||
FDR => FDRE: 4 instances
|
||||
IOBUF => IOBUF (IBUF, OBUFT): 33 instances
|
||||
LD => LDCE: 57 instances
|
||||
SRL16 => SRL16E: 1 instance
|
||||
|
||||
Synth Design complete | Checksum: 8993d7c
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
187 Infos, 142 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2563.801 ; gain = 1259.379 ; free physical = 1759 ; free virtual = 70746
|
||||
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1991.605; main = 1727.861; forked = 379.983
|
||||
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3465.613; main = 2563.770; forked = 1042.766
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2611.777 ; gain = 0.000 ; free physical = 1758 ; free virtual = 70746
|
||||
INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:36:31 2026...
|
||||
Binary file not shown.
@@ -0,0 +1,196 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Wed May 27 16:36:31 2026
|
||||
| Host : mkb running 64-bit unknown
|
||||
| Command : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb
|
||||
| Design : system_wrapper
|
||||
| Device : xc7z035ffg676-2
|
||||
| Speed File : -2
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+----------------------------+------+-------+------------+-----------+-------+
|
||||
| Slice LUTs* | 470 | 0 | 0 | 171900 | 0.27 |
|
||||
| LUT as Logic | 408 | 0 | 0 | 171900 | 0.24 |
|
||||
| LUT as Memory | 62 | 0 | 0 | 70400 | 0.09 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | | |
|
||||
| LUT as Shift Register | 62 | 0 | | | |
|
||||
| Slice Registers | 648 | 0 | 0 | 343800 | 0.19 |
|
||||
| Register as Flip Flop | 591 | 0 | 0 | 343800 | 0.17 |
|
||||
| Register as Latch | 57 | 0 | 0 | 343800 | 0.02 |
|
||||
| F7 Muxes | 0 | 0 | 0 | 109300 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 0 | 54650 | 0.00 |
|
||||
+----------------------------+------+-------+------------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
Warning! LUT value is adjusted to account for LUT combining.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 123 | Yes | - | Reset |
|
||||
| 20 | Yes | Set | - |
|
||||
| 505 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 0 | 500 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 0 | 500 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 0 | 1000 | 0.00 |
|
||||
+----------------+------+-------+------------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 0 | 900 | 0.00 |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+------------+-----------+--------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------------------------+------+-------+------------+-----------+--------+
|
||||
| Bonded IOB | 33 | 0 | 0 | 250 | 13.20 |
|
||||
| Bonded IPADs | 0 | 0 | 0 | 26 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 0 | 16 | 0.00 |
|
||||
| Bonded IOPADs | 130 | 0 | 0 | 130 | 100.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 0 | 240 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 400 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 0 | 250 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 0 | 250 | 0.00 |
|
||||
+-----------------------------+------+-------+------------+-----------+--------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 |
|
||||
| BUFIO | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 0 | 16 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 0 | 32 | 0.00 |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+------------+-----------+--------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------+------+-------+------------+-----------+--------+
|
||||
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 1 | 0 | 0 | 1 | 100.00 |
|
||||
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+------------+-----------+--------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+----------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+----------------------+
|
||||
| FDRE | 505 | Flop & Latch |
|
||||
| LUT3 | 169 | LUT |
|
||||
| BIBUF | 130 | IO |
|
||||
| LUT6 | 118 | LUT |
|
||||
| LUT5 | 71 | LUT |
|
||||
| LUT1 | 69 | LUT |
|
||||
| FDCE | 66 | Flop & Latch |
|
||||
| LDCE | 57 | Flop & Latch |
|
||||
| LUT4 | 52 | LUT |
|
||||
| SRLC32E | 45 | Distributed Memory |
|
||||
| OBUFT | 33 | IO |
|
||||
| IBUF | 33 | IO |
|
||||
| LUT2 | 24 | LUT |
|
||||
| FDSE | 20 | Flop & Latch |
|
||||
| SRL16E | 17 | Distributed Memory |
|
||||
| CARRY4 | 6 | CarryLogic |
|
||||
| PS7 | 1 | Specialized Resource |
|
||||
| DNA_PORT | 1 | Others |
|
||||
| BUFG | 1 | Clock |
|
||||
+----------+------+----------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Wed May 27 16:36:06 2026
|
||||
# Process ID: 958858
|
||||
# Current directory: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1
|
||||
# Command line: vivado -log system_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl
|
||||
# Log file: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.vds
|
||||
# Journal file: /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/vivado.jou
|
||||
# Running On: mkb, OS: Linux, CPU Frequency: 4933.113 MHz, CPU Physical cores: 32, Host memory: 134146 MB
|
||||
#-----------------------------------------------------------
|
||||
source system_wrapper.tcl -notrace
|
||||
Binary file not shown.
Reference in New Issue
Block a user