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This commit is contained in:
Jeremy Shen
2026-05-27 09:56:09 +00:00
commit ee3ede1152
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Debug_FW.ip_user_files/sim_scripts/system/activehdl/README.txt
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################################################################################
# Vivado (TM) v2023.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Mon May 25 15:47:32 CST 2026
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./system.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './system.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
Debug_FW.ip_user_files/sim_scripts/system/activehdl/compile.do
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transcript off
onbreak {quit -force}
onerror {quit -force}
transcript on
vlib work
vlib activehdl/xilinx_vip
vlib activehdl/xpm
vlib activehdl/axi_infrastructure_v1_1_0
vlib activehdl/axi_vip_v1_1_15
vlib activehdl/processing_system7_vip_v1_0_17
vlib activehdl/xil_defaultlib
vlib activehdl/lib_cdc_v1_0_2
vlib activehdl/proc_sys_reset_v5_0_14
vlib activehdl/generic_baseblocks_v2_1_1
vlib activehdl/fifo_generator_v13_2_9
vlib activehdl/axi_data_fifo_v2_1_28
vlib activehdl/axi_register_slice_v2_1_29
vlib activehdl/axi_protocol_converter_v2_1_29
vmap xilinx_vip activehdl/xilinx_vip
vmap xpm activehdl/xpm
vmap axi_infrastructure_v1_1_0 activehdl/axi_infrastructure_v1_1_0
vmap axi_vip_v1_1_15 activehdl/axi_vip_v1_1_15
vmap processing_system7_vip_v1_0_17 activehdl/processing_system7_vip_v1_0_17
vmap xil_defaultlib activehdl/xil_defaultlib
vmap lib_cdc_v1_0_2 activehdl/lib_cdc_v1_0_2
vmap proc_sys_reset_v5_0_14 activehdl/proc_sys_reset_v5_0_14
vmap generic_baseblocks_v2_1_1 activehdl/generic_baseblocks_v2_1_1
vmap fifo_generator_v13_2_9 activehdl/fifo_generator_v13_2_9
vmap axi_data_fifo_v2_1_28 activehdl/axi_data_fifo_v2_1_28
vmap axi_register_slice_v2_1_29 activehdl/axi_register_slice_v2_1_29
vmap axi_protocol_converter_v2_1_29 activehdl/axi_protocol_converter_v2_1_29
vlog -work xilinx_vip -sv2k12 "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
vlog -work xpm -sv2k12 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm - \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work axi_infrastructure_v1_1_0 -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \
vlog -work axi_vip_v1_1_15 -sv2k12 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv" \
vlog -work processing_system7_vip_v1_0_17 -sv2k12 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \
vlog -work xil_defaultlib -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v" \
"../../../bd/system/ip/system_dna_port_read_0_0/sim/system_dna_port_read_0_0.v" \
"../../../bd/system/ip/system_mydna_read_v1_0_0_0/sim/system_mydna_read_v1_0_0_0.v" \
vcom -work lib_cdc_v1_0_2 - \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \
vcom -work proc_sys_reset_v5_0_14 - \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
vcom -work xil_defaultlib - \
"../../../bd/system/ip/system_rst_ps7_0_100M_1/sim/system_rst_ps7_0_100M_1.vhd" \
vlog -work generic_baseblocks_v2_1_1 -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
vlog -work fifo_generator_v13_2_9 -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_2_9 - \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd" \
vlog -work fifo_generator_v13_2_9 -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v" \
vlog -work axi_data_fifo_v2_1_28 -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v" \
vlog -work axi_register_slice_v2_1_29 -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v" \
vlog -work axi_protocol_converter_v2_1_29 -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v" \
vlog -work xil_defaultlib -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../bd/system/ip/system_auto_pc_0/sim/system_auto_pc_0.v" \
"../../../bd/system/sim/system.v" \
vlog -work xil_defaultlib \
"glbl.v"
Debug_FW.ip_user_files/sim_scripts/system/activehdl/file_info.txt
+31
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@@ -0,0 +1,31 @@
axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_cdc.sv,systemverilog,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_memory.sv,systemverilog,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_15,../../../../proj_cal.gen/sources_1/bd/system/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_17,../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_dna_port_read_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_dna_port_read_0_0/sim/system_dna_port_read_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_mydna_read_v1_0_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_mydna_read_v1_0_0_0/sim/system_mydna_read_v1_0_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_14,../../../../proj_cal.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_rst_ps7_0_100M_1.vhd,vhdl,xil_defaultlib,../../../bd/system/ip/system_rst_ps7_0_100M_1/sim/system_rst_ps7_0_100M_1.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_1,../../../../proj_cal.gen/sources_1/bd/system/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/simulation/fifo_generator_vlog_beh.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_28,../../../../proj_cal.gen/sources_1/bd/system/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_register_slice_v2_1_vl_rfs.v,verilog,axi_register_slice_v2_1_29,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../proj_cal.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_auto_pc_0/sim/system_auto_pc_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
Debug_FW.ip_user_files/sim_scripts/system/activehdl/glbl.v
+84
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@@ -0,0 +1,84 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Debug_FW.ip_user_files/sim_scripts/system/activehdl/libps7.dll
+47
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@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/activehdl/libps7.so
+47
View File
@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/activehdl/libremoteport.dll
+47
View File
@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/activehdl/libremoteport.so
+47
View File
@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/activehdl/ps7_init.h
Executable
+117
View File
@@ -0,0 +1,117 @@
/******************************************************************************
*
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Debug_FW.ip_user_files/sim_scripts/system/activehdl/ps7_init.html
+117178
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Debug_FW.ip_user_files/sim_scripts/system/activehdl/ps7_init.tcl
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@@ -0,0 +1,745 @@
proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x0007FFFF 0x00001082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x0003F03F 0x0003C008
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x00010000 0x00000000
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000703FF 0x000003FF
mask_write 0XF800620C 0x000703FF 0x000003FF
mask_write 0XF8006210 0x000703FF 0x000003FF
mask_write 0XF8006214 0x000703FF 0x000003FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x000003FF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_3_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_2_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x000073FF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_1_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666
proc mask_poll { addr mask } {
set count 1
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
while { $maskedval == 0 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
set count [ expr { $count + 1 } ]
if { $count == 100000000 } {
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
break
}
}
}
proc mask_delay { addr val } {
set delay [ get_number_of_cycles_for_delay $val ]
perf_reset_and_start_timer
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
while { $maskedval == 1 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
}
perf_reset_clock
}
proc ps_version { } {
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
return $mask_sil_ver;
}
proc ps7_post_config {} {
set saved_mode [configparams force-mem-accesses]
configparams force-mem-accesses 1
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_post_config_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_post_config_2_0
} else {
ps7_post_config_3_0
}
configparams force-mem-accesses $saved_mode
}
proc ps7_debug {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_debug_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_debug_2_0
} else {
ps7_debug_3_0
}
}
proc ps7_init {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_mio_init_data_1_0
ps7_pll_init_data_1_0
ps7_clock_init_data_1_0
ps7_ddr_init_data_1_0
ps7_peripherals_init_data_1_0
#puts "PCW Silicon Version : 1.0"
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_mio_init_data_2_0
ps7_pll_init_data_2_0
ps7_clock_init_data_2_0
ps7_ddr_init_data_2_0
ps7_peripherals_init_data_2_0
#puts "PCW Silicon Version : 2.0"
} else {
ps7_mio_init_data_3_0
ps7_pll_init_data_3_0
ps7_clock_init_data_3_0
ps7_ddr_init_data_3_0
ps7_peripherals_init_data_3_0
#puts "PCW Silicon Version : 3.0"
}
}
# For delay calculation using global timer
# start timer
proc perf_start_clock { } {
#writing SCU_GLOBAL_TIMER_CONTROL register
mask_write 0xF8F00208 0x00000109 0x00000009
}
# stop timer and reset timer count regs
proc perf_reset_clock { } {
perf_disable_clock
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
}
# Compute mask for given delay in miliseconds
proc get_number_of_cycles_for_delay { delay } {
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
variable APU_FREQ
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
}
# stop timer
proc perf_disable_clock {} {
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
}
proc perf_reset_and_start_timer {} {
perf_reset_clock
perf_start_clock
}
Debug_FW.ip_user_files/sim_scripts/system/activehdl/ps7_init_gpl.h
Executable
+131
View File
@@ -0,0 +1,131 @@
/******************************************************************************
*
* Copyright (C) 2010-2020 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Debug_FW.ip_user_files/sim_scripts/system/activehdl/simulate.do
+14
View File
@@ -0,0 +1,14 @@
transcript off
onbreak {quit -force}
onerror {quit -force}
transcript on
asim +access +r +m+system -L xilinx_vip -L xpm -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_14 -L generic_baseblocks_v2_1_1 -L fifo_generator_v13_2_9 -L axi_data_fifo_v2_1_28 -L axi_register_slice_v2_1_29 -L axi_protocol_converter_v2_1_29 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O2 xil_defaultlib.system xil_defaultlib.glbl
do {system.udo}
run
endsim
quit -force
Debug_FW.ip_user_files/sim_scripts/system/activehdl/system.bda
Executable
+226
View File
@@ -0,0 +1,226 @@
{
"graphjs": {
"version": "1.0",
"keys": [
{
"abrv": "VH",
"name": "vert_hid",
"type": "int",
"for": "node"
},
{
"abrv": "VM",
"name": "vert_name",
"type": "string",
"for": "node"
},
{
"abrv": "VT",
"name": "vert_type",
"type": "string",
"for": "node"
},
{
"abrv": "BA",
"name": "base_addr",
"type": "string",
"for": "node"
},
{
"abrv": "HA",
"name": "high_addr",
"type": "string",
"for": "node"
},
{
"abrv": "BP",
"name": "base_param",
"type": "string",
"for": "node"
},
{
"abrv": "HP",
"name": "high_param",
"type": "string",
"for": "node"
},
{
"abrv": "MA",
"name": "master_addrspace",
"type": "string",
"for": "node"
},
{
"abrv": "MX",
"name": "master_instance",
"type": "string",
"for": "node"
},
{
"abrv": "MI",
"name": "master_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MS",
"name": "master_segment",
"type": "string",
"for": "node"
},
{
"abrv": "MV",
"name": "master_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "SX",
"name": "slave_instance",
"type": "string",
"for": "node"
},
{
"abrv": "SI",
"name": "slave_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MM",
"name": "slave_memmap",
"type": "string",
"for": "node"
},
{
"abrv": "SS",
"name": "slave_segment",
"type": "string",
"for": "node"
},
{
"abrv": "SV",
"name": "slave_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "TM",
"name": "memory_type",
"type": "string",
"for": "node"
},
{
"abrv": "TU",
"name": "usage_type",
"type": "string",
"for": "node"
},
{
"abrv": "LT",
"name": "lock_type",
"type": "string",
"for": "node"
},
{
"abrv": "BT",
"name": "boot_type",
"type": "string",
"for": "node"
},
{
"abrv": "EH",
"name": "edge_hid",
"type": "int",
"for": "edge"
}
],
"vertice_type_order": [
{
"abrv": "BC",
"desc": "Block Container"
},
{
"abrv": "PR",
"desc": "Parital Reference"
},
{
"abrv": "VR",
"desc": "Variant"
},
{
"abrv": "PM",
"desc": "Variant Permutations"
},
{
"abrv": "CX",
"desc": "Boundary Connection"
},
{
"abrv": "AC",
"desc": "Assignment Coordinate"
},
{
"abrv": "ACE",
"desc": "Excluded Assign Coordinate"
},
{
"abrv": "APX",
"desc": "Boundary Aperture"
},
{
"abrv": "CIP",
"desc": "High level Processing System"
}
],
"vertices": {
"V0": {
"VM": "system",
"VT": "BC"
},
"V1": {
"VH": "2",
"VM": "system",
"VT": "VR"
},
"V2": {
"VH": "2",
"VT": "PM",
"TU": "active"
},
"V3": {
"VT": "AC",
"BA": "0x43C00000",
"HA": "0x43C0FFFF",
"BP": "C_BASEADDR",
"HP": "C_HIGHADDR",
"MA": "Data",
"MX": "/processing_system7_0",
"MI": "M_AXI_GP0",
"MS": "SEG_mydna_read_v1_0_0_reg0",
"MV": "xilinx.com:ip:processing_system7:5.5",
"SX": "/mydna_read_v1_0_0",
"SI": "s00_axi",
"SS": "reg0",
"SV": "xilinx.com:module_ref:mydna_read_v1_0:1.0",
"TM": "both",
"TU": "register"
}
},
"edges": [
{
"src": "V0",
"trg": "V1"
},
{
"src": "V1",
"trg": "V2"
},
{
"src": "V3",
"trg": "V2",
"EH": "2"
}
]
}
}
Debug_FW.ip_user_files/sim_scripts/system/activehdl/system.sh
Executable
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#!/usr/bin/env bash
#**********************************************************************************************************
# Vivado (TM) v2023.2 (64-bit)
#
# Script generated by Vivado on Mon May 25 15:47:32 CST 2026
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Filename : system.sh
# Simulator : Aldec Active-HDL Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : system.sh
# system.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# system.sh [-reset_run]
# system.sh [-reset_log]
# system.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
# switch with the directory path where the library is created while generating the script
# with export_simulation.
#
# Alternatively, you can set the library path by setting the following project property:-
#
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
#
# You can also point to the simulation library by either setting the 'lib_map_path' global
# variable in this script or specify it with the '-lib_map_path' switch while executing this
# script (type 'system.sh -help' for more information).
#
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
# sources, then the library path MUST be specified upfront when calling export_simulation.
#
# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#**********************************************************************************************************
# script info
echo -e "system.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./system.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
runvsimsa -do "do {compile.do}" 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
runvsimsa -l simulate.log -do "do {simulate.do}"
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous design library mappings
true
else
# map simulator index file
map_setup_file
fi
}
# map library.cfg file
map_setup_file()
{
file="library.cfg"
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
vmap -link $lib_map_path
fi
fi
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./system.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: system.sh [-help]\n\
Usage: system.sh [-step]\n\
Usage: system.sh [-lib_map_path]\n\
Usage: system.sh [-reset_run]\n\
Usage: system.sh [-reset_log]\n\
Usage: system.sh [-keep_index]\n\
Usage: system.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (compile, simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
Debug_FW.ip_user_files/sim_scripts/system/activehdl/system.udo
View File
Debug_FW.ip_user_files/sim_scripts/system/activehdl/xilinx-zynq.cc
Executable
+106
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/*
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*
* Copyright (c) 2016, Xilinx Inc.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <inttypes.h>
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
using namespace sc_core;
using namespace std;
#include "xilinx-zynq.h"
#include <sys/types.h>
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
// Iremoteport_tlm_sync *sync)
// : remoteport_tlm(name, -1, sk_descr, sync),
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
: remoteport_tlm(name, -1, sk_descr),
rp_m_axi_gp0("rp_m_axi_gp0"),
rp_m_axi_gp1("rp_m_axi_gp1"),
rp_s_axi_gp0("rp_s_axi_gp0"),
rp_s_axi_gp1("rp_s_axi_gp1"),
rp_s_axi_hp0("rp_s_axi_hp0"),
rp_s_axi_hp1("rp_s_axi_hp1"),
rp_s_axi_hp2("rp_s_axi_hp2"),
rp_s_axi_hp3("rp_s_axi_hp3"),
rp_s_axi_acp("rp_s_axi_acp"),
rp_wires_in("wires_in", 20, 0),
rp_wires_out("wires_out", 0, 17),
rp_irq_out("irq_out", 0, 28),
pl2ps_irq("pl2ps_irq", 20),
ps2pl_irq("ps2pl_irq", 28),
ps2pl_rst("ps2pl_rst", 17)
{
int i;
m_axi_gp[0] = &rp_m_axi_gp0.sk;
m_axi_gp[1] = &rp_m_axi_gp1.sk;
s_axi_gp[0] = &rp_s_axi_gp0.sk;
s_axi_gp[1] = &rp_s_axi_gp1.sk;
s_axi_hp[0] = &rp_s_axi_hp0.sk;
s_axi_hp[1] = &rp_s_axi_hp1.sk;
s_axi_hp[2] = &rp_s_axi_hp2.sk;
s_axi_hp[3] = &rp_s_axi_hp3.sk;
s_axi_acp = &rp_s_axi_acp.sk;
/* PL to PS Interrupt signals. */
for (i = 0; i < 20; i++) {
rp_wires_in.wires_in[i](pl2ps_irq[i]);
}
/* PS to PL Interrupt signals. */
for (i = 0; i < 28; i++) {
rp_irq_out.wires_out[i](ps2pl_irq[i]);
}
/* PS to PL resets. */
for (i = 0; i < 17; i++) {
rp_wires_out.wires_out[i](ps2pl_rst[i]);
}
register_dev(0, &rp_s_axi_gp0);
register_dev(1, &rp_s_axi_gp1);
register_dev(2, &rp_s_axi_hp0);
register_dev(3, &rp_s_axi_hp1);
register_dev(4, &rp_s_axi_hp2);
register_dev(5, &rp_s_axi_hp3);
register_dev(6, &rp_s_axi_acp);
register_dev(7, &rp_m_axi_gp0);
register_dev(8, &rp_m_axi_gp1);
register_dev(9, &rp_wires_in);
register_dev(10, &rp_wires_out);
register_dev(11, &rp_irq_out);
}
Debug_FW.ip_user_files/sim_scripts/system/modelsim/README.txt
+50
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@@ -0,0 +1,50 @@
################################################################################
# Vivado (TM) v2023.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Mon May 25 15:47:32 CST 2026
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./system.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './system.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
Debug_FW.ip_user_files/sim_scripts/system/modelsim/compile.do
+100
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@@ -0,0 +1,100 @@
vlib modelsim_lib/work
vlib modelsim_lib/msim
vlib modelsim_lib/msim/xilinx_vip
vlib modelsim_lib/msim/xpm
vlib modelsim_lib/msim/axi_infrastructure_v1_1_0
vlib modelsim_lib/msim/axi_vip_v1_1_15
vlib modelsim_lib/msim/processing_system7_vip_v1_0_17
vlib modelsim_lib/msim/xil_defaultlib
vlib modelsim_lib/msim/lib_cdc_v1_0_2
vlib modelsim_lib/msim/proc_sys_reset_v5_0_14
vlib modelsim_lib/msim/generic_baseblocks_v2_1_1
vlib modelsim_lib/msim/fifo_generator_v13_2_9
vlib modelsim_lib/msim/axi_data_fifo_v2_1_28
vlib modelsim_lib/msim/axi_register_slice_v2_1_29
vlib modelsim_lib/msim/axi_protocol_converter_v2_1_29
vmap xilinx_vip modelsim_lib/msim/xilinx_vip
vmap xpm modelsim_lib/msim/xpm
vmap axi_infrastructure_v1_1_0 modelsim_lib/msim/axi_infrastructure_v1_1_0
vmap axi_vip_v1_1_15 modelsim_lib/msim/axi_vip_v1_1_15
vmap processing_system7_vip_v1_0_17 modelsim_lib/msim/processing_system7_vip_v1_0_17
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
vmap lib_cdc_v1_0_2 modelsim_lib/msim/lib_cdc_v1_0_2
vmap proc_sys_reset_v5_0_14 modelsim_lib/msim/proc_sys_reset_v5_0_14
vmap generic_baseblocks_v2_1_1 modelsim_lib/msim/generic_baseblocks_v2_1_1
vmap fifo_generator_v13_2_9 modelsim_lib/msim/fifo_generator_v13_2_9
vmap axi_data_fifo_v2_1_28 modelsim_lib/msim/axi_data_fifo_v2_1_28
vmap axi_register_slice_v2_1_29 modelsim_lib/msim/axi_register_slice_v2_1_29
vmap axi_protocol_converter_v2_1_29 modelsim_lib/msim/axi_protocol_converter_v2_1_29
vlog -work xilinx_vip -64 -incr -mfcu -sv -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xilinx_vip "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
vlog -work xpm -64 -incr -mfcu -sv -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xilinx_vip "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -64 -93 \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work axi_infrastructure_v1_1_0 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \
vlog -work axi_vip_v1_1_15 -64 -incr -mfcu -sv -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xilinx_vip "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv" \
vlog -work processing_system7_vip_v1_0_17 -64 -incr -mfcu -sv -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xilinx_vip "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \
vlog -work xil_defaultlib -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v" \
"../../../bd/system/ip/system_dna_port_read_0_0/sim/system_dna_port_read_0_0.v" \
"../../../bd/system/ip/system_mydna_read_v1_0_0_0/sim/system_mydna_read_v1_0_0_0.v" \
vcom -work lib_cdc_v1_0_2 -64 -93 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \
vcom -work proc_sys_reset_v5_0_14 -64 -93 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
vcom -work xil_defaultlib -64 -93 \
"../../../bd/system/ip/system_rst_ps7_0_100M_1/sim/system_rst_ps7_0_100M_1.vhd" \
vlog -work generic_baseblocks_v2_1_1 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
vlog -work fifo_generator_v13_2_9 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_2_9 -64 -93 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd" \
vlog -work fifo_generator_v13_2_9 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v" \
vlog -work axi_data_fifo_v2_1_28 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v" \
vlog -work axi_register_slice_v2_1_29 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v" \
vlog -work axi_protocol_converter_v2_1_29 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v" \
vlog -work xil_defaultlib -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../bd/system/ip/system_auto_pc_0/sim/system_auto_pc_0.v" \
"../../../bd/system/sim/system.v" \
vlog -work xil_defaultlib \
"glbl.v"
Debug_FW.ip_user_files/sim_scripts/system/modelsim/file_info.txt
+31
View File
@@ -0,0 +1,31 @@
axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_cdc.sv,systemverilog,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_memory.sv,systemverilog,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_15,../../../../proj_cal.gen/sources_1/bd/system/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_17,../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_dna_port_read_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_dna_port_read_0_0/sim/system_dna_port_read_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_mydna_read_v1_0_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_mydna_read_v1_0_0_0/sim/system_mydna_read_v1_0_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_14,../../../../proj_cal.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_rst_ps7_0_100M_1.vhd,vhdl,xil_defaultlib,../../../bd/system/ip/system_rst_ps7_0_100M_1/sim/system_rst_ps7_0_100M_1.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_1,../../../../proj_cal.gen/sources_1/bd/system/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/simulation/fifo_generator_vlog_beh.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_28,../../../../proj_cal.gen/sources_1/bd/system/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_register_slice_v2_1_vl_rfs.v,verilog,axi_register_slice_v2_1_29,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../proj_cal.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_auto_pc_0/sim/system_auto_pc_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
Debug_FW.ip_user_files/sim_scripts/system/modelsim/glbl.v
+84
View File
@@ -0,0 +1,84 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Debug_FW.ip_user_files/sim_scripts/system/modelsim/libps7.dll
+47
View File
@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/modelsim/libps7.so
+47
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/modelsim/libremoteport.dll
+47
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/modelsim/libremoteport.so
+47
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/modelsim/ps7_init.h
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/******************************************************************************
*
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Debug_FW.ip_user_files/sim_scripts/system/modelsim/ps7_init.html
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Debug_FW.ip_user_files/sim_scripts/system/modelsim/ps7_init.tcl
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proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x0007FFFF 0x00001082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x0003F03F 0x0003C008
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x00010000 0x00000000
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000703FF 0x000003FF
mask_write 0XF800620C 0x000703FF 0x000003FF
mask_write 0XF8006210 0x000703FF 0x000003FF
mask_write 0XF8006214 0x000703FF 0x000003FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x000003FF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_3_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_2_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x000073FF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_1_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666
proc mask_poll { addr mask } {
set count 1
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
while { $maskedval == 0 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
set count [ expr { $count + 1 } ]
if { $count == 100000000 } {
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
break
}
}
}
proc mask_delay { addr val } {
set delay [ get_number_of_cycles_for_delay $val ]
perf_reset_and_start_timer
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
while { $maskedval == 1 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
}
perf_reset_clock
}
proc ps_version { } {
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
return $mask_sil_ver;
}
proc ps7_post_config {} {
set saved_mode [configparams force-mem-accesses]
configparams force-mem-accesses 1
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_post_config_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_post_config_2_0
} else {
ps7_post_config_3_0
}
configparams force-mem-accesses $saved_mode
}
proc ps7_debug {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_debug_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_debug_2_0
} else {
ps7_debug_3_0
}
}
proc ps7_init {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_mio_init_data_1_0
ps7_pll_init_data_1_0
ps7_clock_init_data_1_0
ps7_ddr_init_data_1_0
ps7_peripherals_init_data_1_0
#puts "PCW Silicon Version : 1.0"
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_mio_init_data_2_0
ps7_pll_init_data_2_0
ps7_clock_init_data_2_0
ps7_ddr_init_data_2_0
ps7_peripherals_init_data_2_0
#puts "PCW Silicon Version : 2.0"
} else {
ps7_mio_init_data_3_0
ps7_pll_init_data_3_0
ps7_clock_init_data_3_0
ps7_ddr_init_data_3_0
ps7_peripherals_init_data_3_0
#puts "PCW Silicon Version : 3.0"
}
}
# For delay calculation using global timer
# start timer
proc perf_start_clock { } {
#writing SCU_GLOBAL_TIMER_CONTROL register
mask_write 0xF8F00208 0x00000109 0x00000009
}
# stop timer and reset timer count regs
proc perf_reset_clock { } {
perf_disable_clock
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
}
# Compute mask for given delay in miliseconds
proc get_number_of_cycles_for_delay { delay } {
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
variable APU_FREQ
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
}
# stop timer
proc perf_disable_clock {} {
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
}
proc perf_reset_and_start_timer {} {
perf_reset_clock
perf_start_clock
}
Debug_FW.ip_user_files/sim_scripts/system/modelsim/ps7_init_gpl.h
Executable
+131
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@@ -0,0 +1,131 @@
/******************************************************************************
*
* Copyright (C) 2010-2020 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Debug_FW.ip_user_files/sim_scripts/system/modelsim/simulate.do
+19
View File
@@ -0,0 +1,19 @@
onbreak {quit -f}
onerror {quit -f}
vsim -voptargs="+acc" -L xilinx_vip -L xpm -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_14 -L generic_baseblocks_v2_1_1 -L fifo_generator_v13_2_9 -L axi_data_fifo_v2_1_28 -L axi_register_slice_v2_1_29 -L axi_protocol_converter_v2_1_29 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.system xil_defaultlib.glbl
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do {wave.do}
view wave
view structure
view signals
do {system.udo}
run 1000ns
quit -force
Debug_FW.ip_user_files/sim_scripts/system/modelsim/system.bda
Executable
+226
View File
@@ -0,0 +1,226 @@
{
"graphjs": {
"version": "1.0",
"keys": [
{
"abrv": "VH",
"name": "vert_hid",
"type": "int",
"for": "node"
},
{
"abrv": "VM",
"name": "vert_name",
"type": "string",
"for": "node"
},
{
"abrv": "VT",
"name": "vert_type",
"type": "string",
"for": "node"
},
{
"abrv": "BA",
"name": "base_addr",
"type": "string",
"for": "node"
},
{
"abrv": "HA",
"name": "high_addr",
"type": "string",
"for": "node"
},
{
"abrv": "BP",
"name": "base_param",
"type": "string",
"for": "node"
},
{
"abrv": "HP",
"name": "high_param",
"type": "string",
"for": "node"
},
{
"abrv": "MA",
"name": "master_addrspace",
"type": "string",
"for": "node"
},
{
"abrv": "MX",
"name": "master_instance",
"type": "string",
"for": "node"
},
{
"abrv": "MI",
"name": "master_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MS",
"name": "master_segment",
"type": "string",
"for": "node"
},
{
"abrv": "MV",
"name": "master_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "SX",
"name": "slave_instance",
"type": "string",
"for": "node"
},
{
"abrv": "SI",
"name": "slave_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MM",
"name": "slave_memmap",
"type": "string",
"for": "node"
},
{
"abrv": "SS",
"name": "slave_segment",
"type": "string",
"for": "node"
},
{
"abrv": "SV",
"name": "slave_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "TM",
"name": "memory_type",
"type": "string",
"for": "node"
},
{
"abrv": "TU",
"name": "usage_type",
"type": "string",
"for": "node"
},
{
"abrv": "LT",
"name": "lock_type",
"type": "string",
"for": "node"
},
{
"abrv": "BT",
"name": "boot_type",
"type": "string",
"for": "node"
},
{
"abrv": "EH",
"name": "edge_hid",
"type": "int",
"for": "edge"
}
],
"vertice_type_order": [
{
"abrv": "BC",
"desc": "Block Container"
},
{
"abrv": "PR",
"desc": "Parital Reference"
},
{
"abrv": "VR",
"desc": "Variant"
},
{
"abrv": "PM",
"desc": "Variant Permutations"
},
{
"abrv": "CX",
"desc": "Boundary Connection"
},
{
"abrv": "AC",
"desc": "Assignment Coordinate"
},
{
"abrv": "ACE",
"desc": "Excluded Assign Coordinate"
},
{
"abrv": "APX",
"desc": "Boundary Aperture"
},
{
"abrv": "CIP",
"desc": "High level Processing System"
}
],
"vertices": {
"V0": {
"VM": "system",
"VT": "BC"
},
"V1": {
"VH": "2",
"VM": "system",
"VT": "VR"
},
"V2": {
"VH": "2",
"VT": "PM",
"TU": "active"
},
"V3": {
"VT": "AC",
"BA": "0x43C00000",
"HA": "0x43C0FFFF",
"BP": "C_BASEADDR",
"HP": "C_HIGHADDR",
"MA": "Data",
"MX": "/processing_system7_0",
"MI": "M_AXI_GP0",
"MS": "SEG_mydna_read_v1_0_0_reg0",
"MV": "xilinx.com:ip:processing_system7:5.5",
"SX": "/mydna_read_v1_0_0",
"SI": "s00_axi",
"SS": "reg0",
"SV": "xilinx.com:module_ref:mydna_read_v1_0:1.0",
"TM": "both",
"TU": "register"
}
},
"edges": [
{
"src": "V0",
"trg": "V1"
},
{
"src": "V1",
"trg": "V2"
},
{
"src": "V3",
"trg": "V2",
"EH": "2"
}
]
}
}
Debug_FW.ip_user_files/sim_scripts/system/modelsim/system.sh
Executable
+287
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@@ -0,0 +1,287 @@
#!/usr/bin/env bash
#**********************************************************************************************************
# Vivado (TM) v2023.2 (64-bit)
#
# Script generated by Vivado on Mon May 25 15:47:32 CST 2026
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Filename : system.sh
# Simulator : Siemens ModelSim Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : system.sh
# system.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# system.sh [-reset_run]
# system.sh [-reset_log]
# system.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
# switch with the directory path where the library is created while generating the script
# with export_simulation.
#
# Alternatively, you can set the library path by setting the following project property:-
#
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
#
# You can also point to the simulation library by either setting the 'lib_map_path' global
# variable in this script or specify it with the '-lib_map_path' switch while executing this
# script (type 'system.sh -help' for more information).
#
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
# sources, then the library path MUST be specified upfront when calling export_simulation.
#
# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#**********************************************************************************************************
# catch pipeline exit status
set -Eeuo pipefail
# script info
echo -e "system.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./system.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
vsim -c -do "do {simulate.do}" -l simulate.log
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous simulator index file
true
else
# copy simulator index file to current directory
copy_setup_file
fi
if [[ ($lib_map_path != "") ]]; then
ref_lib_dir=$lib_map_path
fi
if [[ ($b_keep_index == 1) ]]; then
# do not recreate design library directories
true
else
# create design library directories
create_lib_dir
fi
}
# copy modelsim.ini file
copy_setup_file()
{
file="modelsim.ini"
if [[ ($lib_map_path == "") ]]; then
lib_map_path="/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/proj_cal.cache/compile_simlib/modelsim"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
cp $src_file .
fi
fi
}
# create design library directory
create_lib_dir()
{
lib_dir="modelsim_lib"
if [[ -e $lib_dir ]]; then
rm -rf $lib_dir
fi
mkdir $lib_dir
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(compile.log elaborate.log simulate.log)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./system.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: system.sh [-help]\n\
Usage: system.sh [-step]\n\
Usage: system.sh [-lib_map_path]\n\
Usage: system.sh [-reset_run]\n\
Usage: system.sh [-reset_log]\n\
Usage: system.sh [-keep_index]\n\
Usage: system.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (compile, simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
Debug_FW.ip_user_files/sim_scripts/system/modelsim/system.udo
View File
Debug_FW.ip_user_files/sim_scripts/system/modelsim/wave.do
+2
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@@ -0,0 +1,2 @@
add wave *
add wave /glbl/GSR
Debug_FW.ip_user_files/sim_scripts/system/modelsim/xilinx-zynq.cc
Executable
+106
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@@ -0,0 +1,106 @@
/*
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*
* Copyright (c) 2016, Xilinx Inc.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <inttypes.h>
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
using namespace sc_core;
using namespace std;
#include "xilinx-zynq.h"
#include <sys/types.h>
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
// Iremoteport_tlm_sync *sync)
// : remoteport_tlm(name, -1, sk_descr, sync),
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
: remoteport_tlm(name, -1, sk_descr),
rp_m_axi_gp0("rp_m_axi_gp0"),
rp_m_axi_gp1("rp_m_axi_gp1"),
rp_s_axi_gp0("rp_s_axi_gp0"),
rp_s_axi_gp1("rp_s_axi_gp1"),
rp_s_axi_hp0("rp_s_axi_hp0"),
rp_s_axi_hp1("rp_s_axi_hp1"),
rp_s_axi_hp2("rp_s_axi_hp2"),
rp_s_axi_hp3("rp_s_axi_hp3"),
rp_s_axi_acp("rp_s_axi_acp"),
rp_wires_in("wires_in", 20, 0),
rp_wires_out("wires_out", 0, 17),
rp_irq_out("irq_out", 0, 28),
pl2ps_irq("pl2ps_irq", 20),
ps2pl_irq("ps2pl_irq", 28),
ps2pl_rst("ps2pl_rst", 17)
{
int i;
m_axi_gp[0] = &rp_m_axi_gp0.sk;
m_axi_gp[1] = &rp_m_axi_gp1.sk;
s_axi_gp[0] = &rp_s_axi_gp0.sk;
s_axi_gp[1] = &rp_s_axi_gp1.sk;
s_axi_hp[0] = &rp_s_axi_hp0.sk;
s_axi_hp[1] = &rp_s_axi_hp1.sk;
s_axi_hp[2] = &rp_s_axi_hp2.sk;
s_axi_hp[3] = &rp_s_axi_hp3.sk;
s_axi_acp = &rp_s_axi_acp.sk;
/* PL to PS Interrupt signals. */
for (i = 0; i < 20; i++) {
rp_wires_in.wires_in[i](pl2ps_irq[i]);
}
/* PS to PL Interrupt signals. */
for (i = 0; i < 28; i++) {
rp_irq_out.wires_out[i](ps2pl_irq[i]);
}
/* PS to PL resets. */
for (i = 0; i < 17; i++) {
rp_wires_out.wires_out[i](ps2pl_rst[i]);
}
register_dev(0, &rp_s_axi_gp0);
register_dev(1, &rp_s_axi_gp1);
register_dev(2, &rp_s_axi_hp0);
register_dev(3, &rp_s_axi_hp1);
register_dev(4, &rp_s_axi_hp2);
register_dev(5, &rp_s_axi_hp3);
register_dev(6, &rp_s_axi_acp);
register_dev(7, &rp_m_axi_gp0);
register_dev(8, &rp_m_axi_gp1);
register_dev(9, &rp_wires_in);
register_dev(10, &rp_wires_out);
register_dev(11, &rp_irq_out);
}
Debug_FW.ip_user_files/sim_scripts/system/questa/README.txt
+50
View File
@@ -0,0 +1,50 @@
################################################################################
# Vivado (TM) v2023.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Mon May 25 15:47:32 CST 2026
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./system.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './system.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
Debug_FW.ip_user_files/sim_scripts/system/questa/compile.do
+100
View File
@@ -0,0 +1,100 @@
vlib questa_lib/work
vlib questa_lib/msim
vlib questa_lib/msim/xilinx_vip
vlib questa_lib/msim/xpm
vlib questa_lib/msim/axi_infrastructure_v1_1_0
vlib questa_lib/msim/axi_vip_v1_1_15
vlib questa_lib/msim/processing_system7_vip_v1_0_17
vlib questa_lib/msim/xil_defaultlib
vlib questa_lib/msim/lib_cdc_v1_0_2
vlib questa_lib/msim/proc_sys_reset_v5_0_14
vlib questa_lib/msim/generic_baseblocks_v2_1_1
vlib questa_lib/msim/fifo_generator_v13_2_9
vlib questa_lib/msim/axi_data_fifo_v2_1_28
vlib questa_lib/msim/axi_register_slice_v2_1_29
vlib questa_lib/msim/axi_protocol_converter_v2_1_29
vmap xilinx_vip questa_lib/msim/xilinx_vip
vmap xpm questa_lib/msim/xpm
vmap axi_infrastructure_v1_1_0 questa_lib/msim/axi_infrastructure_v1_1_0
vmap axi_vip_v1_1_15 questa_lib/msim/axi_vip_v1_1_15
vmap processing_system7_vip_v1_0_17 questa_lib/msim/processing_system7_vip_v1_0_17
vmap xil_defaultlib questa_lib/msim/xil_defaultlib
vmap lib_cdc_v1_0_2 questa_lib/msim/lib_cdc_v1_0_2
vmap proc_sys_reset_v5_0_14 questa_lib/msim/proc_sys_reset_v5_0_14
vmap generic_baseblocks_v2_1_1 questa_lib/msim/generic_baseblocks_v2_1_1
vmap fifo_generator_v13_2_9 questa_lib/msim/fifo_generator_v13_2_9
vmap axi_data_fifo_v2_1_28 questa_lib/msim/axi_data_fifo_v2_1_28
vmap axi_register_slice_v2_1_29 questa_lib/msim/axi_register_slice_v2_1_29
vmap axi_protocol_converter_v2_1_29 questa_lib/msim/axi_protocol_converter_v2_1_29
vlog -work xilinx_vip -64 -incr -mfcu -sv -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xilinx_vip "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
vlog -work xpm -64 -incr -mfcu -sv -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xilinx_vip "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -64 -93 \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work axi_infrastructure_v1_1_0 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \
vlog -work axi_vip_v1_1_15 -64 -incr -mfcu -sv -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xilinx_vip "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv" \
vlog -work processing_system7_vip_v1_0_17 -64 -incr -mfcu -sv -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xilinx_vip "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \
vlog -work xil_defaultlib -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v" \
"../../../bd/system/ip/system_dna_port_read_0_0/sim/system_dna_port_read_0_0.v" \
"../../../bd/system/ip/system_mydna_read_v1_0_0_0/sim/system_mydna_read_v1_0_0_0.v" \
vcom -work lib_cdc_v1_0_2 -64 -93 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \
vcom -work proc_sys_reset_v5_0_14 -64 -93 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
vcom -work xil_defaultlib -64 -93 \
"../../../bd/system/ip/system_rst_ps7_0_100M_1/sim/system_rst_ps7_0_100M_1.vhd" \
vlog -work generic_baseblocks_v2_1_1 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
vlog -work fifo_generator_v13_2_9 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_2_9 -64 -93 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd" \
vlog -work fifo_generator_v13_2_9 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v" \
vlog -work axi_data_fifo_v2_1_28 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v" \
vlog -work axi_register_slice_v2_1_29 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v" \
vlog -work axi_protocol_converter_v2_1_29 -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v" \
vlog -work xil_defaultlib -64 -incr -mfcu "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../bd/system/ip/system_auto_pc_0/sim/system_auto_pc_0.v" \
"../../../bd/system/sim/system.v" \
vlog -work xil_defaultlib \
"glbl.v"
Debug_FW.ip_user_files/sim_scripts/system/questa/elaborate.do
+1
View File
@@ -0,0 +1 @@
vopt -64 -l elaborate.log +acc=npr -suppress 10016 -L xil_defaultlib -L xilinx_vip -L xpm -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_14 -L generic_baseblocks_v2_1_1 -L fifo_generator_v13_2_9 -L axi_data_fifo_v2_1_28 -L axi_register_slice_v2_1_29 -L axi_protocol_converter_v2_1_29 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.system xil_defaultlib.glbl -o system_opt
Debug_FW.ip_user_files/sim_scripts/system/questa/file_info.txt
+31
View File
@@ -0,0 +1,31 @@
axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_cdc.sv,systemverilog,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_memory.sv,systemverilog,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_15,../../../../proj_cal.gen/sources_1/bd/system/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_17,../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_dna_port_read_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_dna_port_read_0_0/sim/system_dna_port_read_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_mydna_read_v1_0_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_mydna_read_v1_0_0_0/sim/system_mydna_read_v1_0_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_14,../../../../proj_cal.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_rst_ps7_0_100M_1.vhd,vhdl,xil_defaultlib,../../../bd/system/ip/system_rst_ps7_0_100M_1/sim/system_rst_ps7_0_100M_1.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_1,../../../../proj_cal.gen/sources_1/bd/system/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/simulation/fifo_generator_vlog_beh.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_28,../../../../proj_cal.gen/sources_1/bd/system/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_register_slice_v2_1_vl_rfs.v,verilog,axi_register_slice_v2_1_29,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../proj_cal.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_auto_pc_0/sim/system_auto_pc_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
Debug_FW.ip_user_files/sim_scripts/system/questa/glbl.v
+84
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@@ -0,0 +1,84 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Debug_FW.ip_user_files/sim_scripts/system/questa/libps7.dll
+47
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@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/questa/libps7.so
+47
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@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/questa/libremoteport.dll
+47
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@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/questa/libremoteport.so
+47
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@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/questa/ps7_init.h
Executable
+117
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@@ -0,0 +1,117 @@
/******************************************************************************
*
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Debug_FW.ip_user_files/sim_scripts/system/questa/ps7_init.html
+117178
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Debug_FW.ip_user_files/sim_scripts/system/questa/ps7_init.tcl
+745
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@@ -0,0 +1,745 @@
proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x0007FFFF 0x00001082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x0003F03F 0x0003C008
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x00010000 0x00000000
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000703FF 0x000003FF
mask_write 0XF800620C 0x000703FF 0x000003FF
mask_write 0XF8006210 0x000703FF 0x000003FF
mask_write 0XF8006214 0x000703FF 0x000003FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x000003FF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_3_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_2_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x000073FF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_1_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666
proc mask_poll { addr mask } {
set count 1
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
while { $maskedval == 0 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
set count [ expr { $count + 1 } ]
if { $count == 100000000 } {
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
break
}
}
}
proc mask_delay { addr val } {
set delay [ get_number_of_cycles_for_delay $val ]
perf_reset_and_start_timer
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
while { $maskedval == 1 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
}
perf_reset_clock
}
proc ps_version { } {
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
return $mask_sil_ver;
}
proc ps7_post_config {} {
set saved_mode [configparams force-mem-accesses]
configparams force-mem-accesses 1
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_post_config_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_post_config_2_0
} else {
ps7_post_config_3_0
}
configparams force-mem-accesses $saved_mode
}
proc ps7_debug {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_debug_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_debug_2_0
} else {
ps7_debug_3_0
}
}
proc ps7_init {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_mio_init_data_1_0
ps7_pll_init_data_1_0
ps7_clock_init_data_1_0
ps7_ddr_init_data_1_0
ps7_peripherals_init_data_1_0
#puts "PCW Silicon Version : 1.0"
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_mio_init_data_2_0
ps7_pll_init_data_2_0
ps7_clock_init_data_2_0
ps7_ddr_init_data_2_0
ps7_peripherals_init_data_2_0
#puts "PCW Silicon Version : 2.0"
} else {
ps7_mio_init_data_3_0
ps7_pll_init_data_3_0
ps7_clock_init_data_3_0
ps7_ddr_init_data_3_0
ps7_peripherals_init_data_3_0
#puts "PCW Silicon Version : 3.0"
}
}
# For delay calculation using global timer
# start timer
proc perf_start_clock { } {
#writing SCU_GLOBAL_TIMER_CONTROL register
mask_write 0xF8F00208 0x00000109 0x00000009
}
# stop timer and reset timer count regs
proc perf_reset_clock { } {
perf_disable_clock
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
}
# Compute mask for given delay in miliseconds
proc get_number_of_cycles_for_delay { delay } {
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
variable APU_FREQ
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
}
# stop timer
proc perf_disable_clock {} {
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
}
proc perf_reset_and_start_timer {} {
perf_reset_clock
perf_start_clock
}
Debug_FW.ip_user_files/sim_scripts/system/questa/ps7_init_gpl.h
Executable
+131
View File
@@ -0,0 +1,131 @@
/******************************************************************************
*
* Copyright (C) 2010-2020 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Debug_FW.ip_user_files/sim_scripts/system/questa/simulate.do
+19
View File
@@ -0,0 +1,19 @@
onbreak {quit -f}
onerror {quit -f}
vsim -lib xil_defaultlib system_opt
set NumericStdNoWarnings 1
set StdArithNoWarnings 1
do {wave.do}
view wave
view structure
view signals
do {system.udo}
run 1000ns
quit -force
Debug_FW.ip_user_files/sim_scripts/system/questa/system.bda
Executable
+226
View File
@@ -0,0 +1,226 @@
{
"graphjs": {
"version": "1.0",
"keys": [
{
"abrv": "VH",
"name": "vert_hid",
"type": "int",
"for": "node"
},
{
"abrv": "VM",
"name": "vert_name",
"type": "string",
"for": "node"
},
{
"abrv": "VT",
"name": "vert_type",
"type": "string",
"for": "node"
},
{
"abrv": "BA",
"name": "base_addr",
"type": "string",
"for": "node"
},
{
"abrv": "HA",
"name": "high_addr",
"type": "string",
"for": "node"
},
{
"abrv": "BP",
"name": "base_param",
"type": "string",
"for": "node"
},
{
"abrv": "HP",
"name": "high_param",
"type": "string",
"for": "node"
},
{
"abrv": "MA",
"name": "master_addrspace",
"type": "string",
"for": "node"
},
{
"abrv": "MX",
"name": "master_instance",
"type": "string",
"for": "node"
},
{
"abrv": "MI",
"name": "master_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MS",
"name": "master_segment",
"type": "string",
"for": "node"
},
{
"abrv": "MV",
"name": "master_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "SX",
"name": "slave_instance",
"type": "string",
"for": "node"
},
{
"abrv": "SI",
"name": "slave_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MM",
"name": "slave_memmap",
"type": "string",
"for": "node"
},
{
"abrv": "SS",
"name": "slave_segment",
"type": "string",
"for": "node"
},
{
"abrv": "SV",
"name": "slave_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "TM",
"name": "memory_type",
"type": "string",
"for": "node"
},
{
"abrv": "TU",
"name": "usage_type",
"type": "string",
"for": "node"
},
{
"abrv": "LT",
"name": "lock_type",
"type": "string",
"for": "node"
},
{
"abrv": "BT",
"name": "boot_type",
"type": "string",
"for": "node"
},
{
"abrv": "EH",
"name": "edge_hid",
"type": "int",
"for": "edge"
}
],
"vertice_type_order": [
{
"abrv": "BC",
"desc": "Block Container"
},
{
"abrv": "PR",
"desc": "Parital Reference"
},
{
"abrv": "VR",
"desc": "Variant"
},
{
"abrv": "PM",
"desc": "Variant Permutations"
},
{
"abrv": "CX",
"desc": "Boundary Connection"
},
{
"abrv": "AC",
"desc": "Assignment Coordinate"
},
{
"abrv": "ACE",
"desc": "Excluded Assign Coordinate"
},
{
"abrv": "APX",
"desc": "Boundary Aperture"
},
{
"abrv": "CIP",
"desc": "High level Processing System"
}
],
"vertices": {
"V0": {
"VM": "system",
"VT": "BC"
},
"V1": {
"VH": "2",
"VM": "system",
"VT": "VR"
},
"V2": {
"VH": "2",
"VT": "PM",
"TU": "active"
},
"V3": {
"VT": "AC",
"BA": "0x43C00000",
"HA": "0x43C0FFFF",
"BP": "C_BASEADDR",
"HP": "C_HIGHADDR",
"MA": "Data",
"MX": "/processing_system7_0",
"MI": "M_AXI_GP0",
"MS": "SEG_mydna_read_v1_0_0_reg0",
"MV": "xilinx.com:ip:processing_system7:5.5",
"SX": "/mydna_read_v1_0_0",
"SI": "s00_axi",
"SS": "reg0",
"SV": "xilinx.com:module_ref:mydna_read_v1_0:1.0",
"TM": "both",
"TU": "register"
}
},
"edges": [
{
"src": "V0",
"trg": "V1"
},
{
"src": "V1",
"trg": "V2"
},
{
"src": "V3",
"trg": "V2",
"EH": "2"
}
]
}
}
Debug_FW.ip_user_files/sim_scripts/system/questa/system.sh
Executable
+297
View File
@@ -0,0 +1,297 @@
#!/usr/bin/env bash
#**********************************************************************************************************
# Vivado (TM) v2023.2 (64-bit)
#
# Script generated by Vivado on Mon May 25 15:47:32 CST 2026
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Filename : system.sh
# Simulator : Siemens Questa Advanced Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : system.sh
# system.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# system.sh [-reset_run]
# system.sh [-reset_log]
# system.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
# switch with the directory path where the library is created while generating the script
# with export_simulation.
#
# Alternatively, you can set the library path by setting the following project property:-
#
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
#
# You can also point to the simulation library by either setting the 'lib_map_path' global
# variable in this script or specify it with the '-lib_map_path' switch while executing this
# script (type 'system.sh -help' for more information).
#
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
# sources, then the library path MUST be specified upfront when calling export_simulation.
#
# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#**********************************************************************************************************
# catch pipeline exit status
set -Eeuo pipefail
# script info
echo -e "system.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"elaborate" )
elaborate
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./system.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
elaborate
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
source compile.do 2>&1 | tee -a compile.log
}
# RUN_STEP: <elaborate>
elaborate()
{
source elaborate.do 2>&1 | tee elaborate.log
}
# RUN_STEP: <simulate>
simulate()
{
vsim -64 -c -do "do {simulate.do}" -l simulate.log
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous simulator index file
true
else
# copy simulator index file to current directory
copy_setup_file
fi
if [[ ($lib_map_path != "") ]]; then
ref_lib_dir=$lib_map_path
fi
if [[ ($b_keep_index == 1) ]]; then
# do not recreate design library directories
true
else
# create design library directories
create_lib_dir
fi
}
# copy modelsim.ini file
copy_setup_file()
{
file="modelsim.ini"
if [[ ($lib_map_path == "") ]]; then
lib_map_path="/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/proj_cal.cache/compile_simlib/questa"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
cp $src_file .
fi
fi
}
# create design library directory
create_lib_dir()
{
lib_dir="questa_lib"
if [[ -e $lib_dir ]]; then
rm -rf $lib_dir
fi
mkdir $lib_dir
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(compile.log elaborate.log simulate.log)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./system.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: system.sh [-help]\n\
Usage: system.sh [-step]\n\
Usage: system.sh [-lib_map_path]\n\
Usage: system.sh [-reset_run]\n\
Usage: system.sh [-reset_log]\n\
Usage: system.sh [-keep_index]\n\
Usage: system.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (compile, elaborate, simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
Debug_FW.ip_user_files/sim_scripts/system/questa/system.udo
View File
Debug_FW.ip_user_files/sim_scripts/system/questa/wave.do
+2
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@@ -0,0 +1,2 @@
add wave *
add wave /glbl/GSR
Debug_FW.ip_user_files/sim_scripts/system/questa/xilinx-zynq.cc
Executable
+106
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@@ -0,0 +1,106 @@
/*
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*
* Copyright (c) 2016, Xilinx Inc.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <inttypes.h>
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
using namespace sc_core;
using namespace std;
#include "xilinx-zynq.h"
#include <sys/types.h>
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
// Iremoteport_tlm_sync *sync)
// : remoteport_tlm(name, -1, sk_descr, sync),
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
: remoteport_tlm(name, -1, sk_descr),
rp_m_axi_gp0("rp_m_axi_gp0"),
rp_m_axi_gp1("rp_m_axi_gp1"),
rp_s_axi_gp0("rp_s_axi_gp0"),
rp_s_axi_gp1("rp_s_axi_gp1"),
rp_s_axi_hp0("rp_s_axi_hp0"),
rp_s_axi_hp1("rp_s_axi_hp1"),
rp_s_axi_hp2("rp_s_axi_hp2"),
rp_s_axi_hp3("rp_s_axi_hp3"),
rp_s_axi_acp("rp_s_axi_acp"),
rp_wires_in("wires_in", 20, 0),
rp_wires_out("wires_out", 0, 17),
rp_irq_out("irq_out", 0, 28),
pl2ps_irq("pl2ps_irq", 20),
ps2pl_irq("ps2pl_irq", 28),
ps2pl_rst("ps2pl_rst", 17)
{
int i;
m_axi_gp[0] = &rp_m_axi_gp0.sk;
m_axi_gp[1] = &rp_m_axi_gp1.sk;
s_axi_gp[0] = &rp_s_axi_gp0.sk;
s_axi_gp[1] = &rp_s_axi_gp1.sk;
s_axi_hp[0] = &rp_s_axi_hp0.sk;
s_axi_hp[1] = &rp_s_axi_hp1.sk;
s_axi_hp[2] = &rp_s_axi_hp2.sk;
s_axi_hp[3] = &rp_s_axi_hp3.sk;
s_axi_acp = &rp_s_axi_acp.sk;
/* PL to PS Interrupt signals. */
for (i = 0; i < 20; i++) {
rp_wires_in.wires_in[i](pl2ps_irq[i]);
}
/* PS to PL Interrupt signals. */
for (i = 0; i < 28; i++) {
rp_irq_out.wires_out[i](ps2pl_irq[i]);
}
/* PS to PL resets. */
for (i = 0; i < 17; i++) {
rp_wires_out.wires_out[i](ps2pl_rst[i]);
}
register_dev(0, &rp_s_axi_gp0);
register_dev(1, &rp_s_axi_gp1);
register_dev(2, &rp_s_axi_hp0);
register_dev(3, &rp_s_axi_hp1);
register_dev(4, &rp_s_axi_hp2);
register_dev(5, &rp_s_axi_hp3);
register_dev(6, &rp_s_axi_acp);
register_dev(7, &rp_m_axi_gp0);
register_dev(8, &rp_m_axi_gp1);
register_dev(9, &rp_wires_in);
register_dev(10, &rp_wires_out);
register_dev(11, &rp_irq_out);
}
Debug_FW.ip_user_files/sim_scripts/system/riviera/README.txt
+50
View File
@@ -0,0 +1,50 @@
################################################################################
# Vivado (TM) v2023.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Mon May 25 15:47:32 CST 2026
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./system.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './system.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
Debug_FW.ip_user_files/sim_scripts/system/riviera/compile.do
+103
View File
@@ -0,0 +1,103 @@
transcript off
onbreak {quit -force}
onerror {quit -force}
transcript on
vlib work
vlib riviera/xilinx_vip
vlib riviera/xpm
vlib riviera/axi_infrastructure_v1_1_0
vlib riviera/axi_vip_v1_1_15
vlib riviera/processing_system7_vip_v1_0_17
vlib riviera/xil_defaultlib
vlib riviera/lib_cdc_v1_0_2
vlib riviera/proc_sys_reset_v5_0_14
vlib riviera/generic_baseblocks_v2_1_1
vlib riviera/fifo_generator_v13_2_9
vlib riviera/axi_data_fifo_v2_1_28
vlib riviera/axi_register_slice_v2_1_29
vlib riviera/axi_protocol_converter_v2_1_29
vmap xilinx_vip riviera/xilinx_vip
vmap xpm riviera/xpm
vmap axi_infrastructure_v1_1_0 riviera/axi_infrastructure_v1_1_0
vmap axi_vip_v1_1_15 riviera/axi_vip_v1_1_15
vmap processing_system7_vip_v1_0_17 riviera/processing_system7_vip_v1_0_17
vmap xil_defaultlib riviera/xil_defaultlib
vmap lib_cdc_v1_0_2 riviera/lib_cdc_v1_0_2
vmap proc_sys_reset_v5_0_14 riviera/proc_sys_reset_v5_0_14
vmap generic_baseblocks_v2_1_1 riviera/generic_baseblocks_v2_1_1
vmap fifo_generator_v13_2_9 riviera/fifo_generator_v13_2_9
vmap axi_data_fifo_v2_1_28 riviera/axi_data_fifo_v2_1_28
vmap axi_register_slice_v2_1_29 riviera/axi_register_slice_v2_1_29
vmap axi_protocol_converter_v2_1_29 riviera/axi_protocol_converter_v2_1_29
vlog -work xilinx_vip -incr "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
vlog -work xpm -incr "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 -incr \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work axi_infrastructure_v1_1_0 -incr -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \
vlog -work axi_vip_v1_1_15 -incr "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv" \
vlog -work processing_system7_vip_v1_0_17 -incr "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \
vlog -work xil_defaultlib -incr -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v" \
"../../../bd/system/ip/system_dna_port_read_0_0/sim/system_dna_port_read_0_0.v" \
"../../../bd/system/ip/system_mydna_read_v1_0_0_0/sim/system_mydna_read_v1_0_0_0.v" \
vcom -work lib_cdc_v1_0_2 -93 -incr \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \
vcom -work proc_sys_reset_v5_0_14 -93 -incr \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
vcom -work xil_defaultlib -93 -incr \
"../../../bd/system/ip/system_rst_ps7_0_100M_1/sim/system_rst_ps7_0_100M_1.vhd" \
vlog -work generic_baseblocks_v2_1_1 -incr -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
vlog -work fifo_generator_v13_2_9 -incr -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/simulation/fifo_generator_vlog_beh.v" \
vcom -work fifo_generator_v13_2_9 -93 -incr \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd" \
vlog -work fifo_generator_v13_2_9 -incr -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v" \
vlog -work axi_data_fifo_v2_1_28 -incr -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v" \
vlog -work axi_register_slice_v2_1_29 -incr -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v" \
vlog -work axi_protocol_converter_v2_1_29 -incr -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v" \
vlog -work xil_defaultlib -incr -v2k5 "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" "+incdir+../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" "+incdir+/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" -l xilinx_vip -l xpm -l axi_infrastructure_v1_1_0 -l axi_vip_v1_1_15 -l processing_system7_vip_v1_0_17 -l xil_defaultlib -l lib_cdc_v1_0_2 -l proc_sys_reset_v5_0_14 -l generic_baseblocks_v2_1_1 -l fifo_generator_v13_2_9 -l axi_data_fifo_v2_1_28 -l axi_register_slice_v2_1_29 -l axi_protocol_converter_v2_1_29 \
"../../../bd/system/ip/system_auto_pc_0/sim/system_auto_pc_0.v" \
"../../../bd/system/sim/system.v" \
vlog -work xil_defaultlib \
"glbl.v"
Debug_FW.ip_user_files/sim_scripts/system/riviera/file_info.txt
+31
View File
@@ -0,0 +1,31 @@
axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_cdc.sv,systemverilog,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_memory.sv,systemverilog,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_15,../../../../proj_cal.gen/sources_1/bd/system/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_17,../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_dna_port_read_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_dna_port_read_0_0/sim/system_dna_port_read_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_mydna_read_v1_0_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_mydna_read_v1_0_0_0/sim/system_mydna_read_v1_0_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_14,../../../../proj_cal.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_rst_ps7_0_100M_1.vhd,vhdl,xil_defaultlib,../../../bd/system/ip/system_rst_ps7_0_100M_1/sim/system_rst_ps7_0_100M_1.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_1,../../../../proj_cal.gen/sources_1/bd/system/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/simulation/fifo_generator_vlog_beh.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_28,../../../../proj_cal.gen/sources_1/bd/system/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_register_slice_v2_1_vl_rfs.v,verilog,axi_register_slice_v2_1_29,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../proj_cal.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_auto_pc_0/sim/system_auto_pc_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
Debug_FW.ip_user_files/sim_scripts/system/riviera/glbl.v
+84
View File
@@ -0,0 +1,84 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Debug_FW.ip_user_files/sim_scripts/system/riviera/libps7.dll
+47
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/riviera/libps7.so
+47
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/riviera/libremoteport.dll
+47
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/riviera/libremoteport.so
+47
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@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/riviera/ps7_init.h
Executable
+117
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/******************************************************************************
*
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Debug_FW.ip_user_files/sim_scripts/system/riviera/ps7_init.html
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Debug_FW.ip_user_files/sim_scripts/system/riviera/ps7_init.tcl
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proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x0007FFFF 0x00001082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x0003F03F 0x0003C008
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x00010000 0x00000000
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000703FF 0x000003FF
mask_write 0XF800620C 0x000703FF 0x000003FF
mask_write 0XF8006210 0x000703FF 0x000003FF
mask_write 0XF8006214 0x000703FF 0x000003FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x000003FF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_3_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_2_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x000073FF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_1_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666
proc mask_poll { addr mask } {
set count 1
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
while { $maskedval == 0 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
set count [ expr { $count + 1 } ]
if { $count == 100000000 } {
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
break
}
}
}
proc mask_delay { addr val } {
set delay [ get_number_of_cycles_for_delay $val ]
perf_reset_and_start_timer
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
while { $maskedval == 1 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
}
perf_reset_clock
}
proc ps_version { } {
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
return $mask_sil_ver;
}
proc ps7_post_config {} {
set saved_mode [configparams force-mem-accesses]
configparams force-mem-accesses 1
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_post_config_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_post_config_2_0
} else {
ps7_post_config_3_0
}
configparams force-mem-accesses $saved_mode
}
proc ps7_debug {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_debug_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_debug_2_0
} else {
ps7_debug_3_0
}
}
proc ps7_init {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_mio_init_data_1_0
ps7_pll_init_data_1_0
ps7_clock_init_data_1_0
ps7_ddr_init_data_1_0
ps7_peripherals_init_data_1_0
#puts "PCW Silicon Version : 1.0"
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_mio_init_data_2_0
ps7_pll_init_data_2_0
ps7_clock_init_data_2_0
ps7_ddr_init_data_2_0
ps7_peripherals_init_data_2_0
#puts "PCW Silicon Version : 2.0"
} else {
ps7_mio_init_data_3_0
ps7_pll_init_data_3_0
ps7_clock_init_data_3_0
ps7_ddr_init_data_3_0
ps7_peripherals_init_data_3_0
#puts "PCW Silicon Version : 3.0"
}
}
# For delay calculation using global timer
# start timer
proc perf_start_clock { } {
#writing SCU_GLOBAL_TIMER_CONTROL register
mask_write 0xF8F00208 0x00000109 0x00000009
}
# stop timer and reset timer count regs
proc perf_reset_clock { } {
perf_disable_clock
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
}
# Compute mask for given delay in miliseconds
proc get_number_of_cycles_for_delay { delay } {
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
variable APU_FREQ
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
}
# stop timer
proc perf_disable_clock {} {
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
}
proc perf_reset_and_start_timer {} {
perf_reset_clock
perf_start_clock
}
Debug_FW.ip_user_files/sim_scripts/system/riviera/ps7_init_gpl.h
Executable
+131
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@@ -0,0 +1,131 @@
/******************************************************************************
*
* Copyright (C) 2010-2020 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Debug_FW.ip_user_files/sim_scripts/system/riviera/simulate.do
+14
View File
@@ -0,0 +1,14 @@
transcript off
onbreak {quit -force}
onerror {quit -force}
transcript on
asim +access +r +m+system -L xilinx_vip -L xpm -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_15 -L processing_system7_vip_v1_0_17 -L xil_defaultlib -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_14 -L generic_baseblocks_v2_1_1 -L fifo_generator_v13_2_9 -L axi_data_fifo_v2_1_28 -L axi_register_slice_v2_1_29 -L axi_protocol_converter_v2_1_29 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.system xil_defaultlib.glbl
do {system.udo}
run 1000ns
endsim
quit -force
Debug_FW.ip_user_files/sim_scripts/system/riviera/system.bda
Executable
+226
View File
@@ -0,0 +1,226 @@
{
"graphjs": {
"version": "1.0",
"keys": [
{
"abrv": "VH",
"name": "vert_hid",
"type": "int",
"for": "node"
},
{
"abrv": "VM",
"name": "vert_name",
"type": "string",
"for": "node"
},
{
"abrv": "VT",
"name": "vert_type",
"type": "string",
"for": "node"
},
{
"abrv": "BA",
"name": "base_addr",
"type": "string",
"for": "node"
},
{
"abrv": "HA",
"name": "high_addr",
"type": "string",
"for": "node"
},
{
"abrv": "BP",
"name": "base_param",
"type": "string",
"for": "node"
},
{
"abrv": "HP",
"name": "high_param",
"type": "string",
"for": "node"
},
{
"abrv": "MA",
"name": "master_addrspace",
"type": "string",
"for": "node"
},
{
"abrv": "MX",
"name": "master_instance",
"type": "string",
"for": "node"
},
{
"abrv": "MI",
"name": "master_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MS",
"name": "master_segment",
"type": "string",
"for": "node"
},
{
"abrv": "MV",
"name": "master_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "SX",
"name": "slave_instance",
"type": "string",
"for": "node"
},
{
"abrv": "SI",
"name": "slave_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MM",
"name": "slave_memmap",
"type": "string",
"for": "node"
},
{
"abrv": "SS",
"name": "slave_segment",
"type": "string",
"for": "node"
},
{
"abrv": "SV",
"name": "slave_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "TM",
"name": "memory_type",
"type": "string",
"for": "node"
},
{
"abrv": "TU",
"name": "usage_type",
"type": "string",
"for": "node"
},
{
"abrv": "LT",
"name": "lock_type",
"type": "string",
"for": "node"
},
{
"abrv": "BT",
"name": "boot_type",
"type": "string",
"for": "node"
},
{
"abrv": "EH",
"name": "edge_hid",
"type": "int",
"for": "edge"
}
],
"vertice_type_order": [
{
"abrv": "BC",
"desc": "Block Container"
},
{
"abrv": "PR",
"desc": "Parital Reference"
},
{
"abrv": "VR",
"desc": "Variant"
},
{
"abrv": "PM",
"desc": "Variant Permutations"
},
{
"abrv": "CX",
"desc": "Boundary Connection"
},
{
"abrv": "AC",
"desc": "Assignment Coordinate"
},
{
"abrv": "ACE",
"desc": "Excluded Assign Coordinate"
},
{
"abrv": "APX",
"desc": "Boundary Aperture"
},
{
"abrv": "CIP",
"desc": "High level Processing System"
}
],
"vertices": {
"V0": {
"VM": "system",
"VT": "BC"
},
"V1": {
"VH": "2",
"VM": "system",
"VT": "VR"
},
"V2": {
"VH": "2",
"VT": "PM",
"TU": "active"
},
"V3": {
"VT": "AC",
"BA": "0x43C00000",
"HA": "0x43C0FFFF",
"BP": "C_BASEADDR",
"HP": "C_HIGHADDR",
"MA": "Data",
"MX": "/processing_system7_0",
"MI": "M_AXI_GP0",
"MS": "SEG_mydna_read_v1_0_0_reg0",
"MV": "xilinx.com:ip:processing_system7:5.5",
"SX": "/mydna_read_v1_0_0",
"SI": "s00_axi",
"SS": "reg0",
"SV": "xilinx.com:module_ref:mydna_read_v1_0:1.0",
"TM": "both",
"TU": "register"
}
},
"edges": [
{
"src": "V0",
"trg": "V1"
},
{
"src": "V1",
"trg": "V2"
},
{
"src": "V3",
"trg": "V2",
"EH": "2"
}
]
}
}
Debug_FW.ip_user_files/sim_scripts/system/riviera/system.sh
Executable
+264
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@@ -0,0 +1,264 @@
#!/usr/bin/env bash
#**********************************************************************************************************
# Vivado (TM) v2023.2 (64-bit)
#
# Script generated by Vivado on Mon May 25 15:47:32 CST 2026
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Filename : system.sh
# Simulator : Aldec Riviera-PRO Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : system.sh
# system.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# system.sh [-reset_run]
# system.sh [-reset_log]
# system.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
# switch with the directory path where the library is created while generating the script
# with export_simulation.
#
# Alternatively, you can set the library path by setting the following project property:-
#
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
#
# You can also point to the simulation library by either setting the 'lib_map_path' global
# variable in this script or specify it with the '-lib_map_path' switch while executing this
# script (type 'system.sh -help' for more information).
#
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
# sources, then the library path MUST be specified upfront when calling export_simulation.
#
# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#**********************************************************************************************************
# catch pipeline exit status
set -Eeuo pipefail
# script info
echo -e "system.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./system.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
runvsimsa -do "do {compile.do}" 2>&1 | tee -a compile.log
}
# RUN_STEP: <simulate>
simulate()
{
runvsimsa -l simulate.log -do "do {simulate.do}"
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous design library mappings
true
else
# map simulator index file
map_setup_file
fi
}
# map library.cfg file
map_setup_file()
{
file="library.cfg"
if [[ ($lib_map_path == "") ]]; then
lib_map_path="/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/proj_cal.cache/compile_simlib/riviera"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
if [[ -e $src_file ]]; then
vmap -link $lib_map_path
fi
fi
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./system.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: system.sh [-help]\n\
Usage: system.sh [-step]\n\
Usage: system.sh [-lib_map_path]\n\
Usage: system.sh [-reset_run]\n\
Usage: system.sh [-reset_log]\n\
Usage: system.sh [-keep_index]\n\
Usage: system.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (compile, simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
Debug_FW.ip_user_files/sim_scripts/system/riviera/system.udo
View File
Debug_FW.ip_user_files/sim_scripts/system/riviera/xilinx-zynq.cc
Executable
+106
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/*
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*
* Copyright (c) 2016, Xilinx Inc.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <inttypes.h>
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
using namespace sc_core;
using namespace std;
#include "xilinx-zynq.h"
#include <sys/types.h>
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
// Iremoteport_tlm_sync *sync)
// : remoteport_tlm(name, -1, sk_descr, sync),
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
: remoteport_tlm(name, -1, sk_descr),
rp_m_axi_gp0("rp_m_axi_gp0"),
rp_m_axi_gp1("rp_m_axi_gp1"),
rp_s_axi_gp0("rp_s_axi_gp0"),
rp_s_axi_gp1("rp_s_axi_gp1"),
rp_s_axi_hp0("rp_s_axi_hp0"),
rp_s_axi_hp1("rp_s_axi_hp1"),
rp_s_axi_hp2("rp_s_axi_hp2"),
rp_s_axi_hp3("rp_s_axi_hp3"),
rp_s_axi_acp("rp_s_axi_acp"),
rp_wires_in("wires_in", 20, 0),
rp_wires_out("wires_out", 0, 17),
rp_irq_out("irq_out", 0, 28),
pl2ps_irq("pl2ps_irq", 20),
ps2pl_irq("ps2pl_irq", 28),
ps2pl_rst("ps2pl_rst", 17)
{
int i;
m_axi_gp[0] = &rp_m_axi_gp0.sk;
m_axi_gp[1] = &rp_m_axi_gp1.sk;
s_axi_gp[0] = &rp_s_axi_gp0.sk;
s_axi_gp[1] = &rp_s_axi_gp1.sk;
s_axi_hp[0] = &rp_s_axi_hp0.sk;
s_axi_hp[1] = &rp_s_axi_hp1.sk;
s_axi_hp[2] = &rp_s_axi_hp2.sk;
s_axi_hp[3] = &rp_s_axi_hp3.sk;
s_axi_acp = &rp_s_axi_acp.sk;
/* PL to PS Interrupt signals. */
for (i = 0; i < 20; i++) {
rp_wires_in.wires_in[i](pl2ps_irq[i]);
}
/* PS to PL Interrupt signals. */
for (i = 0; i < 28; i++) {
rp_irq_out.wires_out[i](ps2pl_irq[i]);
}
/* PS to PL resets. */
for (i = 0; i < 17; i++) {
rp_wires_out.wires_out[i](ps2pl_rst[i]);
}
register_dev(0, &rp_s_axi_gp0);
register_dev(1, &rp_s_axi_gp1);
register_dev(2, &rp_s_axi_hp0);
register_dev(3, &rp_s_axi_hp1);
register_dev(4, &rp_s_axi_hp2);
register_dev(5, &rp_s_axi_hp3);
register_dev(6, &rp_s_axi_acp);
register_dev(7, &rp_m_axi_gp0);
register_dev(8, &rp_m_axi_gp1);
register_dev(9, &rp_wires_in);
register_dev(10, &rp_wires_out);
register_dev(11, &rp_irq_out);
}
Debug_FW.ip_user_files/sim_scripts/system/vcs/README.txt
+50
View File
@@ -0,0 +1,50 @@
################################################################################
# Vivado (TM) v2023.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Mon May 25 15:47:32 CST 2026
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./system.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './system.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
Debug_FW.ip_user_files/sim_scripts/system/vcs/file_info.txt
+31
View File
@@ -0,0 +1,31 @@
axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_cdc.sv,systemverilog,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_memory.sv,systemverilog,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_15,../../../../proj_cal.gen/sources_1/bd/system/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_17,../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_dna_port_read_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_dna_port_read_0_0/sim/system_dna_port_read_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_mydna_read_v1_0_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_mydna_read_v1_0_0_0/sim/system_mydna_read_v1_0_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_14,../../../../proj_cal.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_rst_ps7_0_100M_1.vhd,vhdl,xil_defaultlib,../../../bd/system/ip/system_rst_ps7_0_100M_1/sim/system_rst_ps7_0_100M_1.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_1,../../../../proj_cal.gen/sources_1/bd/system/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/simulation/fifo_generator_vlog_beh.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_28,../../../../proj_cal.gen/sources_1/bd/system/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_register_slice_v2_1_vl_rfs.v,verilog,axi_register_slice_v2_1_29,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../proj_cal.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_auto_pc_0/sim/system_auto_pc_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
Debug_FW.ip_user_files/sim_scripts/system/vcs/glbl.v
+84
View File
@@ -0,0 +1,84 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Debug_FW.ip_user_files/sim_scripts/system/vcs/libps7.dll
+47
View File
@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/vcs/libps7.so
+47
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/vcs/libremoteport.dll
+47
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// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/vcs/libremoteport.so
+47
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@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/vcs/ps7_init.h
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/******************************************************************************
*
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Debug_FW.ip_user_files/sim_scripts/system/vcs/ps7_init.html
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Debug_FW.ip_user_files/sim_scripts/system/vcs/ps7_init.tcl
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proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x0007FFFF 0x00001082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x0003F03F 0x0003C008
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x00010000 0x00000000
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000703FF 0x000003FF
mask_write 0XF800620C 0x000703FF 0x000003FF
mask_write 0XF8006210 0x000703FF 0x000003FF
mask_write 0XF8006214 0x000703FF 0x000003FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x000003FF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_3_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_2_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x000073FF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_1_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666
proc mask_poll { addr mask } {
set count 1
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
while { $maskedval == 0 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
set count [ expr { $count + 1 } ]
if { $count == 100000000 } {
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
break
}
}
}
proc mask_delay { addr val } {
set delay [ get_number_of_cycles_for_delay $val ]
perf_reset_and_start_timer
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
while { $maskedval == 1 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
}
perf_reset_clock
}
proc ps_version { } {
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
return $mask_sil_ver;
}
proc ps7_post_config {} {
set saved_mode [configparams force-mem-accesses]
configparams force-mem-accesses 1
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_post_config_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_post_config_2_0
} else {
ps7_post_config_3_0
}
configparams force-mem-accesses $saved_mode
}
proc ps7_debug {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_debug_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_debug_2_0
} else {
ps7_debug_3_0
}
}
proc ps7_init {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_mio_init_data_1_0
ps7_pll_init_data_1_0
ps7_clock_init_data_1_0
ps7_ddr_init_data_1_0
ps7_peripherals_init_data_1_0
#puts "PCW Silicon Version : 1.0"
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_mio_init_data_2_0
ps7_pll_init_data_2_0
ps7_clock_init_data_2_0
ps7_ddr_init_data_2_0
ps7_peripherals_init_data_2_0
#puts "PCW Silicon Version : 2.0"
} else {
ps7_mio_init_data_3_0
ps7_pll_init_data_3_0
ps7_clock_init_data_3_0
ps7_ddr_init_data_3_0
ps7_peripherals_init_data_3_0
#puts "PCW Silicon Version : 3.0"
}
}
# For delay calculation using global timer
# start timer
proc perf_start_clock { } {
#writing SCU_GLOBAL_TIMER_CONTROL register
mask_write 0xF8F00208 0x00000109 0x00000009
}
# stop timer and reset timer count regs
proc perf_reset_clock { } {
perf_disable_clock
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
}
# Compute mask for given delay in miliseconds
proc get_number_of_cycles_for_delay { delay } {
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
variable APU_FREQ
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
}
# stop timer
proc perf_disable_clock {} {
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
}
proc perf_reset_and_start_timer {} {
perf_reset_clock
perf_start_clock
}
Debug_FW.ip_user_files/sim_scripts/system/vcs/ps7_init_gpl.h
Executable
+131
View File
@@ -0,0 +1,131 @@
/******************************************************************************
*
* Copyright (C) 2010-2020 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Debug_FW.ip_user_files/sim_scripts/system/vcs/simulate.do
+2
View File
@@ -0,0 +1,2 @@
run 1000ns
quit
Debug_FW.ip_user_files/sim_scripts/system/vcs/system.bda
Executable
+226
View File
@@ -0,0 +1,226 @@
{
"graphjs": {
"version": "1.0",
"keys": [
{
"abrv": "VH",
"name": "vert_hid",
"type": "int",
"for": "node"
},
{
"abrv": "VM",
"name": "vert_name",
"type": "string",
"for": "node"
},
{
"abrv": "VT",
"name": "vert_type",
"type": "string",
"for": "node"
},
{
"abrv": "BA",
"name": "base_addr",
"type": "string",
"for": "node"
},
{
"abrv": "HA",
"name": "high_addr",
"type": "string",
"for": "node"
},
{
"abrv": "BP",
"name": "base_param",
"type": "string",
"for": "node"
},
{
"abrv": "HP",
"name": "high_param",
"type": "string",
"for": "node"
},
{
"abrv": "MA",
"name": "master_addrspace",
"type": "string",
"for": "node"
},
{
"abrv": "MX",
"name": "master_instance",
"type": "string",
"for": "node"
},
{
"abrv": "MI",
"name": "master_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MS",
"name": "master_segment",
"type": "string",
"for": "node"
},
{
"abrv": "MV",
"name": "master_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "SX",
"name": "slave_instance",
"type": "string",
"for": "node"
},
{
"abrv": "SI",
"name": "slave_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MM",
"name": "slave_memmap",
"type": "string",
"for": "node"
},
{
"abrv": "SS",
"name": "slave_segment",
"type": "string",
"for": "node"
},
{
"abrv": "SV",
"name": "slave_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "TM",
"name": "memory_type",
"type": "string",
"for": "node"
},
{
"abrv": "TU",
"name": "usage_type",
"type": "string",
"for": "node"
},
{
"abrv": "LT",
"name": "lock_type",
"type": "string",
"for": "node"
},
{
"abrv": "BT",
"name": "boot_type",
"type": "string",
"for": "node"
},
{
"abrv": "EH",
"name": "edge_hid",
"type": "int",
"for": "edge"
}
],
"vertice_type_order": [
{
"abrv": "BC",
"desc": "Block Container"
},
{
"abrv": "PR",
"desc": "Parital Reference"
},
{
"abrv": "VR",
"desc": "Variant"
},
{
"abrv": "PM",
"desc": "Variant Permutations"
},
{
"abrv": "CX",
"desc": "Boundary Connection"
},
{
"abrv": "AC",
"desc": "Assignment Coordinate"
},
{
"abrv": "ACE",
"desc": "Excluded Assign Coordinate"
},
{
"abrv": "APX",
"desc": "Boundary Aperture"
},
{
"abrv": "CIP",
"desc": "High level Processing System"
}
],
"vertices": {
"V0": {
"VM": "system",
"VT": "BC"
},
"V1": {
"VH": "2",
"VM": "system",
"VT": "VR"
},
"V2": {
"VH": "2",
"VT": "PM",
"TU": "active"
},
"V3": {
"VT": "AC",
"BA": "0x43C00000",
"HA": "0x43C0FFFF",
"BP": "C_BASEADDR",
"HP": "C_HIGHADDR",
"MA": "Data",
"MX": "/processing_system7_0",
"MI": "M_AXI_GP0",
"MS": "SEG_mydna_read_v1_0_0_reg0",
"MV": "xilinx.com:ip:processing_system7:5.5",
"SX": "/mydna_read_v1_0_0",
"SI": "s00_axi",
"SS": "reg0",
"SV": "xilinx.com:module_ref:mydna_read_v1_0:1.0",
"TM": "both",
"TU": "register"
}
},
"edges": [
{
"src": "V0",
"trg": "V1"
},
{
"src": "V1",
"trg": "V2"
},
{
"src": "V3",
"trg": "V2",
"EH": "2"
}
]
}
}
Debug_FW.ip_user_files/sim_scripts/system/vcs/system.sh
Executable
+416
View File
@@ -0,0 +1,416 @@
#!/usr/bin/env bash
#**********************************************************************************************************
# Vivado (TM) v2023.2 (64-bit)
#
# Script generated by Vivado on Mon May 25 15:47:32 CST 2026
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
#
# Filename : system.sh
# Simulator : Synopsys Verilog Compiler Simulator
# Description : Simulation script generated by export_simulation Tcl command
# Purpose : Run 'compile', 'elaborate', 'simulate' steps for compiling, elaborating and simulating the
# design. The script will copy the library mapping file from the compiled library directory,
# create design library directories and library mappings in the mapping file.
#
# Usage : system.sh
# system.sh [-lib_map_path] [-step] [-keep_index] [-noclean_files]*
# system.sh [-reset_run]
# system.sh [-reset_log]
# system.sh [-help]
#
# * The -noclean_files switch is deprecated and will not peform any function (by default, the
# simulator generated files will not be removed unless -reset_run switch is used)
#
# Prerequisite : Before running export_simulation, you must first compile the AMD simulation library
# using the 'compile_simlib' Tcl command (for more information, run 'compile_simlib -help'
# command in the Vivado Tcl shell). After compiling the library, specify the -lib_map_path
# switch with the directory path where the library is created while generating the script
# with export_simulation.
#
# Alternatively, you can set the library path by setting the following project property:-
#
# set_property compxlib.<simulator>_compiled_library_dir <path> [current_project]
#
# You can also point to the simulation library by either setting the 'lib_map_path' global
# variable in this script or specify it with the '-lib_map_path' switch while executing this
# script (type 'system.sh -help' for more information).
#
# Note: For pure RTL based designs, the -lib_map_path switch can be specified later with the
# generated script, but if design is targetted for system simulation containing SystemC/C++/C
# sources, then the library path MUST be specified upfront when calling export_simulation.
#
# For more information, refer 'Vivado Design Suite User Guide:Logic simulation (UG900)'
#
#**********************************************************************************************************
# catch pipeline exit status
set -Eeuo pipefail
# set vhdlan compile options
vhdlan_opts="-full64 -l .tmp_log"
# set vlogan compile options
vlogan_opts="-full64 -l .tmp_log"
# set vcs elaboration options
vcs_elab_opts="-full64 -debug_acc+pp+dmptf -t ps -licqueue -l elaborate.log"
# set vcs simulation options
vcs_sim_opts="-ucli -licqueue -l simulate.log "
# set design libraries
design_libs=(xilinx_vip xpm axi_infrastructure_v1_1_0 axi_vip_v1_1_15 processing_system7_vip_v1_0_17 xil_defaultlib lib_cdc_v1_0_2 proc_sys_reset_v5_0_14 generic_baseblocks_v2_1_1 fifo_generator_v13_2_9 axi_data_fifo_v2_1_28 axi_register_slice_v2_1_29 axi_protocol_converter_v2_1_29)
# simulation root library directory
sim_lib_dir="vcs_lib"
# script info
echo -e "system.sh - Script generated by export_simulation (Vivado v2023.2 (64-bit)-id)\n"
# main steps
run()
{
check_args $*
setup
if [[ ($b_step == 1) ]]; then
case $step in
"compile" )
init_lib
compile
;;
"elaborate" )
elaborate
;;
"simulate" )
simulate
;;
* )
echo -e "ERROR: Invalid or missing step '$step' (type \"./system.sh -help\" for more information)\n"
exit 1
esac
else
init_lib
compile
elaborate
simulate
fi
}
# RUN_STEP: <compile>
compile()
{
vlogan -work xilinx_vip $vlogan_opts -sverilog +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv" \
"/data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv" \
2>&1 | tee compile.log; cat .tmp_log > vlogan.log 2>/dev/null
vlogan -work xpm $vlogan_opts -sverilog +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vhdlan -work xpm $vhdlan_opts \
"/data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd" \
2>&1 | tee -a compile.log; cat .tmp_log > vhdlan.log 2>/dev/null
vlogan -work axi_infrastructure_v1_1_0 $vlogan_opts +v2k +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vlogan -work axi_vip_v1_1_15 $vlogan_opts -sverilog +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vlogan -work processing_system7_vip_v1_0_17 $vlogan_opts -sverilog +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v" \
"../../../bd/system/ip/system_dna_port_read_0_0/sim/system_dna_port_read_0_0.v" \
"../../../bd/system/ip/system_mydna_read_v1_0_0_0/sim/system_mydna_read_v1_0_0_0.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vhdlan -work lib_cdc_v1_0_2 $vhdlan_opts \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd" \
2>&1 | tee -a compile.log; cat .tmp_log >> vhdlan.log 2>/dev/null
vhdlan -work proc_sys_reset_v5_0_14 $vhdlan_opts \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd" \
2>&1 | tee -a compile.log; cat .tmp_log >> vhdlan.log 2>/dev/null
vhdlan -work xil_defaultlib $vhdlan_opts \
"../../../bd/system/ip/system_rst_ps7_0_100M_1/sim/system_rst_ps7_0_100M_1.vhd" \
2>&1 | tee -a compile.log; cat .tmp_log >> vhdlan.log 2>/dev/null
vlogan -work generic_baseblocks_v2_1_1 $vlogan_opts +v2k +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vlogan -work fifo_generator_v13_2_9 $vlogan_opts +v2k +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/simulation/fifo_generator_vlog_beh.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vhdlan -work fifo_generator_v13_2_9 $vhdlan_opts \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd" \
2>&1 | tee -a compile.log; cat .tmp_log >> vhdlan.log 2>/dev/null
vlogan -work fifo_generator_v13_2_9 $vlogan_opts +v2k +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vlogan -work axi_data_fifo_v2_1_28 $vlogan_opts +v2k +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vlogan -work axi_register_slice_v2_1_29 $vlogan_opts +v2k +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vlogan -work axi_protocol_converter_v2_1_29 $vlogan_opts +v2k +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../../proj_cal.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl" +incdir+"../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl" +incdir+"/data/xilinx/Vivado/2023.2/data/xilinx_vip/include" \
"../../../bd/system/ip/system_auto_pc_0/sim/system_auto_pc_0.v" \
"../../../bd/system/sim/system.v" \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
vlogan -work xil_defaultlib $vlogan_opts +v2k \
glbl.v \
2>&1 | tee -a compile.log; cat .tmp_log >> vlogan.log 2>/dev/null
}
# RUN_STEP: <elaborate>
elaborate()
{
vcs $vcs_elab_opts xil_defaultlib.system xil_defaultlib.glbl -o system_simv
}
# RUN_STEP: <simulate>
simulate()
{
./system_simv $vcs_sim_opts -do simulate.do
}
# STEP: setup
setup()
{
# delete previous files for a clean rerun
if [[ ($b_reset_run == 1) ]]; then
reset_run
echo -e "INFO: Simulation run files deleted.\n"
exit 0
fi
# delete previous log files
if [[ ($b_reset_log == 1) ]]; then
reset_log
echo -e "INFO: Simulation run log files deleted.\n"
exit 0
fi
# add any setup/initialization commands here:-
# <user specific commands>
}
# simulator index file/library directory processing
init_lib()
{
if [[ ($b_keep_index == 1) ]]; then
# keep previous design library mappings
true
else
# define design library mappings
create_lib_mappings
fi
if [[ ($b_keep_index == 1) ]]; then
# do not recreate design library directories
true
else
# create design library directories
create_lib_dir
fi
}
# define design library mappings
create_lib_mappings()
{
file="synopsys_sim.setup"
if [[ -e $file ]]; then
if [[ ($lib_map_path == "") ]]; then
return
else
rm -rf $file
fi
fi
touch $file
if [[ ($lib_map_path == "") ]]; then
lib_map_path="/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/proj_cal.cache/compile_simlib/vcs"
fi
for (( i=0; i<${#design_libs[*]}; i++ )); do
lib="${design_libs[i]}"
mapping="$lib:$sim_lib_dir/$lib"
echo $mapping >> $file
done
if [[ ($lib_map_path != "") ]]; then
incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
echo $incl_ref >> $file
fi
}
# create design library directory
create_lib_dir()
{
if [[ -e $sim_lib_dir ]]; then
rm -rf $sim_lib_dir
fi
for (( i=0; i<${#design_libs[*]}; i++ )); do
lib="${design_libs[i]}"
lib_dir="$sim_lib_dir/$lib"
if [[ ! -e $lib_dir ]]; then
mkdir -p $lib_dir
fi
done
}
# delete generated data from the previous run
reset_run()
{
files_to_remove=(ucli.key system_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .tmp_log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log lib_sc.so 64 AN.DB csrc system_simv.daidir vcs_lib c.obj)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# delete generated log files from the previous run
reset_log()
{
files_to_remove=(vlogan.log vhdlan.log compile.log elaborate.log simulate.log .tmp_log)
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
file="${files_to_remove[i]}"
if [[ -e $file ]]; then
rm -rf $file
fi
done
}
# check switch argument value
check_arg_value()
{
if [[ ($1 == "-step") && (($2 != "compile") && ($2 != "elaborate") && ($2 != "simulate")) ]];then
echo -e "ERROR: Invalid or missing step '$2' (type \"./top.sh -help\" for more information)\n"
exit 1
fi
if [[ ($1 == "-lib_map_path") && ($2 == "") ]];then
echo -e "ERROR: Simulation library directory path not specified (type \"./system.sh -help\" for more information)\n"
exit 1
fi
}
# check command line arguments
check_args()
{
arg_count=$#
if [[ ("$#" == 1) && (("$1" == "-help") || ("$1" == "-h")) ]]; then
usage
fi
while [[ "$#" -gt 0 ]]; do
case $1 in
-step) check_arg_value $1 $2;step=$2; b_step=1; shift;;
-lib_map_path) check_arg_value $1 $2;lib_map_path=$2; b_lib_map_path=1; shift;;
-gen_bypass) b_gen_bypass=1 ;;
-reset_run) b_reset_run=1 ;;
-reset_log) b_reset_log=1 ;;
-keep_index) b_keep_index=1 ;;
-noclean_files) b_noclean_files=1 ;;
-help|-h) ;;
*) echo -e "ERROR: Invalid option specified '$1' (type "./top.sh -help" for more information)\n"; exit 1 ;;
esac
shift
done
# -reset_run is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_run == 1) ]]; then
echo -e "ERROR: -reset_run switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -reset_log is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_reset_log == 1) ]]; then
echo -e "ERROR: -reset_log switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -keep_index is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_keep_index == 1) ]]; then
echo -e "ERROR: -keep_index switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
# -noclean_files is not applicable with other switches
if [[ ("$arg_count" -gt 1) && ($b_noclean_files == 1) ]]; then
echo -e "ERROR: -noclean_files switch is not applicable with other switches (type \"./top.sh -help\" for more information)\n"
exit 1
fi
}
# script usage
usage()
{
msg="Usage: system.sh [-help]\n\
Usage: system.sh [-step]\n\
Usage: system.sh [-lib_map_path]\n\
Usage: system.sh [-reset_run]\n\
Usage: system.sh [-reset_log]\n\
Usage: system.sh [-keep_index]\n\
Usage: system.sh [-noclean_files]\n\n\
[-help] -- Print help information for this script\n\n\
[-step <name>] -- Execute specified step (compile, elaborate, simulate)\n\n\
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
[-reset_run] -- Delete simulator generated data files from the previous run and recreate simulator setup\n\
file/library mappings for a clean run. This switch will not execute steps defined in the script.\n\n\
NOTE: To keep simulator index file settings from the previous run, use the -keep_index switch\n\
NOTE: To regenerate simulator index file but keep the simulator generated files, use the -noclean_files switch\n\n\
[-reset_log] -- Delete simulator generated log files from the previous run\n\n\
[-keep_index] -- Keep simulator index file settings from the previous run\n\n\
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run\n"
echo -e $msg
exit 0
}
# initialize globals
step=""
lib_map_path=""
b_step=0
b_lib_map_path=0
b_gen_bypass=0
b_reset_run=0
b_reset_log=0
b_keep_index=0
b_noclean_files=0
# launch script
run $*
Debug_FW.ip_user_files/sim_scripts/system/vcs/xilinx-zynq.cc
Executable
+106
View File
@@ -0,0 +1,106 @@
/*
* Xilinx SystemC/TLM-2.0 Zynq Wrapper.
*
* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
*
* Copyright (c) 2016, Xilinx Inc.
* All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include <inttypes.h>
#include "tlm_utils/simple_initiator_socket.h"
#include "tlm_utils/simple_target_socket.h"
using namespace sc_core;
using namespace std;
#include "xilinx-zynq.h"
#include <sys/types.h>
//xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr,
// Iremoteport_tlm_sync *sync)
// : remoteport_tlm(name, -1, sk_descr, sync),
xilinx_zynq::xilinx_zynq(sc_module_name name, const char *sk_descr)
: remoteport_tlm(name, -1, sk_descr),
rp_m_axi_gp0("rp_m_axi_gp0"),
rp_m_axi_gp1("rp_m_axi_gp1"),
rp_s_axi_gp0("rp_s_axi_gp0"),
rp_s_axi_gp1("rp_s_axi_gp1"),
rp_s_axi_hp0("rp_s_axi_hp0"),
rp_s_axi_hp1("rp_s_axi_hp1"),
rp_s_axi_hp2("rp_s_axi_hp2"),
rp_s_axi_hp3("rp_s_axi_hp3"),
rp_s_axi_acp("rp_s_axi_acp"),
rp_wires_in("wires_in", 20, 0),
rp_wires_out("wires_out", 0, 17),
rp_irq_out("irq_out", 0, 28),
pl2ps_irq("pl2ps_irq", 20),
ps2pl_irq("ps2pl_irq", 28),
ps2pl_rst("ps2pl_rst", 17)
{
int i;
m_axi_gp[0] = &rp_m_axi_gp0.sk;
m_axi_gp[1] = &rp_m_axi_gp1.sk;
s_axi_gp[0] = &rp_s_axi_gp0.sk;
s_axi_gp[1] = &rp_s_axi_gp1.sk;
s_axi_hp[0] = &rp_s_axi_hp0.sk;
s_axi_hp[1] = &rp_s_axi_hp1.sk;
s_axi_hp[2] = &rp_s_axi_hp2.sk;
s_axi_hp[3] = &rp_s_axi_hp3.sk;
s_axi_acp = &rp_s_axi_acp.sk;
/* PL to PS Interrupt signals. */
for (i = 0; i < 20; i++) {
rp_wires_in.wires_in[i](pl2ps_irq[i]);
}
/* PS to PL Interrupt signals. */
for (i = 0; i < 28; i++) {
rp_irq_out.wires_out[i](ps2pl_irq[i]);
}
/* PS to PL resets. */
for (i = 0; i < 17; i++) {
rp_wires_out.wires_out[i](ps2pl_rst[i]);
}
register_dev(0, &rp_s_axi_gp0);
register_dev(1, &rp_s_axi_gp1);
register_dev(2, &rp_s_axi_hp0);
register_dev(3, &rp_s_axi_hp1);
register_dev(4, &rp_s_axi_hp2);
register_dev(5, &rp_s_axi_hp3);
register_dev(6, &rp_s_axi_acp);
register_dev(7, &rp_m_axi_gp0);
register_dev(8, &rp_m_axi_gp1);
register_dev(9, &rp_wires_in);
register_dev(10, &rp_wires_out);
register_dev(11, &rp_irq_out);
}
Debug_FW.ip_user_files/sim_scripts/system/xcelium/README.txt
+50
View File
@@ -0,0 +1,50 @@
################################################################################
# Vivado (TM) v2023.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and how to fetch design source file details
# from the file_info.txt file.
#
# Generated by export_simulation on Mon May 25 15:47:32 CST 2026
#
################################################################################
1. Steps to run the generated simulation script
From the shell prompt in the current directory, issue the following command:-
./system.sh
This command will launch the 'compile', 'elaborate' and 'simulate' functions
implemented in the script file for the 3-step flow. These functions are called
from the main 'run' function in the script file.
The 'run' function first calls the 'check_args' function, the purpose of which
is to verify the generated script arguments and print error if incorrect switch
is specified. The 'run' function then calls the 'setup' function, the purpose of
which is to specify custom or initialization commands. The function also executes
following sub-functions:-
'reset_run' if -reset_run switch is specified.
'reset_log' if -reset_log switch is specified.
The purpose of 'reset_run' function' is to delete the simulator generated design
data from the previous run and the purpose of 'reset_log' function' is to delete
the simulator generated log files.
The 'run' function then calls the 'init_lib' function, the purpose of which is to
create design library mappings and directories. This function is called before the
'compile' step. By default, if '-step' switch is specified with the script then the
script will execute that specfic step, else it will execute all steps applicable
for the target simulator.
For more information on the script, please type './system.sh -help'
2. Design source file information
export_simulation generates a 'file_info.txt' file that contains design file information
based on the compile order when export_simulation was executed from Vivado. The file
contains information about the file name, type, library it is compiled into, whether
it is part of the IP, associated library, file path information in a comma separated
format. This file can be parsed to extract the required information for generating a
custom script or can be read from verification test infra.
Debug_FW.ip_user_files/sim_scripts/system/xcelium/file_info.txt
+31
View File
@@ -0,0 +1,31 @@
axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../../data/xilinx/Vivado/2023.2/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_cdc.sv,systemverilog,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_memory.sv,systemverilog,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../data/xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_infrastructure_v1_1_vl_rfs.v,verilog,axi_infrastructure_v1_1_0,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_vip_v1_1_vl_rfs.sv,systemverilog,axi_vip_v1_1_15,../../../../proj_cal.gen/sources_1/bd/system/ipshared/5753/hdl/axi_vip_v1_1_vl_rfs.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
processing_system7_vip_v1_0_vl_rfs.sv,systemverilog,processing_system7_vip_v1_0_17,../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl/processing_system7_vip_v1_0_vl_rfs.sv,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_processing_system7_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_processing_system7_0_0/sim/system_processing_system7_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_dna_port_read_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_dna_port_read_0_0/sim/system_dna_port_read_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_mydna_read_v1_0_0_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_mydna_read_v1_0_0_0/sim/system_mydna_read_v1_0_0_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
lib_cdc_v1_0_rfs.vhd,vhdl,lib_cdc_v1_0_2,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
proc_sys_reset_v5_0_vh_rfs.vhd,vhdl,proc_sys_reset_v5_0_14,../../../../proj_cal.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_rst_ps7_0_100M_1.vhd,vhdl,xil_defaultlib,../../../bd/system/ip/system_rst_ps7_0_100M_1/sim/system_rst_ps7_0_100M_1.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
generic_baseblocks_v2_1_vl_rfs.v,verilog,generic_baseblocks_v2_1_1,../../../../proj_cal.gen/sources_1/bd/system/ipshared/10ab/hdl/generic_baseblocks_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/simulation/fifo_generator_vlog_beh.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.vhd,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_9,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ac72/hdl/fifo_generator_v13_2_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_data_fifo_v2_1_vl_rfs.v,verilog,axi_data_fifo_v2_1_28,../../../../proj_cal.gen/sources_1/bd/system/ipshared/279e/hdl/axi_data_fifo_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_register_slice_v2_1_vl_rfs.v,verilog,axi_register_slice_v2_1_29,../../../../proj_cal.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
axi_protocol_converter_v2_1_vl_rfs.v,verilog,axi_protocol_converter_v2_1_29,../../../../proj_cal.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system_auto_pc_0.v,verilog,xil_defaultlib,../../../bd/system/ip/system_auto_pc_0/sim/system_auto_pc_0.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
system.v,verilog,xil_defaultlib,../../../bd/system/sim/system.v,incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/ec67/hdl"incdir="../../../../proj_cal.gen/sources_1/bd/system/ipshared/6b2b/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
Debug_FW.ip_user_files/sim_scripts/system/xcelium/glbl.v
+84
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@@ -0,0 +1,84 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif
Debug_FW.ip_user_files/sim_scripts/system/xcelium/hdl.var
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Debug_FW.ip_user_files/sim_scripts/system/xcelium/libps7.dll
+47
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@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/xcelium/libps7.so
+47
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@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/xcelium/libremoteport.dll
+47
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@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/xcelium/libremoteport.so
+47
View File
@@ -0,0 +1,47 @@
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
Debug_FW.ip_user_files/sim_scripts/system/xcelium/ps7_init.h
Executable
+117
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@@ -0,0 +1,117 @@
/******************************************************************************
*
* Copyright (C) 2010-2020 Xilinx, Inc. All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Debug_FW.ip_user_files/sim_scripts/system/xcelium/ps7_init.html
+117178
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Debug_FW.ip_user_files/sim_scripts/system/xcelium/ps7_init.tcl
+745
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@@ -0,0 +1,745 @@
proc ps7_pll_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_3_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x0007FFFF 0x00001082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00000003 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x0003F03F 0x0003C008
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x00010000 0x00000000
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x00000200 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
mask_write 0XF8006120 0x7FFFFFCF 0x40000001
mask_write 0XF8006124 0x7FFFFFCF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000703FF 0x000003FF
mask_write 0XF800620C 0x000703FF 0x000003FF
mask_write 0XF8006210 0x000703FF 0x000003FF
mask_write 0XF8006214 0x000703FF 0x000003FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF5 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000001 0x00000001
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x000003FF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_3_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_3_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_2_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF8006078 0x03FFFFFF 0x00466111
mask_write 0XF800607C 0x000FFFFF 0x00032222
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x00007FFF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_2_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_2_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
proc ps7_pll_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000110 0x003FFFF0 0x000FA220
mask_write 0XF8000100 0x0007F000 0x00028000
mask_write 0XF8000100 0x00000010 0x00000010
mask_write 0XF8000100 0x00000001 0x00000001
mask_write 0XF8000100 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000001
mask_write 0XF8000100 0x00000010 0x00000000
mask_write 0XF8000120 0x1F003F30 0x1F000200
mask_write 0XF8000114 0x003FFFF0 0x0012C220
mask_write 0XF8000104 0x0007F000 0x00020000
mask_write 0XF8000104 0x00000010 0x00000010
mask_write 0XF8000104 0x00000001 0x00000001
mask_write 0XF8000104 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000002
mask_write 0XF8000104 0x00000010 0x00000000
mask_write 0XF8000124 0xFFF00003 0x0C200003
mask_write 0XF8000118 0x003FFFF0 0x001452C0
mask_write 0XF8000108 0x0007F000 0x0001E000
mask_write 0XF8000108 0x00000010 0x00000010
mask_write 0XF8000108 0x00000001 0x00000001
mask_write 0XF8000108 0x00000001 0x00000000
mask_poll 0XF800010C 0x00000004
mask_write 0XF8000108 0x00000010 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_clock_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000128 0x03F03F01 0x00700F01
mask_write 0XF8000138 0x00000011 0x00000001
mask_write 0XF8000140 0x03F03F71 0x00100801
mask_write 0XF800014C 0x00003F31 0x00000701
mask_write 0XF8000150 0x00003F33 0x00001401
mask_write 0XF8000154 0x00003F33 0x00000A02
mask_write 0XF8000168 0x00003F31 0x00000501
mask_write 0XF8000170 0x03F03F30 0x00200500
mask_write 0XF80001C4 0x00000001 0x00000001
mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
mwr -force 0XF8000004 0x0000767B
}
proc ps7_ddr_init_data_1_0 {} {
mask_write 0XF8006000 0x0001FFFF 0x00000080
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
mask_write 0XF800600C 0x03FFFFFF 0x02001001
mask_write 0XF8006010 0x03FFFFFF 0x00014001
mask_write 0XF8006014 0x001FFFFF 0x0004285B
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
mask_write 0XF8006028 0x00003FFF 0x00002007
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
mask_write 0XF8006038 0x00001FC3 0x00000000
mask_write 0XF800603C 0x000FFFFF 0x00000777
mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
mask_write 0XF8006044 0x0FFFFFFF 0x0F666666
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
mask_write 0XF8006058 0x0001FFFF 0x00000101
mask_write 0XF800605C 0x0000FFFF 0x00005003
mask_write 0XF8006060 0x000017FF 0x0000003E
mask_write 0XF8006064 0x00021FE0 0x00020000
mask_write 0XF8006068 0x03FFFFFF 0x00284141
mask_write 0XF800606C 0x0000FFFF 0x00001610
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
mask_write 0XF80060AC 0x000001FF 0x000001FE
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
mask_write 0XF80060B4 0x000007FF 0x00000200
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
mask_write 0XF80060C4 0x00000003 0x00000000
mask_write 0XF80060C8 0x000000FF 0x00000000
mask_write 0XF80060DC 0x00000001 0x00000000
mask_write 0XF80060F0 0x0000FFFF 0x00000000
mask_write 0XF80060F4 0x0000000F 0x00000008
mask_write 0XF8006114 0x000000FF 0x00000000
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
mask_write 0XF8006120 0x7FFFFFFF 0x40000001
mask_write 0XF8006124 0x7FFFFFFF 0x40000001
mask_write 0XF800612C 0x000FFFFF 0x00029000
mask_write 0XF8006130 0x000FFFFF 0x00029000
mask_write 0XF8006134 0x000FFFFF 0x00029000
mask_write 0XF8006138 0x000FFFFF 0x00029000
mask_write 0XF8006140 0x000FFFFF 0x00000035
mask_write 0XF8006144 0x000FFFFF 0x00000035
mask_write 0XF8006148 0x000FFFFF 0x00000035
mask_write 0XF800614C 0x000FFFFF 0x00000035
mask_write 0XF8006154 0x000FFFFF 0x00000080
mask_write 0XF8006158 0x000FFFFF 0x00000080
mask_write 0XF800615C 0x000FFFFF 0x00000080
mask_write 0XF8006160 0x000FFFFF 0x00000080
mask_write 0XF8006168 0x001FFFFF 0x000000F9
mask_write 0XF800616C 0x001FFFFF 0x000000F9
mask_write 0XF8006170 0x001FFFFF 0x000000F9
mask_write 0XF8006174 0x001FFFFF 0x000000F9
mask_write 0XF800617C 0x000FFFFF 0x000000C0
mask_write 0XF8006180 0x000FFFFF 0x000000C0
mask_write 0XF8006184 0x000FFFFF 0x000000C0
mask_write 0XF8006188 0x000FFFFF 0x000000C0
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
mask_write 0XF8006208 0x000F03FF 0x000803FF
mask_write 0XF800620C 0x000F03FF 0x000803FF
mask_write 0XF8006210 0x000F03FF 0x000803FF
mask_write 0XF8006214 0x000F03FF 0x000803FF
mask_write 0XF8006218 0x000F03FF 0x000003FF
mask_write 0XF800621C 0x000F03FF 0x000003FF
mask_write 0XF8006220 0x000F03FF 0x000003FF
mask_write 0XF8006224 0x000F03FF 0x000003FF
mask_write 0XF80062A8 0x00000FF7 0x00000000
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
mask_write 0XF80062B0 0x003FFFFF 0x00005125
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
mask_poll 0XF8000B74 0x00002000
mask_write 0XF8006000 0x0001FFFF 0x00000081
mask_poll 0XF8006054 0x00000007
}
proc ps7_mio_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B40 0x00000FFF 0x00000600
mask_write 0XF8000B44 0x00000FFF 0x00000600
mask_write 0XF8000B48 0x00000FFF 0x00000672
mask_write 0XF8000B4C 0x00000FFF 0x00000672
mask_write 0XF8000B50 0x00000FFF 0x00000674
mask_write 0XF8000B54 0x00000FFF 0x00000674
mask_write 0XF8000B58 0x00000FFF 0x00000600
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
mask_write 0XF8000B6C 0x000073FF 0x00000260
mask_write 0XF8000B70 0x00000021 0x00000021
mask_write 0XF8000B70 0x00000021 0x00000020
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
mask_write 0XF8000704 0x00003FFF 0x00001602
mask_write 0XF8000708 0x00003FFF 0x00000602
mask_write 0XF800070C 0x00003FFF 0x00000602
mask_write 0XF8000710 0x00003FFF 0x00000602
mask_write 0XF8000714 0x00003FFF 0x00000602
mask_write 0XF8000718 0x00003FFF 0x00000602
mask_write 0XF8000720 0x00003FFF 0x00000602
mask_write 0XF8000740 0x00003FFF 0x00001202
mask_write 0XF8000744 0x00003FFF 0x00001202
mask_write 0XF8000748 0x00003FFF 0x00001202
mask_write 0XF800074C 0x00003FFF 0x00001202
mask_write 0XF8000750 0x00003FFF 0x00001202
mask_write 0XF8000754 0x00003FFF 0x00001202
mask_write 0XF8000758 0x00003FFF 0x00001203
mask_write 0XF800075C 0x00003FFF 0x00001203
mask_write 0XF8000760 0x00003FFF 0x00001203
mask_write 0XF8000764 0x00003FFF 0x00001203
mask_write 0XF8000768 0x00003FFF 0x00001203
mask_write 0XF800076C 0x00003FFF 0x00001203
mask_write 0XF80007A0 0x00003FFF 0x00001280
mask_write 0XF80007A4 0x00003FFF 0x00001280
mask_write 0XF80007A8 0x00003FFF 0x00001280
mask_write 0XF80007AC 0x00003FFF 0x00001280
mask_write 0XF80007B0 0x00003FFF 0x00001280
mask_write 0XF80007B4 0x00003FFF 0x00001280
mask_write 0XF80007B8 0x00003F01 0x00001201
mask_write 0XF80007BC 0x00003F01 0x00001201
mask_write 0XF80007C0 0x00003FFF 0x000012E0
mask_write 0XF80007C4 0x00003FFF 0x000012E1
mask_write 0XF80007D0 0x00003FFF 0x00001280
mask_write 0XF80007D4 0x00003FFF 0x00001280
mask_write 0XF8000830 0x003F003F 0x002F002E
mwr -force 0XF8000004 0x0000767B
}
proc ps7_peripherals_init_data_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000B48 0x00000180 0x00000180
mask_write 0XF8000B4C 0x00000180 0x00000180
mask_write 0XF8000B50 0x00000180 0x00000180
mask_write 0XF8000B54 0x00000180 0x00000180
mwr -force 0XF8000004 0x0000767B
mask_write 0XE0001034 0x000000FF 0x00000006
mask_write 0XE0001018 0x0000FFFF 0x0000007C
mask_write 0XE0001000 0x000001FF 0x00000017
mask_write 0XE0001004 0x00000FFF 0x00000020
mask_write 0XE000D000 0x00080000 0x00080000
mask_write 0XF8007000 0x20000000 0x00000000
}
proc ps7_post_config_1_0 {} {
mwr -force 0XF8000008 0x0000DF0D
mask_write 0XF8000900 0x0000000F 0x0000000F
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
mwr -force 0XF8000004 0x0000767B
}
proc ps7_debug_1_0 {} {
mwr -force 0XF8898FB0 0xC5ACCE55
mwr -force 0XF8899FB0 0xC5ACCE55
mwr -force 0XF8809FB0 0xC5ACCE55
}
set PCW_SILICON_VER_1_0 "0x0"
set PCW_SILICON_VER_2_0 "0x1"
set PCW_SILICON_VER_3_0 "0x2"
set APU_FREQ 666666666
proc mask_poll { addr mask } {
set count 1
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
while { $maskedval == 0 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval & $mask}]
set count [ expr { $count + 1 } ]
if { $count == 100000000 } {
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
break
}
}
}
proc mask_delay { addr val } {
set delay [ get_number_of_cycles_for_delay $val ]
perf_reset_and_start_timer
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
while { $maskedval == 1 } {
set curval "0x[string range [mrd $addr] end-8 end]"
set maskedval [expr {$curval < $delay}]
}
perf_reset_clock
}
proc ps_version { } {
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
return $mask_sil_ver;
}
proc ps7_post_config {} {
set saved_mode [configparams force-mem-accesses]
configparams force-mem-accesses 1
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_post_config_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_post_config_2_0
} else {
ps7_post_config_3_0
}
configparams force-mem-accesses $saved_mode
}
proc ps7_debug {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_debug_1_0
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_debug_2_0
} else {
ps7_debug_3_0
}
}
proc ps7_init {} {
variable PCW_SILICON_VER_1_0
variable PCW_SILICON_VER_2_0
variable PCW_SILICON_VER_3_0
set sil_ver [ps_version]
if { $sil_ver == $PCW_SILICON_VER_1_0} {
ps7_mio_init_data_1_0
ps7_pll_init_data_1_0
ps7_clock_init_data_1_0
ps7_ddr_init_data_1_0
ps7_peripherals_init_data_1_0
#puts "PCW Silicon Version : 1.0"
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
ps7_mio_init_data_2_0
ps7_pll_init_data_2_0
ps7_clock_init_data_2_0
ps7_ddr_init_data_2_0
ps7_peripherals_init_data_2_0
#puts "PCW Silicon Version : 2.0"
} else {
ps7_mio_init_data_3_0
ps7_pll_init_data_3_0
ps7_clock_init_data_3_0
ps7_ddr_init_data_3_0
ps7_peripherals_init_data_3_0
#puts "PCW Silicon Version : 3.0"
}
}
# For delay calculation using global timer
# start timer
proc perf_start_clock { } {
#writing SCU_GLOBAL_TIMER_CONTROL register
mask_write 0xF8F00208 0x00000109 0x00000009
}
# stop timer and reset timer count regs
proc perf_reset_clock { } {
perf_disable_clock
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
}
# Compute mask for given delay in miliseconds
proc get_number_of_cycles_for_delay { delay } {
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
variable APU_FREQ
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
}
# stop timer
proc perf_disable_clock {} {
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
}
proc perf_reset_and_start_timer {} {
perf_reset_clock
perf_start_clock
}
Debug_FW.ip_user_files/sim_scripts/system/xcelium/ps7_init_gpl.h
Executable
+131
View File
@@ -0,0 +1,131 @@
/******************************************************************************
*
* Copyright (C) 2010-2020 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 142857132
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 50000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 100000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
Debug_FW.ip_user_files/sim_scripts/system/xcelium/simulate.do
+7
View File
@@ -0,0 +1,7 @@
set pack_assert_off {numeric_std std_logic_arith}
database -open waves -into waves.shm -default
catch {probe -create -shm -all -variables -depth 1} msg
run 1000ns
exit
Debug_FW.ip_user_files/sim_scripts/system/xcelium/system.bda
Executable
+226
View File
@@ -0,0 +1,226 @@
{
"graphjs": {
"version": "1.0",
"keys": [
{
"abrv": "VH",
"name": "vert_hid",
"type": "int",
"for": "node"
},
{
"abrv": "VM",
"name": "vert_name",
"type": "string",
"for": "node"
},
{
"abrv": "VT",
"name": "vert_type",
"type": "string",
"for": "node"
},
{
"abrv": "BA",
"name": "base_addr",
"type": "string",
"for": "node"
},
{
"abrv": "HA",
"name": "high_addr",
"type": "string",
"for": "node"
},
{
"abrv": "BP",
"name": "base_param",
"type": "string",
"for": "node"
},
{
"abrv": "HP",
"name": "high_param",
"type": "string",
"for": "node"
},
{
"abrv": "MA",
"name": "master_addrspace",
"type": "string",
"for": "node"
},
{
"abrv": "MX",
"name": "master_instance",
"type": "string",
"for": "node"
},
{
"abrv": "MI",
"name": "master_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MS",
"name": "master_segment",
"type": "string",
"for": "node"
},
{
"abrv": "MV",
"name": "master_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "SX",
"name": "slave_instance",
"type": "string",
"for": "node"
},
{
"abrv": "SI",
"name": "slave_interface",
"type": "string",
"for": "node"
},
{
"abrv": "MM",
"name": "slave_memmap",
"type": "string",
"for": "node"
},
{
"abrv": "SS",
"name": "slave_segment",
"type": "string",
"for": "node"
},
{
"abrv": "SV",
"name": "slave_vlnv",
"type": "string",
"for": "node"
},
{
"abrv": "TM",
"name": "memory_type",
"type": "string",
"for": "node"
},
{
"abrv": "TU",
"name": "usage_type",
"type": "string",
"for": "node"
},
{
"abrv": "LT",
"name": "lock_type",
"type": "string",
"for": "node"
},
{
"abrv": "BT",
"name": "boot_type",
"type": "string",
"for": "node"
},
{
"abrv": "EH",
"name": "edge_hid",
"type": "int",
"for": "edge"
}
],
"vertice_type_order": [
{
"abrv": "BC",
"desc": "Block Container"
},
{
"abrv": "PR",
"desc": "Parital Reference"
},
{
"abrv": "VR",
"desc": "Variant"
},
{
"abrv": "PM",
"desc": "Variant Permutations"
},
{
"abrv": "CX",
"desc": "Boundary Connection"
},
{
"abrv": "AC",
"desc": "Assignment Coordinate"
},
{
"abrv": "ACE",
"desc": "Excluded Assign Coordinate"
},
{
"abrv": "APX",
"desc": "Boundary Aperture"
},
{
"abrv": "CIP",
"desc": "High level Processing System"
}
],
"vertices": {
"V0": {
"VM": "system",
"VT": "BC"
},
"V1": {
"VH": "2",
"VM": "system",
"VT": "VR"
},
"V2": {
"VH": "2",
"VT": "PM",
"TU": "active"
},
"V3": {
"VT": "AC",
"BA": "0x43C00000",
"HA": "0x43C0FFFF",
"BP": "C_BASEADDR",
"HP": "C_HIGHADDR",
"MA": "Data",
"MX": "/processing_system7_0",
"MI": "M_AXI_GP0",
"MS": "SEG_mydna_read_v1_0_0_reg0",
"MV": "xilinx.com:ip:processing_system7:5.5",
"SX": "/mydna_read_v1_0_0",
"SI": "s00_axi",
"SS": "reg0",
"SV": "xilinx.com:module_ref:mydna_read_v1_0:1.0",
"TM": "both",
"TU": "register"
}
},
"edges": [
{
"src": "V0",
"trg": "V1"
},
{
"src": "V1",
"trg": "V2"
},
{
"src": "V3",
"trg": "V2",
"EH": "2"
}
]
}
}

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