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This commit is contained in:
Jeremy Shen
2026-05-27 09:56:09 +00:00
commit ee3ede1152
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Debug_FW.ip_user_files/bd/system/sim/system.protoinst
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{
"version": "1.0",
"modules": {
"system": {
"proto_instances": {
"/mydna_read_v1_0_0/s00_axi": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "s00_axi_aclk"},
"ARADDR": { "actual": "s00_axi_araddr[3:0]"},
"ARESETN": { "actual": "s00_axi_aresetn"},
"ARPROT": { "actual": "s00_axi_arprot[2:0]"},
"ARREADY": { "actual": "s00_axi_arready"},
"ARVALID": { "actual": "s00_axi_arvalid"},
"AWADDR": { "actual": "s00_axi_awaddr[3:0]"},
"AWPROT": { "actual": "s00_axi_awprot[2:0]"},
"AWREADY": { "actual": "s00_axi_awready"},
"AWVALID": { "actual": "s00_axi_awvalid"},
"BREADY": { "actual": "s00_axi_bready"},
"BRESP": { "actual": "s00_axi_bresp[1:0]"},
"BVALID": { "actual": "s00_axi_bvalid"},
"RDATA": { "actual": "s00_axi_rdata[31:0]"},
"RREADY": { "actual": "s00_axi_rready"},
"RRESP": { "actual": "s00_axi_rresp[1:0]"},
"RVALID": { "actual": "s00_axi_rvalid"},
"WDATA": { "actual": "s00_axi_wdata[31:0]"},
"WREADY": { "actual": "s00_axi_wready"},
"WSTRB": { "actual": "s00_axi_wstrb[3:0]"},
"WVALID": { "actual": "s00_axi_wvalid"}
}
},
"/processing_system7_0/M_AXI_GP0": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_AXI_GP0_ACLK"},
"ARADDR": { "actual": "M_AXI_GP0_ARADDR[31:0]"},
"ARBURST": { "actual": "M_AXI_GP0_ARBURST[1:0]"},
"ARCACHE": { "actual": "M_AXI_GP0_ARCACHE[3:0]"},
"ARID": { "actual": "M_AXI_GP0_ARID[11:0]"},
"ARLEN": { "actual": "M_AXI_GP0_ARLEN[3:0]"},
"ARLOCK": { "actual": "M_AXI_GP0_ARLOCK[1:0]"},
"ARPROT": { "actual": "M_AXI_GP0_ARPROT[2:0]"},
"ARQOS": { "actual": "M_AXI_GP0_ARQOS[3:0]"},
"ARREADY": { "actual": "M_AXI_GP0_ARREADY"},
"ARSIZE": { "actual": "M_AXI_GP0_ARSIZE[2:0]"},
"ARVALID": { "actual": "M_AXI_GP0_ARVALID"},
"AWADDR": { "actual": "M_AXI_GP0_AWADDR[31:0]"},
"AWBURST": { "actual": "M_AXI_GP0_AWBURST[1:0]"},
"AWCACHE": { "actual": "M_AXI_GP0_AWCACHE[3:0]"},
"AWID": { "actual": "M_AXI_GP0_AWID[11:0]"},
"AWLEN": { "actual": "M_AXI_GP0_AWLEN[3:0]"},
"AWLOCK": { "actual": "M_AXI_GP0_AWLOCK[1:0]"},
"AWPROT": { "actual": "M_AXI_GP0_AWPROT[2:0]"},
"AWQOS": { "actual": "M_AXI_GP0_AWQOS[3:0]"},
"AWREADY": { "actual": "M_AXI_GP0_AWREADY"},
"AWSIZE": { "actual": "M_AXI_GP0_AWSIZE[2:0]"},
"AWVALID": { "actual": "M_AXI_GP0_AWVALID"},
"BID": { "actual": "M_AXI_GP0_BID[11:0]"},
"BREADY": { "actual": "M_AXI_GP0_BREADY"},
"BRESP": { "actual": "M_AXI_GP0_BRESP[1:0]"},
"BVALID": { "actual": "M_AXI_GP0_BVALID"},
"RDATA": { "actual": "M_AXI_GP0_RDATA[31:0]"},
"RID": { "actual": "M_AXI_GP0_RID[11:0]"},
"RLAST": { "actual": "M_AXI_GP0_RLAST"},
"RREADY": { "actual": "M_AXI_GP0_RREADY"},
"RRESP": { "actual": "M_AXI_GP0_RRESP[1:0]"},
"RVALID": { "actual": "M_AXI_GP0_RVALID"},
"WDATA": { "actual": "M_AXI_GP0_WDATA[31:0]"},
"WID": { "actual": "M_AXI_GP0_WID[11:0]"},
"WLAST": { "actual": "M_AXI_GP0_WLAST"},
"WREADY": { "actual": "M_AXI_GP0_WREADY"},
"WSTRB": { "actual": "M_AXI_GP0_WSTRB[3:0]"},
"WVALID": { "actual": "M_AXI_GP0_WVALID"}
}
},
"/ps7_0_axi_periph/M00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M00_ACLK"},
"ARADDR": { "actual": "M00_AXI_araddr[31:0]"},
"ARESETN": { "actual": "ARESETN"},
"ARPROT": { "actual": "M00_AXI_arprot[2:0]"},
"ARREADY": { "actual": "M00_AXI_arready"},
"ARVALID": { "actual": "M00_AXI_arvalid"},
"AWADDR": { "actual": "M00_AXI_awaddr[31:0]"},
"AWPROT": { "actual": "M00_AXI_awprot[2:0]"},
"AWREADY": { "actual": "M00_AXI_awready"},
"AWVALID": { "actual": "M00_AXI_awvalid"},
"BREADY": { "actual": "M00_AXI_bready"},
"BRESP": { "actual": "M00_AXI_bresp[1:0]"},
"BVALID": { "actual": "M00_AXI_bvalid"},
"RDATA": { "actual": "M00_AXI_rdata[31:0]"},
"RREADY": { "actual": "M00_AXI_rready"},
"RRESP": { "actual": "M00_AXI_rresp[1:0]"},
"RVALID": { "actual": "M00_AXI_rvalid"},
"WDATA": { "actual": "M00_AXI_wdata[31:0]"},
"WREADY": { "actual": "M00_AXI_wready"},
"WSTRB": { "actual": "M00_AXI_wstrb[3:0]"},
"WVALID": { "actual": "M00_AXI_wvalid"}
}
},
"/ps7_0_axi_periph/S00_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S00_ACLK"},
"ARADDR": { "actual": "S00_AXI_araddr[31:0]"},
"ARBURST": { "actual": "S00_AXI_arburst[1:0]"},
"ARCACHE": { "actual": "S00_AXI_arcache[3:0]"},
"ARESETN": { "actual": "ARESETN"},
"ARID": { "actual": "S00_AXI_arid[11:0]"},
"ARLEN": { "actual": "S00_AXI_arlen[3:0]"},
"ARLOCK": { "actual": "S00_AXI_arlock[1:0]"},
"ARPROT": { "actual": "S00_AXI_arprot[2:0]"},
"ARQOS": { "actual": "S00_AXI_arqos[3:0]"},
"ARREADY": { "actual": "S00_AXI_arready"},
"ARSIZE": { "actual": "S00_AXI_arsize[2:0]"},
"ARVALID": { "actual": "S00_AXI_arvalid"},
"AWADDR": { "actual": "S00_AXI_awaddr[31:0]"},
"AWBURST": { "actual": "S00_AXI_awburst[1:0]"},
"AWCACHE": { "actual": "S00_AXI_awcache[3:0]"},
"AWID": { "actual": "S00_AXI_awid[11:0]"},
"AWLEN": { "actual": "S00_AXI_awlen[3:0]"},
"AWLOCK": { "actual": "S00_AXI_awlock[1:0]"},
"AWPROT": { "actual": "S00_AXI_awprot[2:0]"},
"AWQOS": { "actual": "S00_AXI_awqos[3:0]"},
"AWREADY": { "actual": "S00_AXI_awready"},
"AWSIZE": { "actual": "S00_AXI_awsize[2:0]"},
"AWVALID": { "actual": "S00_AXI_awvalid"},
"BID": { "actual": "S00_AXI_bid[11:0]"},
"BREADY": { "actual": "S00_AXI_bready"},
"BRESP": { "actual": "S00_AXI_bresp[1:0]"},
"BVALID": { "actual": "S00_AXI_bvalid"},
"RDATA": { "actual": "S00_AXI_rdata[31:0]"},
"RID": { "actual": "S00_AXI_rid[11:0]"},
"RLAST": { "actual": "S00_AXI_rlast"},
"RREADY": { "actual": "S00_AXI_rready"},
"RRESP": { "actual": "S00_AXI_rresp[1:0]"},
"RVALID": { "actual": "S00_AXI_rvalid"},
"WDATA": { "actual": "S00_AXI_wdata[31:0]"},
"WID": { "actual": "S00_AXI_wid[11:0]"},
"WLAST": { "actual": "S00_AXI_wlast"},
"WREADY": { "actual": "S00_AXI_wready"},
"WSTRB": { "actual": "S00_AXI_wstrb[3:0]"},
"WVALID": { "actual": "S00_AXI_wvalid"}
}
},
"/ps7_0_axi_periph/s00_couplers/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "M_ACLK"},
"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
"ARESETN": { "actual": "M_ARESETN"},
"ARPROT": { "actual": "M_AXI_arprot[2:0]"},
"ARREADY": { "actual": "M_AXI_arready"},
"ARVALID": { "actual": "M_AXI_arvalid"},
"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
"AWPROT": { "actual": "M_AXI_awprot[2:0]"},
"AWREADY": { "actual": "M_AXI_awready"},
"AWVALID": { "actual": "M_AXI_awvalid"},
"BREADY": { "actual": "M_AXI_bready"},
"BRESP": { "actual": "M_AXI_bresp[1:0]"},
"BVALID": { "actual": "M_AXI_bvalid"},
"RDATA": { "actual": "M_AXI_rdata[31:0]"},
"RREADY": { "actual": "M_AXI_rready"},
"RRESP": { "actual": "M_AXI_rresp[1:0]"},
"RVALID": { "actual": "M_AXI_rvalid"},
"WDATA": { "actual": "M_AXI_wdata[31:0]"},
"WREADY": { "actual": "M_AXI_wready"},
"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
"WVALID": { "actual": "M_AXI_wvalid"}
}
},
"/ps7_0_axi_periph/s00_couplers/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "S_ACLK"},
"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
"ARBURST": { "actual": "S_AXI_arburst[1:0]"},
"ARCACHE": { "actual": "S_AXI_arcache[3:0]"},
"ARESETN": { "actual": "S_ARESETN"},
"ARID": { "actual": "S_AXI_arid[11:0]"},
"ARLEN": { "actual": "S_AXI_arlen[3:0]"},
"ARLOCK": { "actual": "S_AXI_arlock[1:0]"},
"ARPROT": { "actual": "S_AXI_arprot[2:0]"},
"ARQOS": { "actual": "S_AXI_arqos[3:0]"},
"ARREADY": { "actual": "S_AXI_arready"},
"ARSIZE": { "actual": "S_AXI_arsize[2:0]"},
"ARVALID": { "actual": "S_AXI_arvalid"},
"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
"AWBURST": { "actual": "S_AXI_awburst[1:0]"},
"AWCACHE": { "actual": "S_AXI_awcache[3:0]"},
"AWID": { "actual": "S_AXI_awid[11:0]"},
"AWLEN": { "actual": "S_AXI_awlen[3:0]"},
"AWLOCK": { "actual": "S_AXI_awlock[1:0]"},
"AWPROT": { "actual": "S_AXI_awprot[2:0]"},
"AWQOS": { "actual": "S_AXI_awqos[3:0]"},
"AWREADY": { "actual": "S_AXI_awready"},
"AWSIZE": { "actual": "S_AXI_awsize[2:0]"},
"AWVALID": { "actual": "S_AXI_awvalid"},
"BID": { "actual": "S_AXI_bid[11:0]"},
"BREADY": { "actual": "S_AXI_bready"},
"BRESP": { "actual": "S_AXI_bresp[1:0]"},
"BVALID": { "actual": "S_AXI_bvalid"},
"RDATA": { "actual": "S_AXI_rdata[31:0]"},
"RID": { "actual": "S_AXI_rid[11:0]"},
"RLAST": { "actual": "S_AXI_rlast"},
"RREADY": { "actual": "S_AXI_rready"},
"RRESP": { "actual": "S_AXI_rresp[1:0]"},
"RVALID": { "actual": "S_AXI_rvalid"},
"WDATA": { "actual": "S_AXI_wdata[31:0]"},
"WID": { "actual": "S_AXI_wid[11:0]"},
"WLAST": { "actual": "S_AXI_wlast"},
"WREADY": { "actual": "S_AXI_wready"},
"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
"WVALID": { "actual": "S_AXI_wvalid"}
}
},
"/ps7_0_axi_periph/s00_couplers/auto_pc/M_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "m_axi_araddr[31:0]"},
"ARESETN": { "actual": "aresetn"},
"ARPROT": { "actual": "m_axi_arprot[2:0]"},
"ARREADY": { "actual": "m_axi_arready"},
"ARVALID": { "actual": "m_axi_arvalid"},
"AWADDR": { "actual": "m_axi_awaddr[31:0]"},
"AWPROT": { "actual": "m_axi_awprot[2:0]"},
"AWREADY": { "actual": "m_axi_awready"},
"AWVALID": { "actual": "m_axi_awvalid"},
"BREADY": { "actual": "m_axi_bready"},
"BRESP": { "actual": "m_axi_bresp[1:0]"},
"BVALID": { "actual": "m_axi_bvalid"},
"RDATA": { "actual": "m_axi_rdata[31:0]"},
"RREADY": { "actual": "m_axi_rready"},
"RRESP": { "actual": "m_axi_rresp[1:0]"},
"RVALID": { "actual": "m_axi_rvalid"},
"WDATA": { "actual": "m_axi_wdata[31:0]"},
"WREADY": { "actual": "m_axi_wready"},
"WSTRB": { "actual": "m_axi_wstrb[3:0]"},
"WVALID": { "actual": "m_axi_wvalid"}
}
},
"/ps7_0_axi_periph/s00_couplers/auto_pc/S_AXI": {
"interface": "xilinx.com:interface:aximm:1.0",
"ports": {
"ACLK": { "actual": "aclk"},
"ARADDR": { "actual": "s_axi_araddr[31:0]"},
"ARBURST": { "actual": "s_axi_arburst[1:0]"},
"ARCACHE": { "actual": "s_axi_arcache[3:0]"},
"ARESETN": { "actual": "aresetn"},
"ARID": { "actual": "s_axi_arid[11:0]"},
"ARLEN": { "actual": "s_axi_arlen[3:0]"},
"ARLOCK": { "actual": "s_axi_arlock[1:0]"},
"ARPROT": { "actual": "s_axi_arprot[2:0]"},
"ARQOS": { "actual": "s_axi_arqos[3:0]"},
"ARREADY": { "actual": "s_axi_arready"},
"ARSIZE": { "actual": "s_axi_arsize[2:0]"},
"ARVALID": { "actual": "s_axi_arvalid"},
"AWADDR": { "actual": "s_axi_awaddr[31:0]"},
"AWBURST": { "actual": "s_axi_awburst[1:0]"},
"AWCACHE": { "actual": "s_axi_awcache[3:0]"},
"AWID": { "actual": "s_axi_awid[11:0]"},
"AWLEN": { "actual": "s_axi_awlen[3:0]"},
"AWLOCK": { "actual": "s_axi_awlock[1:0]"},
"AWPROT": { "actual": "s_axi_awprot[2:0]"},
"AWQOS": { "actual": "s_axi_awqos[3:0]"},
"AWREADY": { "actual": "s_axi_awready"},
"AWSIZE": { "actual": "s_axi_awsize[2:0]"},
"AWVALID": { "actual": "s_axi_awvalid"},
"BID": { "actual": "s_axi_bid[11:0]"},
"BREADY": { "actual": "s_axi_bready"},
"BRESP": { "actual": "s_axi_bresp[1:0]"},
"BVALID": { "actual": "s_axi_bvalid"},
"RDATA": { "actual": "s_axi_rdata[31:0]"},
"RID": { "actual": "s_axi_rid[11:0]"},
"RLAST": { "actual": "s_axi_rlast"},
"RREADY": { "actual": "s_axi_rready"},
"RRESP": { "actual": "s_axi_rresp[1:0]"},
"RVALID": { "actual": "s_axi_rvalid"},
"WDATA": { "actual": "s_axi_wdata[31:0]"},
"WID": { "actual": "s_axi_wid[11:0]"},
"WLAST": { "actual": "s_axi_wlast"},
"WREADY": { "actual": "s_axi_wready"},
"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
"WVALID": { "actual": "s_axi_wvalid"}
}
}
}
}
}
}
Debug_FW.ip_user_files/bd/system/sim/system.v
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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
//Date : Mon May 25 14:51:47 2026
//Host : mkb running 64-bit unknown
//Command : generate_target system.bd
//Design : system
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module s00_couplers_imp_11SE3QO
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN;
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
system_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
(* CORE_GENERATION_INFO = "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=7,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=2,da_clkrst_cnt=2,da_ps7_cnt=1,synth_mode=None}" *) (* HW_HANDOFF = "system.hwdef" *)
module system
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
EMIO_0_tri_i,
EMIO_0_tri_o,
EMIO_0_tri_t,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_dm;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_dq;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_dqs_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_dqs_p;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 EMIO_0 TRI_I" *) input [32:0]EMIO_0_tri_i;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 EMIO_0 TRI_O" *) output [32:0]EMIO_0_tri_o;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 EMIO_0 TRI_T" *) output [32:0]EMIO_0_tri_t;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]FIXED_IO_mio;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb;
wire [56:0]dna_port_read_0_dna_port;
wire dna_port_read_0_read_vld;
wire mydna_read_v1_0_0_start_vld;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_CLK0;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire [32:0]processing_system7_0_GPIO_0_TRI_I;
wire [32:0]processing_system7_0_GPIO_0_TRI_O;
wire [32:0]processing_system7_0_GPIO_0_TRI_T;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [31:0]ps7_0_axi_periph_M00_AXI_ARADDR;
wire [2:0]ps7_0_axi_periph_M00_AXI_ARPROT;
wire ps7_0_axi_periph_M00_AXI_ARREADY;
wire ps7_0_axi_periph_M00_AXI_ARVALID;
wire [31:0]ps7_0_axi_periph_M00_AXI_AWADDR;
wire [2:0]ps7_0_axi_periph_M00_AXI_AWPROT;
wire ps7_0_axi_periph_M00_AXI_AWREADY;
wire ps7_0_axi_periph_M00_AXI_AWVALID;
wire ps7_0_axi_periph_M00_AXI_BREADY;
wire [1:0]ps7_0_axi_periph_M00_AXI_BRESP;
wire ps7_0_axi_periph_M00_AXI_BVALID;
wire [31:0]ps7_0_axi_periph_M00_AXI_RDATA;
wire ps7_0_axi_periph_M00_AXI_RREADY;
wire [1:0]ps7_0_axi_periph_M00_AXI_RRESP;
wire ps7_0_axi_periph_M00_AXI_RVALID;
wire [31:0]ps7_0_axi_periph_M00_AXI_WDATA;
wire ps7_0_axi_periph_M00_AXI_WREADY;
wire [3:0]ps7_0_axi_periph_M00_AXI_WSTRB;
wire ps7_0_axi_periph_M00_AXI_WVALID;
wire [0:0]rst_ps7_0_100M_interconnect_aresetn;
wire [0:0]rst_ps7_0_100M_peripheral_aresetn;
assign EMIO_0_tri_o[32:0] = processing_system7_0_GPIO_0_TRI_O;
assign EMIO_0_tri_t[32:0] = processing_system7_0_GPIO_0_TRI_T;
assign processing_system7_0_GPIO_0_TRI_I = EMIO_0_tri_i[32:0];
system_dna_port_read_0_0 dna_port_read_0
(.clk(processing_system7_0_FCLK_CLK0),
.dna_port(dna_port_read_0_dna_port),
.read_vld(dna_port_read_0_read_vld),
.rst_n(rst_ps7_0_100M_peripheral_aresetn),
.start_vld(mydna_read_v1_0_0_start_vld));
system_mydna_read_v1_0_0_0 mydna_read_v1_0_0
(.dna_port(dna_port_read_0_dna_port),
.read_vld(dna_port_read_0_read_vld),
.s00_axi_aclk(processing_system7_0_FCLK_CLK0),
.s00_axi_araddr(ps7_0_axi_periph_M00_AXI_ARADDR[3:0]),
.s00_axi_aresetn(rst_ps7_0_100M_peripheral_aresetn),
.s00_axi_arprot(ps7_0_axi_periph_M00_AXI_ARPROT),
.s00_axi_arready(ps7_0_axi_periph_M00_AXI_ARREADY),
.s00_axi_arvalid(ps7_0_axi_periph_M00_AXI_ARVALID),
.s00_axi_awaddr(ps7_0_axi_periph_M00_AXI_AWADDR[3:0]),
.s00_axi_awprot(ps7_0_axi_periph_M00_AXI_AWPROT),
.s00_axi_awready(ps7_0_axi_periph_M00_AXI_AWREADY),
.s00_axi_awvalid(ps7_0_axi_periph_M00_AXI_AWVALID),
.s00_axi_bready(ps7_0_axi_periph_M00_AXI_BREADY),
.s00_axi_bresp(ps7_0_axi_periph_M00_AXI_BRESP),
.s00_axi_bvalid(ps7_0_axi_periph_M00_AXI_BVALID),
.s00_axi_rdata(ps7_0_axi_periph_M00_AXI_RDATA),
.s00_axi_rready(ps7_0_axi_periph_M00_AXI_RREADY),
.s00_axi_rresp(ps7_0_axi_periph_M00_AXI_RRESP),
.s00_axi_rvalid(ps7_0_axi_periph_M00_AXI_RVALID),
.s00_axi_wdata(ps7_0_axi_periph_M00_AXI_WDATA),
.s00_axi_wready(ps7_0_axi_periph_M00_AXI_WREADY),
.s00_axi_wstrb(ps7_0_axi_periph_M00_AXI_WSTRB),
.s00_axi_wvalid(ps7_0_axi_periph_M00_AXI_WVALID),
.start_vld(mydna_read_v1_0_0_start_vld));
system_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.GPIO_I(processing_system7_0_GPIO_0_TRI_I),
.GPIO_O(processing_system7_0_GPIO_0_TRI_O),
.GPIO_T(processing_system7_0_GPIO_0_TRI_T),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb));
system_ps7_0_axi_periph_1 ps7_0_axi_periph
(.ACLK(processing_system7_0_FCLK_CLK0),
.ARESETN(rst_ps7_0_100M_interconnect_aresetn),
.M00_ACLK(processing_system7_0_FCLK_CLK0),
.M00_ARESETN(rst_ps7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(ps7_0_axi_periph_M00_AXI_ARADDR),
.M00_AXI_arprot(ps7_0_axi_periph_M00_AXI_ARPROT),
.M00_AXI_arready(ps7_0_axi_periph_M00_AXI_ARREADY),
.M00_AXI_arvalid(ps7_0_axi_periph_M00_AXI_ARVALID),
.M00_AXI_awaddr(ps7_0_axi_periph_M00_AXI_AWADDR),
.M00_AXI_awprot(ps7_0_axi_periph_M00_AXI_AWPROT),
.M00_AXI_awready(ps7_0_axi_periph_M00_AXI_AWREADY),
.M00_AXI_awvalid(ps7_0_axi_periph_M00_AXI_AWVALID),
.M00_AXI_bready(ps7_0_axi_periph_M00_AXI_BREADY),
.M00_AXI_bresp(ps7_0_axi_periph_M00_AXI_BRESP),
.M00_AXI_bvalid(ps7_0_axi_periph_M00_AXI_BVALID),
.M00_AXI_rdata(ps7_0_axi_periph_M00_AXI_RDATA),
.M00_AXI_rready(ps7_0_axi_periph_M00_AXI_RREADY),
.M00_AXI_rresp(ps7_0_axi_periph_M00_AXI_RRESP),
.M00_AXI_rvalid(ps7_0_axi_periph_M00_AXI_RVALID),
.M00_AXI_wdata(ps7_0_axi_periph_M00_AXI_WDATA),
.M00_AXI_wready(ps7_0_axi_periph_M00_AXI_WREADY),
.M00_AXI_wstrb(ps7_0_axi_periph_M00_AXI_WSTRB),
.M00_AXI_wvalid(ps7_0_axi_periph_M00_AXI_WVALID),
.S00_ACLK(processing_system7_0_FCLK_CLK0),
.S00_ARESETN(rst_ps7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
system_rst_ps7_0_100M_1 rst_ps7_0_100M
(.aux_reset_in(1'b1),
.dcm_locked(1'b1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_ps7_0_100M_interconnect_aresetn),
.mb_debug_sys_rst(1'b0),
.peripheral_aresetn(rst_ps7_0_100M_peripheral_aresetn),
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
endmodule
module system_ps7_0_axi_periph_1
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arprot,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awprot,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input ARESETN;
input M00_ACLK;
input M00_ARESETN;
output [31:0]M00_AXI_araddr;
output [2:0]M00_AXI_arprot;
input M00_AXI_arready;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
output [2:0]M00_AXI_awprot;
input M00_AXI_awready;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire S00_ACLK_1;
wire S00_ARESETN_1;
wire ps7_0_axi_periph_ACLK_net;
wire ps7_0_axi_periph_ARESETN_net;
wire [31:0]ps7_0_axi_periph_to_s00_couplers_ARADDR;
wire [1:0]ps7_0_axi_periph_to_s00_couplers_ARBURST;
wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARCACHE;
wire [11:0]ps7_0_axi_periph_to_s00_couplers_ARID;
wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARLEN;
wire [1:0]ps7_0_axi_periph_to_s00_couplers_ARLOCK;
wire [2:0]ps7_0_axi_periph_to_s00_couplers_ARPROT;
wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARQOS;
wire ps7_0_axi_periph_to_s00_couplers_ARREADY;
wire [2:0]ps7_0_axi_periph_to_s00_couplers_ARSIZE;
wire ps7_0_axi_periph_to_s00_couplers_ARVALID;
wire [31:0]ps7_0_axi_periph_to_s00_couplers_AWADDR;
wire [1:0]ps7_0_axi_periph_to_s00_couplers_AWBURST;
wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWCACHE;
wire [11:0]ps7_0_axi_periph_to_s00_couplers_AWID;
wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWLEN;
wire [1:0]ps7_0_axi_periph_to_s00_couplers_AWLOCK;
wire [2:0]ps7_0_axi_periph_to_s00_couplers_AWPROT;
wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWQOS;
wire ps7_0_axi_periph_to_s00_couplers_AWREADY;
wire [2:0]ps7_0_axi_periph_to_s00_couplers_AWSIZE;
wire ps7_0_axi_periph_to_s00_couplers_AWVALID;
wire [11:0]ps7_0_axi_periph_to_s00_couplers_BID;
wire ps7_0_axi_periph_to_s00_couplers_BREADY;
wire [1:0]ps7_0_axi_periph_to_s00_couplers_BRESP;
wire ps7_0_axi_periph_to_s00_couplers_BVALID;
wire [31:0]ps7_0_axi_periph_to_s00_couplers_RDATA;
wire [11:0]ps7_0_axi_periph_to_s00_couplers_RID;
wire ps7_0_axi_periph_to_s00_couplers_RLAST;
wire ps7_0_axi_periph_to_s00_couplers_RREADY;
wire [1:0]ps7_0_axi_periph_to_s00_couplers_RRESP;
wire ps7_0_axi_periph_to_s00_couplers_RVALID;
wire [31:0]ps7_0_axi_periph_to_s00_couplers_WDATA;
wire [11:0]ps7_0_axi_periph_to_s00_couplers_WID;
wire ps7_0_axi_periph_to_s00_couplers_WLAST;
wire ps7_0_axi_periph_to_s00_couplers_WREADY;
wire [3:0]ps7_0_axi_periph_to_s00_couplers_WSTRB;
wire ps7_0_axi_periph_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_ps7_0_axi_periph_ARADDR;
wire [2:0]s00_couplers_to_ps7_0_axi_periph_ARPROT;
wire s00_couplers_to_ps7_0_axi_periph_ARREADY;
wire s00_couplers_to_ps7_0_axi_periph_ARVALID;
wire [31:0]s00_couplers_to_ps7_0_axi_periph_AWADDR;
wire [2:0]s00_couplers_to_ps7_0_axi_periph_AWPROT;
wire s00_couplers_to_ps7_0_axi_periph_AWREADY;
wire s00_couplers_to_ps7_0_axi_periph_AWVALID;
wire s00_couplers_to_ps7_0_axi_periph_BREADY;
wire [1:0]s00_couplers_to_ps7_0_axi_periph_BRESP;
wire s00_couplers_to_ps7_0_axi_periph_BVALID;
wire [31:0]s00_couplers_to_ps7_0_axi_periph_RDATA;
wire s00_couplers_to_ps7_0_axi_periph_RREADY;
wire [1:0]s00_couplers_to_ps7_0_axi_periph_RRESP;
wire s00_couplers_to_ps7_0_axi_periph_RVALID;
wire [31:0]s00_couplers_to_ps7_0_axi_periph_WDATA;
wire s00_couplers_to_ps7_0_axi_periph_WREADY;
wire [3:0]s00_couplers_to_ps7_0_axi_periph_WSTRB;
wire s00_couplers_to_ps7_0_axi_periph_WVALID;
assign M00_AXI_araddr[31:0] = s00_couplers_to_ps7_0_axi_periph_ARADDR;
assign M00_AXI_arprot[2:0] = s00_couplers_to_ps7_0_axi_periph_ARPROT;
assign M00_AXI_arvalid = s00_couplers_to_ps7_0_axi_periph_ARVALID;
assign M00_AXI_awaddr[31:0] = s00_couplers_to_ps7_0_axi_periph_AWADDR;
assign M00_AXI_awprot[2:0] = s00_couplers_to_ps7_0_axi_periph_AWPROT;
assign M00_AXI_awvalid = s00_couplers_to_ps7_0_axi_periph_AWVALID;
assign M00_AXI_bready = s00_couplers_to_ps7_0_axi_periph_BREADY;
assign M00_AXI_rready = s00_couplers_to_ps7_0_axi_periph_RREADY;
assign M00_AXI_wdata[31:0] = s00_couplers_to_ps7_0_axi_periph_WDATA;
assign M00_AXI_wstrb[3:0] = s00_couplers_to_ps7_0_axi_periph_WSTRB;
assign M00_AXI_wvalid = s00_couplers_to_ps7_0_axi_periph_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN;
assign S00_AXI_arready = ps7_0_axi_periph_to_s00_couplers_ARREADY;
assign S00_AXI_awready = ps7_0_axi_periph_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = ps7_0_axi_periph_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = ps7_0_axi_periph_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = ps7_0_axi_periph_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = ps7_0_axi_periph_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = ps7_0_axi_periph_to_s00_couplers_RID;
assign S00_AXI_rlast = ps7_0_axi_periph_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = ps7_0_axi_periph_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = ps7_0_axi_periph_to_s00_couplers_RVALID;
assign S00_AXI_wready = ps7_0_axi_periph_to_s00_couplers_WREADY;
assign ps7_0_axi_periph_ACLK_net = M00_ACLK;
assign ps7_0_axi_periph_ARESETN_net = M00_ARESETN;
assign ps7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign ps7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign ps7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign ps7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign ps7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign ps7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign ps7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign ps7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign ps7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign ps7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign ps7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign ps7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign ps7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign ps7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign ps7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign ps7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign ps7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign ps7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign ps7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign ps7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign ps7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
assign ps7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
assign ps7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign ps7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign ps7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
assign ps7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign ps7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign s00_couplers_to_ps7_0_axi_periph_ARREADY = M00_AXI_arready;
assign s00_couplers_to_ps7_0_axi_periph_AWREADY = M00_AXI_awready;
assign s00_couplers_to_ps7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
assign s00_couplers_to_ps7_0_axi_periph_BVALID = M00_AXI_bvalid;
assign s00_couplers_to_ps7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
assign s00_couplers_to_ps7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
assign s00_couplers_to_ps7_0_axi_periph_RVALID = M00_AXI_rvalid;
assign s00_couplers_to_ps7_0_axi_periph_WREADY = M00_AXI_wready;
s00_couplers_imp_11SE3QO s00_couplers
(.M_ACLK(ps7_0_axi_periph_ACLK_net),
.M_ARESETN(ps7_0_axi_periph_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_ps7_0_axi_periph_ARADDR),
.M_AXI_arprot(s00_couplers_to_ps7_0_axi_periph_ARPROT),
.M_AXI_arready(s00_couplers_to_ps7_0_axi_periph_ARREADY),
.M_AXI_arvalid(s00_couplers_to_ps7_0_axi_periph_ARVALID),
.M_AXI_awaddr(s00_couplers_to_ps7_0_axi_periph_AWADDR),
.M_AXI_awprot(s00_couplers_to_ps7_0_axi_periph_AWPROT),
.M_AXI_awready(s00_couplers_to_ps7_0_axi_periph_AWREADY),
.M_AXI_awvalid(s00_couplers_to_ps7_0_axi_periph_AWVALID),
.M_AXI_bready(s00_couplers_to_ps7_0_axi_periph_BREADY),
.M_AXI_bresp(s00_couplers_to_ps7_0_axi_periph_BRESP),
.M_AXI_bvalid(s00_couplers_to_ps7_0_axi_periph_BVALID),
.M_AXI_rdata(s00_couplers_to_ps7_0_axi_periph_RDATA),
.M_AXI_rready(s00_couplers_to_ps7_0_axi_periph_RREADY),
.M_AXI_rresp(s00_couplers_to_ps7_0_axi_periph_RRESP),
.M_AXI_rvalid(s00_couplers_to_ps7_0_axi_periph_RVALID),
.M_AXI_wdata(s00_couplers_to_ps7_0_axi_periph_WDATA),
.M_AXI_wready(s00_couplers_to_ps7_0_axi_periph_WREADY),
.M_AXI_wstrb(s00_couplers_to_ps7_0_axi_periph_WSTRB),
.M_AXI_wvalid(s00_couplers_to_ps7_0_axi_periph_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(ps7_0_axi_periph_to_s00_couplers_ARADDR),
.S_AXI_arburst(ps7_0_axi_periph_to_s00_couplers_ARBURST),
.S_AXI_arcache(ps7_0_axi_periph_to_s00_couplers_ARCACHE),
.S_AXI_arid(ps7_0_axi_periph_to_s00_couplers_ARID),
.S_AXI_arlen(ps7_0_axi_periph_to_s00_couplers_ARLEN),
.S_AXI_arlock(ps7_0_axi_periph_to_s00_couplers_ARLOCK),
.S_AXI_arprot(ps7_0_axi_periph_to_s00_couplers_ARPROT),
.S_AXI_arqos(ps7_0_axi_periph_to_s00_couplers_ARQOS),
.S_AXI_arready(ps7_0_axi_periph_to_s00_couplers_ARREADY),
.S_AXI_arsize(ps7_0_axi_periph_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(ps7_0_axi_periph_to_s00_couplers_ARVALID),
.S_AXI_awaddr(ps7_0_axi_periph_to_s00_couplers_AWADDR),
.S_AXI_awburst(ps7_0_axi_periph_to_s00_couplers_AWBURST),
.S_AXI_awcache(ps7_0_axi_periph_to_s00_couplers_AWCACHE),
.S_AXI_awid(ps7_0_axi_periph_to_s00_couplers_AWID),
.S_AXI_awlen(ps7_0_axi_periph_to_s00_couplers_AWLEN),
.S_AXI_awlock(ps7_0_axi_periph_to_s00_couplers_AWLOCK),
.S_AXI_awprot(ps7_0_axi_periph_to_s00_couplers_AWPROT),
.S_AXI_awqos(ps7_0_axi_periph_to_s00_couplers_AWQOS),
.S_AXI_awready(ps7_0_axi_periph_to_s00_couplers_AWREADY),
.S_AXI_awsize(ps7_0_axi_periph_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(ps7_0_axi_periph_to_s00_couplers_AWVALID),
.S_AXI_bid(ps7_0_axi_periph_to_s00_couplers_BID),
.S_AXI_bready(ps7_0_axi_periph_to_s00_couplers_BREADY),
.S_AXI_bresp(ps7_0_axi_periph_to_s00_couplers_BRESP),
.S_AXI_bvalid(ps7_0_axi_periph_to_s00_couplers_BVALID),
.S_AXI_rdata(ps7_0_axi_periph_to_s00_couplers_RDATA),
.S_AXI_rid(ps7_0_axi_periph_to_s00_couplers_RID),
.S_AXI_rlast(ps7_0_axi_periph_to_s00_couplers_RLAST),
.S_AXI_rready(ps7_0_axi_periph_to_s00_couplers_RREADY),
.S_AXI_rresp(ps7_0_axi_periph_to_s00_couplers_RRESP),
.S_AXI_rvalid(ps7_0_axi_periph_to_s00_couplers_RVALID),
.S_AXI_wdata(ps7_0_axi_periph_to_s00_couplers_WDATA),
.S_AXI_wid(ps7_0_axi_periph_to_s00_couplers_WID),
.S_AXI_wlast(ps7_0_axi_periph_to_s00_couplers_WLAST),
.S_AXI_wready(ps7_0_axi_periph_to_s00_couplers_WREADY),
.S_AXI_wstrb(ps7_0_axi_periph_to_s00_couplers_WSTRB),
.S_AXI_wvalid(ps7_0_axi_periph_to_s00_couplers_WVALID));
endmodule