Init Commit
This commit is contained in:
Jeremy Shen
@@ -0,0 +1,354 @@
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// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of AMD and is protected under U.S. and international copyright
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// and other intellectual property laws.
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//
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// DISCLAIMER
|
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// This disclaimer is not a license and does not grant any
|
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// rights to the materials distributed herewith. Except as
|
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// otherwise provided in a valid license issued to you by
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// AMD, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
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// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) AMD shall not be liable (whether in contract or tort,
|
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// including negligence, or under any other theory of
|
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// liability) for any loss or damage of any kind or nature
|
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
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// loss or damage suffered as a result of any action brought
|
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or AMD had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// AMD products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
|
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
|
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// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
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// IP Revision: 29
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`timescale 1ns/1ps
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(* DowngradeIPIdentifiedWarnings = "yes" *)
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module system_auto_pc_0 (
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aclk,
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aresetn,
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s_axi_awid,
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s_axi_awaddr,
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s_axi_awlen,
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s_axi_awsize,
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s_axi_awburst,
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s_axi_awlock,
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s_axi_awcache,
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s_axi_awprot,
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s_axi_awqos,
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s_axi_awvalid,
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s_axi_awready,
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s_axi_wid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wlast,
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s_axi_wvalid,
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s_axi_wready,
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s_axi_bid,
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s_axi_bresp,
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s_axi_bvalid,
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s_axi_bready,
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s_axi_arid,
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s_axi_araddr,
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s_axi_arlen,
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s_axi_arsize,
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s_axi_arburst,
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s_axi_arlock,
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s_axi_arcache,
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s_axi_arprot,
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s_axi_arqos,
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s_axi_arvalid,
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s_axi_arready,
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s_axi_rid,
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s_axi_rdata,
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s_axi_rresp,
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s_axi_rlast,
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s_axi_rvalid,
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s_axi_rready,
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m_axi_awaddr,
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m_axi_awprot,
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m_axi_awvalid,
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m_axi_awready,
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m_axi_wdata,
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m_axi_wstrb,
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m_axi_wvalid,
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m_axi_wready,
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m_axi_bresp,
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m_axi_bvalid,
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m_axi_bready,
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m_axi_araddr,
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m_axi_arprot,
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m_axi_arvalid,
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m_axi_arready,
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m_axi_rdata,
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m_axi_rresp,
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m_axi_rvalid,
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m_axi_rready
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);
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(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
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(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
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input wire aclk;
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(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
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(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
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input wire aresetn;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
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input wire [11 : 0] s_axi_awid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
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input wire [31 : 0] s_axi_awaddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
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input wire [3 : 0] s_axi_awlen;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
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input wire [2 : 0] s_axi_awsize;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
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input wire [1 : 0] s_axi_awburst;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
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input wire [1 : 0] s_axi_awlock;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
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input wire [3 : 0] s_axi_awcache;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
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input wire [2 : 0] s_axi_awprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
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input wire [3 : 0] s_axi_awqos;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
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input wire s_axi_awvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
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output wire s_axi_awready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
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input wire [11 : 0] s_axi_wid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
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input wire [31 : 0] s_axi_wdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
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input wire [3 : 0] s_axi_wstrb;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
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input wire s_axi_wlast;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
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input wire s_axi_wvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
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output wire s_axi_wready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
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output wire [11 : 0] s_axi_bid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
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output wire [1 : 0] s_axi_bresp;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
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output wire s_axi_bvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
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input wire s_axi_bready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
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input wire [11 : 0] s_axi_arid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
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input wire [31 : 0] s_axi_araddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
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input wire [3 : 0] s_axi_arlen;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
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input wire [2 : 0] s_axi_arsize;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
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input wire [1 : 0] s_axi_arburst;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
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input wire [1 : 0] s_axi_arlock;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
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input wire [3 : 0] s_axi_arcache;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
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input wire [2 : 0] s_axi_arprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
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input wire [3 : 0] s_axi_arqos;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
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input wire s_axi_arvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
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output wire s_axi_arready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
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output wire [11 : 0] s_axi_rid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
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output wire [31 : 0] s_axi_rdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
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output wire [1 : 0] s_axi_rresp;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
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output wire s_axi_rlast;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
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output wire s_axi_rvalid;
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(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4,\
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NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
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input wire s_axi_rready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
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output wire [31 : 0] m_axi_awaddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
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output wire [2 : 0] m_axi_awprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
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output wire m_axi_awvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
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input wire m_axi_awready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
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output wire [31 : 0] m_axi_wdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
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output wire [3 : 0] m_axi_wstrb;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
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output wire m_axi_wvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
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input wire m_axi_wready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
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input wire [1 : 0] m_axi_bresp;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
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input wire m_axi_bvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
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output wire m_axi_bready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
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output wire [31 : 0] m_axi_araddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
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output wire [2 : 0] m_axi_arprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
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output wire m_axi_arvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
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input wire m_axi_arready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
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input wire [31 : 0] m_axi_rdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
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input wire [1 : 0] m_axi_rresp;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
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input wire m_axi_rvalid;
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(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS \
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4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
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output wire m_axi_rready;
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axi_protocol_converter_v2_1_29_axi_protocol_converter #(
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.C_FAMILY("zynq"),
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.C_M_AXI_PROTOCOL(2),
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.C_S_AXI_PROTOCOL(1),
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.C_IGNORE_ID(0),
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.C_AXI_ID_WIDTH(12),
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.C_AXI_ADDR_WIDTH(32),
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.C_AXI_DATA_WIDTH(32),
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.C_AXI_SUPPORTS_WRITE(1),
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.C_AXI_SUPPORTS_READ(1),
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.C_AXI_SUPPORTS_USER_SIGNALS(0),
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.C_AXI_AWUSER_WIDTH(1),
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.C_AXI_ARUSER_WIDTH(1),
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.C_AXI_WUSER_WIDTH(1),
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.C_AXI_RUSER_WIDTH(1),
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.C_AXI_BUSER_WIDTH(1),
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.C_TRANSLATION_MODE(2)
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) inst (
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.aclk(aclk),
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.aresetn(aresetn),
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.s_axi_awid(s_axi_awid),
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||||
.s_axi_awaddr(s_axi_awaddr),
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||||
.s_axi_awlen(s_axi_awlen),
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||||
.s_axi_awsize(s_axi_awsize),
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||||
.s_axi_awburst(s_axi_awburst),
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||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
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||||
.s_axi_awregion(4'H0),
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||||
.s_axi_awqos(s_axi_awqos),
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||||
.s_axi_awuser(1'H0),
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||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
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||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+82
@@ -0,0 +1,82 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:module_ref:dna_port_read:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_dna_port_read_0_0 (
|
||||
clk,
|
||||
rst_n,
|
||||
start_vld,
|
||||
read_vld,
|
||||
dna_port
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
|
||||
input wire clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst_n RST" *)
|
||||
input wire rst_n;
|
||||
input wire start_vld;
|
||||
output wire read_vld;
|
||||
output wire [56 : 0] dna_port;
|
||||
|
||||
dna_port_read inst (
|
||||
.clk(clk),
|
||||
.rst_n(rst_n),
|
||||
.start_vld(start_vld),
|
||||
.read_vld(read_vld),
|
||||
.dna_port(dna_port)
|
||||
);
|
||||
endmodule
|
||||
+163
@@ -0,0 +1,163 @@
|
||||
// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of AMD and is protected under U.S. and international copyright
|
||||
// and other intellectual property laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// AMD, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) AMD shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or AMD had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// AMD products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of AMD products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:module_ref:mydna_read_v1_0:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "module_ref" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_mydna_read_v1_0_0_0 (
|
||||
start_vld,
|
||||
read_vld,
|
||||
dna_port,
|
||||
s00_axi_aclk,
|
||||
s00_axi_aresetn,
|
||||
s00_axi_awaddr,
|
||||
s00_axi_awprot,
|
||||
s00_axi_awvalid,
|
||||
s00_axi_awready,
|
||||
s00_axi_wdata,
|
||||
s00_axi_wstrb,
|
||||
s00_axi_wvalid,
|
||||
s00_axi_wready,
|
||||
s00_axi_bresp,
|
||||
s00_axi_bvalid,
|
||||
s00_axi_bready,
|
||||
s00_axi_araddr,
|
||||
s00_axi_arprot,
|
||||
s00_axi_arvalid,
|
||||
s00_axi_arready,
|
||||
s00_axi_rdata,
|
||||
s00_axi_rresp,
|
||||
s00_axi_rvalid,
|
||||
s00_axi_rready
|
||||
);
|
||||
|
||||
output wire start_vld;
|
||||
input wire read_vld;
|
||||
input wire [56 : 0] dna_port;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s00_axi_aclk, ASSOCIATED_BUSIF s00_axi, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
|
||||
input wire s00_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s00_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
|
||||
input wire s00_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
|
||||
input wire [3 : 0] s00_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
|
||||
input wire [2 : 0] s00_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
|
||||
input wire s00_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
|
||||
output wire s00_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
|
||||
input wire [31 : 0] s00_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
|
||||
input wire [3 : 0] s00_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
|
||||
input wire s00_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
|
||||
output wire s00_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
|
||||
output wire [1 : 0] s00_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
|
||||
output wire s00_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
|
||||
input wire s00_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
|
||||
input wire [3 : 0] s00_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
|
||||
input wire [2 : 0] s00_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
|
||||
input wire s00_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
|
||||
output wire s00_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
|
||||
output wire [31 : 0] s00_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
|
||||
output wire [1 : 0] s00_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
|
||||
output wire s00_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s00_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS\
|
||||
4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
|
||||
input wire s00_axi_rready;
|
||||
|
||||
mydna_read_v1_0 #(
|
||||
.C_S00_AXI_DATA_WIDTH(32),
|
||||
.C_S00_AXI_ADDR_WIDTH(4)
|
||||
) inst (
|
||||
.start_vld(start_vld),
|
||||
.read_vld(read_vld),
|
||||
.dna_port(dna_port),
|
||||
.s00_axi_aclk(s00_axi_aclk),
|
||||
.s00_axi_aresetn(s00_axi_aresetn),
|
||||
.s00_axi_awaddr(s00_axi_awaddr),
|
||||
.s00_axi_awprot(s00_axi_awprot),
|
||||
.s00_axi_awvalid(s00_axi_awvalid),
|
||||
.s00_axi_awready(s00_axi_awready),
|
||||
.s00_axi_wdata(s00_axi_wdata),
|
||||
.s00_axi_wstrb(s00_axi_wstrb),
|
||||
.s00_axi_wvalid(s00_axi_wvalid),
|
||||
.s00_axi_wready(s00_axi_wready),
|
||||
.s00_axi_bresp(s00_axi_bresp),
|
||||
.s00_axi_bvalid(s00_axi_bvalid),
|
||||
.s00_axi_bready(s00_axi_bready),
|
||||
.s00_axi_araddr(s00_axi_araddr),
|
||||
.s00_axi_arprot(s00_axi_arprot),
|
||||
.s00_axi_arvalid(s00_axi_arvalid),
|
||||
.s00_axi_arready(s00_axi_arready),
|
||||
.s00_axi_rdata(s00_axi_rdata),
|
||||
.s00_axi_rresp(s00_axi_rresp),
|
||||
.s00_axi_rvalid(s00_axi_rvalid),
|
||||
.s00_axi_rready(s00_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+584
@@ -0,0 +1,584 @@
|
||||
|
||||
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module system_processing_system7_0_0 (
|
||||
GPIO_I,
|
||||
GPIO_O,
|
||||
GPIO_T,
|
||||
M_AXI_GP0_ARVALID,
|
||||
M_AXI_GP0_AWVALID,
|
||||
M_AXI_GP0_BREADY,
|
||||
M_AXI_GP0_RREADY,
|
||||
M_AXI_GP0_WLAST,
|
||||
M_AXI_GP0_WVALID,
|
||||
M_AXI_GP0_ARID,
|
||||
M_AXI_GP0_AWID,
|
||||
M_AXI_GP0_WID,
|
||||
M_AXI_GP0_ARBURST,
|
||||
M_AXI_GP0_ARLOCK,
|
||||
M_AXI_GP0_ARSIZE,
|
||||
M_AXI_GP0_AWBURST,
|
||||
M_AXI_GP0_AWLOCK,
|
||||
M_AXI_GP0_AWSIZE,
|
||||
M_AXI_GP0_ARPROT,
|
||||
M_AXI_GP0_AWPROT,
|
||||
M_AXI_GP0_ARADDR,
|
||||
M_AXI_GP0_AWADDR,
|
||||
M_AXI_GP0_WDATA,
|
||||
M_AXI_GP0_ARCACHE,
|
||||
M_AXI_GP0_ARLEN,
|
||||
M_AXI_GP0_ARQOS,
|
||||
M_AXI_GP0_AWCACHE,
|
||||
M_AXI_GP0_AWLEN,
|
||||
M_AXI_GP0_AWQOS,
|
||||
M_AXI_GP0_WSTRB,
|
||||
M_AXI_GP0_ACLK,
|
||||
M_AXI_GP0_ARREADY,
|
||||
M_AXI_GP0_AWREADY,
|
||||
M_AXI_GP0_BVALID,
|
||||
M_AXI_GP0_RLAST,
|
||||
M_AXI_GP0_RVALID,
|
||||
M_AXI_GP0_WREADY,
|
||||
M_AXI_GP0_BID,
|
||||
M_AXI_GP0_RID,
|
||||
M_AXI_GP0_BRESP,
|
||||
M_AXI_GP0_RRESP,
|
||||
M_AXI_GP0_RDATA,
|
||||
FCLK_CLK0,
|
||||
FCLK_RESET0_N,
|
||||
MIO,
|
||||
DDR_CAS_n,
|
||||
DDR_CKE,
|
||||
DDR_Clk_n,
|
||||
DDR_Clk,
|
||||
DDR_CS_n,
|
||||
DDR_DRSTB,
|
||||
DDR_ODT,
|
||||
DDR_RAS_n,
|
||||
DDR_WEB,
|
||||
DDR_BankAddr,
|
||||
DDR_Addr,
|
||||
DDR_VRN,
|
||||
DDR_VRP,
|
||||
DDR_DM,
|
||||
DDR_DQ,
|
||||
DDR_DQS_n,
|
||||
DDR_DQS,
|
||||
PS_SRSTB,
|
||||
PS_CLK,
|
||||
PS_PORB
|
||||
);
|
||||
input [32 : 0] GPIO_I;
|
||||
output [32 : 0] GPIO_O;
|
||||
output [32 : 0] GPIO_T;
|
||||
output M_AXI_GP0_ARVALID;
|
||||
output M_AXI_GP0_AWVALID;
|
||||
output M_AXI_GP0_BREADY;
|
||||
output M_AXI_GP0_RREADY;
|
||||
output M_AXI_GP0_WLAST;
|
||||
output M_AXI_GP0_WVALID;
|
||||
output [11 : 0] M_AXI_GP0_ARID;
|
||||
output [11 : 0] M_AXI_GP0_AWID;
|
||||
output [11 : 0] M_AXI_GP0_WID;
|
||||
output [1 : 0] M_AXI_GP0_ARBURST;
|
||||
output [1 : 0] M_AXI_GP0_ARLOCK;
|
||||
output [2 : 0] M_AXI_GP0_ARSIZE;
|
||||
output [1 : 0] M_AXI_GP0_AWBURST;
|
||||
output [1 : 0] M_AXI_GP0_AWLOCK;
|
||||
output [2 : 0] M_AXI_GP0_AWSIZE;
|
||||
output [2 : 0] M_AXI_GP0_ARPROT;
|
||||
output [2 : 0] M_AXI_GP0_AWPROT;
|
||||
output [31 : 0] M_AXI_GP0_ARADDR;
|
||||
output [31 : 0] M_AXI_GP0_AWADDR;
|
||||
output [31 : 0] M_AXI_GP0_WDATA;
|
||||
output [3 : 0] M_AXI_GP0_ARCACHE;
|
||||
output [3 : 0] M_AXI_GP0_ARLEN;
|
||||
output [3 : 0] M_AXI_GP0_ARQOS;
|
||||
output [3 : 0] M_AXI_GP0_AWCACHE;
|
||||
output [3 : 0] M_AXI_GP0_AWLEN;
|
||||
output [3 : 0] M_AXI_GP0_AWQOS;
|
||||
output [3 : 0] M_AXI_GP0_WSTRB;
|
||||
input M_AXI_GP0_ACLK;
|
||||
input M_AXI_GP0_ARREADY;
|
||||
input M_AXI_GP0_AWREADY;
|
||||
input M_AXI_GP0_BVALID;
|
||||
input M_AXI_GP0_RLAST;
|
||||
input M_AXI_GP0_RVALID;
|
||||
input M_AXI_GP0_WREADY;
|
||||
input [11 : 0] M_AXI_GP0_BID;
|
||||
input [11 : 0] M_AXI_GP0_RID;
|
||||
input [1 : 0] M_AXI_GP0_BRESP;
|
||||
input [1 : 0] M_AXI_GP0_RRESP;
|
||||
input [31 : 0] M_AXI_GP0_RDATA;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_RESET0_N;
|
||||
input [53 : 0] MIO;
|
||||
input DDR_CAS_n;
|
||||
input DDR_CKE;
|
||||
input DDR_Clk_n;
|
||||
input DDR_Clk;
|
||||
input DDR_CS_n;
|
||||
input DDR_DRSTB;
|
||||
input DDR_ODT;
|
||||
input DDR_RAS_n;
|
||||
input DDR_WEB;
|
||||
input [2 : 0] DDR_BankAddr;
|
||||
input [14 : 0] DDR_Addr;
|
||||
input DDR_VRN;
|
||||
input DDR_VRP;
|
||||
input [3 : 0] DDR_DM;
|
||||
input [31 : 0] DDR_DQ;
|
||||
input [3 : 0] DDR_DQS_n;
|
||||
input [3 : 0] DDR_DQS;
|
||||
input PS_SRSTB;
|
||||
input PS_CLK;
|
||||
input PS_PORB;
|
||||
|
||||
processing_system7_vip_v1_0_17 #(
|
||||
.C_USE_M_AXI_GP0(1),
|
||||
.C_USE_M_AXI_GP1(0),
|
||||
.C_USE_S_AXI_ACP(0),
|
||||
.C_USE_S_AXI_GP0(0),
|
||||
.C_USE_S_AXI_GP1(0),
|
||||
.C_USE_S_AXI_HP0(0),
|
||||
.C_USE_S_AXI_HP1(0),
|
||||
.C_USE_S_AXI_HP2(0),
|
||||
.C_USE_S_AXI_HP3(0),
|
||||
.C_S_AXI_HP0_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP1_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP2_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP3_DATA_WIDTH(64),
|
||||
.C_HIGH_OCM_EN(0),
|
||||
.C_FCLK_CLK0_FREQ(100.0),
|
||||
.C_FCLK_CLK1_FREQ(10.0),
|
||||
.C_FCLK_CLK2_FREQ(10.0),
|
||||
.C_FCLK_CLK3_FREQ(10.0),
|
||||
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
|
||||
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
|
||||
) inst (
|
||||
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
|
||||
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_WID(M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
|
||||
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_BID(M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_RID(M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP1_ARVALID(),
|
||||
.M_AXI_GP1_AWVALID(),
|
||||
.M_AXI_GP1_BREADY(),
|
||||
.M_AXI_GP1_RREADY(),
|
||||
.M_AXI_GP1_WLAST(),
|
||||
.M_AXI_GP1_WVALID(),
|
||||
.M_AXI_GP1_ARID(),
|
||||
.M_AXI_GP1_AWID(),
|
||||
.M_AXI_GP1_WID(),
|
||||
.M_AXI_GP1_ARBURST(),
|
||||
.M_AXI_GP1_ARLOCK(),
|
||||
.M_AXI_GP1_ARSIZE(),
|
||||
.M_AXI_GP1_AWBURST(),
|
||||
.M_AXI_GP1_AWLOCK(),
|
||||
.M_AXI_GP1_AWSIZE(),
|
||||
.M_AXI_GP1_ARPROT(),
|
||||
.M_AXI_GP1_AWPROT(),
|
||||
.M_AXI_GP1_ARADDR(),
|
||||
.M_AXI_GP1_AWADDR(),
|
||||
.M_AXI_GP1_WDATA(),
|
||||
.M_AXI_GP1_ARCACHE(),
|
||||
.M_AXI_GP1_ARLEN(),
|
||||
.M_AXI_GP1_ARQOS(),
|
||||
.M_AXI_GP1_AWCACHE(),
|
||||
.M_AXI_GP1_AWLEN(),
|
||||
.M_AXI_GP1_AWQOS(),
|
||||
.M_AXI_GP1_WSTRB(),
|
||||
.M_AXI_GP1_ACLK(1'B0),
|
||||
.M_AXI_GP1_ARREADY(1'B0),
|
||||
.M_AXI_GP1_AWREADY(1'B0),
|
||||
.M_AXI_GP1_BVALID(1'B0),
|
||||
.M_AXI_GP1_RLAST(1'B0),
|
||||
.M_AXI_GP1_RVALID(1'B0),
|
||||
.M_AXI_GP1_WREADY(1'B0),
|
||||
.M_AXI_GP1_BID(12'B0),
|
||||
.M_AXI_GP1_RID(12'B0),
|
||||
.M_AXI_GP1_BRESP(2'B0),
|
||||
.M_AXI_GP1_RRESP(2'B0),
|
||||
.M_AXI_GP1_RDATA(32'B0),
|
||||
.S_AXI_GP0_ARREADY(),
|
||||
.S_AXI_GP0_AWREADY(),
|
||||
.S_AXI_GP0_BVALID(),
|
||||
.S_AXI_GP0_RLAST(),
|
||||
.S_AXI_GP0_RVALID(),
|
||||
.S_AXI_GP0_WREADY(),
|
||||
.S_AXI_GP0_BRESP(),
|
||||
.S_AXI_GP0_RRESP(),
|
||||
.S_AXI_GP0_RDATA(),
|
||||
.S_AXI_GP0_BID(),
|
||||
.S_AXI_GP0_RID(),
|
||||
.S_AXI_GP0_ACLK(1'B0),
|
||||
.S_AXI_GP0_ARVALID(1'B0),
|
||||
.S_AXI_GP0_AWVALID(1'B0),
|
||||
.S_AXI_GP0_BREADY(1'B0),
|
||||
.S_AXI_GP0_RREADY(1'B0),
|
||||
.S_AXI_GP0_WLAST(1'B0),
|
||||
.S_AXI_GP0_WVALID(1'B0),
|
||||
.S_AXI_GP0_ARBURST(2'B0),
|
||||
.S_AXI_GP0_ARLOCK(2'B0),
|
||||
.S_AXI_GP0_ARSIZE(3'B0),
|
||||
.S_AXI_GP0_AWBURST(2'B0),
|
||||
.S_AXI_GP0_AWLOCK(2'B0),
|
||||
.S_AXI_GP0_AWSIZE(3'B0),
|
||||
.S_AXI_GP0_ARPROT(3'B0),
|
||||
.S_AXI_GP0_AWPROT(3'B0),
|
||||
.S_AXI_GP0_ARADDR(32'B0),
|
||||
.S_AXI_GP0_AWADDR(32'B0),
|
||||
.S_AXI_GP0_WDATA(32'B0),
|
||||
.S_AXI_GP0_ARCACHE(4'B0),
|
||||
.S_AXI_GP0_ARLEN(4'B0),
|
||||
.S_AXI_GP0_ARQOS(4'B0),
|
||||
.S_AXI_GP0_AWCACHE(4'B0),
|
||||
.S_AXI_GP0_AWLEN(4'B0),
|
||||
.S_AXI_GP0_AWQOS(4'B0),
|
||||
.S_AXI_GP0_WSTRB(4'B0),
|
||||
.S_AXI_GP0_ARID(6'B0),
|
||||
.S_AXI_GP0_AWID(6'B0),
|
||||
.S_AXI_GP0_WID(6'B0),
|
||||
.S_AXI_GP1_ARREADY(),
|
||||
.S_AXI_GP1_AWREADY(),
|
||||
.S_AXI_GP1_BVALID(),
|
||||
.S_AXI_GP1_RLAST(),
|
||||
.S_AXI_GP1_RVALID(),
|
||||
.S_AXI_GP1_WREADY(),
|
||||
.S_AXI_GP1_BRESP(),
|
||||
.S_AXI_GP1_RRESP(),
|
||||
.S_AXI_GP1_RDATA(),
|
||||
.S_AXI_GP1_BID(),
|
||||
.S_AXI_GP1_RID(),
|
||||
.S_AXI_GP1_ACLK(1'B0),
|
||||
.S_AXI_GP1_ARVALID(1'B0),
|
||||
.S_AXI_GP1_AWVALID(1'B0),
|
||||
.S_AXI_GP1_BREADY(1'B0),
|
||||
.S_AXI_GP1_RREADY(1'B0),
|
||||
.S_AXI_GP1_WLAST(1'B0),
|
||||
.S_AXI_GP1_WVALID(1'B0),
|
||||
.S_AXI_GP1_ARBURST(2'B0),
|
||||
.S_AXI_GP1_ARLOCK(2'B0),
|
||||
.S_AXI_GP1_ARSIZE(3'B0),
|
||||
.S_AXI_GP1_AWBURST(2'B0),
|
||||
.S_AXI_GP1_AWLOCK(2'B0),
|
||||
.S_AXI_GP1_AWSIZE(3'B0),
|
||||
.S_AXI_GP1_ARPROT(3'B0),
|
||||
.S_AXI_GP1_AWPROT(3'B0),
|
||||
.S_AXI_GP1_ARADDR(32'B0),
|
||||
.S_AXI_GP1_AWADDR(32'B0),
|
||||
.S_AXI_GP1_WDATA(32'B0),
|
||||
.S_AXI_GP1_ARCACHE(4'B0),
|
||||
.S_AXI_GP1_ARLEN(4'B0),
|
||||
.S_AXI_GP1_ARQOS(4'B0),
|
||||
.S_AXI_GP1_AWCACHE(4'B0),
|
||||
.S_AXI_GP1_AWLEN(4'B0),
|
||||
.S_AXI_GP1_AWQOS(4'B0),
|
||||
.S_AXI_GP1_WSTRB(4'B0),
|
||||
.S_AXI_GP1_ARID(6'B0),
|
||||
.S_AXI_GP1_AWID(6'B0),
|
||||
.S_AXI_GP1_WID(6'B0),
|
||||
.S_AXI_ACP_ARREADY(),
|
||||
.S_AXI_ACP_AWREADY(),
|
||||
.S_AXI_ACP_BVALID(),
|
||||
.S_AXI_ACP_RLAST(),
|
||||
.S_AXI_ACP_RVALID(),
|
||||
.S_AXI_ACP_WREADY(),
|
||||
.S_AXI_ACP_BRESP(),
|
||||
.S_AXI_ACP_RRESP(),
|
||||
.S_AXI_ACP_BID(),
|
||||
.S_AXI_ACP_RID(),
|
||||
.S_AXI_ACP_RDATA(),
|
||||
.S_AXI_ACP_ACLK(1'B0),
|
||||
.S_AXI_ACP_ARVALID(1'B0),
|
||||
.S_AXI_ACP_AWVALID(1'B0),
|
||||
.S_AXI_ACP_BREADY(1'B0),
|
||||
.S_AXI_ACP_RREADY(1'B0),
|
||||
.S_AXI_ACP_WLAST(1'B0),
|
||||
.S_AXI_ACP_WVALID(1'B0),
|
||||
.S_AXI_ACP_ARID(3'B0),
|
||||
.S_AXI_ACP_ARPROT(3'B0),
|
||||
.S_AXI_ACP_AWID(3'B0),
|
||||
.S_AXI_ACP_AWPROT(3'B0),
|
||||
.S_AXI_ACP_WID(3'B0),
|
||||
.S_AXI_ACP_ARADDR(32'B0),
|
||||
.S_AXI_ACP_AWADDR(32'B0),
|
||||
.S_AXI_ACP_ARCACHE(4'B0),
|
||||
.S_AXI_ACP_ARLEN(4'B0),
|
||||
.S_AXI_ACP_ARQOS(4'B0),
|
||||
.S_AXI_ACP_AWCACHE(4'B0),
|
||||
.S_AXI_ACP_AWLEN(4'B0),
|
||||
.S_AXI_ACP_AWQOS(4'B0),
|
||||
.S_AXI_ACP_ARBURST(2'B0),
|
||||
.S_AXI_ACP_ARLOCK(2'B0),
|
||||
.S_AXI_ACP_ARSIZE(3'B0),
|
||||
.S_AXI_ACP_AWBURST(2'B0),
|
||||
.S_AXI_ACP_AWLOCK(2'B0),
|
||||
.S_AXI_ACP_AWSIZE(3'B0),
|
||||
.S_AXI_ACP_ARUSER(5'B0),
|
||||
.S_AXI_ACP_AWUSER(5'B0),
|
||||
.S_AXI_ACP_WDATA(64'B0),
|
||||
.S_AXI_ACP_WSTRB(8'B0),
|
||||
.S_AXI_HP0_ARREADY(),
|
||||
.S_AXI_HP0_AWREADY(),
|
||||
.S_AXI_HP0_BVALID(),
|
||||
.S_AXI_HP0_RLAST(),
|
||||
.S_AXI_HP0_RVALID(),
|
||||
.S_AXI_HP0_WREADY(),
|
||||
.S_AXI_HP0_BRESP(),
|
||||
.S_AXI_HP0_RRESP(),
|
||||
.S_AXI_HP0_BID(),
|
||||
.S_AXI_HP0_RID(),
|
||||
.S_AXI_HP0_RDATA(),
|
||||
.S_AXI_HP0_ACLK(1'B0),
|
||||
.S_AXI_HP0_ARVALID(1'B0),
|
||||
.S_AXI_HP0_AWVALID(1'B0),
|
||||
.S_AXI_HP0_BREADY(1'B0),
|
||||
.S_AXI_HP0_RREADY(1'B0),
|
||||
.S_AXI_HP0_WLAST(1'B0),
|
||||
.S_AXI_HP0_WVALID(1'B0),
|
||||
.S_AXI_HP0_ARBURST(2'B0),
|
||||
.S_AXI_HP0_ARLOCK(2'B0),
|
||||
.S_AXI_HP0_ARSIZE(3'B0),
|
||||
.S_AXI_HP0_AWBURST(2'B0),
|
||||
.S_AXI_HP0_AWLOCK(2'B0),
|
||||
.S_AXI_HP0_AWSIZE(3'B0),
|
||||
.S_AXI_HP0_ARPROT(3'B0),
|
||||
.S_AXI_HP0_AWPROT(3'B0),
|
||||
.S_AXI_HP0_ARADDR(32'B0),
|
||||
.S_AXI_HP0_AWADDR(32'B0),
|
||||
.S_AXI_HP0_ARCACHE(4'B0),
|
||||
.S_AXI_HP0_ARLEN(4'B0),
|
||||
.S_AXI_HP0_ARQOS(4'B0),
|
||||
.S_AXI_HP0_AWCACHE(4'B0),
|
||||
.S_AXI_HP0_AWLEN(4'B0),
|
||||
.S_AXI_HP0_AWQOS(4'B0),
|
||||
.S_AXI_HP0_ARID(6'B0),
|
||||
.S_AXI_HP0_AWID(6'B0),
|
||||
.S_AXI_HP0_WID(6'B0),
|
||||
.S_AXI_HP0_WDATA(64'B0),
|
||||
.S_AXI_HP0_WSTRB(8'B0),
|
||||
.S_AXI_HP1_ARREADY(),
|
||||
.S_AXI_HP1_AWREADY(),
|
||||
.S_AXI_HP1_BVALID(),
|
||||
.S_AXI_HP1_RLAST(),
|
||||
.S_AXI_HP1_RVALID(),
|
||||
.S_AXI_HP1_WREADY(),
|
||||
.S_AXI_HP1_BRESP(),
|
||||
.S_AXI_HP1_RRESP(),
|
||||
.S_AXI_HP1_BID(),
|
||||
.S_AXI_HP1_RID(),
|
||||
.S_AXI_HP1_RDATA(),
|
||||
.S_AXI_HP1_ACLK(1'B0),
|
||||
.S_AXI_HP1_ARVALID(1'B0),
|
||||
.S_AXI_HP1_AWVALID(1'B0),
|
||||
.S_AXI_HP1_BREADY(1'B0),
|
||||
.S_AXI_HP1_RREADY(1'B0),
|
||||
.S_AXI_HP1_WLAST(1'B0),
|
||||
.S_AXI_HP1_WVALID(1'B0),
|
||||
.S_AXI_HP1_ARBURST(2'B0),
|
||||
.S_AXI_HP1_ARLOCK(2'B0),
|
||||
.S_AXI_HP1_ARSIZE(3'B0),
|
||||
.S_AXI_HP1_AWBURST(2'B0),
|
||||
.S_AXI_HP1_AWLOCK(2'B0),
|
||||
.S_AXI_HP1_AWSIZE(3'B0),
|
||||
.S_AXI_HP1_ARPROT(3'B0),
|
||||
.S_AXI_HP1_AWPROT(3'B0),
|
||||
.S_AXI_HP1_ARADDR(32'B0),
|
||||
.S_AXI_HP1_AWADDR(32'B0),
|
||||
.S_AXI_HP1_ARCACHE(4'B0),
|
||||
.S_AXI_HP1_ARLEN(4'B0),
|
||||
.S_AXI_HP1_ARQOS(4'B0),
|
||||
.S_AXI_HP1_AWCACHE(4'B0),
|
||||
.S_AXI_HP1_AWLEN(4'B0),
|
||||
.S_AXI_HP1_AWQOS(4'B0),
|
||||
.S_AXI_HP1_ARID(6'B0),
|
||||
.S_AXI_HP1_AWID(6'B0),
|
||||
.S_AXI_HP1_WID(6'B0),
|
||||
.S_AXI_HP1_WDATA(64'B0),
|
||||
.S_AXI_HP1_WSTRB(8'B0),
|
||||
.S_AXI_HP2_ARREADY(),
|
||||
.S_AXI_HP2_AWREADY(),
|
||||
.S_AXI_HP2_BVALID(),
|
||||
.S_AXI_HP2_RLAST(),
|
||||
.S_AXI_HP2_RVALID(),
|
||||
.S_AXI_HP2_WREADY(),
|
||||
.S_AXI_HP2_BRESP(),
|
||||
.S_AXI_HP2_RRESP(),
|
||||
.S_AXI_HP2_BID(),
|
||||
.S_AXI_HP2_RID(),
|
||||
.S_AXI_HP2_RDATA(),
|
||||
.S_AXI_HP2_ACLK(1'B0),
|
||||
.S_AXI_HP2_ARVALID(1'B0),
|
||||
.S_AXI_HP2_AWVALID(1'B0),
|
||||
.S_AXI_HP2_BREADY(1'B0),
|
||||
.S_AXI_HP2_RREADY(1'B0),
|
||||
.S_AXI_HP2_WLAST(1'B0),
|
||||
.S_AXI_HP2_WVALID(1'B0),
|
||||
.S_AXI_HP2_ARBURST(2'B0),
|
||||
.S_AXI_HP2_ARLOCK(2'B0),
|
||||
.S_AXI_HP2_ARSIZE(3'B0),
|
||||
.S_AXI_HP2_AWBURST(2'B0),
|
||||
.S_AXI_HP2_AWLOCK(2'B0),
|
||||
.S_AXI_HP2_AWSIZE(3'B0),
|
||||
.S_AXI_HP2_ARPROT(3'B0),
|
||||
.S_AXI_HP2_AWPROT(3'B0),
|
||||
.S_AXI_HP2_ARADDR(32'B0),
|
||||
.S_AXI_HP2_AWADDR(32'B0),
|
||||
.S_AXI_HP2_ARCACHE(4'B0),
|
||||
.S_AXI_HP2_ARLEN(4'B0),
|
||||
.S_AXI_HP2_ARQOS(4'B0),
|
||||
.S_AXI_HP2_AWCACHE(4'B0),
|
||||
.S_AXI_HP2_AWLEN(4'B0),
|
||||
.S_AXI_HP2_AWQOS(4'B0),
|
||||
.S_AXI_HP2_ARID(6'B0),
|
||||
.S_AXI_HP2_AWID(6'B0),
|
||||
.S_AXI_HP2_WID(6'B0),
|
||||
.S_AXI_HP2_WDATA(64'B0),
|
||||
.S_AXI_HP2_WSTRB(8'B0),
|
||||
.S_AXI_HP3_ARREADY(),
|
||||
.S_AXI_HP3_AWREADY(),
|
||||
.S_AXI_HP3_BVALID(),
|
||||
.S_AXI_HP3_RLAST(),
|
||||
.S_AXI_HP3_RVALID(),
|
||||
.S_AXI_HP3_WREADY(),
|
||||
.S_AXI_HP3_BRESP(),
|
||||
.S_AXI_HP3_RRESP(),
|
||||
.S_AXI_HP3_BID(),
|
||||
.S_AXI_HP3_RID(),
|
||||
.S_AXI_HP3_RDATA(),
|
||||
.S_AXI_HP3_ACLK(1'B0),
|
||||
.S_AXI_HP3_ARVALID(1'B0),
|
||||
.S_AXI_HP3_AWVALID(1'B0),
|
||||
.S_AXI_HP3_BREADY(1'B0),
|
||||
.S_AXI_HP3_RREADY(1'B0),
|
||||
.S_AXI_HP3_WLAST(1'B0),
|
||||
.S_AXI_HP3_WVALID(1'B0),
|
||||
.S_AXI_HP3_ARBURST(2'B0),
|
||||
.S_AXI_HP3_ARLOCK(2'B0),
|
||||
.S_AXI_HP3_ARSIZE(3'B0),
|
||||
.S_AXI_HP3_AWBURST(2'B0),
|
||||
.S_AXI_HP3_AWLOCK(2'B0),
|
||||
.S_AXI_HP3_AWSIZE(3'B0),
|
||||
.S_AXI_HP3_ARPROT(3'B0),
|
||||
.S_AXI_HP3_AWPROT(3'B0),
|
||||
.S_AXI_HP3_ARADDR(32'B0),
|
||||
.S_AXI_HP3_AWADDR(32'B0),
|
||||
.S_AXI_HP3_ARCACHE(4'B0),
|
||||
.S_AXI_HP3_ARLEN(4'B0),
|
||||
.S_AXI_HP3_ARQOS(4'B0),
|
||||
.S_AXI_HP3_AWCACHE(4'B0),
|
||||
.S_AXI_HP3_AWLEN(4'B0),
|
||||
.S_AXI_HP3_AWQOS(4'B0),
|
||||
.S_AXI_HP3_ARID(6'B0),
|
||||
.S_AXI_HP3_AWID(6'B0),
|
||||
.S_AXI_HP3_WID(6'B0),
|
||||
.S_AXI_HP3_WDATA(64'B0),
|
||||
.S_AXI_HP3_WSTRB(8'B0),
|
||||
.FCLK_CLK0(FCLK_CLK0),
|
||||
|
||||
.FCLK_CLK1(),
|
||||
|
||||
.FCLK_CLK2(),
|
||||
|
||||
.FCLK_CLK3(),
|
||||
.FCLK_RESET0_N(FCLK_RESET0_N),
|
||||
.FCLK_RESET1_N(),
|
||||
.FCLK_RESET2_N(),
|
||||
.FCLK_RESET3_N(),
|
||||
.IRQ_F2P(16'B0),
|
||||
.PS_SRSTB(PS_SRSTB),
|
||||
.PS_CLK(PS_CLK),
|
||||
.PS_PORB(PS_PORB)
|
||||
);
|
||||
endmodule
|
||||
+147
@@ -0,0 +1,147 @@
|
||||
-- (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
-- (c) Copyright 2022-2026 Advanced Micro Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of AMD and is protected under U.S. and international copyright
|
||||
-- and other intellectual property laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- AMD, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) AMD shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or AMD had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- AMD products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of AMD products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 14
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_14;
|
||||
USE proc_sys_reset_v5_0_14.proc_sys_reset;
|
||||
|
||||
ENTITY system_rst_ps7_0_100M_1 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END system_rst_ps7_0_100M_1;
|
||||
|
||||
ARCHITECTURE system_rst_ps7_0_100M_1_arch OF system_rst_ps7_0_100M_1 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_ps7_0_100M_1_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END system_rst_ps7_0_100M_1_arch;
|
||||
@@ -0,0 +1,292 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"modules": {
|
||||
"system": {
|
||||
"proto_instances": {
|
||||
"/mydna_read_v1_0_0/s00_axi": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "s00_axi_aclk"},
|
||||
"ARADDR": { "actual": "s00_axi_araddr[3:0]"},
|
||||
"ARESETN": { "actual": "s00_axi_aresetn"},
|
||||
"ARPROT": { "actual": "s00_axi_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "s00_axi_arready"},
|
||||
"ARVALID": { "actual": "s00_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s00_axi_awaddr[3:0]"},
|
||||
"AWPROT": { "actual": "s00_axi_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "s00_axi_awready"},
|
||||
"AWVALID": { "actual": "s00_axi_awvalid"},
|
||||
"BREADY": { "actual": "s00_axi_bready"},
|
||||
"BRESP": { "actual": "s00_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "s00_axi_bvalid"},
|
||||
"RDATA": { "actual": "s00_axi_rdata[31:0]"},
|
||||
"RREADY": { "actual": "s00_axi_rready"},
|
||||
"RRESP": { "actual": "s00_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "s00_axi_rvalid"},
|
||||
"WDATA": { "actual": "s00_axi_wdata[31:0]"},
|
||||
"WREADY": { "actual": "s00_axi_wready"},
|
||||
"WSTRB": { "actual": "s00_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "s00_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/processing_system7_0/M_AXI_GP0": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M_AXI_GP0_ACLK"},
|
||||
"ARADDR": { "actual": "M_AXI_GP0_ARADDR[31:0]"},
|
||||
"ARBURST": { "actual": "M_AXI_GP0_ARBURST[1:0]"},
|
||||
"ARCACHE": { "actual": "M_AXI_GP0_ARCACHE[3:0]"},
|
||||
"ARID": { "actual": "M_AXI_GP0_ARID[11:0]"},
|
||||
"ARLEN": { "actual": "M_AXI_GP0_ARLEN[3:0]"},
|
||||
"ARLOCK": { "actual": "M_AXI_GP0_ARLOCK[1:0]"},
|
||||
"ARPROT": { "actual": "M_AXI_GP0_ARPROT[2:0]"},
|
||||
"ARQOS": { "actual": "M_AXI_GP0_ARQOS[3:0]"},
|
||||
"ARREADY": { "actual": "M_AXI_GP0_ARREADY"},
|
||||
"ARSIZE": { "actual": "M_AXI_GP0_ARSIZE[2:0]"},
|
||||
"ARVALID": { "actual": "M_AXI_GP0_ARVALID"},
|
||||
"AWADDR": { "actual": "M_AXI_GP0_AWADDR[31:0]"},
|
||||
"AWBURST": { "actual": "M_AXI_GP0_AWBURST[1:0]"},
|
||||
"AWCACHE": { "actual": "M_AXI_GP0_AWCACHE[3:0]"},
|
||||
"AWID": { "actual": "M_AXI_GP0_AWID[11:0]"},
|
||||
"AWLEN": { "actual": "M_AXI_GP0_AWLEN[3:0]"},
|
||||
"AWLOCK": { "actual": "M_AXI_GP0_AWLOCK[1:0]"},
|
||||
"AWPROT": { "actual": "M_AXI_GP0_AWPROT[2:0]"},
|
||||
"AWQOS": { "actual": "M_AXI_GP0_AWQOS[3:0]"},
|
||||
"AWREADY": { "actual": "M_AXI_GP0_AWREADY"},
|
||||
"AWSIZE": { "actual": "M_AXI_GP0_AWSIZE[2:0]"},
|
||||
"AWVALID": { "actual": "M_AXI_GP0_AWVALID"},
|
||||
"BID": { "actual": "M_AXI_GP0_BID[11:0]"},
|
||||
"BREADY": { "actual": "M_AXI_GP0_BREADY"},
|
||||
"BRESP": { "actual": "M_AXI_GP0_BRESP[1:0]"},
|
||||
"BVALID": { "actual": "M_AXI_GP0_BVALID"},
|
||||
"RDATA": { "actual": "M_AXI_GP0_RDATA[31:0]"},
|
||||
"RID": { "actual": "M_AXI_GP0_RID[11:0]"},
|
||||
"RLAST": { "actual": "M_AXI_GP0_RLAST"},
|
||||
"RREADY": { "actual": "M_AXI_GP0_RREADY"},
|
||||
"RRESP": { "actual": "M_AXI_GP0_RRESP[1:0]"},
|
||||
"RVALID": { "actual": "M_AXI_GP0_RVALID"},
|
||||
"WDATA": { "actual": "M_AXI_GP0_WDATA[31:0]"},
|
||||
"WID": { "actual": "M_AXI_GP0_WID[11:0]"},
|
||||
"WLAST": { "actual": "M_AXI_GP0_WLAST"},
|
||||
"WREADY": { "actual": "M_AXI_GP0_WREADY"},
|
||||
"WSTRB": { "actual": "M_AXI_GP0_WSTRB[3:0]"},
|
||||
"WVALID": { "actual": "M_AXI_GP0_WVALID"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/M00_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M00_ACLK"},
|
||||
"ARADDR": { "actual": "M00_AXI_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"ARPROT": { "actual": "M00_AXI_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "M00_AXI_arready"},
|
||||
"ARVALID": { "actual": "M00_AXI_arvalid"},
|
||||
"AWADDR": { "actual": "M00_AXI_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "M00_AXI_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "M00_AXI_awready"},
|
||||
"AWVALID": { "actual": "M00_AXI_awvalid"},
|
||||
"BREADY": { "actual": "M00_AXI_bready"},
|
||||
"BRESP": { "actual": "M00_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "M00_AXI_bvalid"},
|
||||
"RDATA": { "actual": "M00_AXI_rdata[31:0]"},
|
||||
"RREADY": { "actual": "M00_AXI_rready"},
|
||||
"RRESP": { "actual": "M00_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "M00_AXI_rvalid"},
|
||||
"WDATA": { "actual": "M00_AXI_wdata[31:0]"},
|
||||
"WREADY": { "actual": "M00_AXI_wready"},
|
||||
"WSTRB": { "actual": "M00_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "M00_AXI_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/S00_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "S00_ACLK"},
|
||||
"ARADDR": { "actual": "S00_AXI_araddr[31:0]"},
|
||||
"ARBURST": { "actual": "S00_AXI_arburst[1:0]"},
|
||||
"ARCACHE": { "actual": "S00_AXI_arcache[3:0]"},
|
||||
"ARESETN": { "actual": "ARESETN"},
|
||||
"ARID": { "actual": "S00_AXI_arid[11:0]"},
|
||||
"ARLEN": { "actual": "S00_AXI_arlen[3:0]"},
|
||||
"ARLOCK": { "actual": "S00_AXI_arlock[1:0]"},
|
||||
"ARPROT": { "actual": "S00_AXI_arprot[2:0]"},
|
||||
"ARQOS": { "actual": "S00_AXI_arqos[3:0]"},
|
||||
"ARREADY": { "actual": "S00_AXI_arready"},
|
||||
"ARSIZE": { "actual": "S00_AXI_arsize[2:0]"},
|
||||
"ARVALID": { "actual": "S00_AXI_arvalid"},
|
||||
"AWADDR": { "actual": "S00_AXI_awaddr[31:0]"},
|
||||
"AWBURST": { "actual": "S00_AXI_awburst[1:0]"},
|
||||
"AWCACHE": { "actual": "S00_AXI_awcache[3:0]"},
|
||||
"AWID": { "actual": "S00_AXI_awid[11:0]"},
|
||||
"AWLEN": { "actual": "S00_AXI_awlen[3:0]"},
|
||||
"AWLOCK": { "actual": "S00_AXI_awlock[1:0]"},
|
||||
"AWPROT": { "actual": "S00_AXI_awprot[2:0]"},
|
||||
"AWQOS": { "actual": "S00_AXI_awqos[3:0]"},
|
||||
"AWREADY": { "actual": "S00_AXI_awready"},
|
||||
"AWSIZE": { "actual": "S00_AXI_awsize[2:0]"},
|
||||
"AWVALID": { "actual": "S00_AXI_awvalid"},
|
||||
"BID": { "actual": "S00_AXI_bid[11:0]"},
|
||||
"BREADY": { "actual": "S00_AXI_bready"},
|
||||
"BRESP": { "actual": "S00_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "S00_AXI_bvalid"},
|
||||
"RDATA": { "actual": "S00_AXI_rdata[31:0]"},
|
||||
"RID": { "actual": "S00_AXI_rid[11:0]"},
|
||||
"RLAST": { "actual": "S00_AXI_rlast"},
|
||||
"RREADY": { "actual": "S00_AXI_rready"},
|
||||
"RRESP": { "actual": "S00_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "S00_AXI_rvalid"},
|
||||
"WDATA": { "actual": "S00_AXI_wdata[31:0]"},
|
||||
"WID": { "actual": "S00_AXI_wid[11:0]"},
|
||||
"WLAST": { "actual": "S00_AXI_wlast"},
|
||||
"WREADY": { "actual": "S00_AXI_wready"},
|
||||
"WSTRB": { "actual": "S00_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "S00_AXI_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/s00_couplers/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "M_ACLK"},
|
||||
"ARADDR": { "actual": "M_AXI_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "M_ARESETN"},
|
||||
"ARPROT": { "actual": "M_AXI_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "M_AXI_arready"},
|
||||
"ARVALID": { "actual": "M_AXI_arvalid"},
|
||||
"AWADDR": { "actual": "M_AXI_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "M_AXI_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "M_AXI_awready"},
|
||||
"AWVALID": { "actual": "M_AXI_awvalid"},
|
||||
"BREADY": { "actual": "M_AXI_bready"},
|
||||
"BRESP": { "actual": "M_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "M_AXI_bvalid"},
|
||||
"RDATA": { "actual": "M_AXI_rdata[31:0]"},
|
||||
"RREADY": { "actual": "M_AXI_rready"},
|
||||
"RRESP": { "actual": "M_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "M_AXI_rvalid"},
|
||||
"WDATA": { "actual": "M_AXI_wdata[31:0]"},
|
||||
"WREADY": { "actual": "M_AXI_wready"},
|
||||
"WSTRB": { "actual": "M_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "M_AXI_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/s00_couplers/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "S_ACLK"},
|
||||
"ARADDR": { "actual": "S_AXI_araddr[31:0]"},
|
||||
"ARBURST": { "actual": "S_AXI_arburst[1:0]"},
|
||||
"ARCACHE": { "actual": "S_AXI_arcache[3:0]"},
|
||||
"ARESETN": { "actual": "S_ARESETN"},
|
||||
"ARID": { "actual": "S_AXI_arid[11:0]"},
|
||||
"ARLEN": { "actual": "S_AXI_arlen[3:0]"},
|
||||
"ARLOCK": { "actual": "S_AXI_arlock[1:0]"},
|
||||
"ARPROT": { "actual": "S_AXI_arprot[2:0]"},
|
||||
"ARQOS": { "actual": "S_AXI_arqos[3:0]"},
|
||||
"ARREADY": { "actual": "S_AXI_arready"},
|
||||
"ARSIZE": { "actual": "S_AXI_arsize[2:0]"},
|
||||
"ARVALID": { "actual": "S_AXI_arvalid"},
|
||||
"AWADDR": { "actual": "S_AXI_awaddr[31:0]"},
|
||||
"AWBURST": { "actual": "S_AXI_awburst[1:0]"},
|
||||
"AWCACHE": { "actual": "S_AXI_awcache[3:0]"},
|
||||
"AWID": { "actual": "S_AXI_awid[11:0]"},
|
||||
"AWLEN": { "actual": "S_AXI_awlen[3:0]"},
|
||||
"AWLOCK": { "actual": "S_AXI_awlock[1:0]"},
|
||||
"AWPROT": { "actual": "S_AXI_awprot[2:0]"},
|
||||
"AWQOS": { "actual": "S_AXI_awqos[3:0]"},
|
||||
"AWREADY": { "actual": "S_AXI_awready"},
|
||||
"AWSIZE": { "actual": "S_AXI_awsize[2:0]"},
|
||||
"AWVALID": { "actual": "S_AXI_awvalid"},
|
||||
"BID": { "actual": "S_AXI_bid[11:0]"},
|
||||
"BREADY": { "actual": "S_AXI_bready"},
|
||||
"BRESP": { "actual": "S_AXI_bresp[1:0]"},
|
||||
"BVALID": { "actual": "S_AXI_bvalid"},
|
||||
"RDATA": { "actual": "S_AXI_rdata[31:0]"},
|
||||
"RID": { "actual": "S_AXI_rid[11:0]"},
|
||||
"RLAST": { "actual": "S_AXI_rlast"},
|
||||
"RREADY": { "actual": "S_AXI_rready"},
|
||||
"RRESP": { "actual": "S_AXI_rresp[1:0]"},
|
||||
"RVALID": { "actual": "S_AXI_rvalid"},
|
||||
"WDATA": { "actual": "S_AXI_wdata[31:0]"},
|
||||
"WID": { "actual": "S_AXI_wid[11:0]"},
|
||||
"WLAST": { "actual": "S_AXI_wlast"},
|
||||
"WREADY": { "actual": "S_AXI_wready"},
|
||||
"WSTRB": { "actual": "S_AXI_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "S_AXI_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/s00_couplers/auto_pc/M_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "m_axi_araddr[31:0]"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARPROT": { "actual": "m_axi_arprot[2:0]"},
|
||||
"ARREADY": { "actual": "m_axi_arready"},
|
||||
"ARVALID": { "actual": "m_axi_arvalid"},
|
||||
"AWADDR": { "actual": "m_axi_awaddr[31:0]"},
|
||||
"AWPROT": { "actual": "m_axi_awprot[2:0]"},
|
||||
"AWREADY": { "actual": "m_axi_awready"},
|
||||
"AWVALID": { "actual": "m_axi_awvalid"},
|
||||
"BREADY": { "actual": "m_axi_bready"},
|
||||
"BRESP": { "actual": "m_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "m_axi_bvalid"},
|
||||
"RDATA": { "actual": "m_axi_rdata[31:0]"},
|
||||
"RREADY": { "actual": "m_axi_rready"},
|
||||
"RRESP": { "actual": "m_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "m_axi_rvalid"},
|
||||
"WDATA": { "actual": "m_axi_wdata[31:0]"},
|
||||
"WREADY": { "actual": "m_axi_wready"},
|
||||
"WSTRB": { "actual": "m_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "m_axi_wvalid"}
|
||||
}
|
||||
},
|
||||
"/ps7_0_axi_periph/s00_couplers/auto_pc/S_AXI": {
|
||||
"interface": "xilinx.com:interface:aximm:1.0",
|
||||
"ports": {
|
||||
"ACLK": { "actual": "aclk"},
|
||||
"ARADDR": { "actual": "s_axi_araddr[31:0]"},
|
||||
"ARBURST": { "actual": "s_axi_arburst[1:0]"},
|
||||
"ARCACHE": { "actual": "s_axi_arcache[3:0]"},
|
||||
"ARESETN": { "actual": "aresetn"},
|
||||
"ARID": { "actual": "s_axi_arid[11:0]"},
|
||||
"ARLEN": { "actual": "s_axi_arlen[3:0]"},
|
||||
"ARLOCK": { "actual": "s_axi_arlock[1:0]"},
|
||||
"ARPROT": { "actual": "s_axi_arprot[2:0]"},
|
||||
"ARQOS": { "actual": "s_axi_arqos[3:0]"},
|
||||
"ARREADY": { "actual": "s_axi_arready"},
|
||||
"ARSIZE": { "actual": "s_axi_arsize[2:0]"},
|
||||
"ARVALID": { "actual": "s_axi_arvalid"},
|
||||
"AWADDR": { "actual": "s_axi_awaddr[31:0]"},
|
||||
"AWBURST": { "actual": "s_axi_awburst[1:0]"},
|
||||
"AWCACHE": { "actual": "s_axi_awcache[3:0]"},
|
||||
"AWID": { "actual": "s_axi_awid[11:0]"},
|
||||
"AWLEN": { "actual": "s_axi_awlen[3:0]"},
|
||||
"AWLOCK": { "actual": "s_axi_awlock[1:0]"},
|
||||
"AWPROT": { "actual": "s_axi_awprot[2:0]"},
|
||||
"AWQOS": { "actual": "s_axi_awqos[3:0]"},
|
||||
"AWREADY": { "actual": "s_axi_awready"},
|
||||
"AWSIZE": { "actual": "s_axi_awsize[2:0]"},
|
||||
"AWVALID": { "actual": "s_axi_awvalid"},
|
||||
"BID": { "actual": "s_axi_bid[11:0]"},
|
||||
"BREADY": { "actual": "s_axi_bready"},
|
||||
"BRESP": { "actual": "s_axi_bresp[1:0]"},
|
||||
"BVALID": { "actual": "s_axi_bvalid"},
|
||||
"RDATA": { "actual": "s_axi_rdata[31:0]"},
|
||||
"RID": { "actual": "s_axi_rid[11:0]"},
|
||||
"RLAST": { "actual": "s_axi_rlast"},
|
||||
"RREADY": { "actual": "s_axi_rready"},
|
||||
"RRESP": { "actual": "s_axi_rresp[1:0]"},
|
||||
"RVALID": { "actual": "s_axi_rvalid"},
|
||||
"WDATA": { "actual": "s_axi_wdata[31:0]"},
|
||||
"WID": { "actual": "s_axi_wid[11:0]"},
|
||||
"WLAST": { "actual": "s_axi_wlast"},
|
||||
"WREADY": { "actual": "s_axi_wready"},
|
||||
"WSTRB": { "actual": "s_axi_wstrb[3:0]"},
|
||||
"WVALID": { "actual": "s_axi_wvalid"}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,945 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
//Date : Mon May 25 14:51:47 2026
|
||||
//Host : mkb running 64-bit unknown
|
||||
//Command : generate_target system.bd
|
||||
//Design : system
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module s00_couplers_imp_11SE3QO
|
||||
(M_ACLK,
|
||||
M_ARESETN,
|
||||
M_AXI_araddr,
|
||||
M_AXI_arprot,
|
||||
M_AXI_arready,
|
||||
M_AXI_arvalid,
|
||||
M_AXI_awaddr,
|
||||
M_AXI_awprot,
|
||||
M_AXI_awready,
|
||||
M_AXI_awvalid,
|
||||
M_AXI_bready,
|
||||
M_AXI_bresp,
|
||||
M_AXI_bvalid,
|
||||
M_AXI_rdata,
|
||||
M_AXI_rready,
|
||||
M_AXI_rresp,
|
||||
M_AXI_rvalid,
|
||||
M_AXI_wdata,
|
||||
M_AXI_wready,
|
||||
M_AXI_wstrb,
|
||||
M_AXI_wvalid,
|
||||
S_ACLK,
|
||||
S_ARESETN,
|
||||
S_AXI_araddr,
|
||||
S_AXI_arburst,
|
||||
S_AXI_arcache,
|
||||
S_AXI_arid,
|
||||
S_AXI_arlen,
|
||||
S_AXI_arlock,
|
||||
S_AXI_arprot,
|
||||
S_AXI_arqos,
|
||||
S_AXI_arready,
|
||||
S_AXI_arsize,
|
||||
S_AXI_arvalid,
|
||||
S_AXI_awaddr,
|
||||
S_AXI_awburst,
|
||||
S_AXI_awcache,
|
||||
S_AXI_awid,
|
||||
S_AXI_awlen,
|
||||
S_AXI_awlock,
|
||||
S_AXI_awprot,
|
||||
S_AXI_awqos,
|
||||
S_AXI_awready,
|
||||
S_AXI_awsize,
|
||||
S_AXI_awvalid,
|
||||
S_AXI_bid,
|
||||
S_AXI_bready,
|
||||
S_AXI_bresp,
|
||||
S_AXI_bvalid,
|
||||
S_AXI_rdata,
|
||||
S_AXI_rid,
|
||||
S_AXI_rlast,
|
||||
S_AXI_rready,
|
||||
S_AXI_rresp,
|
||||
S_AXI_rvalid,
|
||||
S_AXI_wdata,
|
||||
S_AXI_wid,
|
||||
S_AXI_wlast,
|
||||
S_AXI_wready,
|
||||
S_AXI_wstrb,
|
||||
S_AXI_wvalid);
|
||||
input M_ACLK;
|
||||
input M_ARESETN;
|
||||
output [31:0]M_AXI_araddr;
|
||||
output [2:0]M_AXI_arprot;
|
||||
input M_AXI_arready;
|
||||
output M_AXI_arvalid;
|
||||
output [31:0]M_AXI_awaddr;
|
||||
output [2:0]M_AXI_awprot;
|
||||
input M_AXI_awready;
|
||||
output M_AXI_awvalid;
|
||||
output M_AXI_bready;
|
||||
input [1:0]M_AXI_bresp;
|
||||
input M_AXI_bvalid;
|
||||
input [31:0]M_AXI_rdata;
|
||||
output M_AXI_rready;
|
||||
input [1:0]M_AXI_rresp;
|
||||
input M_AXI_rvalid;
|
||||
output [31:0]M_AXI_wdata;
|
||||
input M_AXI_wready;
|
||||
output [3:0]M_AXI_wstrb;
|
||||
output M_AXI_wvalid;
|
||||
input S_ACLK;
|
||||
input S_ARESETN;
|
||||
input [31:0]S_AXI_araddr;
|
||||
input [1:0]S_AXI_arburst;
|
||||
input [3:0]S_AXI_arcache;
|
||||
input [11:0]S_AXI_arid;
|
||||
input [3:0]S_AXI_arlen;
|
||||
input [1:0]S_AXI_arlock;
|
||||
input [2:0]S_AXI_arprot;
|
||||
input [3:0]S_AXI_arqos;
|
||||
output S_AXI_arready;
|
||||
input [2:0]S_AXI_arsize;
|
||||
input S_AXI_arvalid;
|
||||
input [31:0]S_AXI_awaddr;
|
||||
input [1:0]S_AXI_awburst;
|
||||
input [3:0]S_AXI_awcache;
|
||||
input [11:0]S_AXI_awid;
|
||||
input [3:0]S_AXI_awlen;
|
||||
input [1:0]S_AXI_awlock;
|
||||
input [2:0]S_AXI_awprot;
|
||||
input [3:0]S_AXI_awqos;
|
||||
output S_AXI_awready;
|
||||
input [2:0]S_AXI_awsize;
|
||||
input S_AXI_awvalid;
|
||||
output [11:0]S_AXI_bid;
|
||||
input S_AXI_bready;
|
||||
output [1:0]S_AXI_bresp;
|
||||
output S_AXI_bvalid;
|
||||
output [31:0]S_AXI_rdata;
|
||||
output [11:0]S_AXI_rid;
|
||||
output S_AXI_rlast;
|
||||
input S_AXI_rready;
|
||||
output [1:0]S_AXI_rresp;
|
||||
output S_AXI_rvalid;
|
||||
input [31:0]S_AXI_wdata;
|
||||
input [11:0]S_AXI_wid;
|
||||
input S_AXI_wlast;
|
||||
output S_AXI_wready;
|
||||
input [3:0]S_AXI_wstrb;
|
||||
input S_AXI_wvalid;
|
||||
|
||||
wire S_ACLK_1;
|
||||
wire S_ARESETN_1;
|
||||
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
|
||||
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
|
||||
wire auto_pc_to_s00_couplers_ARREADY;
|
||||
wire auto_pc_to_s00_couplers_ARVALID;
|
||||
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
|
||||
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
|
||||
wire auto_pc_to_s00_couplers_AWREADY;
|
||||
wire auto_pc_to_s00_couplers_AWVALID;
|
||||
wire auto_pc_to_s00_couplers_BREADY;
|
||||
wire [1:0]auto_pc_to_s00_couplers_BRESP;
|
||||
wire auto_pc_to_s00_couplers_BVALID;
|
||||
wire [31:0]auto_pc_to_s00_couplers_RDATA;
|
||||
wire auto_pc_to_s00_couplers_RREADY;
|
||||
wire [1:0]auto_pc_to_s00_couplers_RRESP;
|
||||
wire auto_pc_to_s00_couplers_RVALID;
|
||||
wire [31:0]auto_pc_to_s00_couplers_WDATA;
|
||||
wire auto_pc_to_s00_couplers_WREADY;
|
||||
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
|
||||
wire auto_pc_to_s00_couplers_WVALID;
|
||||
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
|
||||
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
|
||||
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
|
||||
wire [11:0]s00_couplers_to_auto_pc_ARID;
|
||||
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
|
||||
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
|
||||
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
|
||||
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
|
||||
wire s00_couplers_to_auto_pc_ARREADY;
|
||||
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
|
||||
wire s00_couplers_to_auto_pc_ARVALID;
|
||||
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
|
||||
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
|
||||
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
|
||||
wire [11:0]s00_couplers_to_auto_pc_AWID;
|
||||
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
|
||||
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
|
||||
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
|
||||
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
|
||||
wire s00_couplers_to_auto_pc_AWREADY;
|
||||
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
|
||||
wire s00_couplers_to_auto_pc_AWVALID;
|
||||
wire [11:0]s00_couplers_to_auto_pc_BID;
|
||||
wire s00_couplers_to_auto_pc_BREADY;
|
||||
wire [1:0]s00_couplers_to_auto_pc_BRESP;
|
||||
wire s00_couplers_to_auto_pc_BVALID;
|
||||
wire [31:0]s00_couplers_to_auto_pc_RDATA;
|
||||
wire [11:0]s00_couplers_to_auto_pc_RID;
|
||||
wire s00_couplers_to_auto_pc_RLAST;
|
||||
wire s00_couplers_to_auto_pc_RREADY;
|
||||
wire [1:0]s00_couplers_to_auto_pc_RRESP;
|
||||
wire s00_couplers_to_auto_pc_RVALID;
|
||||
wire [31:0]s00_couplers_to_auto_pc_WDATA;
|
||||
wire [11:0]s00_couplers_to_auto_pc_WID;
|
||||
wire s00_couplers_to_auto_pc_WLAST;
|
||||
wire s00_couplers_to_auto_pc_WREADY;
|
||||
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
|
||||
wire s00_couplers_to_auto_pc_WVALID;
|
||||
|
||||
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
|
||||
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
|
||||
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
|
||||
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
|
||||
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
|
||||
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
|
||||
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
|
||||
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
|
||||
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
|
||||
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
|
||||
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
|
||||
assign S_ACLK_1 = S_ACLK;
|
||||
assign S_ARESETN_1 = S_ARESETN;
|
||||
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
|
||||
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
|
||||
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
|
||||
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
|
||||
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
|
||||
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
|
||||
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
|
||||
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
|
||||
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
|
||||
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
|
||||
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
|
||||
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
|
||||
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
|
||||
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
|
||||
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
|
||||
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
|
||||
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
|
||||
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
|
||||
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
|
||||
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
|
||||
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
|
||||
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
|
||||
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
|
||||
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
|
||||
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
|
||||
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
|
||||
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
|
||||
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
|
||||
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
|
||||
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
|
||||
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
|
||||
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
|
||||
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
|
||||
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
|
||||
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
|
||||
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
|
||||
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
|
||||
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
|
||||
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
|
||||
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
|
||||
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
|
||||
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
|
||||
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
|
||||
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
|
||||
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
|
||||
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
|
||||
system_auto_pc_0 auto_pc
|
||||
(.aclk(S_ACLK_1),
|
||||
.aresetn(S_ARESETN_1),
|
||||
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
|
||||
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
|
||||
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
|
||||
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
|
||||
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
|
||||
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
|
||||
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
|
||||
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
|
||||
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
|
||||
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
|
||||
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
|
||||
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
|
||||
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
|
||||
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
|
||||
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
|
||||
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
|
||||
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
|
||||
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
|
||||
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
|
||||
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
|
||||
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
|
||||
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
|
||||
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
|
||||
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
|
||||
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
|
||||
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
|
||||
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
|
||||
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
|
||||
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
|
||||
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
|
||||
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
|
||||
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
|
||||
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
|
||||
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
|
||||
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
|
||||
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
|
||||
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
|
||||
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
|
||||
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
|
||||
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
|
||||
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
|
||||
.s_axi_bid(s00_couplers_to_auto_pc_BID),
|
||||
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
|
||||
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
|
||||
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
|
||||
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
|
||||
.s_axi_rid(s00_couplers_to_auto_pc_RID),
|
||||
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
|
||||
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
|
||||
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
|
||||
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
|
||||
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
|
||||
.s_axi_wid(s00_couplers_to_auto_pc_WID),
|
||||
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
|
||||
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
|
||||
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
|
||||
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
|
||||
endmodule
|
||||
|
||||
(* CORE_GENERATION_INFO = "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=7,numReposBlks=5,numNonXlnxBlks=0,numHierBlks=2,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=2,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=2,da_clkrst_cnt=2,da_ps7_cnt=1,synth_mode=None}" *) (* HW_HANDOFF = "system.hwdef" *)
|
||||
module system
|
||||
(DDR_addr,
|
||||
DDR_ba,
|
||||
DDR_cas_n,
|
||||
DDR_ck_n,
|
||||
DDR_ck_p,
|
||||
DDR_cke,
|
||||
DDR_cs_n,
|
||||
DDR_dm,
|
||||
DDR_dq,
|
||||
DDR_dqs_n,
|
||||
DDR_dqs_p,
|
||||
DDR_odt,
|
||||
DDR_ras_n,
|
||||
DDR_reset_n,
|
||||
DDR_we_n,
|
||||
EMIO_0_tri_i,
|
||||
EMIO_0_tri_o,
|
||||
EMIO_0_tri_t,
|
||||
FIXED_IO_ddr_vrn,
|
||||
FIXED_IO_ddr_vrp,
|
||||
FIXED_IO_mio,
|
||||
FIXED_IO_ps_clk,
|
||||
FIXED_IO_ps_porb,
|
||||
FIXED_IO_ps_srstb);
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_dm;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_dq;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_dqs_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [3:0]DDR_dqs_p;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 EMIO_0 TRI_I" *) input [32:0]EMIO_0_tri_i;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 EMIO_0 TRI_O" *) output [32:0]EMIO_0_tri_o;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 EMIO_0 TRI_T" *) output [32:0]EMIO_0_tri_t;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]FIXED_IO_mio;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb;
|
||||
|
||||
wire [56:0]dna_port_read_0_dna_port;
|
||||
wire dna_port_read_0_read_vld;
|
||||
wire mydna_read_v1_0_0_start_vld;
|
||||
wire [14:0]processing_system7_0_DDR_ADDR;
|
||||
wire [2:0]processing_system7_0_DDR_BA;
|
||||
wire processing_system7_0_DDR_CAS_N;
|
||||
wire processing_system7_0_DDR_CKE;
|
||||
wire processing_system7_0_DDR_CK_N;
|
||||
wire processing_system7_0_DDR_CK_P;
|
||||
wire processing_system7_0_DDR_CS_N;
|
||||
wire [3:0]processing_system7_0_DDR_DM;
|
||||
wire [31:0]processing_system7_0_DDR_DQ;
|
||||
wire [3:0]processing_system7_0_DDR_DQS_N;
|
||||
wire [3:0]processing_system7_0_DDR_DQS_P;
|
||||
wire processing_system7_0_DDR_ODT;
|
||||
wire processing_system7_0_DDR_RAS_N;
|
||||
wire processing_system7_0_DDR_RESET_N;
|
||||
wire processing_system7_0_DDR_WE_N;
|
||||
wire processing_system7_0_FCLK_CLK0;
|
||||
wire processing_system7_0_FCLK_RESET0_N;
|
||||
wire processing_system7_0_FIXED_IO_DDR_VRN;
|
||||
wire processing_system7_0_FIXED_IO_DDR_VRP;
|
||||
wire [53:0]processing_system7_0_FIXED_IO_MIO;
|
||||
wire processing_system7_0_FIXED_IO_PS_CLK;
|
||||
wire processing_system7_0_FIXED_IO_PS_PORB;
|
||||
wire processing_system7_0_FIXED_IO_PS_SRSTB;
|
||||
wire [32:0]processing_system7_0_GPIO_0_TRI_I;
|
||||
wire [32:0]processing_system7_0_GPIO_0_TRI_O;
|
||||
wire [32:0]processing_system7_0_GPIO_0_TRI_T;
|
||||
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
|
||||
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
|
||||
wire processing_system7_0_M_AXI_GP0_ARREADY;
|
||||
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
|
||||
wire processing_system7_0_M_AXI_GP0_ARVALID;
|
||||
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
|
||||
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
|
||||
wire processing_system7_0_M_AXI_GP0_AWREADY;
|
||||
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
|
||||
wire processing_system7_0_M_AXI_GP0_AWVALID;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
|
||||
wire processing_system7_0_M_AXI_GP0_BREADY;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
|
||||
wire processing_system7_0_M_AXI_GP0_BVALID;
|
||||
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
|
||||
wire processing_system7_0_M_AXI_GP0_RLAST;
|
||||
wire processing_system7_0_M_AXI_GP0_RREADY;
|
||||
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
|
||||
wire processing_system7_0_M_AXI_GP0_RVALID;
|
||||
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
|
||||
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
|
||||
wire processing_system7_0_M_AXI_GP0_WLAST;
|
||||
wire processing_system7_0_M_AXI_GP0_WREADY;
|
||||
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
|
||||
wire processing_system7_0_M_AXI_GP0_WVALID;
|
||||
wire [31:0]ps7_0_axi_periph_M00_AXI_ARADDR;
|
||||
wire [2:0]ps7_0_axi_periph_M00_AXI_ARPROT;
|
||||
wire ps7_0_axi_periph_M00_AXI_ARREADY;
|
||||
wire ps7_0_axi_periph_M00_AXI_ARVALID;
|
||||
wire [31:0]ps7_0_axi_periph_M00_AXI_AWADDR;
|
||||
wire [2:0]ps7_0_axi_periph_M00_AXI_AWPROT;
|
||||
wire ps7_0_axi_periph_M00_AXI_AWREADY;
|
||||
wire ps7_0_axi_periph_M00_AXI_AWVALID;
|
||||
wire ps7_0_axi_periph_M00_AXI_BREADY;
|
||||
wire [1:0]ps7_0_axi_periph_M00_AXI_BRESP;
|
||||
wire ps7_0_axi_periph_M00_AXI_BVALID;
|
||||
wire [31:0]ps7_0_axi_periph_M00_AXI_RDATA;
|
||||
wire ps7_0_axi_periph_M00_AXI_RREADY;
|
||||
wire [1:0]ps7_0_axi_periph_M00_AXI_RRESP;
|
||||
wire ps7_0_axi_periph_M00_AXI_RVALID;
|
||||
wire [31:0]ps7_0_axi_periph_M00_AXI_WDATA;
|
||||
wire ps7_0_axi_periph_M00_AXI_WREADY;
|
||||
wire [3:0]ps7_0_axi_periph_M00_AXI_WSTRB;
|
||||
wire ps7_0_axi_periph_M00_AXI_WVALID;
|
||||
wire [0:0]rst_ps7_0_100M_interconnect_aresetn;
|
||||
wire [0:0]rst_ps7_0_100M_peripheral_aresetn;
|
||||
|
||||
assign EMIO_0_tri_o[32:0] = processing_system7_0_GPIO_0_TRI_O;
|
||||
assign EMIO_0_tri_t[32:0] = processing_system7_0_GPIO_0_TRI_T;
|
||||
assign processing_system7_0_GPIO_0_TRI_I = EMIO_0_tri_i[32:0];
|
||||
system_dna_port_read_0_0 dna_port_read_0
|
||||
(.clk(processing_system7_0_FCLK_CLK0),
|
||||
.dna_port(dna_port_read_0_dna_port),
|
||||
.read_vld(dna_port_read_0_read_vld),
|
||||
.rst_n(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.start_vld(mydna_read_v1_0_0_start_vld));
|
||||
system_mydna_read_v1_0_0_0 mydna_read_v1_0_0
|
||||
(.dna_port(dna_port_read_0_dna_port),
|
||||
.read_vld(dna_port_read_0_read_vld),
|
||||
.s00_axi_aclk(processing_system7_0_FCLK_CLK0),
|
||||
.s00_axi_araddr(ps7_0_axi_periph_M00_AXI_ARADDR[3:0]),
|
||||
.s00_axi_aresetn(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.s00_axi_arprot(ps7_0_axi_periph_M00_AXI_ARPROT),
|
||||
.s00_axi_arready(ps7_0_axi_periph_M00_AXI_ARREADY),
|
||||
.s00_axi_arvalid(ps7_0_axi_periph_M00_AXI_ARVALID),
|
||||
.s00_axi_awaddr(ps7_0_axi_periph_M00_AXI_AWADDR[3:0]),
|
||||
.s00_axi_awprot(ps7_0_axi_periph_M00_AXI_AWPROT),
|
||||
.s00_axi_awready(ps7_0_axi_periph_M00_AXI_AWREADY),
|
||||
.s00_axi_awvalid(ps7_0_axi_periph_M00_AXI_AWVALID),
|
||||
.s00_axi_bready(ps7_0_axi_periph_M00_AXI_BREADY),
|
||||
.s00_axi_bresp(ps7_0_axi_periph_M00_AXI_BRESP),
|
||||
.s00_axi_bvalid(ps7_0_axi_periph_M00_AXI_BVALID),
|
||||
.s00_axi_rdata(ps7_0_axi_periph_M00_AXI_RDATA),
|
||||
.s00_axi_rready(ps7_0_axi_periph_M00_AXI_RREADY),
|
||||
.s00_axi_rresp(ps7_0_axi_periph_M00_AXI_RRESP),
|
||||
.s00_axi_rvalid(ps7_0_axi_periph_M00_AXI_RVALID),
|
||||
.s00_axi_wdata(ps7_0_axi_periph_M00_AXI_WDATA),
|
||||
.s00_axi_wready(ps7_0_axi_periph_M00_AXI_WREADY),
|
||||
.s00_axi_wstrb(ps7_0_axi_periph_M00_AXI_WSTRB),
|
||||
.s00_axi_wvalid(ps7_0_axi_periph_M00_AXI_WVALID),
|
||||
.start_vld(mydna_read_v1_0_0_start_vld));
|
||||
system_processing_system7_0_0 processing_system7_0
|
||||
(.DDR_Addr(DDR_addr[14:0]),
|
||||
.DDR_BankAddr(DDR_ba[2:0]),
|
||||
.DDR_CAS_n(DDR_cas_n),
|
||||
.DDR_CKE(DDR_cke),
|
||||
.DDR_CS_n(DDR_cs_n),
|
||||
.DDR_Clk(DDR_ck_p),
|
||||
.DDR_Clk_n(DDR_ck_n),
|
||||
.DDR_DM(DDR_dm[3:0]),
|
||||
.DDR_DQ(DDR_dq[31:0]),
|
||||
.DDR_DQS(DDR_dqs_p[3:0]),
|
||||
.DDR_DQS_n(DDR_dqs_n[3:0]),
|
||||
.DDR_DRSTB(DDR_reset_n),
|
||||
.DDR_ODT(DDR_odt),
|
||||
.DDR_RAS_n(DDR_ras_n),
|
||||
.DDR_VRN(FIXED_IO_ddr_vrn),
|
||||
.DDR_VRP(FIXED_IO_ddr_vrp),
|
||||
.DDR_WEB(DDR_we_n),
|
||||
.FCLK_CLK0(processing_system7_0_FCLK_CLK0),
|
||||
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
|
||||
.GPIO_I(processing_system7_0_GPIO_0_TRI_I),
|
||||
.GPIO_O(processing_system7_0_GPIO_0_TRI_O),
|
||||
.GPIO_T(processing_system7_0_GPIO_0_TRI_T),
|
||||
.MIO(FIXED_IO_mio[53:0]),
|
||||
.M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0),
|
||||
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
|
||||
.PS_CLK(FIXED_IO_ps_clk),
|
||||
.PS_PORB(FIXED_IO_ps_porb),
|
||||
.PS_SRSTB(FIXED_IO_ps_srstb));
|
||||
system_ps7_0_axi_periph_1 ps7_0_axi_periph
|
||||
(.ACLK(processing_system7_0_FCLK_CLK0),
|
||||
.ARESETN(rst_ps7_0_100M_interconnect_aresetn),
|
||||
.M00_ACLK(processing_system7_0_FCLK_CLK0),
|
||||
.M00_ARESETN(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.M00_AXI_araddr(ps7_0_axi_periph_M00_AXI_ARADDR),
|
||||
.M00_AXI_arprot(ps7_0_axi_periph_M00_AXI_ARPROT),
|
||||
.M00_AXI_arready(ps7_0_axi_periph_M00_AXI_ARREADY),
|
||||
.M00_AXI_arvalid(ps7_0_axi_periph_M00_AXI_ARVALID),
|
||||
.M00_AXI_awaddr(ps7_0_axi_periph_M00_AXI_AWADDR),
|
||||
.M00_AXI_awprot(ps7_0_axi_periph_M00_AXI_AWPROT),
|
||||
.M00_AXI_awready(ps7_0_axi_periph_M00_AXI_AWREADY),
|
||||
.M00_AXI_awvalid(ps7_0_axi_periph_M00_AXI_AWVALID),
|
||||
.M00_AXI_bready(ps7_0_axi_periph_M00_AXI_BREADY),
|
||||
.M00_AXI_bresp(ps7_0_axi_periph_M00_AXI_BRESP),
|
||||
.M00_AXI_bvalid(ps7_0_axi_periph_M00_AXI_BVALID),
|
||||
.M00_AXI_rdata(ps7_0_axi_periph_M00_AXI_RDATA),
|
||||
.M00_AXI_rready(ps7_0_axi_periph_M00_AXI_RREADY),
|
||||
.M00_AXI_rresp(ps7_0_axi_periph_M00_AXI_RRESP),
|
||||
.M00_AXI_rvalid(ps7_0_axi_periph_M00_AXI_RVALID),
|
||||
.M00_AXI_wdata(ps7_0_axi_periph_M00_AXI_WDATA),
|
||||
.M00_AXI_wready(ps7_0_axi_periph_M00_AXI_WREADY),
|
||||
.M00_AXI_wstrb(ps7_0_axi_periph_M00_AXI_WSTRB),
|
||||
.M00_AXI_wvalid(ps7_0_axi_periph_M00_AXI_WVALID),
|
||||
.S00_ACLK(processing_system7_0_FCLK_CLK0),
|
||||
.S00_ARESETN(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
|
||||
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
|
||||
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
|
||||
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
|
||||
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
|
||||
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
|
||||
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
|
||||
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
|
||||
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
|
||||
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
|
||||
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
|
||||
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
|
||||
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
|
||||
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
|
||||
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
|
||||
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
|
||||
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
|
||||
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
|
||||
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
|
||||
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
|
||||
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
|
||||
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
|
||||
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
|
||||
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
|
||||
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
|
||||
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
|
||||
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
|
||||
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
|
||||
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
|
||||
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
|
||||
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
|
||||
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
|
||||
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
|
||||
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
|
||||
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
|
||||
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
|
||||
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
|
||||
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
|
||||
system_rst_ps7_0_100M_1 rst_ps7_0_100M
|
||||
(.aux_reset_in(1'b1),
|
||||
.dcm_locked(1'b1),
|
||||
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
|
||||
.interconnect_aresetn(rst_ps7_0_100M_interconnect_aresetn),
|
||||
.mb_debug_sys_rst(1'b0),
|
||||
.peripheral_aresetn(rst_ps7_0_100M_peripheral_aresetn),
|
||||
.slowest_sync_clk(processing_system7_0_FCLK_CLK0));
|
||||
endmodule
|
||||
|
||||
module system_ps7_0_axi_periph_1
|
||||
(ACLK,
|
||||
ARESETN,
|
||||
M00_ACLK,
|
||||
M00_ARESETN,
|
||||
M00_AXI_araddr,
|
||||
M00_AXI_arprot,
|
||||
M00_AXI_arready,
|
||||
M00_AXI_arvalid,
|
||||
M00_AXI_awaddr,
|
||||
M00_AXI_awprot,
|
||||
M00_AXI_awready,
|
||||
M00_AXI_awvalid,
|
||||
M00_AXI_bready,
|
||||
M00_AXI_bresp,
|
||||
M00_AXI_bvalid,
|
||||
M00_AXI_rdata,
|
||||
M00_AXI_rready,
|
||||
M00_AXI_rresp,
|
||||
M00_AXI_rvalid,
|
||||
M00_AXI_wdata,
|
||||
M00_AXI_wready,
|
||||
M00_AXI_wstrb,
|
||||
M00_AXI_wvalid,
|
||||
S00_ACLK,
|
||||
S00_ARESETN,
|
||||
S00_AXI_araddr,
|
||||
S00_AXI_arburst,
|
||||
S00_AXI_arcache,
|
||||
S00_AXI_arid,
|
||||
S00_AXI_arlen,
|
||||
S00_AXI_arlock,
|
||||
S00_AXI_arprot,
|
||||
S00_AXI_arqos,
|
||||
S00_AXI_arready,
|
||||
S00_AXI_arsize,
|
||||
S00_AXI_arvalid,
|
||||
S00_AXI_awaddr,
|
||||
S00_AXI_awburst,
|
||||
S00_AXI_awcache,
|
||||
S00_AXI_awid,
|
||||
S00_AXI_awlen,
|
||||
S00_AXI_awlock,
|
||||
S00_AXI_awprot,
|
||||
S00_AXI_awqos,
|
||||
S00_AXI_awready,
|
||||
S00_AXI_awsize,
|
||||
S00_AXI_awvalid,
|
||||
S00_AXI_bid,
|
||||
S00_AXI_bready,
|
||||
S00_AXI_bresp,
|
||||
S00_AXI_bvalid,
|
||||
S00_AXI_rdata,
|
||||
S00_AXI_rid,
|
||||
S00_AXI_rlast,
|
||||
S00_AXI_rready,
|
||||
S00_AXI_rresp,
|
||||
S00_AXI_rvalid,
|
||||
S00_AXI_wdata,
|
||||
S00_AXI_wid,
|
||||
S00_AXI_wlast,
|
||||
S00_AXI_wready,
|
||||
S00_AXI_wstrb,
|
||||
S00_AXI_wvalid);
|
||||
input ACLK;
|
||||
input ARESETN;
|
||||
input M00_ACLK;
|
||||
input M00_ARESETN;
|
||||
output [31:0]M00_AXI_araddr;
|
||||
output [2:0]M00_AXI_arprot;
|
||||
input M00_AXI_arready;
|
||||
output M00_AXI_arvalid;
|
||||
output [31:0]M00_AXI_awaddr;
|
||||
output [2:0]M00_AXI_awprot;
|
||||
input M00_AXI_awready;
|
||||
output M00_AXI_awvalid;
|
||||
output M00_AXI_bready;
|
||||
input [1:0]M00_AXI_bresp;
|
||||
input M00_AXI_bvalid;
|
||||
input [31:0]M00_AXI_rdata;
|
||||
output M00_AXI_rready;
|
||||
input [1:0]M00_AXI_rresp;
|
||||
input M00_AXI_rvalid;
|
||||
output [31:0]M00_AXI_wdata;
|
||||
input M00_AXI_wready;
|
||||
output [3:0]M00_AXI_wstrb;
|
||||
output M00_AXI_wvalid;
|
||||
input S00_ACLK;
|
||||
input S00_ARESETN;
|
||||
input [31:0]S00_AXI_araddr;
|
||||
input [1:0]S00_AXI_arburst;
|
||||
input [3:0]S00_AXI_arcache;
|
||||
input [11:0]S00_AXI_arid;
|
||||
input [3:0]S00_AXI_arlen;
|
||||
input [1:0]S00_AXI_arlock;
|
||||
input [2:0]S00_AXI_arprot;
|
||||
input [3:0]S00_AXI_arqos;
|
||||
output S00_AXI_arready;
|
||||
input [2:0]S00_AXI_arsize;
|
||||
input S00_AXI_arvalid;
|
||||
input [31:0]S00_AXI_awaddr;
|
||||
input [1:0]S00_AXI_awburst;
|
||||
input [3:0]S00_AXI_awcache;
|
||||
input [11:0]S00_AXI_awid;
|
||||
input [3:0]S00_AXI_awlen;
|
||||
input [1:0]S00_AXI_awlock;
|
||||
input [2:0]S00_AXI_awprot;
|
||||
input [3:0]S00_AXI_awqos;
|
||||
output S00_AXI_awready;
|
||||
input [2:0]S00_AXI_awsize;
|
||||
input S00_AXI_awvalid;
|
||||
output [11:0]S00_AXI_bid;
|
||||
input S00_AXI_bready;
|
||||
output [1:0]S00_AXI_bresp;
|
||||
output S00_AXI_bvalid;
|
||||
output [31:0]S00_AXI_rdata;
|
||||
output [11:0]S00_AXI_rid;
|
||||
output S00_AXI_rlast;
|
||||
input S00_AXI_rready;
|
||||
output [1:0]S00_AXI_rresp;
|
||||
output S00_AXI_rvalid;
|
||||
input [31:0]S00_AXI_wdata;
|
||||
input [11:0]S00_AXI_wid;
|
||||
input S00_AXI_wlast;
|
||||
output S00_AXI_wready;
|
||||
input [3:0]S00_AXI_wstrb;
|
||||
input S00_AXI_wvalid;
|
||||
|
||||
wire S00_ACLK_1;
|
||||
wire S00_ARESETN_1;
|
||||
wire ps7_0_axi_periph_ACLK_net;
|
||||
wire ps7_0_axi_periph_ARESETN_net;
|
||||
wire [31:0]ps7_0_axi_periph_to_s00_couplers_ARADDR;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_ARBURST;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARCACHE;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_ARID;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARLEN;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_ARLOCK;
|
||||
wire [2:0]ps7_0_axi_periph_to_s00_couplers_ARPROT;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_ARQOS;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_ARREADY;
|
||||
wire [2:0]ps7_0_axi_periph_to_s00_couplers_ARSIZE;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_ARVALID;
|
||||
wire [31:0]ps7_0_axi_periph_to_s00_couplers_AWADDR;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_AWBURST;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWCACHE;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_AWID;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWLEN;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_AWLOCK;
|
||||
wire [2:0]ps7_0_axi_periph_to_s00_couplers_AWPROT;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_AWQOS;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_AWREADY;
|
||||
wire [2:0]ps7_0_axi_periph_to_s00_couplers_AWSIZE;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_AWVALID;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_BID;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_BREADY;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_BRESP;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_BVALID;
|
||||
wire [31:0]ps7_0_axi_periph_to_s00_couplers_RDATA;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_RID;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_RLAST;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_RREADY;
|
||||
wire [1:0]ps7_0_axi_periph_to_s00_couplers_RRESP;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_RVALID;
|
||||
wire [31:0]ps7_0_axi_periph_to_s00_couplers_WDATA;
|
||||
wire [11:0]ps7_0_axi_periph_to_s00_couplers_WID;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_WLAST;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_WREADY;
|
||||
wire [3:0]ps7_0_axi_periph_to_s00_couplers_WSTRB;
|
||||
wire ps7_0_axi_periph_to_s00_couplers_WVALID;
|
||||
wire [31:0]s00_couplers_to_ps7_0_axi_periph_ARADDR;
|
||||
wire [2:0]s00_couplers_to_ps7_0_axi_periph_ARPROT;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_ARREADY;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_ARVALID;
|
||||
wire [31:0]s00_couplers_to_ps7_0_axi_periph_AWADDR;
|
||||
wire [2:0]s00_couplers_to_ps7_0_axi_periph_AWPROT;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_AWREADY;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_AWVALID;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_BREADY;
|
||||
wire [1:0]s00_couplers_to_ps7_0_axi_periph_BRESP;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_BVALID;
|
||||
wire [31:0]s00_couplers_to_ps7_0_axi_periph_RDATA;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_RREADY;
|
||||
wire [1:0]s00_couplers_to_ps7_0_axi_periph_RRESP;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_RVALID;
|
||||
wire [31:0]s00_couplers_to_ps7_0_axi_periph_WDATA;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_WREADY;
|
||||
wire [3:0]s00_couplers_to_ps7_0_axi_periph_WSTRB;
|
||||
wire s00_couplers_to_ps7_0_axi_periph_WVALID;
|
||||
|
||||
assign M00_AXI_araddr[31:0] = s00_couplers_to_ps7_0_axi_periph_ARADDR;
|
||||
assign M00_AXI_arprot[2:0] = s00_couplers_to_ps7_0_axi_periph_ARPROT;
|
||||
assign M00_AXI_arvalid = s00_couplers_to_ps7_0_axi_periph_ARVALID;
|
||||
assign M00_AXI_awaddr[31:0] = s00_couplers_to_ps7_0_axi_periph_AWADDR;
|
||||
assign M00_AXI_awprot[2:0] = s00_couplers_to_ps7_0_axi_periph_AWPROT;
|
||||
assign M00_AXI_awvalid = s00_couplers_to_ps7_0_axi_periph_AWVALID;
|
||||
assign M00_AXI_bready = s00_couplers_to_ps7_0_axi_periph_BREADY;
|
||||
assign M00_AXI_rready = s00_couplers_to_ps7_0_axi_periph_RREADY;
|
||||
assign M00_AXI_wdata[31:0] = s00_couplers_to_ps7_0_axi_periph_WDATA;
|
||||
assign M00_AXI_wstrb[3:0] = s00_couplers_to_ps7_0_axi_periph_WSTRB;
|
||||
assign M00_AXI_wvalid = s00_couplers_to_ps7_0_axi_periph_WVALID;
|
||||
assign S00_ACLK_1 = S00_ACLK;
|
||||
assign S00_ARESETN_1 = S00_ARESETN;
|
||||
assign S00_AXI_arready = ps7_0_axi_periph_to_s00_couplers_ARREADY;
|
||||
assign S00_AXI_awready = ps7_0_axi_periph_to_s00_couplers_AWREADY;
|
||||
assign S00_AXI_bid[11:0] = ps7_0_axi_periph_to_s00_couplers_BID;
|
||||
assign S00_AXI_bresp[1:0] = ps7_0_axi_periph_to_s00_couplers_BRESP;
|
||||
assign S00_AXI_bvalid = ps7_0_axi_periph_to_s00_couplers_BVALID;
|
||||
assign S00_AXI_rdata[31:0] = ps7_0_axi_periph_to_s00_couplers_RDATA;
|
||||
assign S00_AXI_rid[11:0] = ps7_0_axi_periph_to_s00_couplers_RID;
|
||||
assign S00_AXI_rlast = ps7_0_axi_periph_to_s00_couplers_RLAST;
|
||||
assign S00_AXI_rresp[1:0] = ps7_0_axi_periph_to_s00_couplers_RRESP;
|
||||
assign S00_AXI_rvalid = ps7_0_axi_periph_to_s00_couplers_RVALID;
|
||||
assign S00_AXI_wready = ps7_0_axi_periph_to_s00_couplers_WREADY;
|
||||
assign ps7_0_axi_periph_ACLK_net = M00_ACLK;
|
||||
assign ps7_0_axi_periph_ARESETN_net = M00_ARESETN;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
|
||||
assign ps7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_ARREADY = M00_AXI_arready;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_AWREADY = M00_AXI_awready;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
|
||||
assign s00_couplers_to_ps7_0_axi_periph_BVALID = M00_AXI_bvalid;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
|
||||
assign s00_couplers_to_ps7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
|
||||
assign s00_couplers_to_ps7_0_axi_periph_RVALID = M00_AXI_rvalid;
|
||||
assign s00_couplers_to_ps7_0_axi_periph_WREADY = M00_AXI_wready;
|
||||
s00_couplers_imp_11SE3QO s00_couplers
|
||||
(.M_ACLK(ps7_0_axi_periph_ACLK_net),
|
||||
.M_ARESETN(ps7_0_axi_periph_ARESETN_net),
|
||||
.M_AXI_araddr(s00_couplers_to_ps7_0_axi_periph_ARADDR),
|
||||
.M_AXI_arprot(s00_couplers_to_ps7_0_axi_periph_ARPROT),
|
||||
.M_AXI_arready(s00_couplers_to_ps7_0_axi_periph_ARREADY),
|
||||
.M_AXI_arvalid(s00_couplers_to_ps7_0_axi_periph_ARVALID),
|
||||
.M_AXI_awaddr(s00_couplers_to_ps7_0_axi_periph_AWADDR),
|
||||
.M_AXI_awprot(s00_couplers_to_ps7_0_axi_periph_AWPROT),
|
||||
.M_AXI_awready(s00_couplers_to_ps7_0_axi_periph_AWREADY),
|
||||
.M_AXI_awvalid(s00_couplers_to_ps7_0_axi_periph_AWVALID),
|
||||
.M_AXI_bready(s00_couplers_to_ps7_0_axi_periph_BREADY),
|
||||
.M_AXI_bresp(s00_couplers_to_ps7_0_axi_periph_BRESP),
|
||||
.M_AXI_bvalid(s00_couplers_to_ps7_0_axi_periph_BVALID),
|
||||
.M_AXI_rdata(s00_couplers_to_ps7_0_axi_periph_RDATA),
|
||||
.M_AXI_rready(s00_couplers_to_ps7_0_axi_periph_RREADY),
|
||||
.M_AXI_rresp(s00_couplers_to_ps7_0_axi_periph_RRESP),
|
||||
.M_AXI_rvalid(s00_couplers_to_ps7_0_axi_periph_RVALID),
|
||||
.M_AXI_wdata(s00_couplers_to_ps7_0_axi_periph_WDATA),
|
||||
.M_AXI_wready(s00_couplers_to_ps7_0_axi_periph_WREADY),
|
||||
.M_AXI_wstrb(s00_couplers_to_ps7_0_axi_periph_WSTRB),
|
||||
.M_AXI_wvalid(s00_couplers_to_ps7_0_axi_periph_WVALID),
|
||||
.S_ACLK(S00_ACLK_1),
|
||||
.S_ARESETN(S00_ARESETN_1),
|
||||
.S_AXI_araddr(ps7_0_axi_periph_to_s00_couplers_ARADDR),
|
||||
.S_AXI_arburst(ps7_0_axi_periph_to_s00_couplers_ARBURST),
|
||||
.S_AXI_arcache(ps7_0_axi_periph_to_s00_couplers_ARCACHE),
|
||||
.S_AXI_arid(ps7_0_axi_periph_to_s00_couplers_ARID),
|
||||
.S_AXI_arlen(ps7_0_axi_periph_to_s00_couplers_ARLEN),
|
||||
.S_AXI_arlock(ps7_0_axi_periph_to_s00_couplers_ARLOCK),
|
||||
.S_AXI_arprot(ps7_0_axi_periph_to_s00_couplers_ARPROT),
|
||||
.S_AXI_arqos(ps7_0_axi_periph_to_s00_couplers_ARQOS),
|
||||
.S_AXI_arready(ps7_0_axi_periph_to_s00_couplers_ARREADY),
|
||||
.S_AXI_arsize(ps7_0_axi_periph_to_s00_couplers_ARSIZE),
|
||||
.S_AXI_arvalid(ps7_0_axi_periph_to_s00_couplers_ARVALID),
|
||||
.S_AXI_awaddr(ps7_0_axi_periph_to_s00_couplers_AWADDR),
|
||||
.S_AXI_awburst(ps7_0_axi_periph_to_s00_couplers_AWBURST),
|
||||
.S_AXI_awcache(ps7_0_axi_periph_to_s00_couplers_AWCACHE),
|
||||
.S_AXI_awid(ps7_0_axi_periph_to_s00_couplers_AWID),
|
||||
.S_AXI_awlen(ps7_0_axi_periph_to_s00_couplers_AWLEN),
|
||||
.S_AXI_awlock(ps7_0_axi_periph_to_s00_couplers_AWLOCK),
|
||||
.S_AXI_awprot(ps7_0_axi_periph_to_s00_couplers_AWPROT),
|
||||
.S_AXI_awqos(ps7_0_axi_periph_to_s00_couplers_AWQOS),
|
||||
.S_AXI_awready(ps7_0_axi_periph_to_s00_couplers_AWREADY),
|
||||
.S_AXI_awsize(ps7_0_axi_periph_to_s00_couplers_AWSIZE),
|
||||
.S_AXI_awvalid(ps7_0_axi_periph_to_s00_couplers_AWVALID),
|
||||
.S_AXI_bid(ps7_0_axi_periph_to_s00_couplers_BID),
|
||||
.S_AXI_bready(ps7_0_axi_periph_to_s00_couplers_BREADY),
|
||||
.S_AXI_bresp(ps7_0_axi_periph_to_s00_couplers_BRESP),
|
||||
.S_AXI_bvalid(ps7_0_axi_periph_to_s00_couplers_BVALID),
|
||||
.S_AXI_rdata(ps7_0_axi_periph_to_s00_couplers_RDATA),
|
||||
.S_AXI_rid(ps7_0_axi_periph_to_s00_couplers_RID),
|
||||
.S_AXI_rlast(ps7_0_axi_periph_to_s00_couplers_RLAST),
|
||||
.S_AXI_rready(ps7_0_axi_periph_to_s00_couplers_RREADY),
|
||||
.S_AXI_rresp(ps7_0_axi_periph_to_s00_couplers_RRESP),
|
||||
.S_AXI_rvalid(ps7_0_axi_periph_to_s00_couplers_RVALID),
|
||||
.S_AXI_wdata(ps7_0_axi_periph_to_s00_couplers_WDATA),
|
||||
.S_AXI_wid(ps7_0_axi_periph_to_s00_couplers_WID),
|
||||
.S_AXI_wlast(ps7_0_axi_periph_to_s00_couplers_WLAST),
|
||||
.S_AXI_wready(ps7_0_axi_periph_to_s00_couplers_WREADY),
|
||||
.S_AXI_wstrb(ps7_0_axi_periph_to_s00_couplers_WSTRB),
|
||||
.S_AXI_wvalid(ps7_0_axi_periph_to_s00_couplers_WVALID));
|
||||
endmodule
|
||||
Reference in New Issue
Block a user