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Add CPLD_Checkin and other functions

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yuysh
2026-06-17 17:23:59 +08:00
parent 6991600083
commit 72b55f165d
11 changed files with 313 additions and 21 deletions
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Vitis_Classic/NewInstrCalBoard/src/CPLD_Con.c
+141 -3
View File
@@ -1,5 +1,142 @@
#include "CPLD_Con.h"
int CPLD_Checkin()
{
int iStatus = -255;
u32 ureg_data = 0x0;
u8 uCPLD_Count = 3;
xil_printf("[I] Start CPLD Check In...\r\n");
xil_printf("[-]\t Checking CPLD #1\r\n");
//Read CPLD IDENT Reg
iStatus = CPLD_Read(0x1,0x0,&ureg_data);
if (iStatus != XST_SUCCESS)
{
xil_printf("[E] CPLD #1 Communication Failed!\r\n");
uCPLD_Count -= 1;
}
else
{
if (ureg_data == 0x0)
{
xil_printf("[E] CPLD #1 Not present! Or SPI communication Failed!\r\n");
uCPLD_Count -= 1;
}
else
{
if ((ureg_data & 0x200000) != 0x200000)
{
u8 uCID = 0;
uCID = (u8)(ureg_data >> 16);
xil_printf("[E] CPLD #1 Firmware mismatch!\r\n[D] Expect CPLD ID == 1, but we received CPLD ID = 0x%02X\r\n",uCID);
uCPLD_Count -= 1;
}
else
{
u8 uMajorV = 0;
u8 uMinorV = 0;
u8 uFixV = 0;
uMajorV = (u8)((ureg_data & 0x0f00)>>8);
uMinorV = (u8)((ureg_data & 0xf0)>>4);
uFixV = (u8)(ureg_data & 0xf);
xil_printf("[I]\t Successfully Found CPLD #1!\r\n");
xil_printf("[I]\t CPLD #1 Version: v%02d.%02d.%02d\r\n",uMajorV,uMinorV,uFixV);
}
}
}
xil_printf("[-]\t Checking CPLD #2\r\n");
//Read CPLD IDENT Reg
iStatus = CPLD_Read(0x2,0x0,&ureg_data);
if (iStatus != XST_SUCCESS)
{
xil_printf("[E] CPLD #2 Communication Failed!\r\n");
uCPLD_Count -= 1;
}
else
{
if (ureg_data == 0x0)
{
xil_printf("[E] CPLD #2 Not present! Or SPI communication Failed!\r\n");
uCPLD_Count -= 1;
}
else
{
if ((ureg_data & 0x400000) != 0x400000)
{
u8 uCID = 0;
uCID = (u8)(ureg_data >> 16);
xil_printf("[E] CPLD #2 Firmware mismatch!\r\n[D] Expect CPLD ID == 2, but we received CPLD ID = 0x%02X\r\n",uCID);
uCPLD_Count -= 1;
}
else
{
u8 uMajorV = 0;
u8 uMinorV = 0;
u8 uFixV = 0;
uMajorV = (u8)((ureg_data & 0x0f00)>>8);
uMinorV = (u8)((ureg_data & 0xf0)>>4);
uFixV = (u8)(ureg_data & 0xf);
xil_printf("[I]\t Successfully Found CPLD #2!\r\n");
xil_printf("[I]\t CPLD #2 Version: v%02d.%02d.%02d\r\n",uMajorV,uMinorV,uFixV);
}
}
}
xil_printf("[-]\t Checking CPLD #3\r\n");
//Read CPLD IDENT Reg
iStatus = CPLD_Read(0x3,0x0,&ureg_data);
if (iStatus != XST_SUCCESS)
{
xil_printf("[E] CPLD #3 Communication Failed!\r\n");
uCPLD_Count -= 1;
}
else
{
if (ureg_data == 0x0)
{
xil_printf("[E] CPLD #3 Not present! Or SPI communication Failed!\r\n");
uCPLD_Count -= 1;
}
else
{
if ((ureg_data & 0x800000) != 0x800000)
{
u8 uCID = 0;
uCID = (u8)(ureg_data >> 16);
xil_printf("[E] CPLD #3 Firmware mismatch! Expect CPLD ID == 3, but we received CPLD ID = 0x%02X\r\n",uCID);
uCPLD_Count -= 1;
}
else
{
u8 uMajorV = 0;
u8 uMinorV = 0;
u8 uFixV = 0;
uMajorV = (u8)((ureg_data & 0x0f00)>>8);
uMinorV = (u8)((ureg_data & 0xf0)>>4);
uFixV = (u8)(ureg_data & 0xf);
xil_printf("[I]\t Successfully Found CPLD #3!\r\n");
xil_printf("[I]\t CPLD #3 Version: v%02d.%02d.%02d\r\n",uMajorV,uMinorV,uFixV);
}
}
}
if(uCPLD_Count == 3)
{
return XST_SUCCESS;
}
else
{
xil_printf("[E] Only %d/3 CPLD Device is/are healthy\r\n",uCPLD_Count);
return XST_DEVICE_NOT_FOUND;
}
}
int CPLD_Write(u8 addr,u32 data)
{
u16 reg_addr = addr | 0x80; //Write bit set to 1'b1
@@ -27,17 +164,17 @@ int CPLD_Read(u8 CPLDSel, u8 reg_addr, u32* reg_data)
{
case 1:
{
reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U1);
*reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U1);
break;
}
case 2:
{
reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U2);
*reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U2);
break;
}
case 3:
{
reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U3);
*reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U3);
break;
}
@@ -47,6 +184,7 @@ int CPLD_Read(u8 CPLDSel, u8 reg_addr, u32* reg_data)
return XST_INVALID_PARAM;
}
}
return XST_SUCCESS;
}
int CPLD_Read_ALL(u8 reg_addr, u32* reg_data)
Vitis_Classic/NewInstrCalBoard/src/CPLD_Con.h
+1
View File
@@ -9,6 +9,7 @@
#define dat_width 3
int CPLD_Checkin();
int CPLD_Write(u8 addr,u32 data);
int CPLD_Read(u8 CPLDSel, u8 reg_addr, u32* reg_data);
int CPLD_Read_ALL(u8 reg_addr, u32* reg_data);
Vitis_Classic/NewInstrCalBoard/src/cal_meas.c
+20 -7
View File
@@ -9,6 +9,7 @@
int Command_Parser(u8* recvbuffer, u8 len)
{
int iStatus = -255;
switch (recvbuffer[0])
{
case 0x00:
@@ -17,10 +18,11 @@ int Command_Parser(u8* recvbuffer, u8 len)
if (len != CPLD_SPI_READ + 1)
{
xil_printf("[E] Command Length Mismatch!\r\n[I] CPLD Read Format: \"00 [CPLD] [REG Addr]\"\r\n");
return XST_INVALID_PARAM;
}
u32 reg_data = 0x0;
reg_data = CPLD_Read(recvbuffer + 1, recvbuffer + 2, reg_data);
xil_printf("[I] CPLD #%d: REG Addr #0x%01X: Data=0x%03X\r\n",recvbuffer + 1, recvbuffer + 2, reg_data);
iStatus = CPLD_Read(recvbuffer[1], recvbuffer[2], &reg_data);
xil_printf("[I] CPLD #%d: REG Addr #0x%01X: Data=0x%06X\r\n",recvbuffer[1], recvbuffer[2], reg_data);
break;
}
case 0x01:
@@ -37,11 +39,22 @@ int Command_Parser(u8* recvbuffer, u8 len)
}
case 0xA0:
{
int iStatus = -255;
xil_printf("[D] Matched Command Reset\r\n");
rst_CPLD(CPLD_U1,4);
rst_CPLD(CPLD_U2,4);
rst_CPLD(CPLD_U3,4);
xil_printf("[I] CPLD RST Done\r\n");
iStatus = CPLD_Checkin();
if (iStatus != XST_SUCCESS)
{
xil_printf("[E] CPLD Check-in Failed!\r\n");
return XST_FAILURE;
}
else
{
xil_printf("[I] All 3/3 CPLD Checked In!\r\n");
}
break;
}
case 0xA1: //DC Cal
@@ -105,9 +118,9 @@ int DC_Control(u8* idata)
//Let's do some sanity check
//Slot
if ((u_slot > 4) || (u_slot == 0))
if (u_slot > 4)
{
xil_printf("[E] Illege Slot Num check Command! (Slot:1-4)\r\n");
xil_printf("[E] Illege Slot Num check Command! (Slot:0(OFF)-4)\r\n");
cmdValid = -1;
}
//Dev Sel
@@ -132,7 +145,7 @@ int DC_Control(u8* idata)
if ((u_ch_Num < 1) || (u_ch_Num > 64))
{
xil_printf("[E] Illege Channel! (PMU Ch:0x0001-0x0040)\r\n");
xil_printf("[E] Illege Channel! (DPS Ch:0x0000-0x0040)\r\n");
cmdValid = -3;
}
}
@@ -144,9 +157,9 @@ int DC_Control(u8* idata)
cmdValid = -5;
}
//RLoad Sel
if ((u_rLoad > 18) || (u_rLoad == 0))
if (u_rLoad > 18)
{
xil_printf("[E] Illege RLoad Select check Command! (RLoad:0x01-0x12)\r\n");
xil_printf("[E] Illege RLoad Select check Command! (RLoad:0x00(OPEN)-0x12)\r\n");
cmdValid = -6;
}
if (cmdValid != 1)
Vitis_Classic/NewInstrCalBoard/src/main.c
+23 -7
View File
@@ -41,29 +41,45 @@
#include "cal_meas.h"
#include "uart_IO.h"
#define MAJORV 0
#define MINORV 1
#define FIXV 2
u8 recvbuffer[1024] = {0};
int main()
{
int iStatus = -255;
init_platform();
xil_printf("=====================\r\n[I] System Init Done!\r\n");
xil_printf("=====================\r\n[I] System Init Done!=====================\r\n");
xil_printf("\r\n[I] Zynq Version:NewInstCal v%d.%d.%d\r\n\r\n",MAJORV,MINORV,FIXV);
xil_printf("[D] Start EMIO Config\r\n");
EMIO_config();
xil_printf("[D] End of EMIO Config\r\n");
xil_printf("[D] Config CPLD SPI to known state\r\n");
interface_initial(CPLD_U1);
interface_initial(CPLD_U2);
interface_initial(CPLD_U3);
xil_printf("[D] Start CPLD Reset\r\n");
rst_CPLD(CPLD_U1,4);
rst_CPLD(CPLD_U2,4);
rst_CPLD(CPLD_U3,4);
xil_printf("[D] End of CPLD Reset\r\n");
iStatus = CPLD_Checkin();
if (iStatus != XST_SUCCESS)
{
xil_printf("[E] main() stopped!\r\n");
return XST_FAILURE;
}
else
{
xil_printf("[I] All 3/3 CPLD Checked In!\r\n");
}
xil_printf("[D] Config CPLD SPI to known state\r\n");
interface_initial(CPLD_U1);
interface_initial(CPLD_U2);
interface_initial(CPLD_U3);
xil_printf("[I] Board Init Complete!\r\n[I] Waiting for Command...\r\n");
/* receive and process Instructions */