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Add CPLD_Con.c/h: Move CPLD Control Code to seperate file.

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Add CPLD Read/Write Command.
This commit is contained in:
Jeremy Shen
2026-06-01 10:50:36 +08:00
parent a4abf50594
commit 6991600083
6 changed files with 198 additions and 45 deletions
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Vitis_Classic/NewInstrCalBoard/src/CPLD_Con.c
+77
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@@ -0,0 +1,77 @@
#include "CPLD_Con.h"
int CPLD_Write(u8 addr,u32 data)
{
u16 reg_addr = addr | 0x80; //Write bit set to 1'b1
u8 reg_data[dat_width] = {0};
//Data Sanity Check
if ((data >> 24) > 0)
{
xil_printf("[E] CPLD data length should within 24 bits!\r\n");
return XST_INVALID_PARAM;
}
reg_data[0] = (u8)(data >> 16);
reg_data[1] = (u8)(((data)&0xff00)>>8);
reg_data[2] = (u8)data;
spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U1);
spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U2);
spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U3);
return XST_SUCCESS;
}
int CPLD_Read(u8 CPLDSel, u8 reg_addr, u32* reg_data)
{
switch (CPLDSel)
{
case 1:
{
reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U1);
break;
}
case 2:
{
reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U2);
break;
}
case 3:
{
reg_data = uspi_read_onewire(reg_addr, dat_width,CPLD_U3);
break;
}
default:
{
xil_printf("[E] CPLD Select Num Error (Range 1-3)\r\n");
return XST_INVALID_PARAM;
}
}
}
int CPLD_Read_ALL(u8 reg_addr, u32* reg_data)
{
//TODO:Sanity Check
reg_data[0]=uspi_read_onewire(reg_addr, dat_width,CPLD_U1);
reg_data[1]=uspi_read_onewire(reg_addr, dat_width,CPLD_U2);
reg_data[2]=uspi_read_onewire(reg_addr, dat_width,CPLD_U3);
//TODO:SUCCESS Check
return XST_SUCCESS;
}
int CPLD_exec()
{
u8 reg_addr = 0x01;
u8 sw_config_data[3] = {0x00,0x00,0x00};
sw_config_data[0] = 0x00;
sw_config_data[1] = 0x00;
sw_config_data[2] = 0x01;
reg_addr = reg_addr | 0x80;
spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U3);
return XST_SUCCESS;
}
Vitis_Classic/NewInstrCalBoard/src/CPLD_Con.h
+19
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@@ -0,0 +1,19 @@
#ifndef CPLD_CON_H_
#define CPLD_CON_H_
#include <stdio.h>
#include <xstatus.h>
#include <xparameters.h>
#include "GPIO_Driv.h"
#include "SPI_Driv.h"
#define dat_width 3
int CPLD_Write(u8 addr,u32 data);
int CPLD_Read(u8 CPLDSel, u8 reg_addr, u32* reg_data);
int CPLD_Read_ALL(u8 reg_addr, u32* reg_data);
int CPLD_exec();
#endif /* CPLD_CON_H_ */
Vitis_Classic/NewInstrCalBoard/src/SPI_Driv.c
+69 -1
View File
@@ -128,7 +128,7 @@ void spi_write_onewire(u8 addr, u8 *data, u8 width, u32* device)
* data -- 数据
* width -- 数据长度
* device -- CPLD
* Return : void
* Return : void //??????
******************************************************************************/
u32 spi_read_onewire(char addr, char width, u32* device,char* read_data)
{
@@ -193,6 +193,74 @@ u32 spi_read_onewire(char addr, char width, u32* device,char* read_data)
return temp_data;
}
/******************************************************************************
* Function : u32 uspi_read_onewire(char addr, char width, u32* device)
* Description : spi onewire read
* Parameter : addr -- 地址
* width -- 数据长度
* device -- CPLD
* Return : u32 reg_data
******************************************************************************/
u32 uspi_read_onewire(char addr, char width, u32* device)
{
char temp_addr=0;
u32 temp_data=0;
char i=0,j=0;
u32 sck = *(device+0);
u32 cs= *(device+1);
u32 sdi= *(device+2);
u32 sdo= *(device+3);
temp_addr = addr;
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 0);
//XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0); // w/r标志位 1=w 0=r
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
//XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
for(i = 0; i < 8; i++) // 8bit地址
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
if(temp_addr&0x80)
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 1); //sck低电平传输数据 数据从中间变量到通信线上
else
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
temp_addr = temp_addr<<1; //sck高电平准备数据,此处为准备第二个数据，第一个数据已经传输完毕
}
for(j=0; j<width; j++)
{
for(i = 0; i < 8; i++) //nbit数据
{
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
temp_data = temp_data << 1; //sck低电平准备数据 准备好数位，此时的数据相当于从右边的FPGA移进MCU(先准备好中间变量)
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 1);
if(XGpioPs_ReadPin(&psGpioInstancePtr,sdo)) //sck高电平接收数据 数据匹配到准备好的数位，等待一起传递到MCU
temp_data = temp_data| 0x00000001;
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
}
}
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, sck, 0);
XGpioPs_WritePin(&psGpioInstancePtr, cs, 1);
XGpioPs_WritePin(&psGpioInstancePtr, sdi, 0);
return temp_data;
}
/******************************************************************************
* Function : void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3)
* Description : forwire write to reg
Vitis_Classic/NewInstrCalBoard/src/SPI_Driv.h
+2
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@@ -36,6 +36,8 @@ void rst(char *d);
void spi_write_onewire(u8 addr, u8 *data, u8 width, u32* device);
u32 spi_read_onewire(char addr,char width,u32* device,char* read_data);
u32 uspi_read_onewire(char addr, char width, u32* device);
void fourwire_write(u8 txdata, u32 sdi0, u32 sdi1, u32 sdi2, u32 sdi3);
u16 fourwire_read(u32 sdo0, u32 sdo1, u32 sdo2, u32 sdo3);
void spi_write_fourwire(char addr,u16 data,u32* device);
Vitis_Classic/NewInstrCalBoard/src/cal_meas.c
+28 -41
View File
@@ -6,13 +6,35 @@
*/
#include "cal_meas.h"
#include "SPI_Driv.h"
u8 sw_config_data[3] = {0x00,0x00,0x00};
int Command_Parser(u8* recvbuffer, u8 len)
{
switch (recvbuffer[0])
{
case 0x00:
{
xil_printf("[D] Match Command CPLD Read\r\n");
if (len != CPLD_SPI_READ + 1)
{
xil_printf("[E] Command Length Mismatch!\r\n[I] CPLD Read Format: \"00 [CPLD] [REG Addr]\"\r\n");
}
u32 reg_data = 0x0;
reg_data = CPLD_Read(recvbuffer + 1, recvbuffer + 2, reg_data);
xil_printf("[I] CPLD #%d: REG Addr #0x%01X: Data=0x%03X\r\n",recvbuffer + 1, recvbuffer + 2, reg_data);
break;
}
case 0x01:
{
xil_printf("[D] Match Command CPLD Write\r\n");
if (len != CPLD_SPI_WRITE + 1)
{
xil_printf("[E] Command Length Mismatch!\r\n[I] CPLD Write Format: \"01 [CPLD] [REG Addr] [Data]\"\r\n");
return XST_INVALID_PARAM;
}
xil_printf("[D] TBD!\r\n");
break;
}
case 0xA0:
{
xil_printf("[D] Matched Command Reset\r\n");
@@ -28,7 +50,7 @@ int Command_Parser(u8* recvbuffer, u8 len)
//Command Len Sanity Check
if (len != DC_CMD_LEN + 1) //Do NOT forget the command header
{
xil_printf("[E] \r\n");
xil_printf("[E] Command Length Mismatch!\r\n[I] DC Cal Format: \"A1 [01-04:SLOT] [01:PMU/02:DPS] [0001-0100:Channel_Num] [01:V/02:I] [01-12:RLoad]\"\r\n");
return XST_INVALID_PARAM;
}
DC_Control(recvbuffer + 1); //Op-out the command header
@@ -39,8 +61,8 @@ int Command_Parser(u8* recvbuffer, u8 len)
xil_printf("[D] Matched Command Freq Cal\r\n");
if (len > Freq_CMD_LEN + 1) //Do NOT forget the command header
{
xil_printf("[E] \r\n");
//TODO: ADD Freq Command Format Hint
xil_printf("[E] Command Length Mismatch!\r\n[I] Freq Cal Format: TBD\r\n");
return XST_INVALID_PARAM;
}
sw_config(recvbuffer + 1); //Op-out the command header
@@ -254,42 +276,6 @@ int DC_Control(u8* idata)
return XST_SUCCESS;
}
int CPLD_Write(u8 addr,u32 data)
{
u16 reg_addr = addr | 0x80; //Write bit set to 1'b1
u8 reg_data[dat_width] = {0};
//Data Sanity Check
if ((data >> 24) > 0)
{
xil_printf("[E] CPLD data length should within 24 bits!\r\n");
return XST_INVALID_PARAM;
}
reg_data[0] = (u8)(data >> 16);
reg_data[1] = (u8)(((data)&0xff00)>>8);
reg_data[2] = (u8)data;
spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U1);
spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U2);
spi_write_onewire(reg_addr, reg_data, dat_width, CPLD_U3);
return XST_SUCCESS;
}
int CPLD_exec()
{
u8 reg_addr = 0x01;
sw_config_data[0] = 0x00;
sw_config_data[1] = 0x00;
sw_config_data[2] = 0x01;
reg_addr = reg_addr | 0x80;
spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U1);
spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U2);
spi_write_onewire(reg_addr, sw_config_data, dat_width, CPLD_U3);
return XST_SUCCESS;
}
void sw_config(char *slot_start)
{
@@ -308,6 +294,7 @@ void sw_config(char *slot_start)
u8 cpld_addr = 0;
u32 cpld_dat = 0;
u8 sw_config_data[3] = {0x00,0x00,0x00};
ch_num = (((u16)ch_num_h)<<8) + ((u16)ch_num_l);
Vitis_Classic/NewInstrCalBoard/src/cal_meas.h
+3 -3
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@@ -13,11 +13,11 @@
#include "xstatus.h"
#include "xgpiops.h"
#include "SPI_Driv.h"
#include "GPIO_Driv.h"
#include "CPLD_Con.h"
#define dat_width 3
#define CPLD_SPI_WRITE 5
#define CPLD_SPI_READ 2
#define DC_CMD_LEN 6
#define Freq_CMD_LEN 7 //TODO: Update sw_config()!