From 67faaf25d20aaeada3e664a9e1387436f8070677 Mon Sep 17 00:00:00 2001 From: yuysh Date: Thu, 28 May 2026 17:30:52 +0800 Subject: [PATCH] Remove unnecessary tracked files --- Debug_FW.runs/impl_1/runme.log | 845 --- Debug_FW.runs/synth_1/runme.log | 696 -- Debug_FW.sdk/SDK.log | 2262 ------- Debug_FW.sdk/webtalk/webtalk.log | 58 - Debug_FW.sdk/webtalk/webtalk_20184.backup.log | 73 - Debug_FW.sdk/webtalk/webtalk_5900.backup.log | 62 - Debug_FW.sdk/webtalk/webtalk_7548.backup.log | 58 - Vitis_Classic/IDE.log | 13 - .../.log/NewInstCal_bsp_.build.ui.log | 2 - .../NewInstCal_bsp/logs/platform.log | 5743 ----------------- 10 files changed, 9812 deletions(-) delete mode 100644 Debug_FW.runs/impl_1/runme.log delete mode 100644 Debug_FW.runs/synth_1/runme.log delete mode 100644 Debug_FW.sdk/SDK.log delete mode 100644 Debug_FW.sdk/webtalk/webtalk.log delete mode 100644 Debug_FW.sdk/webtalk/webtalk_20184.backup.log delete mode 100644 Debug_FW.sdk/webtalk/webtalk_5900.backup.log delete mode 100644 Debug_FW.sdk/webtalk/webtalk_7548.backup.log delete mode 100644 Vitis_Classic/IDE.log delete mode 100644 Vitis_Classic/NewInstCal_bsp/.log/NewInstCal_bsp_.build.ui.log delete mode 100644 Vitis_Classic/NewInstCal_bsp/logs/platform.log diff --git a/Debug_FW.runs/impl_1/runme.log b/Debug_FW.runs/impl_1/runme.log deleted file mode 100644 index ac9647e..0000000 --- a/Debug_FW.runs/impl_1/runme.log +++ /dev/null @@ -1,845 +0,0 @@ - -*** Running vivado - with args -log system_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source system_wrapper.tcl -notrace - - -****** Vivado v2023.2 (64-bit) - **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 - **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 - **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 - ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. - ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. - -source system_wrapper.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1704] No user IP repositories specified -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'. -Command: link_design -top system_wrapper -part xc7z035ffg676-2 -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Device 21-403] Loading part xc7z035ffg676-2 -Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1722.395 ; gain = 0.000 ; free physical = 1995 ; free virtual = 71203 -INFO: [Netlist 29-17] Analyzing 39 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2023.2 -INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst' -Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst' -Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0' -Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0' -Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0' -WARNING: [Vivado_Tcl 4-921] Waiver ID 'CDC-11' -to list should not be empty. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc:50] -Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0' -Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc] -Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc] -Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc] -Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc] -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Project 1-1687] 1 scoped IP constraints or related sub-commands were skipped due to synthesis logic optimizations usually triggered by constant connectivity or unconnected output pins. To review the skipped constraints and messages, run the command 'set_param netlist.IPMsgFiltering false' before opening the design. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2307.883 ; gain = 0.000 ; free physical = 1722 ; free virtual = 70993 -INFO: [Project 1-111] Unisim Transformation Summary: - A total of 33 instances were transformed. - IOBUF => IOBUF (IBUF, OBUFT): 33 instances - -11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2307.883 ; gain = 962.004 ; free physical = 1730 ; free virtual = 71000 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z035' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 8 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2307.883 ; gain = 0.000 ; free physical = 1727 ; free virtual = 71012 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 2382775f8 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2762.520 ; gain = 454.637 ; free physical = 1293 ; free virtual = 70618 - -Starting Logic Optimization Task - -Phase 1 Initialization - -Phase 1.1 Core Generation And Design Setup - -Phase 1.1.1 Generate And Synthesize Debug Cores -INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub -INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV. -INFO: [Chipscope 16-329] Generating Script for core instance : u_ila_0 -INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:ila:6.2 for cell u_ila_0_CV. -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3095.020 ; gain = 0.000 ; free physical = 9128 ; free virtual = 68708 -Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3201.777 ; gain = 0.000 ; free physical = 8923 ; free virtual = 68563 -Netlist sorting complete. Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3378.160 ; gain = 0.000 ; free physical = 8306 ; free virtual = 68085 -Phase 1.1.1 Generate And Synthesize Debug Cores | Checksum: 1a85f7bbe - -Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68085 -Phase 1.1 Core Generation And Design Setup | Checksum: 1a85f7bbe - -Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68085 - -Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1a85f7bbe - -Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8306 ; free virtual = 68086 -Phase 1 Initialization | Checksum: 1a85f7bbe - -Time (s): cpu = 00:03:04 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8300 ; free virtual = 68083 - -Phase 2 Timer Update And Timing Data Collection - -Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 1a85f7bbe - -Time (s): cpu = 00:03:06 ; elapsed = 00:03:16 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8296 ; free virtual = 68078 - -Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 1a85f7bbe - -Time (s): cpu = 00:03:06 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8279 ; free virtual = 68065 -Phase 2 Timer Update And Timing Data Collection | Checksum: 1a85f7bbe - -Time (s): cpu = 00:03:06 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8279 ; free virtual = 68065 - -Phase 3 Retarget -INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: 20e292eaa - -Time (s): cpu = 00:03:07 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8270 ; free virtual = 68062 -Retarget | Checksum: 20e292eaa -INFO: [Opt 31-389] Phase Retarget created 4 cells and removed 35 cells -INFO: [Opt 31-1021] In phase Retarget, 99 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 4 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: 1fb9c5663 - -Time (s): cpu = 00:03:07 ; elapsed = 00:03:17 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8271 ; free virtual = 68063 -Constant propagation | Checksum: 1fb9c5663 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 16 cells -INFO: [Opt 31-1021] In phase Constant propagation, 49 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 5 Sweep -Phase 5 Sweep | Checksum: 1dd19d44b - -Time (s): cpu = 00:03:08 ; elapsed = 00:03:18 . Memory (MB): peak = 3378.160 ; gain = 312.891 ; free physical = 8274 ; free virtual = 68074 -Sweep | Checksum: 1dd19d44b -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 46 cells -INFO: [Opt 31-1021] In phase Sweep, 956 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 6 BUFG optimization -INFO: [Opt 31-194] Inserted BUFG system_i/dna_port_read_0/inst/read_vld_BUFG_inst to drive 57 load(s) on clock net system_i/dna_port_read_0/inst/read_vld_BUFG -INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets -Phase 6 BUFG optimization | Checksum: 202feca59 - -Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8266 ; free virtual = 68070 -BUFG optimization | Checksum: 202feca59 -INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells. - -Phase 7 Shift Register Optimization -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/I_YESLUT6.U_SRLC16E due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/I_YESLUT6.U_SRLC16E due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_A due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from u_ila_0/inst/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_B due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 due to none static srl address bits -WARNING: [Opt 31-1131] Can not pull register out from system_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 due to none static srl address bits -INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: 202feca59 - -Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8263 ; free virtual = 68069 -Shift Register Optimization | Checksum: 202feca59 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: 202feca59 - -Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8260 ; free virtual = 68067 -Post Processing Netlist | Checksum: 202feca59 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -INFO: [Opt 31-1021] In phase Post Processing Netlist, 57 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. - -Phase 9 Finalization - -Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 2572a104c - -Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8258 ; free virtual = 68070 - -Phase 9.2 Verifying Netlist Connectivity - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3442.176 ; gain = 0.000 ; free physical = 8255 ; free virtual = 68068 -Phase 9.2 Verifying Netlist Connectivity | Checksum: 2572a104c - -Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8255 ; free virtual = 68068 -Phase 9 Finalization | Checksum: 2572a104c - -Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8255 ; free virtual = 68068 -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 4 | 35 | 99 | -| Constant propagation | 0 | 16 | 49 | -| Sweep | 0 | 46 | 956 | -| BUFG optimization | 1 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 57 | -------------------------------------------------------------------------------------------------------------------------- - - -Ending Logic Optimization Task | Checksum: 2572a104c - -Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 3442.176 ; gain = 376.906 ; free physical = 8254 ; free virtual = 68068 -INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3442.176 ; gain = 0.000 ; free physical = 8253 ; free virtual = 68067 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -INFO: [Power 33-23] Power model is not available for DNA_PORT_inst -INFO: [Pwropt 34-9] Applying IDT optimizations ... -INFO: [Pwropt 34-10] Applying ODC optimizations ... -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation - - -Starting PowerOpt Patch Enables Task -INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 3 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. -INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports -Number of BRAM Ports augmented: 3 newly gated: 0 Total Ports: 6 -Ending PowerOpt Patch Enables Task | Checksum: 1c6a995af - -Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.24 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7922 ; free virtual = 67775 -Ending Power Optimization Task | Checksum: 1c6a995af - -Time (s): cpu = 00:00:11 ; elapsed = 00:00:04 . Memory (MB): peak = 3998.043 ; gain = 555.867 ; free physical = 7922 ; free virtual = 67775 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 1c6a995af - -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7922 ; free virtual = 67774 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7921 ; free virtual = 67776 -Ending Netlist Obfuscation Task | Checksum: 1b06a1b26 - -Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7921 ; free virtual = 67776 -INFO: [Common 17-83] Releasing license: Implementation -54 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:03:26 ; elapsed = 00:03:28 . Memory (MB): peak = 3998.043 ; gain = 1690.160 ; free physical = 7921 ; free virtual = 67776 -INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx -Command: report_drc -file system_wrapper_drc_opted.rpt -pb system_wrapper_drc_opted.pb -rpx system_wrapper_drc_opted.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 8 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_drc_opted.rpt. -report_drc completed successfully -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Timing 38-480] Writing timing data to binary archive. -Wrote PlaceDB: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7766 ; free virtual = 67648 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7766 ; free virtual = 67648 -Writing XDEF routing. -Writing XDEF routing logical nets. -Write ShapeDB Complete: Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.05 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67652 -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67653 -Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67653 -Wrote Device Cache: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67654 -Write Physdb Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7763 ; free virtual = 67654 -INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_opt.dcp' has been generated. -INFO: [Chipscope 16-240] Debug cores have already been implemented -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z035' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035' -INFO: [Common 17-83] Releasing license: Implementation -INFO: [DRC 23-27] Running DRC with 8 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 8 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs - -Starting Placer Task - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7612 ; free virtual = 67560 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 19758bd7a - -Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7612 ; free virtual = 67559 -Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7611 ; free virtual = 67559 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8751fbf6 - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7587 ; free virtual = 67558 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: dd0b0e99 - -Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7431 ; free virtual = 67481 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: dd0b0e99 - -Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7428 ; free virtual = 67479 -Phase 1 Placer Initialization | Checksum: dd0b0e99 - -Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7428 ; free virtual = 67479 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: eecb6848 - -Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7404 ; free virtual = 67474 - -Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: db55687b - -Time (s): cpu = 00:00:23 ; elapsed = 00:00:12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7407 ; free virtual = 67493 - -Phase 2.3 Post-Processing in Floorplanning -Phase 2.3 Post-Processing in Floorplanning | Checksum: db55687b - -Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7401 ; free virtual = 67488 - -Phase 2.4 Global Placement Core - -Phase 2.4.1 UpdateTiming Before Physical Synthesis -Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1e9ca9de9 - -Time (s): cpu = 00:00:54 ; elapsed = 00:00:25 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7017 ; free virtual = 67264 - -Phase 2.4.2 Physical Synthesis In Placer -INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 1172 LUT instances to create LUTNM shape -INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 -INFO: [Physopt 32-1138] End 1 Pass. Optimized 565 nets or LUTs. Breaked 0 LUT, combined 565 existing LUTs and moved 0 existing LUT -INFO: [Physopt 32-65] No nets found for high-fanout optimization. -INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. -INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. -INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7022 ; free virtual = 67279 - -Summary of Physical Synthesis Optimizations -============================================ - - ------------------------------------------------------------------------------------------------------------------------------------------------------------ -| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------ -| LUT Combining | 0 | 565 | 565 | 0 | 1 | 00:00:00 | -| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | -| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 0 | 565 | 565 | 0 | 4 | 00:00:01 | ------------------------------------------------------------------------------------------------------------------------------------------------------------ - - -Phase 2.4.2 Physical Synthesis In Placer | Checksum: 2be40b2db - -Time (s): cpu = 00:00:59 ; elapsed = 00:00:28 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7014 ; free virtual = 67290 -Phase 2.4 Global Placement Core | Checksum: 2859c5ffd - -Time (s): cpu = 00:01:01 ; elapsed = 00:00:29 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7011 ; free virtual = 67293 -Phase 2 Global Placement | Checksum: 2859c5ffd - -Time (s): cpu = 00:01:01 ; elapsed = 00:00:29 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7011 ; free virtual = 67293 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 1ea091a8d - -Time (s): cpu = 00:01:05 ; elapsed = 00:00:30 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 7007 ; free virtual = 67305 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 29969cf51 - -Time (s): cpu = 00:01:13 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6986 ; free virtual = 67345 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 2b62d77e5 - -Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6984 ; free virtual = 67343 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 1ed299be3 - -Time (s): cpu = 00:01:14 ; elapsed = 00:00:35 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6982 ; free virtual = 67342 - -Phase 3.5 Small Shape Detail Placement - -Phase 3.5.1 Place Remaining -Phase 3.5.1 Place Remaining | Checksum: 21b5bb37c - -Time (s): cpu = 00:01:20 ; elapsed = 00:00:41 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6918 ; free virtual = 67346 -Phase 3.5 Small Shape Detail Placement | Checksum: 21b5bb37c - -Time (s): cpu = 00:01:20 ; elapsed = 00:00:41 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6849 ; free virtual = 67281 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 1a6b845f5 - -Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6838 ; free virtual = 67277 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 1a81ce610 - -Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6834 ; free virtual = 67277 -Phase 3 Detail Placement | Checksum: 1a81ce610 - -Time (s): cpu = 00:01:21 ; elapsed = 00:00:42 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6828 ; free virtual = 67276 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -INFO: [Timing 38-35] Done setting XDC timing constraints. - -Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 1472dfedc - -Phase 4.1.1.1 BUFG Insertion - -Starting Physical Synthesis Task - -Phase 1 Physical Synthesis Initialization -INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.626 | TNS=0.000 | -Phase 1 Physical Synthesis Initialization | Checksum: a925bbef - -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6782 ; free virtual = 67315 -INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. -Ending Physical Synthesis Task | Checksum: a925bbef - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6769 ; free virtual = 67309 -Phase 4.1.1.1 BUFG Insertion | Checksum: 1472dfedc - -Time (s): cpu = 00:01:38 ; elapsed = 00:00:50 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6768 ; free virtual = 67314 - -Phase 4.1.1.2 Post Placement Timing Optimization -INFO: [Place 30-746] Post Placement Timing Summary WNS=2.626. For the most accurate timing information please run report_timing. -Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 14f55351a - -Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307 - -Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307 -Phase 4.1 Post Commit Optimization | Checksum: 14f55351a - -Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6755 ; free virtual = 67307 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 14f55351a - -Time (s): cpu = 00:01:39 ; elapsed = 00:00:51 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6750 ; free virtual = 67308 - -Phase 4.3 Placer Reporting - -Phase 4.3.1 Print Estimated Congestion -INFO: [Place 30-612] Post-Placement Estimated Congestion - ____________________________________________________ -| | Global Congestion | Short Congestion | -| Direction | Region Size | Region Size | -|___________|___________________|___________________| -| North| 2x2| 2x2| -|___________|___________________|___________________| -| South| 1x1| 1x1| -|___________|___________________|___________________| -| East| 1x1| 1x1| -|___________|___________________|___________________| -| West| 1x1| 1x1| -|___________|___________________|___________________| - -Phase 4.3.1 Print Estimated Congestion | Checksum: 14f55351a - -Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6748 ; free virtual = 67312 -Phase 4.3 Placer Reporting | Checksum: 14f55351a - -Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321 - -Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6751 ; free virtual = 67321 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 19c30fa75 - -Time (s): cpu = 00:01:40 ; elapsed = 00:00:52 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6741 ; free virtual = 67314 -Ending Placer Task | Checksum: dcf0239e - -Time (s): cpu = 00:01:41 ; elapsed = 00:00:53 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6725 ; free virtual = 67298 -90 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -place_design: Time (s): cpu = 00:01:44 ; elapsed = 00:00:54 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6725 ; free virtual = 67298 -INFO: [runtcl-4] Executing : report_io -file system_wrapper_io_placed.rpt -report_io: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6722 ; free virtual = 67295 -INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_placed.rpt -pb system_wrapper_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file system_wrapper_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.12 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6708 ; free virtual = 67293 -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.09 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6731 ; free virtual = 67329 -Wrote PlaceDB: Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67235 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67235 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6584 ; free virtual = 67236 -Wrote Netlist Cache: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6582 ; free virtual = 67237 -Wrote Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6582 ; free virtual = 67238 -Write Physdb Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 6581 ; free virtual = 67237 -INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_placed.dcp' has been generated. -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7z035' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 8 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs - -Phase 1 Build RT Design -Checksum: PlaceDB: 76da8209 ConstDB: 0 ShapeSum: 6615a195 RouteDB: 0 -Post Restoration Checksum: NetGraph: 4a144a14 | NumContArr: af14b29e | Constraints: c2a8fa9d | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 27e7af1ec - -Time (s): cpu = 00:00:49 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5905 ; free virtual = 66985 - -Phase 2 Router Initialization - -Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 27e7af1ec - -Time (s): cpu = 00:00:50 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5899 ; free virtual = 66984 - -Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 27e7af1ec - -Time (s): cpu = 00:00:50 ; elapsed = 00:00:32 . Memory (MB): peak = 3998.043 ; gain = 0.000 ; free physical = 5899 ; free virtual = 66984 - Number of Nodes with overlaps = 0 - -Phase 2.3 Update Timing -Phase 2.3 Update Timing | Checksum: 32928bcd2 - -Time (s): cpu = 00:01:06 ; elapsed = 00:00:40 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5635 ; free virtual = 66801 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.632 | TNS=0.000 | WHS=-0.263 | THS=-1616.164| - - -Phase 2.4 Update Timing for Bus Skew - -Phase 2.4.1 Update Timing -Phase 2.4.1 Update Timing | Checksum: 2864114c5 - -Time (s): cpu = 00:01:19 ; elapsed = 00:00:43 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5449 ; free virtual = 66672 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.632 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 2.4 Update Timing for Bus Skew | Checksum: 291576a87 - -Time (s): cpu = 00:01:19 ; elapsed = 00:00:44 . Memory (MB): peak = 4046.500 ; gain = 48.457 ; free physical = 5447 ; free virtual = 66671 - -Router Utilization Summary - Global Vertical Routing Utilization = 0.0211705 % - Global Horizontal Routing Utilization = 0.00488761 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 38492 - (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 38484 - Number of Partially Routed Nets = 8 - Number of Node Overlaps = 6 - -Phase 2 Router Initialization | Checksum: 2a426d310 - -Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5405 ; free virtual = 66633 - -Phase 3 Initial Routing - -Phase 3.1 Global Routing -Phase 3.1 Global Routing | Checksum: 2a426d310 - -Time (s): cpu = 00:01:20 ; elapsed = 00:00:44 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5405 ; free virtual = 66633 - -Phase 3.2 Initial Net Routing -Phase 3.2 Initial Net Routing | Checksum: 22defbe6f - -Time (s): cpu = 00:01:27 ; elapsed = 00:00:46 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5394 ; free virtual = 66641 -Phase 3 Initial Routing | Checksum: 22defbe6f - -Time (s): cpu = 00:01:27 ; elapsed = 00:00:46 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5394 ; free virtual = 66641 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 2836 - Number of Nodes with overlaps = 86 - Number of Nodes with overlaps = 3 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.177 | TNS=0.000 | WHS=N/A | THS=N/A | - -Phase 4.1 Global Iteration 0 | Checksum: 23a222cd5 - -Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5385 ; free virtual = 66739 -Phase 4 Rip-up And Reroute | Checksum: 23a222cd5 - -Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5385 ; free virtual = 66739 - -Phase 5 Delay and Skew Optimization - -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 23a222cd5 - -Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738 - -Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 23a222cd5 - -Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738 -Phase 5 Delay and Skew Optimization | Checksum: 23a222cd5 - -Time (s): cpu = 00:01:43 ; elapsed = 00:00:54 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5384 ; free virtual = 66738 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter - -Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 2a8514d39 - -Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5382 ; free virtual = 66749 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.189 | TNS=0.000 | WHS=0.028 | THS=0.000 | - -Phase 6.1 Hold Fix Iter | Checksum: 253fa4620 - -Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748 -Phase 6 Post Hold Fix | Checksum: 253fa4620 - -Time (s): cpu = 00:01:47 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 2.42898 % - Global Horizontal Routing Utilization = 2.87613 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Phase 7 Route finalize | Checksum: 253fa4620 - -Time (s): cpu = 00:01:48 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 253fa4620 - -Time (s): cpu = 00:01:48 ; elapsed = 00:00:56 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5381 ; free virtual = 66748 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 24ae08112 - -Time (s): cpu = 00:01:50 ; elapsed = 00:00:57 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5378 ; free virtual = 66754 - -Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=1.189 | TNS=0.000 | WHS=0.028 | THS=0.000 | - -INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 24ae08112 - -Time (s): cpu = 00:01:53 ; elapsed = 00:00:58 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5367 ; free virtual = 66762 -INFO: [Route 35-16] Router Completed Successfully - -Phase 11 Post-Route Event Processing -Phase 11 Post-Route Event Processing | Checksum: 10a817867 - -Time (s): cpu = 00:01:54 ; elapsed = 00:00:59 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5358 ; free virtual = 66761 -Ending Routing Task | Checksum: 10a817867 - -Time (s): cpu = 00:01:55 ; elapsed = 00:01:00 . Memory (MB): peak = 4082.977 ; gain = 84.934 ; free physical = 5334 ; free virtual = 66752 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -108 Infos, 82 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:01:59 ; elapsed = 00:01:02 . Memory (MB): peak = 4083.043 ; gain = 85.000 ; free physical = 5335 ; free virtual = 66757 -INFO: [runtcl-4] Executing : report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx -Command: report_drc -file system_wrapper_drc_routed.rpt -pb system_wrapper_drc_routed.pb -rpx system_wrapper_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 8 threads -INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx -Command: report_methodology -file system_wrapper_methodology_drc_routed.rpt -pb system_wrapper_methodology_drc_routed.pb -rpx system_wrapper_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 8 threads -INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_methodology_drc_routed.rpt. -report_methodology completed successfully -report_methodology: Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5233 ; free virtual = 66738 -INFO: [runtcl-4] Executing : report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx -Command: report_power -file system_wrapper_power_routed.rpt -pb system_wrapper_power_summary_routed.pb -rpx system_wrapper_power_routed.rpx -INFO: [Power 33-23] Power model is not available for DNA_PORT_inst -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. -Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. -119 Infos, 83 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -report_power: Time (s): cpu = 00:00:16 ; elapsed = 00:00:06 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5140 ; free virtual = 66731 -INFO: [runtcl-4] Executing : report_route_status -file system_wrapper_route_status.rpt -pb system_wrapper_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file system_wrapper_timing_summary_routed.rpt -pb system_wrapper_timing_summary_routed.pb -rpx system_wrapper_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs -WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met. -INFO: [runtcl-4] Executing : report_incremental_reuse -file system_wrapper_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file system_wrapper_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file system_wrapper_bus_skew_routed.rpt -pb system_wrapper_bus_skew_routed.pb -rpx system_wrapper_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs -INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5090 ; free virtual = 66740 -Wrote PlaceDB: Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5008 ; free virtual = 66718 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 5008 ; free virtual = 66718 -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.29 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66717 -Wrote Netlist Cache: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66719 -Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66720 -Write Physdb Complete: Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4299.051 ; gain = 0.000 ; free physical = 4994 ; free virtual = 66721 -INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/impl_1/system_wrapper_routed.dcp' has been generated. -Command: write_bitstream -force system_wrapper.bit -Attempting to get a license for feature 'Implementation' and/or device 'xc7z035' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z035' -Running DRC as a precondition to command write_bitstream -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 8 threads -WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I0) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. -WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A3' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.id_state[0]_i_1/I0) is not included in the LUT equation: 'O6=(A6+~A6)*((A5))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. -WARNING: [DRC PDCN-1569] LUT equation term check: Used physical LUT pin 'A5' of cell dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1 (pin dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[31]_i_1/I1) is not included in the LUT equation: 'O5=(A1*A2)+(A1*(~A2)*(~A4))+((~A1))'. If this cell is a user instantiated LUT in the design, please remove connectivity to the pin or change the equation and/or INIT string of the LUT to prevent this issue. If the cell is inferred or IP created LUT, please regenerate the IP and/or resynthesize the design to attempt to correct the issue. -WARNING: [DRC RTSTAT-10] No routable loads: 21 net(s) have no routable loads. The problem bus(es) and/or net(s) are dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TMS, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg[2:0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_en_2[1], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_capture[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0], dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_runtest[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg[0], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg[2], dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwhf.whf/overflow, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gras.rsts/ram_empty_i, dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i... and (the first 15 of 19 listed). -INFO: [Vivado 12-3199] DRC finished with 0 Errors, 4 Warnings -INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. -INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. -Loading data files... -Loading site data... -Loading route data... -Processing options... -Creating bitmap... -Creating bitstream... -Writing bitstream ./system_wrapper.bit... -INFO: [Vivado 12-1842] Bitgen Completed Successfully. -INFO: [Common 17-83] Releasing license: Implementation -13 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. -write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 4599.906 ; gain = 300.855 ; free physical = 4256 ; free virtual = 66217 -INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:43:10 2026... diff --git a/Debug_FW.runs/synth_1/runme.log b/Debug_FW.runs/synth_1/runme.log deleted file mode 100644 index c2c8d69..0000000 --- a/Debug_FW.runs/synth_1/runme.log +++ /dev/null @@ -1,696 +0,0 @@ - -*** Running vivado - with args -log system_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source system_wrapper.tcl - - -****** Vivado v2023.2 (64-bit) - **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 - **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 - **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 - ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. - ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. - -source system_wrapper.tcl -notrace -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1704] No user IP repositories specified -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/data/xilinx/Vivado/2023.2/data/ip'. -Command: synth_design -top system_wrapper -part xc7z035ffg676-2 -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7z035' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z035' -INFO: [Device 21-403] Loading part xc7z035ffg676-2 -INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. -INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 958941 ---------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2149.453 ; gain = 411.629 ; free physical = 845 ; free virtual = 70077 ---------------------------------------------------------------------------------- -WARNING: [Synth 8-11121] redeclaration of ANSI port 'read_vld' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:33] -WARNING: [Synth 8-11121] redeclaration of ANSI port 'dna_port' is not allowed [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:34] -INFO: [Synth 8-6157] synthesizing module 'system_wrapper' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13] -INFO: [Synth 8-6157] synthesizing module 'IOBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197] -INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:78197] -INFO: [Synth 8-6157] synthesizing module 'system' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318] -INFO: [Synth 8-6157] synthesizing module 'system_dna_port_read_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53] -INFO: [Synth 8-6157] synthesizing module 'dna_port_read' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23] -INFO: [Synth 8-6157] synthesizing module 'DNA_PORT' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264] - Parameter SIM_DNA_VALUE bound to: 57'b000000000000000000000000000000000000000000000000000000000 -INFO: [Synth 8-6155] done synthesizing module 'DNA_PORT' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:39264] -INFO: [Synth 8-6155] done synthesizing module 'dna_port_read' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/dna_port_read.v:23] -INFO: [Synth 8-6155] done synthesizing module 'system_dna_port_read_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_dna_port_read_0_0/synth/system_dna_port_read_0_0.v:53] -INFO: [Synth 8-6157] synthesizing module 'system_mydna_read_v1_0_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53] -INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4] - Parameter C_S00_AXI_DATA_WIDTH bound to: 32 - type: integer - Parameter C_S00_AXI_ADDR_WIDTH bound to: 4 - type: integer -INFO: [Synth 8-6157] synthesizing module 'mydna_read_v1_0_S00_AXI' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4] - Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer - Parameter C_S_AXI_ADDR_WIDTH bound to: 4 - type: integer -INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:235] -INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:379] -INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0_S00_AXI' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:4] -INFO: [Synth 8-6155] done synthesizing module 'mydna_read_v1_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0.v:4] -INFO: [Synth 8-6155] done synthesizing module 'system_mydna_read_v1_0_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_mydna_read_v1_0_0_0/synth/system_mydna_read_v1_0_0_0.v:53] -INFO: [Synth 8-6157] synthesizing module 'system_processing_system7_0_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53] -INFO: [Synth 8-6157] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152] -INFO: [Synth 8-6157] synthesizing module 'BUFG' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951] -INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951] -INFO: [Synth 8-6157] synthesizing module 'BIBUF' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598] -INFO: [Synth 8-6155] done synthesizing module 'BIBUF' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1598] -INFO: [Synth 8-6157] synthesizing module 'PS7' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859] -INFO: [Synth 8-6155] done synthesizing module 'PS7' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111859] -INFO: [Synth 8-6155] done synthesizing module 'processing_system7_v5_5_processing_system7' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:152] -WARNING: [Synth 8-7071] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7071] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7071] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7071] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7071] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7071] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7071] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7071] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7071] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7071] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7071] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7071] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7071] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -WARNING: [Synth 8-7023] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:323] -INFO: [Synth 8-6155] done synthesizing module 'system_processing_system7_0_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/synth/system_processing_system7_0_0.v:53] -INFO: [Synth 8-6157] synthesizing module 'system_ps7_0_axi_periph_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632] -INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_11SE3QO' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13] -INFO: [Synth 8-6157] synthesizing module 'system_auto_pc_0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_incr_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3216] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wrap_cmd' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2982] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_cmd_translator' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3720] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392] -INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3446] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3392] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_aw_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4360] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_b_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3906] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546] -INFO: [Synth 8-226] default block is never used [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3608] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3546] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_ar_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4516] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] -INFO: [Synth 8-6157] synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_simple_fifo__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:2852] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s_r_channel' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4155] -INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] -INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] -INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] -INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] -INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] -INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized2' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] -WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'SI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871] -WARNING: [Synth 8-7023] instance 'SI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4871] -INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] -INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] -INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_axi2vector__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:59] -INFO: [Synth 8-6157] synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] -INFO: [Synth 8-6155] done synthesizing module 'axi_infrastructure_v1_1_0_vector2axi__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v:473] -INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized3' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized4' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized5' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6157] synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axic_register_slice__parameterized6' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1492] -INFO: [Synth 8-6155] done synthesizing module 'axi_register_slice_v2_1_29_axi_register_slice__parameterized0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:3718] -WARNING: [Synth 8-7071] port 'aclk2x' of module 'axi_register_slice_v2_1_29_axi_register_slice' is unconnected for instance 'MI_REG' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126] -WARNING: [Synth 8-7023] instance 'MI_REG' of module 'axi_register_slice_v2_1_29_axi_register_slice' has 93 connections declared, but only 92 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5126] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_b2s' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4704] -INFO: [Synth 8-6155] done synthesizing module 'axi_protocol_converter_v2_1_29_axi_protocol_converter' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:5285] -INFO: [Synth 8-6155] done synthesizing module 'system_auto_pc_0' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_auto_pc_0/synth/system_auto_pc_0.v:53] -INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_11SE3QO' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:13] -INFO: [Synth 8-6155] done synthesizing module 'system_ps7_0_axi_periph_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:632] -INFO: [Synth 8-638] synthesizing module 'system_rst_ps7_0_100M_1' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74] - Parameter C_FAMILY bound to: zynq - type: string - Parameter C_EXT_RST_WIDTH bound to: 4 - type: integer - Parameter C_AUX_RST_WIDTH bound to: 4 - type: integer - Parameter C_EXT_RESET_HIGH bound to: 1'b0 - Parameter C_AUX_RESET_HIGH bound to: 1'b0 - Parameter C_NUM_BUS_RST bound to: 1 - type: integer - Parameter C_NUM_PERP_RST bound to: 1 - type: integer - Parameter C_NUM_INTERCONNECT_ARESETN bound to: 1 - type: integer - Parameter C_NUM_PERP_ARESETN bound to: 1 - type: integer -INFO: [Synth 8-3491] module 'proc_sys_reset' declared at '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1271' bound to instance 'U0' of component 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:129] -INFO: [Synth 8-638] synthesizing module 'proc_sys_reset' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330] - Parameter INIT bound to: 1'b1 -INFO: [Synth 8-113] binding component instance 'FDRE_inst' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1399] - Parameter INIT bound to: 1'b1 -INFO: [Synth 8-113] binding component instance 'FDRE_BSR' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1415] - Parameter INIT bound to: 1'b0 -INFO: [Synth 8-113] binding component instance 'FDRE_BSR_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1441] - Parameter INIT bound to: 1'b1 -INFO: [Synth 8-113] binding component instance 'FDRE_PER' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1464] - Parameter INIT bound to: 1'b0 -INFO: [Synth 8-113] binding component instance 'FDRE_PER_N' to cell 'FDRE' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1488] -INFO: [Synth 8-638] synthesizing module 'lpf' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821] -INFO: [Synth 8-3491] module 'SRL16' declared at '/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721' bound to instance 'POR_SRL_I' of component 'SRL16' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:873] -INFO: [Synth 8-6157] synthesizing module 'SRL16' [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721] -INFO: [Synth 8-6155] done synthesizing module 'SRL16' (0#1) [/data/xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:133721] -INFO: [Synth 8-638] synthesizing module 'cdc_sync' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] - Parameter INIT bound to: 1'b0 -INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:514] - Parameter INIT bound to: 1'b0 -INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:545] - Parameter INIT bound to: 1'b0 -INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:554] - Parameter INIT bound to: 1'b0 -INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:564] - Parameter INIT bound to: 1'b0 -INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:574] - Parameter INIT bound to: 1'b0 -INFO: [Synth 8-113] binding component instance 'CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6' to cell 'FDR' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:584] -INFO: [Synth 8-256] done synthesizing module 'cdc_sync' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd:106] -INFO: [Synth 8-256] done synthesizing module 'lpf' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:821] -INFO: [Synth 8-638] synthesizing module 'sequence_psr' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304] -INFO: [Synth 8-638] synthesizing module 'upcnt_n' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126] -INFO: [Synth 8-256] done synthesizing module 'upcnt_n' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:126] -INFO: [Synth 8-256] done synthesizing module 'sequence_psr' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:304] -INFO: [Synth 8-256] done synthesizing module 'proc_sys_reset' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/408c/hdl/proc_sys_reset_v5_0_vh_rfs.vhd:1330] -INFO: [Synth 8-256] done synthesizing module 'system_rst_ps7_0_100M_1' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/synth/system_rst_ps7_0_100M_1.vhd:74] -WARNING: [Synth 8-7071] port 'mb_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622] -WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622] -WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'system_rst_ps7_0_100M_1' is unconnected for instance 'rst_ps7_0_100M' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622] -WARNING: [Synth 8-7023] instance 'rst_ps7_0_100M' of module 'system_rst_ps7_0_100M_1' has 10 connections declared, but only 7 given [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:622] -INFO: [Synth 8-6155] done synthesizing module 'system' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/synth/system.v:318] -INFO: [Synth 8-6155] done synthesizing module 'system_wrapper' (0#1) [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:13] -WARNING: [Synth 8-6014] Unused sequential element slv_reg1_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:228] -WARNING: [Synth 8-6014] Unused sequential element slv_reg2_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:229] -WARNING: [Synth 8-6014] Unused sequential element state_r1_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3596] -WARNING: [Synth 8-6014] Unused sequential element s_arlen_r_reg was removed. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/a63f/hdl/axi_protocol_converter_v2_1_vl_rfs.v:3597] -WARNING: [Synth 8-7129] Port prmry_aclk in module cdc_sync is either unconnected or has no load -WARNING: [Synth 8-7129] Port prmry_resetn in module cdc_sync is either unconnected or has no load -WARNING: [Synth 8-7129] Port prmry_vect_in[1] in module cdc_sync is either unconnected or has no load -WARNING: [Synth 8-7129] Port prmry_vect_in[0] in module cdc_sync is either unconnected or has no load -WARNING: [Synth 8-7129] Port scndry_resetn in module cdc_sync is either unconnected or has no load -WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load -WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized6 is either unconnected or has no load -WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load -WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized3 is either unconnected or has no load -WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load -WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized5 is either unconnected or has no load -WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load -WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized4 is either unconnected or has no load -WARNING: [Synth 8-7129] Port m_axi_bid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port m_axi_rid[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port m_axi_rlast in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_wid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_wlast in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arid[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arlen[7] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arlen[6] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arlen[5] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arlen[4] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arlen[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arlen[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arlen[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arlen[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arsize[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arsize[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arsize[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arburst[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arburst[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arlock[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arcache[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arcache[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arcache[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arcache[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arqos[3] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arqos[2] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arqos[1] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arqos[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port ACLK in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port ARESET in module axi_register_slice_v2_1_29_axic_register_slice__parameterized0 is either unconnected or has no load -WARNING: [Synth 8-7129] Port m_axi_buser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load -WARNING: [Synth 8-7129] Port m_axi_ruser[0] in module axi_infrastructure_v1_1_0_vector2axi is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_awuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_wuser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arregion[3] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arregion[2] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arregion[1] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_arregion[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_axi_aruser[0] in module axi_infrastructure_v1_1_0_axi2vector is either unconnected or has no load -WARNING: [Synth 8-7129] Port aclk2x in module axi_register_slice_v2_1_29_axi_register_slice is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_arlen[7] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_arlen[6] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_arlen[5] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_arlen[4] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_arlen[3] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load -WARNING: [Synth 8-7129] Port s_arlen[2] in module axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm is either unconnected or has no load -INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. ---------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 767 ; free virtual = 69885 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2356.422 ; gain = 618.598 ; free physical = 768 ; free virtual = 69891 ---------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2359.391 ; gain = 0.000 ; free physical = 749 ; free virtual = 69874 -INFO: [Netlist 29-17] Analyzing 46 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization - -Processing XDC Constraints -Initializing timing engine -Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst' -Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc] for cell 'system_i/processing_system7_0/inst' -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0' -Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1_board.xdc] for cell 'system_i/rst_ps7_0_100M/U0' -Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0' -Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc] for cell 'system_i/rst_ps7_0_100M/U0' -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ip/system_rst_ps7_0_100M_1/system_rst_ps7_0_100M_1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc] -Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_cons.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc] -Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc] -Finished Parsing XDC File [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc] -INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/system_wrapper_propImpl.xdc]. -Resolution: To avoid this warning, move constraints listed in [.Xil/system_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. -Completed Processing XDC Constraints - -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2518.867 ; gain = 0.000 ; free physical = 714 ; free virtual = 69858 -INFO: [Project 1-111] Unisim Transformation Summary: - A total of 46 instances were transformed. - FDR => FDRE: 12 instances - IOBUF => IOBUF (IBUF, OBUFT): 33 instances - SRL16 => SRL16E: 1 instance - -Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 872 ; free virtual = 69870 ---------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 946 ; free virtual = 69833 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Loading Part and Timing Information ---------------------------------------------------------------------------------- -Loading part: xc7z035ffg676-2 ---------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 945 ; free virtual = 69833 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying 'set_property' XDC Constraints ---------------------------------------------------------------------------------- -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 1). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_1. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 2). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_2. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 3). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_3. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 4). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_4. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 5). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_5. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 6). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_6. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 7). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_7. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 8). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_8. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 9). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_9. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 10). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_10. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 11). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_11. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 12). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_12. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 13). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_13. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 14). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_14. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 15). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_15. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 16). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_16. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 17). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_17. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 18). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_18. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 19). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_19. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 20). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_20. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 21). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_21. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 22). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_22. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 23). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_23. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 24). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_24. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 25). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_25. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 26). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_28. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 27). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_29. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 28). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_30. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 29). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_26. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 30). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_27. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 31). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_31. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 32). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_i_32. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 33). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_o_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 34). -Applied set_property MARK_DEBUG = true for EMIO_0_tri_t_0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/constrs_1/new/pin_debug.xdc, line 67). -Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0/inst. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 30). -Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M/U0. (constraint file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/dont_touch.xdc, line 35). -Applied set_property KEEP_HIERARCHY = SOFT for system_i. (constraint file auto generated constraint). -Applied set_property KEEP_HIERARCHY = SOFT for system_i/processing_system7_0. (constraint file auto generated constraint). -Applied set_property KEEP_HIERARCHY = SOFT for system_i/dna_port_read_0. (constraint file auto generated constraint). -Applied set_property KEEP_HIERARCHY = SOFT for system_i/mydna_read_v1_0_0. (constraint file auto generated constraint). -Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph/s00_couplers/auto_pc. (constraint file auto generated constraint). -Applied set_property KEEP_HIERARCHY = SOFT for system_i/ps7_0_axi_periph. (constraint file auto generated constraint). -Applied set_property KEEP_HIERARCHY = SOFT for system_i/rst_ps7_0_100M. (constraint file auto generated constraint). ---------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 940 ; free virtual = 69830 ---------------------------------------------------------------------------------- -INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' -INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_0'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:213] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_1'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:218] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_2'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:273] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_3'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:328] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_4'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:348] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_5'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:353] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_6'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:358] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_7'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:363] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_8'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:368] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_9'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:373] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_10'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:223] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_11'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:228] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_12'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:233] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_13'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:238] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_14'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:243] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_15'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:248] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_16'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:253] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_17'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:258] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_18'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:263] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_19'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:268] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_20'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:278] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_21'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:283] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_22'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:288] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_23'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:293] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_24'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:298] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_25'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:303] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_28'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:318] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_29'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:323] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_30'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:333] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_26'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:308] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_27'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:313] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_31'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:338] -INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'EMIO_0_tri_iobuf_32'. This will prevent further optimization [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/hdl/system_wrapper.v:343] -WARNING: [Synth 8-327] inferring latch for variable 'dna_port_reg_reg' [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.srcs/sources_1/src/mydna_read_v1_0_S00_AXI.v:413] ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- - SM_IDLE | 01 | 00 - SM_CMD_EN | 11 | 01 - SM_CMD_ACCEPTED | 10 | 10 - SM_DONE_WAIT | 00 | 11 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_wr_cmd_fsm' ---------------------------------------------------------------------------------------------------- - State | New Encoding | Previous Encoding ---------------------------------------------------------------------------------------------------- - SM_IDLE | 01 | 00 - SM_CMD_EN | 11 | 01 - SM_CMD_ACCEPTED | 10 | 10 - SM_DONE | 00 | 11 ---------------------------------------------------------------------------------------------------- -INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'axi_protocol_converter_v2_1_29_b2s_rd_cmd_fsm' ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 929 ; free virtual = 69825 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start RTL Component Statistics ---------------------------------------------------------------------------------- -Detailed RTL Component Info : -+---Adders : - 2 Input 12 Bit Adders := 8 - 2 Input 9 Bit Adders := 2 - 2 Input 8 Bit Adders := 2 - 2 Input 6 Bit Adders := 1 - 2 Input 5 Bit Adders := 4 - 2 Input 4 Bit Adders := 4 - 2 Input 2 Bit Adders := 2 -+---Registers : - 66 Bit Registers := 4 - 57 Bit Registers := 1 - 47 Bit Registers := 2 - 32 Bit Registers := 3 - 14 Bit Registers := 2 - 12 Bit Registers := 9 - 9 Bit Registers := 2 - 8 Bit Registers := 3 - 6 Bit Registers := 1 - 5 Bit Registers := 4 - 4 Bit Registers := 8 - 3 Bit Registers := 3 - 2 Bit Registers := 9 - 1 Bit Registers := 43 -+---Muxes : - 2 Input 66 Bit Muxes := 4 - 2 Input 47 Bit Muxes := 2 - 4 Input 32 Bit Muxes := 3 - 2 Input 32 Bit Muxes := 9 - 2 Input 14 Bit Muxes := 2 - 2 Input 12 Bit Muxes := 6 - 2 Input 9 Bit Muxes := 4 - 2 Input 8 Bit Muxes := 1 - 2 Input 6 Bit Muxes := 1 - 2 Input 5 Bit Muxes := 4 - 2 Input 4 Bit Muxes := 18 - 2 Input 2 Bit Muxes := 17 - 4 Input 2 Bit Muxes := 4 - 2 Input 1 Bit Muxes := 37 ---------------------------------------------------------------------------------- -Finished RTL Component Statistics ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Part Resource Summary ---------------------------------------------------------------------------------- -Part Resources: -DSPs: 900 (col length:140) -BRAMs: 1000 (col length: RAMB18 140 RAMB36 70) ---------------------------------------------------------------------------------- -Finished Part Resource Summary ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Cross Boundary and Area Optimization ---------------------------------------------------------------------------------- -WARNING: [Synth 8-7080] Parallel synthesis criteria is not met -INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] -INFO: [Synth 8-3936] Found unconnected internal register 'inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_payload_i_reg' and it is trimmed from '66' to '62' bits. [/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.gen/sources_1/bd/system/ipshared/ff9f/hdl/axi_register_slice_v2_1_vl_rfs.v:1726] -WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset. -WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset. -WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to) is unused and will be removed from module proc_sys_reset. -WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2) is unused and will be removed from module proc_sys_reset. -WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3) is unused and will be removed from module proc_sys_reset. -WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4) is unused and will be removed from module proc_sys_reset. -WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d5) is unused and will be removed from module proc_sys_reset. -WARNING: [Synth 8-3332] Sequential element (EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d6) is unused and will be removed from module proc_sys_reset. -WARNING: [Synth 8-3332] Sequential element (FDRE_inst) is unused and will be removed from module proc_sys_reset. -WARNING: [Synth 8-3332] Sequential element (BSR_OUT_DFF[0].FDRE_BSR) is unused and will be removed from module proc_sys_reset. -WARNING: [Synth 8-3332] Sequential element (ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N) is unused and will be removed from module proc_sys_reset. -WARNING: [Synth 8-3332] Sequential element (PR_OUT_DFF[0].FDRE_PER) is unused and will be removed from module proc_sys_reset. ---------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1838 ; free virtual = 70743 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Applying XDC Timing Constraints ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1815 ; free virtual = 70747 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Timing Optimization ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1781 ; free virtual = 70713 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Technology Mapping ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1765 ; free virtual = 70711 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Flattening Before IO Insertion ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Final Netlist Cleanup ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Instances ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70517 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Rebuilding User Hierarchy ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Ports ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Handling Custom Attributes ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Renaming Generated Nets ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516 ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start ROM, RAM, DSP, Shift Register and Retiming Reporting ---------------------------------------------------------------------------------- - -Dynamic Shift Register Report: -+------------+----------------+--------+------------+--------+---------+--------+--------+--------+ -|Module Name | RTL Name | Length | Data Width | SRL16E | SRLC32E | Mux F7 | Mux F8 | Mux F9 | -+------------+----------------+--------+------------+--------+---------+--------+--------+--------+ -|dsrl | memory_reg[3] | 20 | 20 | 20 | 0 | 0 | 0 | 0 | -|dsrl__1 | memory_reg[3] | 2 | 2 | 2 | 0 | 0 | 0 | 0 | -|dsrl__2 | memory_reg[31] | 34 | 34 | 0 | 34 | 0 | 0 | 0 | -|dsrl__3 | memory_reg[31] | 13 | 13 | 0 | 13 | 0 | 0 | 0 | -+------------+----------------+--------+------------+--------+---------+--------+--------+--------+ - ---------------------------------------------------------------------------------- -Finished ROM, RAM, DSP, Shift Register and Retiming Reporting ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -Start Writing Synthesis Report ---------------------------------------------------------------------------------- - -Report BlackBoxes: -+-+--------------+----------+ -| |BlackBox name |Instances | -+-+--------------+----------+ -+-+--------------+----------+ - -Report Cell Usage: -+------+---------+------+ -| |Cell |Count | -+------+---------+------+ -|1 |BIBUF | 130| -|2 |BUFG | 1| -|3 |CARRY4 | 6| -|4 |DNA_PORT | 1| -|5 |LUT1 | 69| -|6 |LUT2 | 24| -|7 |LUT3 | 169| -|8 |LUT4 | 52| -|9 |LUT5 | 71| -|10 |LUT6 | 118| -|11 |PS7 | 1| -|12 |SRL16 | 1| -|13 |SRL16E | 16| -|14 |SRLC32E | 45| -|15 |FDCE | 66| -|16 |FDR | 4| -|17 |FDRE | 501| -|18 |FDSE | 20| -|19 |LD | 57| -|20 |IOBUF | 33| -+------+---------+------+ ---------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1541 ; free virtual = 70516 ---------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 136 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2518.902 ; gain = 618.598 ; free physical = 1531 ; free virtual = 70510 -Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2518.902 ; gain = 781.078 ; free physical = 1531 ; free virtual = 70509 -INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2518.902 ; gain = 0.000 ; free physical = 1748 ; free virtual = 70732 -INFO: [Netlist 29-17] Analyzing 101 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-570] Preparing netlist for logic optimization -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2563.766 ; gain = 0.000 ; free physical = 1757 ; free virtual = 70743 -INFO: [Project 1-111] Unisim Transformation Summary: - A total of 95 instances were transformed. - FDR => FDRE: 4 instances - IOBUF => IOBUF (IBUF, OBUFT): 33 instances - LD => LDCE: 57 instances - SRL16 => SRL16E: 1 instance - -Synth Design complete | Checksum: 8993d7c -INFO: [Common 17-83] Releasing license: Synthesis -187 Infos, 142 Warnings, 0 Critical Warnings and 0 Errors encountered. -synth_design completed successfully -synth_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2563.801 ; gain = 1259.379 ; free physical = 1759 ; free virtual = 70746 -INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1991.605; main = 1727.861; forked = 379.983 -INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3465.613; main = 2563.770; forked = 1042.766 -Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2611.777 ; gain = 0.000 ; free physical = 1758 ; free virtual = 70746 -INFO: [Common 17-1381] The checkpoint '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Debug_FW.runs/synth_1/system_wrapper.dcp' has been generated. -INFO: [runtcl-4] Executing : report_utilization -file system_wrapper_utilization_synth.rpt -pb system_wrapper_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Wed May 27 16:36:31 2026... diff --git a/Debug_FW.sdk/SDK.log b/Debug_FW.sdk/SDK.log deleted file mode 100644 index 17a161e..0000000 --- a/Debug_FW.sdk/SDK.log +++ /dev/null @@ -1,2262 +0,0 @@ -10:59:26 INFO : Registering command handlers for SDK TCF services -10:59:27 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -10:59:29 INFO : XSCT server has started successfully. -10:59:29 INFO : Successfully done setting XSCT server connection channel -10:59:29 INFO : Successfully done setting SDK workspace -10:59:29 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -11:18:50 INFO : Connected to target on host '127.0.0.1' and port '3121'. -11:18:50 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -11:18:50 INFO : 'jtag frequency' command is executed. -11:18:50 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -11:18:50 INFO : Context for 'APU' is selected. -11:18:50 INFO : System reset is completed. -11:18:53 INFO : 'after 3000' command is executed. -11:18:53 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -11:19:00 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -11:19:00 INFO : Context for 'APU' is selected. -11:19:00 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -11:19:00 INFO : 'configparams force-mem-access 1' command is executed. -11:19:01 INFO : Context for 'APU' is selected. -11:19:01 INFO : 'ps7_init' command is executed. -11:19:01 INFO : 'ps7_post_config' command is executed. -11:19:01 INFO : Context for processor 'ps7_cortexa9_0' is selected. -11:19:02 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -11:19:02 INFO : 'configparams force-mem-access 0' command is executed. -11:19:02 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -11:19:02 INFO : Memory regions updated for context APU -11:19:02 INFO : Context for processor 'ps7_cortexa9_0' is selected. -11:19:02 INFO : 'con' command is executed. -11:19:02 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -11:19:02 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -11:32:52 INFO : Disconnected from the channel tcfchan#1. -11:32:53 INFO : Connected to target on host '127.0.0.1' and port '3121'. -11:32:54 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -11:32:54 INFO : 'jtag frequency' command is executed. -11:32:54 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -11:32:54 INFO : Context for 'APU' is selected. -11:32:54 INFO : System reset is completed. -11:32:57 INFO : 'after 3000' command is executed. -11:32:57 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -11:33:04 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -11:33:04 INFO : Context for 'APU' is selected. -11:33:05 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -11:33:05 INFO : 'configparams force-mem-access 1' command is executed. -11:33:05 INFO : Context for 'APU' is selected. -11:33:05 INFO : 'ps7_init' command is executed. -11:33:05 INFO : 'ps7_post_config' command is executed. -11:33:05 INFO : Context for processor 'ps7_cortexa9_0' is selected. -11:33:06 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -11:33:06 INFO : 'configparams force-mem-access 0' command is executed. -11:33:06 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -11:33:06 INFO : Memory regions updated for context APU -11:33:06 INFO : Context for processor 'ps7_cortexa9_0' is selected. -11:33:06 INFO : 'con' command is executed. -11:33:06 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -11:33:06 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -11:46:31 INFO : Disconnected from the channel tcfchan#2. -11:46:32 INFO : Connected to target on host '127.0.0.1' and port '3121'. -11:46:33 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -11:46:33 INFO : 'jtag frequency' command is executed. -11:46:33 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -11:46:33 INFO : Context for 'APU' is selected. -11:46:33 INFO : System reset is completed. -11:46:36 INFO : 'after 3000' command is executed. -11:46:36 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -11:46:43 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -11:46:43 INFO : Context for 'APU' is selected. -11:46:44 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -11:46:44 INFO : 'configparams force-mem-access 1' command is executed. -11:46:44 INFO : Context for 'APU' is selected. -11:46:44 INFO : 'ps7_init' command is executed. -11:46:44 INFO : 'ps7_post_config' command is executed. -11:46:44 INFO : Context for processor 'ps7_cortexa9_0' is selected. -11:46:45 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -11:46:45 INFO : 'configparams force-mem-access 0' command is executed. -11:46:45 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -11:46:45 INFO : Memory regions updated for context APU -11:46:45 INFO : Context for processor 'ps7_cortexa9_0' is selected. -11:46:45 INFO : 'con' command is executed. -11:46:45 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -11:46:45 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -14:12:21 INFO : Disconnected from the channel tcfchan#3. -14:12:22 INFO : Connected to target on host '127.0.0.1' and port '3121'. -14:12:22 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -14:12:22 INFO : 'jtag frequency' command is executed. -14:12:22 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -14:12:22 INFO : Context for 'APU' is selected. -14:12:22 INFO : System reset is completed. -14:12:25 INFO : 'after 3000' command is executed. -14:12:25 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -14:12:32 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -14:12:32 INFO : Context for 'APU' is selected. -14:12:34 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -14:12:34 INFO : 'configparams force-mem-access 1' command is executed. -14:12:34 INFO : Context for 'APU' is selected. -14:12:34 INFO : 'ps7_init' command is executed. -14:12:34 INFO : 'ps7_post_config' command is executed. -14:12:34 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:12:35 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -14:12:35 INFO : 'configparams force-mem-access 0' command is executed. -14:12:35 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -14:12:35 INFO : Memory regions updated for context APU -14:12:35 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:12:35 INFO : 'con' command is executed. -14:12:35 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -14:12:35 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -14:17:02 INFO : Disconnected from the channel tcfchan#4. -14:17:03 INFO : Connected to target on host '127.0.0.1' and port '3121'. -14:17:03 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -14:17:03 INFO : 'jtag frequency' command is executed. -14:17:03 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -14:17:03 INFO : Context for 'APU' is selected. -14:17:03 INFO : System reset is completed. -14:17:06 INFO : 'after 3000' command is executed. -14:17:06 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -14:17:13 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -14:17:13 INFO : Context for 'APU' is selected. -14:17:14 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -14:17:14 INFO : 'configparams force-mem-access 1' command is executed. -14:17:15 INFO : Context for 'APU' is selected. -14:17:15 INFO : 'ps7_init' command is executed. -14:17:15 INFO : 'ps7_post_config' command is executed. -14:17:15 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:17:16 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -14:17:16 INFO : 'configparams force-mem-access 0' command is executed. -14:17:16 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -14:17:16 INFO : Memory regions updated for context APU -14:17:16 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:17:16 INFO : 'con' command is executed. -14:17:16 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -14:17:16 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -14:17:31 INFO : Disconnected from the channel tcfchan#5. -14:17:32 INFO : Connected to target on host '127.0.0.1' and port '3121'. -14:17:32 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -14:17:32 INFO : 'jtag frequency' command is executed. -14:17:32 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -14:17:32 INFO : Context for 'APU' is selected. -14:17:32 INFO : System reset is completed. -14:17:35 INFO : 'after 3000' command is executed. -14:17:35 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -14:17:42 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -14:17:42 INFO : Context for 'APU' is selected. -14:17:43 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -14:17:43 INFO : 'configparams force-mem-access 1' command is executed. -14:17:43 INFO : Context for 'APU' is selected. -14:17:44 INFO : 'ps7_init' command is executed. -14:17:44 INFO : 'ps7_post_config' command is executed. -14:17:44 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:17:44 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -14:17:44 INFO : 'configparams force-mem-access 0' command is executed. -14:17:44 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -14:17:44 INFO : Memory regions updated for context APU -14:17:44 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:17:44 INFO : 'con' command is executed. -14:17:44 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -14:17:44 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -14:32:13 INFO : Disconnected from the channel tcfchan#6. -14:32:14 INFO : Connected to target on host '127.0.0.1' and port '3121'. -14:32:14 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -14:32:14 INFO : 'jtag frequency' command is executed. -14:32:14 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -14:32:14 INFO : Context for 'APU' is selected. -14:32:14 INFO : System reset is completed. -14:32:17 INFO : 'after 3000' command is executed. -14:32:17 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -14:32:24 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -14:32:24 INFO : Context for 'APU' is selected. -14:32:25 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -14:32:25 INFO : 'configparams force-mem-access 1' command is executed. -14:32:25 INFO : Context for 'APU' is selected. -14:32:25 INFO : 'ps7_init' command is executed. -14:32:25 INFO : 'ps7_post_config' command is executed. -14:32:26 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:32:26 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -14:32:26 INFO : 'configparams force-mem-access 0' command is executed. -14:32:26 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -14:32:26 INFO : Memory regions updated for context APU -14:32:26 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:32:26 INFO : 'con' command is executed. -14:32:26 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -14:32:26 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -15:08:59 INFO : Disconnected from the channel tcfchan#7. -15:09:00 INFO : Connected to target on host '127.0.0.1' and port '3121'. -15:09:00 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -15:09:00 INFO : 'jtag frequency' command is executed. -15:09:00 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -15:09:00 INFO : Context for 'APU' is selected. -15:09:00 INFO : System reset is completed. -15:09:03 INFO : 'after 3000' command is executed. -15:09:03 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -15:09:10 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -15:09:10 INFO : Context for 'APU' is selected. -15:09:11 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -15:09:11 INFO : 'configparams force-mem-access 1' command is executed. -15:09:11 INFO : Context for 'APU' is selected. -15:09:12 INFO : 'ps7_init' command is executed. -15:09:12 INFO : 'ps7_post_config' command is executed. -15:09:12 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:09:12 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -15:09:12 INFO : 'configparams force-mem-access 0' command is executed. -15:09:12 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -15:09:12 INFO : Memory regions updated for context APU -15:09:12 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:09:12 INFO : 'con' command is executed. -15:09:12 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -15:09:12 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -15:27:54 INFO : Disconnected from the channel tcfchan#8. -15:27:55 INFO : Connected to target on host '127.0.0.1' and port '3121'. -15:27:55 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -15:27:55 INFO : 'jtag frequency' command is executed. -15:27:55 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -15:27:55 INFO : Context for 'APU' is selected. -15:27:55 INFO : System reset is completed. -15:27:58 INFO : 'after 3000' command is executed. -15:27:58 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -15:28:05 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -15:28:05 INFO : Context for 'APU' is selected. -15:28:06 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -15:28:06 INFO : 'configparams force-mem-access 1' command is executed. -15:28:06 INFO : Context for 'APU' is selected. -15:28:07 INFO : 'ps7_init' command is executed. -15:28:07 INFO : 'ps7_post_config' command is executed. -15:28:07 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:28:07 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -15:28:07 INFO : 'configparams force-mem-access 0' command is executed. -15:28:07 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -15:28:07 INFO : Memory regions updated for context APU -15:28:07 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:28:08 INFO : 'con' command is executed. -15:28:08 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -15:28:08 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -15:49:07 INFO : Disconnected from the channel tcfchan#9. -15:49:08 INFO : Connected to target on host '127.0.0.1' and port '3121'. -15:49:08 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -15:49:08 INFO : 'jtag frequency' command is executed. -15:49:08 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -15:49:09 INFO : Context for 'APU' is selected. -15:49:09 INFO : System reset is completed. -15:49:12 INFO : 'after 3000' command is executed. -15:49:12 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -15:49:19 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -15:49:19 INFO : Context for 'APU' is selected. -15:49:20 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -15:49:20 INFO : 'configparams force-mem-access 1' command is executed. -15:49:20 INFO : Context for 'APU' is selected. -15:49:20 INFO : 'ps7_init' command is executed. -15:49:20 INFO : 'ps7_post_config' command is executed. -15:49:20 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:49:21 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -15:49:21 INFO : 'configparams force-mem-access 0' command is executed. -15:49:21 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -15:49:21 INFO : Memory regions updated for context APU -15:49:21 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:49:21 INFO : 'con' command is executed. -15:49:21 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -15:49:21 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -16:00:32 INFO : Disconnected from the channel tcfchan#10. -16:00:33 INFO : Connected to target on host '127.0.0.1' and port '3121'. -16:00:33 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -16:00:33 INFO : 'jtag frequency' command is executed. -16:00:33 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -16:00:33 INFO : Context for 'APU' is selected. -16:00:33 INFO : System reset is completed. -16:00:36 INFO : 'after 3000' command is executed. -16:00:36 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -16:00:43 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -16:00:43 INFO : Context for 'APU' is selected. -16:00:45 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -16:00:45 INFO : 'configparams force-mem-access 1' command is executed. -16:00:45 INFO : Context for 'APU' is selected. -16:00:45 INFO : 'ps7_init' command is executed. -16:00:45 INFO : 'ps7_post_config' command is executed. -16:00:45 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:00:46 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -16:00:46 INFO : 'configparams force-mem-access 0' command is executed. -16:00:46 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -16:00:46 INFO : Memory regions updated for context APU -16:00:46 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:00:46 INFO : 'con' command is executed. -16:00:46 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -16:00:46 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -16:04:57 INFO : Disconnected from the channel tcfchan#11. -16:04:58 INFO : Connected to target on host '127.0.0.1' and port '3121'. -16:04:58 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -16:04:58 INFO : 'jtag frequency' command is executed. -16:04:58 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -16:04:58 INFO : Context for 'APU' is selected. -16:04:58 INFO : System reset is completed. -16:05:01 INFO : 'after 3000' command is executed. -16:05:01 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -16:05:08 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -16:05:08 INFO : Context for 'APU' is selected. -16:05:09 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -16:05:09 INFO : 'configparams force-mem-access 1' command is executed. -16:05:10 INFO : Context for 'APU' is selected. -16:05:10 INFO : 'ps7_init' command is executed. -16:05:10 INFO : 'ps7_post_config' command is executed. -16:05:10 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:05:11 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -16:05:11 INFO : 'configparams force-mem-access 0' command is executed. -16:05:11 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -16:05:11 INFO : Memory regions updated for context APU -16:05:11 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:05:11 INFO : 'con' command is executed. -16:05:11 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -16:05:11 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -16:07:15 INFO : Disconnected from the channel tcfchan#12. -16:07:16 INFO : Connected to target on host '127.0.0.1' and port '3121'. -16:07:16 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -16:07:16 INFO : 'jtag frequency' command is executed. -16:07:16 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -16:07:16 INFO : Context for 'APU' is selected. -16:07:16 INFO : System reset is completed. -16:07:19 INFO : 'after 3000' command is executed. -16:07:19 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -16:07:26 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -16:07:26 INFO : Context for 'APU' is selected. -16:07:28 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -16:07:28 INFO : 'configparams force-mem-access 1' command is executed. -16:07:28 INFO : Context for 'APU' is selected. -16:07:28 INFO : 'ps7_init' command is executed. -16:07:28 INFO : 'ps7_post_config' command is executed. -16:07:28 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:07:29 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -16:07:29 INFO : 'configparams force-mem-access 0' command is executed. -16:07:29 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -16:07:29 INFO : Memory regions updated for context APU -16:07:29 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:07:29 INFO : 'con' command is executed. -16:07:29 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -16:07:29 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -16:19:25 INFO : Disconnected from the channel tcfchan#13. -16:19:26 INFO : Connected to target on host '127.0.0.1' and port '3121'. -16:19:26 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -16:19:26 INFO : 'jtag frequency' command is executed. -16:19:26 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -16:19:26 INFO : Context for 'APU' is selected. -16:19:26 INFO : System reset is completed. -16:19:29 INFO : 'after 3000' command is executed. -16:19:29 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -16:19:36 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -16:19:36 INFO : Context for 'APU' is selected. -16:19:37 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -16:19:37 INFO : 'configparams force-mem-access 1' command is executed. -16:19:37 INFO : Context for 'APU' is selected. -16:19:38 INFO : 'ps7_init' command is executed. -16:19:38 INFO : 'ps7_post_config' command is executed. -16:19:38 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:19:38 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -16:19:38 INFO : 'configparams force-mem-access 0' command is executed. -16:19:38 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -16:19:38 INFO : Memory regions updated for context APU -16:19:38 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:19:38 INFO : 'con' command is executed. -16:19:38 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -16:19:38 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -16:29:43 INFO : Disconnected from the channel tcfchan#14. -16:29:44 INFO : Connected to target on host '127.0.0.1' and port '3121'. -16:29:44 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -16:29:44 INFO : 'jtag frequency' command is executed. -16:29:44 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -16:29:44 INFO : Context for 'APU' is selected. -16:29:44 INFO : System reset is completed. -16:29:47 INFO : 'after 3000' command is executed. -16:29:48 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -16:29:54 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -16:29:54 INFO : Context for 'APU' is selected. -16:29:56 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -16:29:56 INFO : 'configparams force-mem-access 1' command is executed. -16:29:56 INFO : Context for 'APU' is selected. -16:29:56 INFO : 'ps7_init' command is executed. -16:29:56 INFO : 'ps7_post_config' command is executed. -16:29:56 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:29:57 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -16:29:57 INFO : 'configparams force-mem-access 0' command is executed. -16:29:57 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -16:29:57 INFO : Memory regions updated for context APU -16:29:57 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:29:57 INFO : 'con' command is executed. -16:29:57 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -16:29:57 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -16:37:07 INFO : Disconnected from the channel tcfchan#15. -16:37:08 INFO : Connected to target on host '127.0.0.1' and port '3121'. -16:37:08 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -16:37:08 INFO : 'jtag frequency' command is executed. -16:37:08 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -16:37:08 INFO : Context for 'APU' is selected. -16:37:09 INFO : System reset is completed. -16:37:12 INFO : 'after 3000' command is executed. -16:37:12 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -16:37:19 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -16:37:19 INFO : Context for 'APU' is selected. -16:37:20 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -16:37:20 INFO : 'configparams force-mem-access 1' command is executed. -16:37:20 INFO : Context for 'APU' is selected. -16:37:20 INFO : 'ps7_init' command is executed. -16:37:20 INFO : 'ps7_post_config' command is executed. -16:37:20 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:37:21 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -16:37:21 INFO : 'configparams force-mem-access 0' command is executed. -16:37:21 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -16:37:21 INFO : Memory regions updated for context APU -16:37:21 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:37:21 INFO : 'con' command is executed. -16:37:21 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -16:37:21 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -16:48:56 INFO : Disconnected from the channel tcfchan#16. -16:48:57 INFO : Connected to target on host '127.0.0.1' and port '3121'. -16:48:57 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -16:48:57 INFO : 'jtag frequency' command is executed. -16:48:57 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -16:48:57 INFO : Context for 'APU' is selected. -16:48:57 INFO : System reset is completed. -16:49:00 INFO : 'after 3000' command is executed. -16:49:00 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -16:49:07 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -16:49:07 INFO : Context for 'APU' is selected. -16:49:08 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -16:49:08 INFO : 'configparams force-mem-access 1' command is executed. -16:49:08 INFO : Context for 'APU' is selected. -16:49:09 INFO : 'ps7_init' command is executed. -16:49:09 INFO : 'ps7_post_config' command is executed. -16:49:09 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:49:10 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -16:49:10 INFO : 'configparams force-mem-access 0' command is executed. -16:49:10 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -16:49:10 INFO : Memory regions updated for context APU -16:49:10 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:49:10 INFO : 'con' command is executed. -16:49:10 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -16:49:10 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -16:50:03 INFO : Disconnected from the channel tcfchan#17. -16:50:04 INFO : Connected to target on host '127.0.0.1' and port '3121'. -16:50:04 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -16:50:04 INFO : 'jtag frequency' command is executed. -16:50:04 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -16:50:04 INFO : Context for 'APU' is selected. -16:50:04 INFO : System reset is completed. -16:50:07 INFO : 'after 3000' command is executed. -16:50:07 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -16:50:14 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -16:50:14 INFO : Context for 'APU' is selected. -16:50:15 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -16:50:15 INFO : 'configparams force-mem-access 1' command is executed. -16:50:15 INFO : Context for 'APU' is selected. -16:50:16 INFO : 'ps7_init' command is executed. -16:50:16 INFO : 'ps7_post_config' command is executed. -16:50:16 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:50:16 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -16:50:16 INFO : 'configparams force-mem-access 0' command is executed. -16:50:16 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -16:50:16 INFO : Memory regions updated for context APU -16:50:16 INFO : Context for processor 'ps7_cortexa9_0' is selected. -16:50:16 INFO : 'con' command is executed. -16:50:16 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -16:50:16 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -17:30:21 INFO : Disconnected from the channel tcfchan#18. -17:30:22 INFO : Connected to target on host '127.0.0.1' and port '3121'. -17:30:22 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -17:30:22 INFO : 'jtag frequency' command is executed. -17:30:22 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -17:30:22 INFO : Context for 'APU' is selected. -17:30:22 INFO : System reset is completed. -17:30:25 INFO : 'after 3000' command is executed. -17:30:25 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -17:30:32 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -17:30:32 INFO : Context for 'APU' is selected. -17:30:33 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -17:30:33 INFO : 'configparams force-mem-access 1' command is executed. -17:30:33 INFO : Context for 'APU' is selected. -17:30:34 INFO : 'ps7_init' command is executed. -17:30:34 INFO : 'ps7_post_config' command is executed. -17:30:34 INFO : Context for processor 'ps7_cortexa9_0' is selected. -17:30:34 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -17:30:34 INFO : 'configparams force-mem-access 0' command is executed. -17:30:34 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -17:30:34 INFO : Memory regions updated for context APU -17:30:35 INFO : Context for processor 'ps7_cortexa9_0' is selected. -17:30:35 INFO : 'con' command is executed. -17:30:35 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -17:30:35 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -18:23:36 INFO : Disconnected from the channel tcfchan#19. -09:55:08 INFO : Registering command handlers for SDK TCF services -09:55:10 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -09:55:15 INFO : XSCT server has started successfully. -09:55:22 INFO : Successfully done setting XSCT server connection channel -09:55:22 INFO : Successfully done setting SDK workspace -09:55:22 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -09:55:22 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -10:02:14 INFO : Connected to target on host '127.0.0.1' and port '3121'. -10:02:16 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -10:02:16 INFO : 'jtag frequency' command is executed. -10:02:16 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -10:02:16 INFO : Context for 'APU' is selected. -10:02:16 INFO : System reset is completed. -10:02:19 INFO : 'after 3000' command is executed. -10:02:19 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -10:02:26 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -10:02:26 INFO : Context for 'APU' is selected. -10:02:26 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -10:02:26 INFO : 'configparams force-mem-access 1' command is executed. -10:02:26 INFO : Context for 'APU' is selected. -10:02:26 INFO : 'ps7_init' command is executed. -10:02:26 INFO : 'ps7_post_config' command is executed. -10:02:27 INFO : Context for processor 'ps7_cortexa9_0' is selected. -10:02:27 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -10:02:27 INFO : 'configparams force-mem-access 0' command is executed. -10:02:27 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -10:02:27 INFO : Memory regions updated for context APU -10:02:27 INFO : Context for processor 'ps7_cortexa9_0' is selected. -10:02:27 INFO : 'con' command is executed. -10:02:27 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -10:02:27 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -10:46:16 INFO : Disconnected from the channel tcfchan#1. -10:46:17 INFO : Connected to target on host '127.0.0.1' and port '3121'. -10:46:18 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -10:46:18 INFO : 'jtag frequency' command is executed. -10:46:18 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -10:46:18 INFO : Context for 'APU' is selected. -10:46:18 INFO : System reset is completed. -10:46:21 INFO : 'after 3000' command is executed. -10:46:21 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -10:46:28 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -10:46:28 INFO : Context for 'APU' is selected. -10:46:29 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -10:46:29 INFO : 'configparams force-mem-access 1' command is executed. -10:46:29 INFO : Context for 'APU' is selected. -10:46:29 INFO : 'ps7_init' command is executed. -10:46:29 INFO : 'ps7_post_config' command is executed. -10:46:29 INFO : Context for processor 'ps7_cortexa9_0' is selected. -10:46:30 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -10:46:30 INFO : 'configparams force-mem-access 0' command is executed. -10:46:30 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -10:46:30 INFO : Memory regions updated for context APU -10:46:30 INFO : Context for processor 'ps7_cortexa9_0' is selected. -10:46:30 INFO : 'con' command is executed. -10:46:30 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -10:46:30 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -10:49:28 INFO : Disconnected from the channel tcfchan#2. -10:49:29 INFO : Connected to target on host '127.0.0.1' and port '3121'. -10:49:29 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -10:49:29 INFO : 'jtag frequency' command is executed. -10:49:29 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -10:49:29 INFO : Context for 'APU' is selected. -10:49:29 INFO : System reset is completed. -10:49:32 INFO : 'after 3000' command is executed. -10:49:32 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -10:49:39 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -10:49:39 INFO : Context for 'APU' is selected. -10:49:41 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -10:49:41 INFO : 'configparams force-mem-access 1' command is executed. -10:49:41 INFO : Context for 'APU' is selected. -10:49:41 INFO : 'ps7_init' command is executed. -10:49:41 INFO : 'ps7_post_config' command is executed. -10:49:41 INFO : Context for processor 'ps7_cortexa9_0' is selected. -10:49:42 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -10:49:42 INFO : 'configparams force-mem-access 0' command is executed. -10:49:42 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -10:49:42 INFO : Memory regions updated for context APU -10:49:42 INFO : Context for processor 'ps7_cortexa9_0' is selected. -10:49:42 INFO : 'con' command is executed. -10:49:42 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -10:49:42 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -10:55:20 INFO : Disconnected from the channel tcfchan#3. -10:55:21 INFO : Connected to target on host '127.0.0.1' and port '3121'. -10:55:21 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -10:55:21 INFO : 'jtag frequency' command is executed. -10:55:21 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -10:55:21 INFO : Context for 'APU' is selected. -10:55:21 INFO : System reset is completed. -10:55:24 INFO : 'after 3000' command is executed. -10:55:24 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -10:55:27 ERROR : 'fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit' is cancelled. -10:55:27 INFO : Issued abort command to xsdb. -10:55:27 ERROR : Exception occured while running Program FPGA. -java.lang.RuntimeException: 'fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit' is cancelled. -10:55:27 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -----------------End of Script---------------- - -10:55:49 INFO : Connected to target on host '127.0.0.1' and port '3121'. -10:55:49 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -10:55:49 INFO : 'jtag frequency' command is executed. -10:55:49 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -10:55:49 INFO : Context for 'APU' is selected. -10:55:50 INFO : System reset is completed. -10:55:53 INFO : 'after 3000' command is executed. -10:55:53 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -10:56:00 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -10:56:00 INFO : Context for 'APU' is selected. -10:56:01 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -10:56:01 INFO : 'configparams force-mem-access 1' command is executed. -10:56:01 INFO : Context for 'APU' is selected. -10:56:01 INFO : 'ps7_init' command is executed. -10:56:01 INFO : 'ps7_post_config' command is executed. -10:56:01 INFO : Context for processor 'ps7_cortexa9_0' is selected. -10:56:02 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -10:56:02 INFO : 'configparams force-mem-access 0' command is executed. -10:56:02 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -10:56:02 INFO : Memory regions updated for context APU -10:56:02 INFO : Context for processor 'ps7_cortexa9_0' is selected. -10:56:02 INFO : 'con' command is executed. -10:56:02 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -10:56:02 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -11:07:45 INFO : Disconnected from the channel tcfchan#4. -11:07:46 INFO : Connected to target on host '127.0.0.1' and port '3121'. -11:07:47 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -11:07:47 INFO : 'jtag frequency' command is executed. -11:07:47 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -11:07:47 INFO : Context for 'APU' is selected. -11:07:47 INFO : System reset is completed. -11:07:50 INFO : 'after 3000' command is executed. -11:07:50 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -11:07:57 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -11:07:57 INFO : Context for 'APU' is selected. -11:07:58 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -11:07:58 INFO : 'configparams force-mem-access 1' command is executed. -11:07:58 INFO : Context for 'APU' is selected. -11:07:58 INFO : 'ps7_init' command is executed. -11:07:58 INFO : 'ps7_post_config' command is executed. -11:07:58 INFO : Context for processor 'ps7_cortexa9_0' is selected. -11:07:59 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -11:07:59 INFO : 'configparams force-mem-access 0' command is executed. -11:07:59 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -11:07:59 INFO : Memory regions updated for context APU -11:07:59 INFO : Context for processor 'ps7_cortexa9_0' is selected. -11:07:59 INFO : 'con' command is executed. -11:07:59 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -11:07:59 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -14:45:09 INFO : Disconnected from the channel tcfchan#5. -14:45:10 INFO : Connected to target on host '127.0.0.1' and port '3121'. -14:45:10 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -14:45:10 INFO : 'jtag frequency' command is executed. -14:45:10 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -14:45:10 INFO : Context for 'APU' is selected. -14:45:10 INFO : System reset is completed. -14:45:13 INFO : 'after 3000' command is executed. -14:45:13 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -14:45:20 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -14:45:20 INFO : Context for 'APU' is selected. -14:45:22 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -14:45:22 INFO : 'configparams force-mem-access 1' command is executed. -14:45:22 INFO : Context for 'APU' is selected. -14:45:22 INFO : 'ps7_init' command is executed. -14:45:22 INFO : 'ps7_post_config' command is executed. -14:45:22 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:45:23 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -14:45:23 INFO : 'configparams force-mem-access 0' command is executed. -14:45:23 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -14:45:23 INFO : Memory regions updated for context APU -14:45:23 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:45:23 INFO : 'con' command is executed. -14:45:23 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -14:45:23 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -14:51:01 INFO : Disconnected from the channel tcfchan#6. -14:51:02 INFO : Connected to target on host '127.0.0.1' and port '3121'. -14:51:03 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -14:51:03 INFO : 'jtag frequency' command is executed. -14:51:03 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -14:51:03 INFO : Context for 'APU' is selected. -14:51:03 INFO : System reset is completed. -14:51:06 INFO : 'after 3000' command is executed. -14:51:06 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -14:51:13 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -14:51:13 INFO : Context for 'APU' is selected. -14:51:14 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -14:51:14 INFO : 'configparams force-mem-access 1' command is executed. -14:51:14 INFO : Context for 'APU' is selected. -14:51:15 INFO : 'ps7_init' command is executed. -14:51:15 INFO : 'ps7_post_config' command is executed. -14:51:15 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:51:15 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -14:51:15 INFO : 'configparams force-mem-access 0' command is executed. -14:51:15 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -14:51:15 INFO : Memory regions updated for context APU -14:51:15 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:51:15 INFO : 'con' command is executed. -14:51:15 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -14:51:15 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -15:03:32 INFO : Disconnected from the channel tcfchan#7. -15:03:33 INFO : Connected to target on host '127.0.0.1' and port '3121'. -15:03:33 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -15:03:33 INFO : 'jtag frequency' command is executed. -15:03:33 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -15:03:33 INFO : Context for 'APU' is selected. -15:03:33 INFO : System reset is completed. -15:03:36 INFO : 'after 3000' command is executed. -15:03:36 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -15:03:43 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -15:03:43 INFO : Context for 'APU' is selected. -15:03:44 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -15:03:44 INFO : 'configparams force-mem-access 1' command is executed. -15:03:44 INFO : Context for 'APU' is selected. -15:03:45 INFO : 'ps7_init' command is executed. -15:03:45 INFO : 'ps7_post_config' command is executed. -15:03:45 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:03:45 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -15:03:45 INFO : 'configparams force-mem-access 0' command is executed. -15:03:45 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -15:03:45 INFO : Memory regions updated for context APU -15:03:46 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:03:46 INFO : 'con' command is executed. -15:03:46 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -15:03:46 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -15:08:15 INFO : Disconnected from the channel tcfchan#8. -15:08:16 INFO : Connected to target on host '127.0.0.1' and port '3121'. -15:08:16 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -15:08:16 INFO : 'jtag frequency' command is executed. -15:08:16 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -15:08:16 INFO : Context for 'APU' is selected. -15:08:17 INFO : System reset is completed. -15:08:20 INFO : 'after 3000' command is executed. -15:08:20 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -15:08:27 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -15:08:27 INFO : Context for 'APU' is selected. -15:08:28 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -15:08:28 INFO : 'configparams force-mem-access 1' command is executed. -15:08:28 INFO : Context for 'APU' is selected. -15:08:28 INFO : 'ps7_init' command is executed. -15:08:28 INFO : 'ps7_post_config' command is executed. -15:08:28 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:08:29 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -15:08:29 INFO : 'configparams force-mem-access 0' command is executed. -15:08:29 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -15:08:29 INFO : Memory regions updated for context APU -15:08:29 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:08:29 INFO : 'con' command is executed. -15:08:29 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -15:08:29 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -15:25:30 INFO : Disconnected from the channel tcfchan#9. -15:25:31 INFO : Connected to target on host '127.0.0.1' and port '3121'. -15:25:31 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -15:25:31 INFO : 'jtag frequency' command is executed. -15:25:31 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -15:25:31 INFO : Context for 'APU' is selected. -15:25:31 INFO : System reset is completed. -15:25:34 INFO : 'after 3000' command is executed. -15:25:34 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -15:25:41 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -15:25:41 INFO : Context for 'APU' is selected. -15:25:43 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -15:25:43 INFO : 'configparams force-mem-access 1' command is executed. -15:25:43 INFO : Context for 'APU' is selected. -15:25:43 INFO : 'ps7_init' command is executed. -15:25:43 INFO : 'ps7_post_config' command is executed. -15:25:43 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:25:44 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -15:25:44 INFO : 'configparams force-mem-access 0' command is executed. -15:25:44 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -15:25:44 INFO : Memory regions updated for context APU -15:25:44 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:25:44 INFO : 'con' command is executed. -15:25:44 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -15:25:44 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -18:18:17 INFO : Disconnected from the channel tcfchan#10. -10:09:48 INFO : Registering command handlers for SDK TCF services -10:09:49 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -10:09:52 INFO : XSCT server has started successfully. -10:09:56 INFO : Successfully done setting XSCT server connection channel -10:09:56 INFO : Successfully done setting SDK workspace -10:09:56 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -10:09:56 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -11:27:58 INFO : Registering command handlers for SDK TCF services -11:27:59 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -11:28:01 INFO : XSCT server has started successfully. -11:28:01 INFO : Successfully done setting XSCT server connection channel -11:28:01 INFO : Successfully done setting SDK workspace -11:28:01 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -11:28:01 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -14:22:45 INFO : Connected to target on host '127.0.0.1' and port '3121'. -14:22:46 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -14:22:46 INFO : 'jtag frequency' command is executed. -14:22:46 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -14:22:46 INFO : Context for 'APU' is selected. -14:22:46 INFO : System reset is completed. -14:22:49 INFO : 'after 3000' command is executed. -14:22:49 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -14:22:56 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -14:22:56 INFO : Context for 'APU' is selected. -14:22:56 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -14:22:56 INFO : 'configparams force-mem-access 1' command is executed. -14:22:56 INFO : Context for 'APU' is selected. -14:22:56 INFO : 'ps7_init' command is executed. -14:22:56 INFO : 'ps7_post_config' command is executed. -14:22:56 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:22:57 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -14:22:57 INFO : 'configparams force-mem-access 0' command is executed. -14:22:57 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -14:22:57 INFO : Memory regions updated for context APU -14:22:57 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:22:57 INFO : 'con' command is executed. -14:22:57 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -14:22:57 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -14:58:06 INFO : Disconnected from the channel tcfchan#1. -14:58:07 INFO : Connected to target on host '127.0.0.1' and port '3121'. -14:58:07 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -14:58:07 INFO : 'jtag frequency' command is executed. -14:58:07 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -14:58:07 INFO : Context for 'APU' is selected. -14:58:07 INFO : System reset is completed. -14:58:10 INFO : 'after 3000' command is executed. -14:58:10 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -14:58:17 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -14:58:17 INFO : Context for 'APU' is selected. -14:58:19 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -14:58:19 INFO : 'configparams force-mem-access 1' command is executed. -14:58:19 INFO : Context for 'APU' is selected. -14:58:19 INFO : 'ps7_init' command is executed. -14:58:19 INFO : 'ps7_post_config' command is executed. -14:58:19 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:58:20 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -14:58:20 INFO : 'configparams force-mem-access 0' command is executed. -14:58:20 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -14:58:20 INFO : Memory regions updated for context APU -14:58:20 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:58:20 INFO : 'con' command is executed. -14:58:20 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -14:58:20 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -18:18:05 INFO : Disconnected from the channel tcfchan#2. -11:22:29 INFO : Registering command handlers for SDK TCF services -11:22:31 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -11:22:35 INFO : XSCT server has started successfully. -11:22:35 INFO : Successfully done setting XSCT server connection channel -11:22:41 INFO : Successfully done setting SDK workspace -11:22:41 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -11:22:41 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -11:22:48 INFO : SDK has detected change in the last modified timestamps for source hardware specification file Source:1690773689986, Project:1689819746145 -11:22:48 INFO : The hardware specification for project 'system_wrapper_hw_platform_0' is different from G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -11:22:48 INFO : Copied contents of G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf into \system_wrapper_hw_platform_0\system.hdf. -11:22:51 INFO : Synchronizing projects in the workspace with the hardware platform specification changes. -11:23:05 INFO : -11:23:06 INFO : Updating hardware inferred compiler options for calboard. -11:23:06 INFO : Clearing existing target manager status. -11:32:04 INFO : Invoking Bootgen: bootgen -image calboard.bif -arch zynq -o G:\CALBOARD\z035_mars1k\debug_bin\bin_7.31\BOOT.bin -11:32:04 INFO : Creating new bif file G:\CALBOARD\z035_mars1k\debug_bin\bin_7.31\calboard.bif -11:32:06 INFO : Bootgen command execution is done. -13:59:55 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -13:59:57 INFO : XSCT server has started successfully. -13:59:57 INFO : Successfully done setting XSCT server connection channel -13:59:57 INFO : Successfully done setting SDK workspace -14:00:01 INFO : Registering command handlers for SDK TCF services -14:00:01 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -14:00:01 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -14:00:54 INFO : Connected to target on host '127.0.0.1' and port '3121'. -14:00:54 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -14:00:54 INFO : 'jtag frequency' command is executed. -14:00:54 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -14:00:54 INFO : Context for 'APU' is selected. -14:00:54 INFO : System reset is completed. -14:00:57 INFO : 'after 3000' command is executed. -14:00:58 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -14:01:04 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -14:01:05 INFO : Context for 'APU' is selected. -14:01:05 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -14:01:05 INFO : 'configparams force-mem-access 1' command is executed. -14:01:05 INFO : Context for 'APU' is selected. -14:01:05 INFO : 'ps7_init' command is executed. -14:01:05 INFO : 'ps7_post_config' command is executed. -14:01:05 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:01:06 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -14:01:06 INFO : 'configparams force-mem-access 0' command is executed. -14:01:06 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -14:01:06 INFO : Memory regions updated for context APU -14:01:06 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:01:06 INFO : 'con' command is executed. -14:01:06 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -14:01:06 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -14:30:05 INFO : Disconnected from the channel tcfchan#1. -14:30:24 INFO : Registering command handlers for SDK TCF services -14:30:24 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -14:30:26 INFO : XSCT server has started successfully. -14:30:26 INFO : Successfully done setting XSCT server connection channel -14:30:27 INFO : Successfully done setting SDK workspace -14:30:27 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -14:30:27 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -14:30:40 INFO : Connected to target on host '127.0.0.1' and port '3121'. -14:30:40 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -14:30:40 INFO : 'jtag frequency' command is executed. -14:30:40 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -14:30:40 INFO : Context for 'APU' is selected. -14:30:40 INFO : System reset is completed. -14:30:43 INFO : 'after 3000' command is executed. -14:30:43 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -14:30:50 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -14:30:50 INFO : Context for 'APU' is selected. -14:30:50 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -14:30:50 INFO : 'configparams force-mem-access 1' command is executed. -14:30:50 INFO : Context for 'APU' is selected. -14:30:51 INFO : 'ps7_init' command is executed. -14:30:51 INFO : 'ps7_post_config' command is executed. -14:30:51 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:30:51 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -14:30:51 INFO : 'configparams force-mem-access 0' command is executed. -14:30:51 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -14:30:51 INFO : Memory regions updated for context APU -14:30:51 INFO : Context for processor 'ps7_cortexa9_0' is selected. -14:30:51 INFO : 'con' command is executed. -14:30:51 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -14:30:51 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -15:35:51 INFO : Disconnected from the channel tcfchan#1. -15:35:52 INFO : Connected to target on host '127.0.0.1' and port '3121'. -15:35:52 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -15:35:52 INFO : 'jtag frequency' command is executed. -15:35:52 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -15:35:52 INFO : Context for 'APU' is selected. -15:35:52 INFO : System reset is completed. -15:35:55 INFO : 'after 3000' command is executed. -15:35:55 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -15:36:02 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -15:36:02 INFO : Context for 'APU' is selected. -15:36:04 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -15:36:04 INFO : 'configparams force-mem-access 1' command is executed. -15:36:04 INFO : Context for 'APU' is selected. -15:36:04 INFO : 'ps7_init' command is executed. -15:36:04 INFO : 'ps7_post_config' command is executed. -15:36:04 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:36:05 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -15:36:05 INFO : 'configparams force-mem-access 0' command is executed. -15:36:05 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -15:36:05 INFO : Memory regions updated for context APU -15:36:05 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:36:05 INFO : 'con' command is executed. -15:36:05 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -15:36:05 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -15:43:42 INFO : Disconnected from the channel tcfchan#2. -15:43:43 INFO : Connected to target on host '127.0.0.1' and port '3121'. -15:43:44 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -15:43:44 INFO : 'jtag frequency' command is executed. -15:43:44 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -15:43:44 INFO : Context for 'APU' is selected. -15:43:44 INFO : System reset is completed. -15:43:47 INFO : 'after 3000' command is executed. -15:43:47 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -15:43:54 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -15:43:54 INFO : Context for 'APU' is selected. -15:43:55 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -15:43:55 INFO : 'configparams force-mem-access 1' command is executed. -15:43:55 INFO : Context for 'APU' is selected. -15:43:56 INFO : 'ps7_init' command is executed. -15:43:56 INFO : 'ps7_post_config' command is executed. -15:43:56 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:43:56 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -15:43:56 INFO : 'configparams force-mem-access 0' command is executed. -15:43:56 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -15:43:56 INFO : Memory regions updated for context APU -15:43:56 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:43:56 INFO : 'con' command is executed. -15:43:56 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -15:43:56 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -15:44:58 INFO : Disconnected from the channel tcfchan#3. -15:44:59 INFO : Connected to target on host '127.0.0.1' and port '3121'. -15:44:59 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -15:44:59 INFO : 'jtag frequency' command is executed. -15:44:59 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -15:44:59 INFO : Context for 'APU' is selected. -15:45:00 INFO : System reset is completed. -15:45:03 INFO : 'after 3000' command is executed. -15:45:03 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -15:45:10 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -15:45:10 INFO : Context for 'APU' is selected. -15:45:11 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -15:45:11 INFO : 'configparams force-mem-access 1' command is executed. -15:45:11 INFO : Context for 'APU' is selected. -15:45:12 INFO : 'ps7_init' command is executed. -15:45:12 INFO : 'ps7_post_config' command is executed. -15:45:12 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:45:12 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -15:45:12 INFO : 'configparams force-mem-access 0' command is executed. -15:45:12 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -15:45:12 INFO : Memory regions updated for context APU -15:45:13 INFO : Context for processor 'ps7_cortexa9_0' is selected. -15:45:13 INFO : 'con' command is executed. -15:45:13 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -15:45:13 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -17:14:06 INFO : Disconnected from the channel tcfchan#4. -17:14:22 INFO : Registering command handlers for SDK TCF services -17:14:22 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -17:14:24 INFO : XSCT server has started successfully. -17:14:25 INFO : Successfully done setting XSCT server connection channel -17:14:25 INFO : Successfully done setting SDK workspace -17:14:25 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -17:14:25 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -17:14:44 INFO : Connected to target on host '127.0.0.1' and port '3121'. -17:14:44 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -17:14:44 INFO : 'jtag frequency' command is executed. -17:14:44 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -17:14:44 INFO : Context for 'APU' is selected. -17:14:44 INFO : System reset is completed. -17:14:47 INFO : 'after 3000' command is executed. -17:14:47 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -17:14:54 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -17:14:54 INFO : Context for 'APU' is selected. -17:14:54 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -17:14:54 INFO : 'configparams force-mem-access 1' command is executed. -17:14:54 INFO : Context for 'APU' is selected. -17:14:55 INFO : 'ps7_init' command is executed. -17:14:55 INFO : 'ps7_post_config' command is executed. -17:14:55 INFO : Context for processor 'ps7_cortexa9_0' is selected. -17:14:55 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -17:14:55 INFO : 'configparams force-mem-access 0' command is executed. -17:14:55 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -17:14:56 INFO : Memory regions updated for context APU -17:14:56 INFO : Context for processor 'ps7_cortexa9_0' is selected. -17:14:56 INFO : 'con' command is executed. -17:14:56 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -17:14:56 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -18:37:58 INFO : Disconnected from the channel tcfchan#1. -10:16:07 INFO : Registering command handlers for SDK TCF services -10:16:07 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -10:16:09 INFO : XSCT server has started successfully. -10:16:09 INFO : Successfully done setting XSCT server connection channel -10:16:10 INFO : Successfully done setting SDK workspace -10:16:10 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -10:16:10 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -10:16:12 INFO : SDK has detected change in the last modified timestamps for source hardware specification file Source:1690800220289, Project:1690773689986 -10:16:12 INFO : The hardware specification for project 'system_wrapper_hw_platform_0' is different from G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -10:16:12 INFO : Copied contents of G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf into \system_wrapper_hw_platform_0\system.hdf. -10:16:17 INFO : Synchronizing projects in the workspace with the hardware platform specification changes. -10:16:19 INFO : -10:16:23 INFO : -10:16:24 INFO : Updating hardware inferred compiler options for FSBL. -10:16:24 INFO : Updating hardware inferred compiler options for calboard. -10:16:24 INFO : Clearing existing target manager status. -10:23:51 INFO : Registering command handlers for SDK TCF services -10:23:51 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -10:23:53 INFO : XSCT server has started successfully. -10:23:53 INFO : Successfully done setting XSCT server connection channel -10:23:54 INFO : Successfully done setting SDK workspace -10:23:54 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -10:23:54 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -10:25:04 INFO : Connected to target on host '127.0.0.1' and port '3121'. -10:25:04 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -10:25:04 INFO : 'jtag frequency' command is executed. -10:25:04 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -10:25:04 INFO : Context for 'APU' is selected. -10:25:04 INFO : System reset is completed. -10:25:07 INFO : 'after 3000' command is executed. -10:25:07 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -10:25:14 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -10:25:14 INFO : Context for 'APU' is selected. -10:25:14 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -10:25:14 INFO : 'configparams force-mem-access 1' command is executed. -10:25:14 INFO : Context for 'APU' is selected. -10:25:15 INFO : 'ps7_init' command is executed. -10:25:15 INFO : 'ps7_post_config' command is executed. -10:25:15 INFO : Context for processor 'ps7_cortexa9_0' is selected. -10:25:15 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -10:25:15 INFO : 'configparams force-mem-access 0' command is executed. -10:25:15 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -10:25:16 INFO : Memory regions updated for context APU -10:25:16 INFO : Context for processor 'ps7_cortexa9_0' is selected. -10:25:16 INFO : 'con' command is executed. -10:25:16 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -10:25:16 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -10:38:53 INFO : Disconnected from the channel tcfchan#1. -10:39:19 INFO : Registering command handlers for SDK TCF services -10:39:20 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -10:39:22 INFO : XSCT server has started successfully. -10:39:22 INFO : Successfully done setting XSCT server connection channel -10:39:22 INFO : Successfully done setting SDK workspace -10:39:22 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -10:39:22 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -10:39:37 INFO : Connected to target on host '127.0.0.1' and port '3121'. -10:39:37 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -10:39:37 INFO : 'jtag frequency' command is executed. -10:39:37 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -10:39:37 INFO : Context for 'APU' is selected. -10:39:37 INFO : System reset is completed. -10:39:40 INFO : 'after 3000' command is executed. -10:39:40 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -10:39:47 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -10:39:47 INFO : Context for 'APU' is selected. -10:39:47 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -10:39:47 INFO : 'configparams force-mem-access 1' command is executed. -10:39:47 INFO : Context for 'APU' is selected. -10:39:48 INFO : 'ps7_init' command is executed. -10:39:48 INFO : 'ps7_post_config' command is executed. -10:39:48 INFO : Context for processor 'ps7_cortexa9_0' is selected. -10:39:48 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -10:39:48 INFO : 'configparams force-mem-access 0' command is executed. -10:39:48 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -10:39:49 INFO : Memory regions updated for context APU -10:39:49 INFO : Context for processor 'ps7_cortexa9_0' is selected. -10:39:49 INFO : 'con' command is executed. -10:39:49 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -10:39:49 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -13:53:40 INFO : Disconnected from the channel tcfchan#1. -13:53:41 INFO : Connected to target on host '127.0.0.1' and port '3121'. -13:53:41 INFO : Jtag cable 'Digilent JTAG-SMT2 210251A08870' is selected. -13:53:41 INFO : 'jtag frequency' command is executed. -13:53:41 INFO : Sourcing of 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl' is done. -13:53:41 INFO : Context for 'APU' is selected. -13:53:42 INFO : System reset is completed. -13:53:45 INFO : 'after 3000' command is executed. -13:53:45 INFO : 'targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1' command is executed. -13:53:51 INFO : FPGA configured successfully with bitstream "G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit" -13:53:52 INFO : Context for 'APU' is selected. -13:53:53 INFO : Hardware design information is loaded from 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf'. -13:53:53 INFO : 'configparams force-mem-access 1' command is executed. -13:53:53 INFO : Context for 'APU' is selected. -13:53:54 INFO : 'ps7_init' command is executed. -13:53:54 INFO : 'ps7_post_config' command is executed. -13:53:54 INFO : Context for processor 'ps7_cortexa9_0' is selected. -13:53:54 INFO : The application 'G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf' is downloaded to processor 'ps7_cortexa9_0'. -13:53:54 INFO : 'configparams force-mem-access 0' command is executed. -13:53:54 INFO : ----------------XSDB Script---------------- -connect -url tcp:127.0.0.1:3121 -source G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/ps7_init.tcl -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -rst -system -after 3000 -targets -set -filter {jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870" && level==0} -index 1 -fpga -file G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system_wrapper.bit -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -loadhw -hw G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] -configparams force-mem-access 1 -targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -ps7_init -ps7_post_config -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -dow G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/calboard/Debug/calboard.elf -configparams force-mem-access 0 -----------------End of Script---------------- - -13:53:55 INFO : Memory regions updated for context APU -13:53:55 INFO : Context for processor 'ps7_cortexa9_0' is selected. -13:53:55 INFO : 'con' command is executed. -13:53:55 INFO : ----------------XSDB Script (After Launch)---------------- -targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent JTAG-SMT2 210251A08870"} -index 0 -con -----------------End of Script---------------- - -13:53:55 INFO : Launch script is exported to file 'G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_calboard.elf_on_local.tcl' -14:51:37 INFO : Invoking Bootgen: bootgen -image calboard.bif -arch zynq -o G:\CALBOARD\z035_mars1k\debug_bin\bin_8.1\BOOT.bin -14:51:37 INFO : Creating new bif file G:\CALBOARD\z035_mars1k\debug_bin\bin_8.1\calboard.bif -14:51:39 INFO : Bootgen command execution is done. -14:55:28 INFO : Disconnected from the channel tcfchan#2. -15:03:17 INFO : Registering command handlers for SDK TCF services -15:03:18 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -15:03:20 INFO : XSCT server has started successfully. -15:03:20 INFO : Successfully done setting XSCT server connection channel -15:03:22 INFO : Successfully done setting SDK workspace -15:03:22 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -15:03:22 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -15:21:32 INFO : Registering command handlers for SDK TCF services -15:21:32 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -15:21:35 INFO : XSCT server has started successfully. -15:21:35 INFO : Successfully done setting XSCT server connection channel -15:21:35 INFO : Successfully done setting SDK workspace -15:21:35 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -15:21:35 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -15:21:37 INFO : SDK has detected change in the last modified timestamps for source hardware specification file Source:1690874457292, Project:1690800220289 -15:21:37 INFO : The hardware specification for project 'system_wrapper_hw_platform_0' is different from G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -15:21:38 INFO : Copied contents of G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf into \system_wrapper_hw_platform_0\system.hdf. -15:22:02 INFO : Synchronizing projects in the workspace with the hardware platform specification changes. -15:22:10 INFO : -15:22:18 INFO : -15:22:49 INFO : Updating hardware inferred compiler options for FSBL. -15:22:50 INFO : Updating hardware inferred compiler options for calboard. -15:22:50 INFO : Clearing existing target manager status. -15:25:02 INFO : Invoking Bootgen: bootgen -image calboard.bif -arch zynq -o G:\CALBOARD\z035_mars1k\debug_bin\bin_8.1\BOOT.bin -15:25:02 INFO : Creating new bif file G:\CALBOARD\z035_mars1k\debug_bin\bin_8.1\calboard.bif -15:25:04 INFO : Bootgen command execution is done. -15:30:12 INFO : Registering command handlers for SDK TCF services -15:30:12 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -15:30:14 INFO : XSCT server has started successfully. -15:30:14 INFO : Successfully done setting XSCT server connection channel -15:30:14 INFO : Successfully done setting SDK workspace -15:30:14 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -15:30:14 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -17:30:47 INFO : Registering command handlers for SDK TCF services -17:30:47 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -17:30:49 INFO : XSCT server has started successfully. -17:30:50 INFO : Successfully done setting XSCT server connection channel -17:30:50 INFO : Successfully done setting SDK workspace -17:30:50 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -17:30:50 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -14:01:53 INFO : Registering command handlers for SDK TCF services -14:01:54 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -14:01:58 INFO : XSCT server has started successfully. -14:01:58 INFO : Successfully done setting XSCT server connection channel -14:02:00 INFO : Successfully done setting SDK workspace -14:02:00 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -14:02:00 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -14:26:39 INFO : Invoking Bootgen: bootgen -image calboard.bif -arch zynq -o G:\CALBOARD\z035_mars1k\debug_bin\bin_8.2\BOOT.bin -14:26:39 INFO : Creating new bif file G:\CALBOARD\z035_mars1k\debug_bin\bin_8.2\calboard.bif -14:26:41 INFO : Bootgen command execution is done. -17:43:39 INFO : Registering command handlers for SDK TCF services -17:43:40 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -17:43:42 INFO : XSCT server has started successfully. -17:43:42 INFO : Successfully done setting XSCT server connection channel -17:43:42 INFO : Successfully done setting SDK workspace -17:43:42 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -17:43:42 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -09:50:33 INFO : Registering command handlers for SDK TCF services -09:50:33 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -09:50:35 INFO : XSCT server has started successfully. -09:50:35 INFO : Successfully done setting XSCT server connection channel -09:50:35 INFO : Successfully done setting SDK workspace -09:50:35 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -09:50:35 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -10:00:28 INFO : Registering command handlers for SDK TCF services -10:00:29 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -10:00:31 INFO : XSCT server has started successfully. -10:00:31 INFO : Successfully done setting XSCT server connection channel -10:00:31 INFO : Successfully done setting SDK workspace -10:00:31 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -10:00:31 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -10:00:33 INFO : SDK has detected change in the last modified timestamps for source hardware specification file Source:1691027937690, Project:1690874457292 -10:00:33 INFO : The hardware specification for project 'system_wrapper_hw_platform_0' is different from G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -10:00:33 INFO : Copied contents of G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf into \system_wrapper_hw_platform_0\system.hdf. -10:00:37 INFO : Synchronizing projects in the workspace with the hardware platform specification changes. -10:00:45 INFO : -10:00:53 INFO : -10:00:53 INFO : Updating hardware inferred compiler options for FSBL. -10:00:54 INFO : Updating hardware inferred compiler options for calboard. -10:00:54 INFO : Clearing existing target manager status. -10:07:46 INFO : Invoking Bootgen: bootgen -image calboard.bif -arch zynq -o G:\CALBOARD\z035_mars1k\debug_bin\bin_8.3\BOOT.bin -10:07:46 INFO : Creating new bif file G:\CALBOARD\z035_mars1k\debug_bin\bin_8.3\calboard.bif -10:07:48 INFO : Bootgen command execution is done. -16:02:36 INFO : Registering command handlers for SDK TCF services -16:02:37 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -16:02:40 INFO : XSCT server has started successfully. -16:02:40 INFO : Successfully done setting XSCT server connection channel -16:02:42 INFO : Successfully done setting SDK workspace -16:02:42 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -16:02:42 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -16:16:04 INFO : Invoking Bootgen: bootgen -image calboard.bif -arch zynq -o G:\CALBOARD\z035_mars1k\debug_bin\bin_8.11\BOOT.bin -16:16:04 INFO : Creating new bif file G:\CALBOARD\z035_mars1k\debug_bin\bin_8.11\calboard.bif -16:16:06 INFO : Bootgen command execution is done. -15:58:29 INFO : Registering command handlers for SDK TCF services -15:58:30 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -15:58:32 INFO : XSCT server has started successfully. -15:58:32 INFO : Successfully done setting XSCT server connection channel -15:58:32 INFO : Successfully done setting SDK workspace -15:58:32 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -15:58:32 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -16:46:49 INFO : Registering command handlers for SDK TCF services -16:46:49 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -16:46:51 INFO : XSCT server has started successfully. -16:46:51 INFO : Successfully done setting XSCT server connection channel -16:46:51 INFO : Successfully done setting SDK workspace -15:25:02 INFO : Registering command handlers for SDK TCF services -15:25:02 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -15:25:04 INFO : XSCT server has started successfully. -15:25:05 INFO : Successfully done setting XSCT server connection channel -15:25:05 INFO : Successfully done setting SDK workspace -11:03:59 INFO : Registering command handlers for SDK TCF services -11:04:00 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -11:04:02 INFO : XSCT server has started successfully. -11:04:02 INFO : Successfully done setting XSCT server connection channel -11:04:02 INFO : Successfully done setting SDK workspace -10:55:47 INFO : Registering command handlers for SDK TCF services -10:55:49 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -10:55:52 INFO : XSCT server has started successfully. -10:55:52 INFO : Successfully done setting XSCT server connection channel -10:55:55 INFO : Successfully done setting SDK workspace -10:55:55 INFO : Processing command line option -hwspec G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -10:55:55 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_0. -18:05:17 INFO : Registering command handlers for SDK TCF services -18:05:17 INFO : Launching XSCT server: xsct.bat -interactive G:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -18:05:19 INFO : XSCT server has started successfully. -18:05:19 INFO : Successfully done setting XSCT server connection channel -18:05:19 INFO : Successfully done setting SDK workspace -13:43:11 INFO : Registering command handlers for SDK TCF services -13:43:11 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -13:43:13 INFO : XSCT server has started successfully. -13:43:13 INFO : Successfully done setting XSCT server connection channel -13:43:13 INFO : Successfully done setting SDK workspace -13:43:13 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -13:53:45 INFO : Invoking Bootgen: bootgen -image BOOT.bif -arch zynq -o E:\CALBOARD\z035_mars1k\debug_bin\bin_2024_11.22\BOOT.bin -13:53:45 INFO : Creating new bif file E:\CALBOARD\z035_mars1k\debug_bin\bin_2024_11.22\BOOT.bif -13:53:47 INFO : Bootgen command execution is done. -14:56:57 INFO : Registering command handlers for SDK TCF services -14:56:58 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -14:57:00 INFO : XSCT server has started successfully. -14:57:00 INFO : Successfully done setting XSCT server connection channel -14:57:00 INFO : Successfully done setting SDK workspace -14:57:00 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -14:57:00 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_1. -15:50:45 INFO : Registering command handlers for SDK TCF services -15:50:46 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -15:50:48 INFO : XSCT server has started successfully. -15:50:48 INFO : Successfully done setting XSCT server connection channel -15:50:48 INFO : Successfully done setting SDK workspace -15:50:48 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -15:50:48 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_1. -12:44:27 INFO : Registering command handlers for SDK TCF services -12:44:28 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -12:44:30 INFO : XSCT server has started successfully. -12:44:30 INFO : Successfully done setting XSCT server connection channel -12:44:30 INFO : Successfully done setting SDK workspace -12:44:30 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -12:44:30 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_1. -12:53:04 INFO : Invoking Bootgen: bootgen -image calboard.bif -arch zynq -o E:\CALBOARD\z035_mars1k\bin\bin_11.13\BOOT.bin -12:53:04 INFO : Creating new bif file E:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\calboard\bootimage\calboard.bif -12:53:07 INFO : Bootgen command execution is done. -12:56:37 INFO : Registering command handlers for SDK TCF services -12:56:37 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -12:56:39 INFO : XSCT server has started successfully. -12:56:40 INFO : Successfully done setting XSCT server connection channel -12:56:40 INFO : Successfully done setting SDK workspace -12:56:40 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -12:56:40 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_1. -12:58:45 INFO : Invoking Bootgen: bootgen -image BOOTbif.bif -arch zynq -o E:\CALBOARD\z035_mars1k\bin\bin_11.13\BOOT.bin -12:58:45 INFO : Creating new bif file E:\CALBOARD\z035_mars1k\bin\bin_11.13\BOOTbif.bif -12:58:47 INFO : Bootgen command execution is done. -13:57:59 INFO : Registering command handlers for SDK TCF services -13:58:00 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k\calboard_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -13:58:02 INFO : XSCT server has started successfully. -13:58:02 INFO : Successfully done setting XSCT server connection channel -13:58:02 INFO : Successfully done setting SDK workspace -13:58:02 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -13:58:02 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_1. -14:00:59 INFO : Invoking Bootgen: bootgen -image BOOT.bif -arch zynq -o E:\CALBOARD\z035_mars1k\bin\bin_11.13\BOOT.bin -14:00:59 INFO : Creating new bif file E:\CALBOARD\z035_mars1k\bin\bin_11.13\BOOT.bif -14:01:01 INFO : Bootgen command execution is done. -17:48:57 INFO : Registering command handlers for SDK TCF services -17:49:00 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -17:49:03 INFO : XSCT server has started successfully. -17:49:05 INFO : Successfully done setting XSCT server connection channel -17:49:05 INFO : Successfully done setting SDK workspace -17:49:05 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -18:09:35 INFO : Registering command handlers for SDK TCF services -18:09:36 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -18:09:38 INFO : XSCT server has started successfully. -18:09:38 INFO : Successfully done setting XSCT server connection channel -18:09:38 INFO : Successfully done setting SDK workspace -18:09:38 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -18:09:38 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_2. -09:55:15 INFO : Registering command handlers for SDK TCF services -09:55:17 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -09:55:22 INFO : XSCT server has started successfully. -09:55:27 INFO : Successfully done setting XSCT server connection channel -09:55:27 INFO : Successfully done setting SDK workspace -09:55:27 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -09:55:27 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_2. -17:51:43 INFO : Invoking Bootgen: bootgen -image BOOT.bif -arch zynq -o E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.13\BOOT.bin -17:51:43 INFO : Creating new bif file E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.13\BOOT.bif -17:51:45 INFO : Bootgen command execution is done. -14:00:28 INFO : Registering command handlers for SDK TCF services -14:00:29 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -14:00:32 INFO : XSCT server has started successfully. -14:00:32 INFO : Successfully done setting XSCT server connection channel -14:00:34 INFO : Successfully done setting SDK workspace -14:00:34 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -14:00:34 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_2. -14:37:54 INFO : Registering command handlers for SDK TCF services -14:37:55 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -14:37:57 INFO : XSCT server has started successfully. -14:37:57 INFO : Successfully done setting XSCT server connection channel -14:37:57 INFO : Successfully done setting SDK workspace -14:37:57 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -14:37:57 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_2. -14:42:44 INFO : Invoking Bootgen: bootgen -image BOOT.bif -arch zynq -o E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.14\BOOT.bin -14:42:44 INFO : Creating new bif file E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.14\BOOT.bif -14:42:46 INFO : Bootgen command execution is done. -15:02:25 INFO : Registering command handlers for SDK TCF services -15:02:25 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -15:02:27 INFO : XSCT server has started successfully. -15:02:27 INFO : Successfully done setting XSCT server connection channel -15:02:27 INFO : Successfully done setting SDK workspace -15:02:27 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -15:02:28 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_2. -15:13:00 INFO : Invoking Bootgen: bootgen -image BOOT.bif -arch zynq -o E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.14.1\BOOT.bin -15:13:00 INFO : Creating new bif file E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.14.1\BOOT.bif -15:13:02 INFO : Bootgen command execution is done. -15:21:21 INFO : Invoking Bootgen: bootgen -image BOOT.bif -arch zynq -o E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.14.1\BOOT.bin -15:21:21 INFO : Creating new bif file E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.14.1\BOOT.bif -15:21:23 INFO : Bootgen command execution is done. -16:03:10 INFO : Registering command handlers for SDK TCF services -16:03:11 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -16:03:13 INFO : XSCT server has started successfully. -16:03:13 INFO : Successfully done setting XSCT server connection channel -16:03:13 INFO : Successfully done setting SDK workspace -16:03:13 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -16:03:13 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_2. -16:45:40 INFO : Invoking Bootgen: bootgen -image BOOT.bif -arch zynq -o E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.14.2\BOOT.bin -16:45:40 INFO : Creating new bif file E:\CALBOARD\z035_mars1k_a1_sc1\bin\bin_1.14.2\BOOT.bif -16:45:43 INFO : Bootgen command execution is done. -17:47:09 INFO : Registering command handlers for SDK TCF services -17:47:10 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -17:47:12 INFO : XSCT server has started successfully. -17:47:12 INFO : Successfully done setting XSCT server connection channel -17:47:12 INFO : Successfully done setting SDK workspace -17:47:12 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -17:47:12 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_2. -15:04:02 INFO : Registering command handlers for SDK TCF services -15:04:04 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -15:04:08 INFO : XSCT server has started successfully. -15:04:13 INFO : Successfully done setting XSCT server connection channel -15:04:13 INFO : Successfully done setting SDK workspace -15:04:13 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -15:04:13 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_2. -10:54:47 INFO : Registering command handlers for SDK TCF services -10:54:49 INFO : Launching XSCT server: xsct.bat -interactive E:\CALBOARD\z035_mars1k_a1_sc1\calboard_cp_a1\proj_cal\proj_cal.sdk\temp_xsdb_launch_script.tcl -10:54:53 INFO : XSCT server has started successfully. -10:54:53 INFO : Successfully done setting XSCT server connection channel -10:54:59 INFO : Successfully done setting SDK workspace -10:54:59 INFO : Processing command line option -hwspec E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/system_wrapper.hdf. -10:54:59 INFO : Checking for hwspec changes in the project system_wrapper_hw_platform_2. diff --git a/Debug_FW.sdk/webtalk/webtalk.log b/Debug_FW.sdk/webtalk/webtalk.log deleted file mode 100644 index 667aa9f..0000000 --- a/Debug_FW.sdk/webtalk/webtalk.log +++ /dev/null @@ -1,58 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# -# Start of session at: Mon Jan 12 17:58:43 2026 -# Process ID: 9264 -# Current directory: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/webtalk -# Command line: wbtcv.exe -mode batch -source sdk_webtalk.tcl -# Log file: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/webtalk/webtalk.log -# Journal file: E:/CALBOARD/z035_mars1k_a1_sc1/calboard_cp_a1/proj_cal/proj_cal.sdk/webtalk\webtalk.jou -#----------------------------------------------------------- -source sdk_webtalk.tcl -# webtalk_init -webtalk_dir E:\\CALBOARD\\z035_mars1k_a1_sc1\\calboard_cp_a1\\proj_cal\\proj_cal.sdk\\webtalk -# webtalk_register_client -client project -# webtalk_add_data -client project -key date_generated -value "2026-01-12 17:58:41" -context "software_version_and_target_device" -# webtalk_add_data -client project -key product_version -value "SDK v2018.3" -context "software_version_and_target_device" -# webtalk_add_data -client project -key build_version -value "2018.3" -context "software_version_and_target_device" -# webtalk_add_data -client project -key os_platform -value "amd64" -context "software_version_and_target_device" -# webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" -# webtalk_add_data -client project -key tool_flow -value "SDK" -context "software_version_and_target_device" -# webtalk_add_data -client project -key beta -value "false" -context "software_version_and_target_device" -# webtalk_add_data -client project -key route_design -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_family -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_device -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_package -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_speed -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key random_id -value "2nggfjdmptbjko2tf7jbetillv" -context "software_version_and_target_device" -# webtalk_add_data -client project -key project_id -value "2018.3_84" -context "software_version_and_target_device" -# webtalk_add_data -client project -key project_iteration -value "84" -context "software_version_and_target_device" -# webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" -# webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" -# webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz" -context "user_environment" -# webtalk_add_data -client project -key cpu_speed -value "3096 MHz" -context "user_environment" -# webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -# webtalk_add_data -client project -key system_ram -value "68.455 GB" -context "user_environment" -# webtalk_register_client -client sdk -# webtalk_add_data -client sdk -key uid -value "1768211353816" -context "sdk\\\\hardware/1768211353816" -# webtalk_add_data -client sdk -key isZynq -value "true" -context "sdk\\\\hardware/1768211353816" -# webtalk_add_data -client sdk -key isZynqMP -value "false" -context "sdk\\\\hardware/1768211353816" -# webtalk_add_data -client sdk -key Processors -value "2" -context "sdk\\\\hardware/1768211353816" -# webtalk_add_data -client sdk -key VivadoVersion -value "2018.3" -context "sdk\\\\hardware/1768211353816" -# webtalk_add_data -client sdk -key Arch -value "zynq" -context "sdk\\\\hardware/1768211353816" -# webtalk_add_data -client sdk -key Device -value "7z035" -context "sdk\\\\hardware/1768211353816" -# webtalk_add_data -client sdk -key IsHandoff -value "true" -context "sdk\\\\hardware/1768211353816" -# webtalk_add_data -client sdk -key os -value "NA" -context "sdk\\\\hardware/1768211353816" -# webtalk_add_data -client sdk -key apptemplate -value "NA" -context "sdk\\\\hardware/1768211353816" -# webtalk_add_data -client sdk -key RecordType -value "HWCreation" -context "sdk\\\\hardware/1768211353816" -# webtalk_add_data -client sdk -key uid -value "NA" -context "sdk\\\\bsp/1768211921541" -# webtalk_add_data -client sdk -key RecordType -value "ToolUsage" -context "sdk\\\\bsp/1768211921541" -# webtalk_add_data -client sdk -key BootgenCount -value "0" -context "sdk\\\\bsp/1768211921541" -# webtalk_add_data -client sdk -key DebugCount -value "0" -context "sdk\\\\bsp/1768211921541" -# webtalk_add_data -client sdk -key PerfCount -value "0" -context "sdk\\\\bsp/1768211921541" -# webtalk_add_data -client sdk -key FlashCount -value "0" -context "sdk\\\\bsp/1768211921541" -# webtalk_add_data -client sdk -key CrossTriggCount -value "0" -context "sdk\\\\bsp/1768211921541" -# webtalk_add_data -client sdk -key QemuDebugCount -value "0" -context "sdk\\\\bsp/1768211921541" -# webtalk_transmit -clientid 5615683 -regid "" -xml E:\\CALBOARD\\z035_mars1k_a1_sc1\\calboard_cp_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.xml -html E:\\CALBOARD\\z035_mars1k_a1_sc1\\calboard_cp_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.html -wdm E:\\CALBOARD\\z035_mars1k_a1_sc1\\calboard_cp_a1\\proj_cal\\proj_cal.sdk\\webtalk\\sdk_webtalk.wdm -intro "

SDK Usage Report


" -# webtalk_terminate -INFO: [Common 17-206] Exiting Webtalk at Mon Jan 12 17:58:45 2026... diff --git a/Debug_FW.sdk/webtalk/webtalk_20184.backup.log b/Debug_FW.sdk/webtalk/webtalk_20184.backup.log deleted file mode 100644 index e04067d..0000000 --- a/Debug_FW.sdk/webtalk/webtalk_20184.backup.log +++ /dev/null @@ -1,73 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# -# Start of session at: Thu Jul 20 18:23:39 2023 -# Process ID: 20184 -# Current directory: G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk -# Command line: wbtcv.exe -mode batch -source sdk_webtalk.tcl -# Log file: G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk/webtalk.log -# Journal file: G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk\webtalk.jou -#----------------------------------------------------------- -source sdk_webtalk.tcl -# webtalk_init -webtalk_dir G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk -# webtalk_register_client -client project -# webtalk_add_data -client project -key date_generated -value "2023-07-20 18:23:36" -context "software_version_and_target_device" -# webtalk_add_data -client project -key product_version -value "SDK v2018.3" -context "software_version_and_target_device" -# webtalk_add_data -client project -key build_version -value "2018.3" -context "software_version_and_target_device" -# webtalk_add_data -client project -key os_platform -value "amd64" -context "software_version_and_target_device" -# webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" -# webtalk_add_data -client project -key tool_flow -value "SDK" -context "software_version_and_target_device" -# webtalk_add_data -client project -key beta -value "false" -context "software_version_and_target_device" -# webtalk_add_data -client project -key route_design -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_family -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_device -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_package -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_speed -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key random_id -value "d93rb3douagiiu2qng7tjq9f0f" -context "software_version_and_target_device" -# webtalk_add_data -client project -key project_id -value "2018.3_39" -context "software_version_and_target_device" -# webtalk_add_data -client project -key project_iteration -value "39" -context "software_version_and_target_device" -# webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" -# webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" -# webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz" -context "user_environment" -# webtalk_add_data -client project -key cpu_speed -value "3096 MHz" -context "user_environment" -# webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -# webtalk_add_data -client project -key system_ram -value "16.915 GB" -context "user_environment" -# webtalk_register_client -client sdk -# webtalk_add_data -client sdk -key uid -value "1689821971742" -context "sdk\\\\hardware/1689821971742" -# webtalk_add_data -client sdk -key isZynq -value "true" -context "sdk\\\\hardware/1689821971742" -# webtalk_add_data -client sdk -key isZynqMP -value "false" -context "sdk\\\\hardware/1689821971742" -# webtalk_add_data -client sdk -key Processors -value "2" -context "sdk\\\\hardware/1689821971742" -# webtalk_add_data -client sdk -key VivadoVersion -value "2018.3" -context "sdk\\\\hardware/1689821971742" -# webtalk_add_data -client sdk -key Arch -value "zynq" -context "sdk\\\\hardware/1689821971742" -# webtalk_add_data -client sdk -key Device -value "7z035" -context "sdk\\\\hardware/1689821971742" -# webtalk_add_data -client sdk -key IsHandoff -value "true" -context "sdk\\\\hardware/1689821971742" -# webtalk_add_data -client sdk -key os -value "NA" -context "sdk\\\\hardware/1689821971742" -# webtalk_add_data -client sdk -key apptemplate -value "NA" -context "sdk\\\\hardware/1689821971742" -# webtalk_add_data -client sdk -key RecordType -value "HWCreation" -context "sdk\\\\hardware/1689821971742" -# webtalk_add_data -client sdk -key uid -value "1689822029590" -context "sdk\\\\bsp/1689822029590" -# webtalk_add_data -client sdk -key hwid -value "1689821971742" -context "sdk\\\\bsp/1689822029590" -# webtalk_add_data -client sdk -key os -value "standalone" -context "sdk\\\\bsp/1689822029590" -# webtalk_add_data -client sdk -key apptemplate -value "lwip_echo_server" -context "sdk\\\\bsp/1689822029590" -# webtalk_add_data -client sdk -key RecordType -value "BSPCreation" -context "sdk\\\\bsp/1689822029590" -# webtalk_add_data -client sdk -key uid -value "1689822033349" -context "sdk\\\\application/1689822033349" -# webtalk_add_data -client sdk -key hwid -value "1689821971742" -context "sdk\\\\application/1689822033349" -# webtalk_add_data -client sdk -key bspid -value "1689822029590" -context "sdk\\\\application/1689822033349" -# webtalk_add_data -client sdk -key newbsp -value "true" -context "sdk\\\\application/1689822033349" -# webtalk_add_data -client sdk -key os -value "standalone" -context "sdk\\\\application/1689822033349" -# webtalk_add_data -client sdk -key apptemplate -value "lwip_echo_server" -context "sdk\\\\application/1689822033349" -# webtalk_add_data -client sdk -key RecordType -value "APPCreation" -context "sdk\\\\application/1689822033349" -# webtalk_add_data -client sdk -key LangUsed -value "C" -context "sdk\\\\application/1689822033349" -# webtalk_add_data -client sdk -key Procused -value "ps7_cortexa9" -context "sdk\\\\application/1689822033349" -# webtalk_add_data -client sdk -key projSize -value "1030.41015625" -context "sdk\\\\application/1689822033349" -# webtalk_add_data -client sdk -key uid -value "NA" -context "sdk\\\\bsp/1689848616439" -# webtalk_add_data -client sdk -key RecordType -value "ToolUsage" -context "sdk\\\\bsp/1689848616439" -# webtalk_add_data -client sdk -key BootgenCount -value "0" -context "sdk\\\\bsp/1689848616439" -# webtalk_add_data -client sdk -key DebugCount -value "19" -context "sdk\\\\bsp/1689848616439" -# webtalk_add_data -client sdk -key PerfCount -value "0" -context "sdk\\\\bsp/1689848616439" -# webtalk_add_data -client sdk -key FlashCount -value "0" -context "sdk\\\\bsp/1689848616439" -# webtalk_add_data -client sdk -key CrossTriggCount -value "0" -context "sdk\\\\bsp/1689848616439" -# webtalk_add_data -client sdk -key QemuDebugCount -value "0" -context "sdk\\\\bsp/1689848616439" -# webtalk_transmit -clientid 3912584924 -regid "" -xml G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.xml -html G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.html -wdm G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\sdk_webtalk.wdm -intro "

SDK Usage Report


" -# webtalk_terminate -INFO: [Common 17-206] Exiting Webtalk at Thu Jul 20 18:23:42 2023... diff --git a/Debug_FW.sdk/webtalk/webtalk_5900.backup.log b/Debug_FW.sdk/webtalk/webtalk_5900.backup.log deleted file mode 100644 index 86f710b..0000000 --- a/Debug_FW.sdk/webtalk/webtalk_5900.backup.log +++ /dev/null @@ -1,62 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# -# Start of session at: Mon Jul 31 11:37:17 2023 -# Process ID: 5900 -# Current directory: G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk -# Command line: wbtcv.exe -mode batch -source sdk_webtalk.tcl -# Log file: G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk/webtalk.log -# Journal file: G:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk\webtalk.jou -#----------------------------------------------------------- -source sdk_webtalk.tcl -# webtalk_init -webtalk_dir G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk -# webtalk_register_client -client project -# webtalk_add_data -client project -key date_generated -value "2023-07-31 11:37:16" -context "software_version_and_target_device" -# webtalk_add_data -client project -key product_version -value "SDK v2018.3" -context "software_version_and_target_device" -# webtalk_add_data -client project -key build_version -value "2018.3" -context "software_version_and_target_device" -# webtalk_add_data -client project -key os_platform -value "amd64" -context "software_version_and_target_device" -# webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" -# webtalk_add_data -client project -key tool_flow -value "SDK" -context "software_version_and_target_device" -# webtalk_add_data -client project -key beta -value "false" -context "software_version_and_target_device" -# webtalk_add_data -client project -key route_design -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_family -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_device -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_package -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_speed -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key random_id -value "6lutd0oqhp462m5qicot7tp33v" -context "software_version_and_target_device" -# webtalk_add_data -client project -key project_id -value "2018.3_40" -context "software_version_and_target_device" -# webtalk_add_data -client project -key project_iteration -value "40" -context "software_version_and_target_device" -# webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" -# webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" -# webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz" -context "user_environment" -# webtalk_add_data -client project -key cpu_speed -value "3096 MHz" -context "user_environment" -# webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -# webtalk_add_data -client project -key system_ram -value "16.915 GB" -context "user_environment" -# webtalk_register_client -client sdk -# webtalk_add_data -client sdk -key uid -value "1690773826104" -context "sdk\\\\bsp/1690773826104" -# webtalk_add_data -client sdk -key hwid -value "1689821971742" -context "sdk\\\\bsp/1690773826104" -# webtalk_add_data -client sdk -key os -value "standalone" -context "sdk\\\\bsp/1690773826104" -# webtalk_add_data -client sdk -key apptemplate -value "zynq_fsbl" -context "sdk\\\\bsp/1690773826104" -# webtalk_add_data -client sdk -key RecordType -value "BSPCreation" -context "sdk\\\\bsp/1690773826104" -# webtalk_add_data -client sdk -key uid -value "1690773834491" -context "sdk\\\\application/1690773834491" -# webtalk_add_data -client sdk -key hwid -value "1689821971742" -context "sdk\\\\application/1690773834491" -# webtalk_add_data -client sdk -key bspid -value "1690773826104" -context "sdk\\\\application/1690773834491" -# webtalk_add_data -client sdk -key newbsp -value "true" -context "sdk\\\\application/1690773834491" -# webtalk_add_data -client sdk -key os -value "standalone" -context "sdk\\\\application/1690773834491" -# webtalk_add_data -client sdk -key apptemplate -value "zynq_fsbl" -context "sdk\\\\application/1690773834491" -# webtalk_add_data -client sdk -key RecordType -value "APPCreation" -context "sdk\\\\application/1690773834491" -# webtalk_add_data -client sdk -key LangUsed -value "C" -context "sdk\\\\application/1690773834491" -# webtalk_add_data -client sdk -key Procused -value "ps7_cortexa9" -context "sdk\\\\application/1690773834491" -# webtalk_add_data -client sdk -key projSize -value "593.01953125" -context "sdk\\\\application/1690773834491" -# webtalk_add_data -client sdk -key uid -value "NA" -context "sdk\\\\bsp/1690774636169" -# webtalk_add_data -client sdk -key RecordType -value "ToolUsage" -context "sdk\\\\bsp/1690774636169" -# webtalk_add_data -client sdk -key BootgenCount -value "1" -context "sdk\\\\bsp/1690774636169" -# webtalk_add_data -client sdk -key DebugCount -value "0" -context "sdk\\\\bsp/1690774636169" -# webtalk_add_data -client sdk -key PerfCount -value "0" -context "sdk\\\\bsp/1690774636169" -# webtalk_add_data -client sdk -key FlashCount -value "0" -context "sdk\\\\bsp/1690774636169" -# webtalk_add_data -client sdk -key CrossTriggCount -value "0" -context "sdk\\\\bsp/1690774636169" -# webtalk_add_data -client sdk -key QemuDebugCount -value "0" -context "sdk\\\\bsp/1690774636169" -# webtalk_transmit -clientid 2374953459 -regid "" -xml G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.xml -html G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.html -wdm G:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\sdk_webtalk.wdm -intro "

SDK Usage Report


" -# webtalk_terminate -INFO: [Common 17-206] Exiting Webtalk at Mon Jul 31 11:37:19 2023... diff --git a/Debug_FW.sdk/webtalk/webtalk_7548.backup.log b/Debug_FW.sdk/webtalk/webtalk_7548.backup.log deleted file mode 100644 index 0ce22a4..0000000 --- a/Debug_FW.sdk/webtalk/webtalk_7548.backup.log +++ /dev/null @@ -1,58 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# -# Start of session at: Fri Nov 22 13:59:32 2024 -# Process ID: 7548 -# Current directory: E:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk -# Command line: wbtcv.exe -mode batch -source sdk_webtalk.tcl -# Log file: E:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk/webtalk.log -# Journal file: E:/CALBOARD/z035_mars1k/calboard_a1/proj_cal/proj_cal.sdk/webtalk\webtalk.jou -#----------------------------------------------------------- -source sdk_webtalk.tcl -# webtalk_init -webtalk_dir E:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk -# webtalk_register_client -client project -# webtalk_add_data -client project -key date_generated -value "2024-11-22 13:59:31" -context "software_version_and_target_device" -# webtalk_add_data -client project -key product_version -value "SDK v2018.3" -context "software_version_and_target_device" -# webtalk_add_data -client project -key build_version -value "2018.3" -context "software_version_and_target_device" -# webtalk_add_data -client project -key os_platform -value "amd64" -context "software_version_and_target_device" -# webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" -# webtalk_add_data -client project -key tool_flow -value "SDK" -context "software_version_and_target_device" -# webtalk_add_data -client project -key beta -value "false" -context "software_version_and_target_device" -# webtalk_add_data -client project -key route_design -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_family -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_device -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_package -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key target_speed -value "NA" -context "software_version_and_target_device" -# webtalk_add_data -client project -key random_id -value "um90256p7r8dnau11ussq547e5" -context "software_version_and_target_device" -# webtalk_add_data -client project -key project_id -value "2018.3_78" -context "software_version_and_target_device" -# webtalk_add_data -client project -key project_iteration -value "78" -context "software_version_and_target_device" -# webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" -# webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" -# webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-10500 CPU @ 3.10GHz" -context "user_environment" -# webtalk_add_data -client project -key cpu_speed -value "3096 MHz" -context "user_environment" -# webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -# webtalk_add_data -client project -key system_ram -value "68.455 GB" -context "user_environment" -# webtalk_register_client -client sdk -# webtalk_add_data -client sdk -key uid -value "1732254221461" -context "sdk\\\\hardware/1732254221461" -# webtalk_add_data -client sdk -key isZynq -value "true" -context "sdk\\\\hardware/1732254221461" -# webtalk_add_data -client sdk -key isZynqMP -value "false" -context "sdk\\\\hardware/1732254221461" -# webtalk_add_data -client sdk -key Processors -value "2" -context "sdk\\\\hardware/1732254221461" -# webtalk_add_data -client sdk -key VivadoVersion -value "2018.3" -context "sdk\\\\hardware/1732254221461" -# webtalk_add_data -client sdk -key Arch -value "zynq" -context "sdk\\\\hardware/1732254221461" -# webtalk_add_data -client sdk -key Device -value "7z035" -context "sdk\\\\hardware/1732254221461" -# webtalk_add_data -client sdk -key IsHandoff -value "true" -context "sdk\\\\hardware/1732254221461" -# webtalk_add_data -client sdk -key os -value "NA" -context "sdk\\\\hardware/1732254221461" -# webtalk_add_data -client sdk -key apptemplate -value "NA" -context "sdk\\\\hardware/1732254221461" -# webtalk_add_data -client sdk -key RecordType -value "HWCreation" -context "sdk\\\\hardware/1732254221461" -# webtalk_add_data -client sdk -key uid -value "NA" -context "sdk\\\\bsp/1732255170972" -# webtalk_add_data -client sdk -key RecordType -value "ToolUsage" -context "sdk\\\\bsp/1732255170972" -# webtalk_add_data -client sdk -key BootgenCount -value "1" -context "sdk\\\\bsp/1732255170972" -# webtalk_add_data -client sdk -key DebugCount -value "0" -context "sdk\\\\bsp/1732255170972" -# webtalk_add_data -client sdk -key PerfCount -value "0" -context "sdk\\\\bsp/1732255170972" -# webtalk_add_data -client sdk -key FlashCount -value "0" -context "sdk\\\\bsp/1732255170972" -# webtalk_add_data -client sdk -key CrossTriggCount -value "0" -context "sdk\\\\bsp/1732255170972" -# webtalk_add_data -client sdk -key QemuDebugCount -value "0" -context "sdk\\\\bsp/1732255170972" -# webtalk_transmit -clientid 61313245 -regid "" -xml E:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.xml -html E:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\usage_statistics_ext_sdk.html -wdm E:\\CALBOARD\\z035_mars1k\\calboard_a1\\proj_cal\\proj_cal.sdk\\webtalk\\sdk_webtalk.wdm -intro "

SDK Usage Report


" -# webtalk_terminate -INFO: [Common 17-206] Exiting Webtalk at Fri Nov 22 13:59:37 2024... diff --git a/Vitis_Classic/IDE.log b/Vitis_Classic/IDE.log deleted file mode 100644 index 76adf97..0000000 --- a/Vitis_Classic/IDE.log +++ /dev/null @@ -1,13 +0,0 @@ -09:47:19 DEBUG : Logs will be stored at '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/IDE.log'. -09:47:20 INFO : Launching XSCT server: xsct -n -interactive /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/temp_xsdb_launch_script.tcl -09:47:20 INFO : Platform repository initialization has completed. -09:47:20 INFO : Registering command handlers for Vitis TCF services -09:47:21 INFO : XSCT server has started successfully. -09:47:21 INFO : Successfully done setting XSCT server connection channel -09:47:21 INFO : Successfully done query RDI_DATADIR -09:47:21 INFO : Successfully done setting workspace for the tool. -09:47:22 INFO : plnx-install-location is set to '' -09:48:02 INFO : Platform 'NewInstCal_bsp' is added to custom repositories. -09:48:28 INFO : Hardware specification for platform project 'NewInstCal_bsp' is updated. -09:48:46 INFO : Result from executing command 'getProjects': NewInstCal_bsp -09:48:46 INFO : Result from executing command 'getPlatforms': NewInstCal_bsp|/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/NewInstCal_bsp.xpfm diff --git a/Vitis_Classic/NewInstCal_bsp/.log/NewInstCal_bsp_.build.ui.log b/Vitis_Classic/NewInstCal_bsp/.log/NewInstCal_bsp_.build.ui.log deleted file mode 100644 index d8403c3..0000000 --- a/Vitis_Classic/NewInstCal_bsp/.log/NewInstCal_bsp_.build.ui.log +++ /dev/null @@ -1,2 +0,0 @@ -2026-05-27T18:04:35.5315588000-Nothing to build in platform 'NewInstCal_bsp' - diff --git a/Vitis_Classic/NewInstCal_bsp/logs/platform.log b/Vitis_Classic/NewInstCal_bsp/logs/platform.log deleted file mode 100644 index 0f18a59..0000000 --- a/Vitis_Classic/NewInstCal_bsp/logs/platform.log +++ /dev/null @@ -1,5743 +0,0 @@ -TRACE::2026-05-26.18:22:03::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:03::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:03::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:03::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:03::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:03::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:03::SCWPlatform::Do not have an existing db opened. -TRACE::2026-05-26.18:22:04::SCWPlatform::Opened new HwDB with name system_wrapper_0 -TRACE::2026-05-26.18:22:04::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "platPreBuiltFlag": false, - "platformSamplesDir": "" -} -TRACE::2026-05-26.18:22:04::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "platPreBuiltFlag": false, - "platformSamplesDir": "", - "platActiveSys": "NewInstCal_bsp", - "systems": [{ - "systemName": "NewInstCal_bsp", - "systemDesc": "NewInstCal_bsp", - "sysIsBootAutoGen": "true", - "systemDispName": "NewInstCal_bsp" - }] -} -TRACE::2026-05-26.18:22:04::SCWPlatform::Boot application domains not present, creating them -TRACE::2026-05-26.18:22:04::SCWDomain::checking for install qemu data : -TRACE::2026-05-26.18:22:04::SCWDomain:: Using the QEMU Data from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/ -TRACE::2026-05-26.18:22:04::SCWDomain:: Using the QEMU args from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt -TRACE::2026-05-26.18:22:04::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:04::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:04::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:04::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:04::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:04::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:04::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:04::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:04::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:04::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:04::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:04::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:04::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:04::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:04::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:04::SCWPlatform::Boot application domain added for zynq_fsbl -TRACE::2026-05-26.18:22:04::SCWPlatform::Generating the sources . -TRACE::2026-05-26.18:22:04::SCWBDomain::Generating boot domain sources. -TRACE::2026-05-26.18:22:04::SCWBDomain:: Generating the zynq_fsbl Application. -TRACE::2026-05-26.18:22:04::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:04::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:04::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:04::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:04::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:04::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:04::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:04::SCWMssOS::DEBUG: swdes dump -TRACE::2026-05-26.18:22:04::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:04::SCWMssOS::mss does not exists at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:04::SCWMssOS::Creating sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:04::SCWMssOS::Adding the swdes entry, created swdb /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:04::SCWMssOS::updating the scw layer changes to swdes at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:04::SCWMssOS::Writing mss at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:04::SCWMssOS::Completed writing the mss file at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp -TRACE::2026-05-26.18:22:04::SCWMssOS::Picking up changes from newly written mss file into SCW Layer. -TRACE::2026-05-26.18:22:04::SCWMssOS::Updated the changes from newly written mss file into SCW Layer. -TRACE::2026-05-26.18:22:04::SCWBDomain::Completed writing the mss file at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp -TRACE::2026-05-26.18:22:06::SCWPlatform::Generating sources Done. -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump -TRACE::2026-05-26.18:22:06::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system -TRACE::2026-05-26.18:22:06::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-26.18:22:06::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:06::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "platFsblTarget": "ps7_cortexa9_0", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ", - "platPreBuiltFlag": false, - "platformSamplesDir": "", - "platActiveSys": "NewInstCal_bsp", - "systems": [{ - "systemName": "NewInstCal_bsp", - "systemDesc": "NewInstCal_bsp", - "sysIsBootAutoGen": "true", - "systemDispName": "NewInstCal_bsp", - "sysActiveDom": "zynq_fsbl", - "sysDefaultDom": "", - "domains": [{ - "domainName": "zynq_fsbl", - "domainDispName": "zynq_fsbl", - "domainDesc": "FSBL Application BSP - Auto Generated.", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "debugEnable": "", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "88a630cf45945e27dbb40d72cff1145a", - "compatibleApp": "zynq_fsbl", - "domType": "bootDomain", - "arch": "32-bit", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["xilffs:5.1", "xilrsa:1.7"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }] - }] -} -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWDomain::checking for install qemu data : -TRACE::2026-05-26.18:22:06::SCWDomain:: Using the QEMU Data from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/ -TRACE::2026-05-26.18:22:06::SCWDomain:: Using the QEMU args from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWDomain::Qemu Directory name is changed from "" to "qemu" -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::mss does not exists at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Creating sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Adding the swdes entry, created swdb /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::updating the scw layer changes to swdes at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Writing mss at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writing the mss file at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp -TRACE::2026-05-26.18:22:06::SCWMssOS::Picking up changes from newly written mss file into SCW Layer. -TRACE::2026-05-26.18:22:06::SCWMssOS::Updated the changes from newly written mss file into SCW Layer. -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writing the mss file at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp -TRACE::2026-05-26.18:22:06::SCWMssOS::Forcing BSP Sources regeneration. -TRACE::2026-05-26.18:22:06::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:06::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:06::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Adding the swdes entry, mss present, able to open swdb /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-26.18:22:06::SCWMssOS::Writing the mss file completed /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "platFsblTarget": "ps7_cortexa9_0", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ", - "platPreBuiltFlag": false, - "platformSamplesDir": "", - "platActiveSys": "NewInstCal_bsp", - "systems": [{ - "systemName": "NewInstCal_bsp", - "systemDesc": "NewInstCal_bsp", - "sysIsBootAutoGen": "true", - "systemDispName": "NewInstCal_bsp", - "sysActiveDom": "standalone_domain", - "sysDefaultDom": "standalone_domain", - "domains": [{ - "domainName": "zynq_fsbl", - "domainDispName": "zynq_fsbl", - "domainDesc": "FSBL Application BSP - Auto Generated.", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "debugEnable": "", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "88a630cf45945e27dbb40d72cff1145a", - "compatibleApp": "zynq_fsbl", - "domType": "bootDomain", - "arch": "32-bit", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["xilffs:5.1", "xilrsa:1.7"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }, { - "domainName": "standalone_domain", - "domainDispName": "standalone_domain", - "domainDesc": "standalone_domain", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "qemuArgs": "/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt", - "qemuData": "/resources/NewInstCal_bsp/standalone_domain/qemu", - "debugEnable": "False", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "2d072b4c02d1a56550682e3a117d4e42", - "compatibleApp": "", - "domType": "mssDomain", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": [], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }] - }] -} -LOG::2026-05-26.18:22:06::SCWPlatform::Started generating the artifacts platform NewInstCal_bsp -TRACE::2026-05-26.18:22:06::SCWPlatform::Sanity checking of platform is completed -LOG::2026-05-26.18:22:06::SCWPlatform::Started generating the artifacts for system configuration NewInstCal_bsp -LOG::2026-05-26.18:22:06::SCWSystem::Checking the domain zynq_fsbl -LOG::2026-05-26.18:22:06::SCWSystem::Doing application build for : zynq_fsbl -TRACE::2026-05-26.18:22:06::SCWBDomain::Not a forced makefile updation, No changes are present. -TRACE::2026-05-26.18:22:06::SCWDomain::Skipping the build for domain : zynq_fsbl -LOG::2026-05-26.18:22:06::SCWSystem::Checking the domain standalone_domain -LOG::2026-05-26.18:22:06::SCWSystem::Not a boot domain -LOG::2026-05-26.18:22:06::SCWSystem::Started Processing the domain standalone_domain -TRACE::2026-05-26.18:22:06::SCWDomain::Generating domain artifcats -TRACE::2026-05-26.18:22:06::SCWMssOS::Generating standalone artifcats -TRACE::2026-05-26.18:22:06::SCWMssOS::Copying the qemu file from /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt To /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/qemu/ -TRACE::2026-05-26.18:22:06::SCWMssOS::Copying the qemu file from /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt To /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/qemu/ -TRACE::2026-05-26.18:22:06::SCWMssOS:: Copying the user libraries. -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writing the mss file at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp -TRACE::2026-05-26.18:22:06::SCWMssOS::Mss edits present, copying mssfile into export location /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::bsp generated is upto date with the mss file. Skipping bsp generation. -TRACE::2026-05-26.18:22:06::SCWMssOS::BSP is already built. skipping the bsp build ... -TRACE::2026-05-26.18:22:06::SCWDomain::Skipping the build for domain : standalone_domain -TRACE::2026-05-26.18:22:06::SCWMssOS::skipping the bsp build ... -TRACE::2026-05-26.18:22:06::SCWMssOS::Copying to export directory. -TRACE::2026-05-26.18:22:06::SCWMssOS:: Checking if to create the Supporting Applications -TRACE::2026-05-26.18:22:06::SCWMssOS:: No Linux domain exists, trying to generate FSBL -TRACE::2026-05-26.18:22:06::SCWMssOS:: Completed Standalone Artifacts creation -LOG::2026-05-26.18:22:06::SCWSystem::Completed Processing the domain standalone_domain -LOG::2026-05-26.18:22:06::SCWSystem::Completed Processing the sysconfig NewInstCal_bsp -LOG::2026-05-26.18:22:06::SCWPlatform::Completed generating the artifacts for system configuration NewInstCal_bsp -TRACE::2026-05-26.18:22:06::SCWPlatform::Started preparing the platform -TRACE::2026-05-26.18:22:06::SCWSystem::Writing the bif file for system config NewInstCal_bsp -TRACE::2026-05-26.18:22:06::SCWSystem::dir created -TRACE::2026-05-26.18:22:06::SCWSystem::Writing the bif -TRACE::2026-05-26.18:22:06::SCWPlatform::Started writing the spfm file -TRACE::2026-05-26.18:22:06::SCWPlatform::Started writing the xpfm file -TRACE::2026-05-26.18:22:06::SCWPlatform::Completed generating the platform -TRACE::2026-05-26.18:22:06::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:06::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:06::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:06::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "platFsblTarget": "ps7_cortexa9_0", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ", - "platPreBuiltFlag": false, - "platformSamplesDir": "", - "platActiveSys": "NewInstCal_bsp", - "systems": [{ - "systemName": "NewInstCal_bsp", - "systemDesc": "NewInstCal_bsp", - "sysIsBootAutoGen": "true", - "systemDispName": "NewInstCal_bsp", - "sysActiveDom": "standalone_domain", - "sysDefaultDom": "standalone_domain", - "domains": [{ - "domainName": "zynq_fsbl", - "domainDispName": "zynq_fsbl", - "domainDesc": "FSBL Application BSP - Auto Generated.", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "debugEnable": "", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "88a630cf45945e27dbb40d72cff1145a", - "compatibleApp": "zynq_fsbl", - "domType": "bootDomain", - "arch": "32-bit", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["xilffs:5.1", "xilrsa:1.7"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }, { - "domainName": "standalone_domain", - "domainDispName": "standalone_domain", - "domainDesc": "standalone_domain", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "qemuArgs": "/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt", - "qemuData": "/resources/NewInstCal_bsp/standalone_domain/qemu", - "debugEnable": "False", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "2d072b4c02d1a56550682e3a117d4e42", - "compatibleApp": "", - "domType": "mssDomain", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": [], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }] - }] -} -KEYINFO::2026-05-26.18:22:06::SCWPlatform::updated the xpfm file. -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:06::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:06::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:06::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "platFsblTarget": "ps7_cortexa9_0", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ", - "platPreBuiltFlag": false, - "platformSamplesDir": "", - "platActiveSys": "NewInstCal_bsp", - "systems": [{ - "systemName": "NewInstCal_bsp", - "systemDesc": "NewInstCal_bsp", - "sysIsBootAutoGen": "true", - "systemDispName": "NewInstCal_bsp", - "sysActiveDom": "standalone_domain", - "sysDefaultDom": "standalone_domain", - "domains": [{ - "domainName": "zynq_fsbl", - "domainDispName": "zynq_fsbl", - "domainDesc": "FSBL Application BSP - Auto Generated.", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "debugEnable": "", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "88a630cf45945e27dbb40d72cff1145a", - "compatibleApp": "zynq_fsbl", - "domType": "bootDomain", - "arch": "32-bit", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["xilffs:5.1", "xilrsa:1.7"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }, { - "domainName": "standalone_domain", - "domainDispName": "standalone_domain", - "domainDesc": "standalone_domain", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "qemuArgs": "/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt", - "qemuData": "/resources/NewInstCal_bsp/standalone_domain/qemu", - "debugEnable": "False", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "2d072b4c02d1a56550682e3a117d4e42", - "compatibleApp": "", - "domType": "mssDomain", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": [], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }] - }] -} -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:06::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:06::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:06::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "platFsblTarget": "ps7_cortexa9_0", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ", - "platPreBuiltFlag": false, - "platformSamplesDir": "", - "platActiveSys": "NewInstCal_bsp", - "systems": [{ - "systemName": "NewInstCal_bsp", - "systemDesc": "NewInstCal_bsp", - "sysIsBootAutoGen": "true", - "systemDispName": "NewInstCal_bsp", - "sysActiveDom": "standalone_domain", - "sysDefaultDom": "standalone_domain", - "domains": [{ - "domainName": "zynq_fsbl", - "domainDispName": "zynq_fsbl", - "domainDesc": "FSBL Application BSP - Auto Generated.", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "debugEnable": "", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "88a630cf45945e27dbb40d72cff1145a", - "compatibleApp": "zynq_fsbl", - "domType": "bootDomain", - "arch": "32-bit", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["xilffs:5.1", "xilrsa:1.7"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }, { - "domainName": "standalone_domain", - "domainDispName": "standalone on ps7_cortexa9_0", - "domainDesc": "standalone_domain", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "qemuArgs": "/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt", - "qemuData": "/resources/NewInstCal_bsp/standalone_domain/qemu", - "debugEnable": "False", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "2d072b4c02d1a56550682e3a117d4e42", - "compatibleApp": "", - "domType": "mssDomain", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": [], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }] - }] -} -TRACE::2026-05-26.18:22:06::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:06::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:06::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:06::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:06::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Opened existing hwdb system_wrapper_0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:06::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:06::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "platFsblTarget": "ps7_cortexa9_0", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ", - "platPreBuiltFlag": false, - "platformSamplesDir": "", - "platActiveSys": "NewInstCal_bsp", - "systems": [{ - "systemName": "NewInstCal_bsp", - "systemDesc": "NewInstCal_bsp", - "sysIsBootAutoGen": "true", - "systemDispName": "NewInstCal_bsp", - "sysActiveDom": "standalone_domain", - "sysDefaultDom": "standalone_domain", - "domains": [{ - "domainName": "zynq_fsbl", - "domainDispName": "zynq_fsbl", - "domainDesc": "FSBL Application BSP - Auto Generated.", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "debugEnable": "", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "88a630cf45945e27dbb40d72cff1145a", - "compatibleApp": "zynq_fsbl", - "domType": "bootDomain", - "arch": "32-bit", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["xilffs:5.1", "xilrsa:1.7"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }, { - "domainName": "standalone_domain", - "domainDispName": "standalone on ps7_cortexa9_0", - "domainDesc": "standalone_domain", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "qemuArgs": "/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt", - "qemuData": "/resources/NewInstCal_bsp/standalone_domain/qemu", - "debugEnable": "False", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "2d072b4c02d1a56550682e3a117d4e42", - "compatibleApp": "", - "domType": "mssDomain", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": [], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }] - }] -} -TRACE::2026-05-26.18:22:06::SCWPlatform::Clearing the existing platform -TRACE::2026-05-26.18:22:06::SCWSystem::Clearing the existing sysconfig -TRACE::2026-05-26.18:22:06::SCWBDomain::clearing the fsbl build -TRACE::2026-05-26.18:22:06::SCWMssOS::Removing the swdes entry for /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWMssOS::Removing the swdes entry for /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:06::SCWSystem::Clearing the domains completed. -TRACE::2026-05-26.18:22:06::SCWPlatform::Clearing the opened hw db. -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform location is /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Removing the HwDB with name /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:06::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:06::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:06::SCWPlatform::Do not have an existing db opened. -TRACE::2026-05-26.18:22:08::SCWPlatform::Opened new HwDB with name system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWReader::Active system found as NewInstCal_bsp -TRACE::2026-05-26.18:22:08::SCWReader::Handling sysconfig NewInstCal_bsp -TRACE::2026-05-26.18:22:08::SCWDomain::checking for install qemu data : -TRACE::2026-05-26.18:22:08::SCWDomain:: Using the QEMU Data from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/ -TRACE::2026-05-26.18:22:08::SCWDomain:: Using the QEMU args from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:08::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:08::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:08::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:08::SCWReader::Boot application domain added for zynq_fsbl -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:08::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:08::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::DEBUG: swdes dump -TRACE::2026-05-26.18:22:08::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system -TRACE::2026-05-26.18:22:08::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-26.18:22:08::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:08::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:08::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:08::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS:: library already available in sw design: xilffs:5.1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:08::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:08::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:08::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS:: library already available in sw design: xilrsa:1.7 -TRACE::2026-05-26.18:22:08::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:08::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:08::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:08::SCWReader::Adding prebuilt librarypaths as -TRACE::2026-05-26.18:22:08::SCWReader::Adding prebuilt incpaths as -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:08::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:08::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:08::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWReader::No isolation master present -TRACE::2026-05-26.18:22:08::SCWDomain::checking for install qemu data : -TRACE::2026-05-26.18:22:08::SCWDomain:: Using the QEMU Data from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/ -TRACE::2026-05-26.18:22:08::SCWDomain:: Using the QEMU args from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:08::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:08::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:08::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:08::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:08::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-26.18:22:08::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-26.18:22:08::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:08::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:08::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:08::SCWReader::Adding prebuilt librarypaths as -TRACE::2026-05-26.18:22:08::SCWReader::Adding prebuilt incpaths as -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:08::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:08::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:08::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:08::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:08::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:08::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:08::SCWReader::No isolation master present -TRACE::2026-05-26.18:22:10::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:10::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:10::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:10::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:10::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:10::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:10::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:10::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:10::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:10::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:10::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:10::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:10::SCWMssOS::In reload Mss file. -TRACE::2026-05-26.18:22:10::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:10::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:10::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:10::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:10::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:10::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:10::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:10::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:10::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:10::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:10::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:10::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:10::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:10::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:10::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-26.18:22:10::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-26.18:22:10::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:10::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:10::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:10::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:10::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:10::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:10::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:10::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:10::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:10::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:10::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:10::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:10::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:10::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:10::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:10::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:10::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:10::SCWMssOS::Removing the swdes entry for /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:14::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:14::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:14::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:14::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:14::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:14::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:14::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:14::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:14::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:14::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:14::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:14::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:14::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:14::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:14::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-26.18:22:14::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-26.18:22:14::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:19::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:19::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:19::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:19::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:19::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:19::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:19::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:19::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:19::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:19::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:19::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:19::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:19::SCWMssOS::Adding Library: lwip213:1.1 -TRACE::2026-05-26.18:22:19::SCWMssOS::Added Library: lwip213 -TRACE::2026-05-26.18:22:19::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:19::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:19::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:19::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:19::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:19::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:19::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:19::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:19::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:19::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:19::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:19::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:23::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:23::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:23::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:23::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:23::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:23::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:23::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:23::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:23::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:23::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:23::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ", - "platPreBuiltFlag": false, - "platformSamplesDir": "", - "platActiveSys": "NewInstCal_bsp", - "systems": [{ - "systemName": "NewInstCal_bsp", - "systemDesc": "NewInstCal_bsp", - "sysIsBootAutoGen": "true", - "systemDispName": "NewInstCal_bsp", - "sysActiveDom": "standalone_domain", - "sysDefaultDom": "standalone_domain", - "domains": [{ - "domainName": "zynq_fsbl", - "domainDispName": "zynq_fsbl", - "domainDesc": "FSBL Application BSP - Auto Generated.", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "debugEnable": "", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "88a630cf45945e27dbb40d72cff1145a", - "compatibleApp": "zynq_fsbl", - "domType": "bootDomain", - "arch": "32-bit", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["xilffs:5.1", "xilrsa:1.7"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }, { - "domainName": "standalone_domain", - "domainDispName": "standalone on ps7_cortexa9_0", - "domainDesc": "standalone_domain", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "qemuArgs": "/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt", - "qemuData": "/resources/NewInstCal_bsp/standalone_domain/qemu", - "debugEnable": "False", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "2d072b4c02d1a56550682e3a117d4e42", - "compatibleApp": "", - "domType": "mssDomain", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["lwip213:1.1"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }] - }] -} -TRACE::2026-05-26.18:22:23::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:23::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:23::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:23::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:23::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:23::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::Removing the swdes entry for /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::In reload Mss file. -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:23::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:23::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:23::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-26.18:22:23::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-26.18:22:23::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:23::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:23::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:23::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS:: library already available in sw design: lwip213:1.1 -TRACE::2026-05-26.18:22:23::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:22:23::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:22:23::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:23::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:23::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:23::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::Removing the swdes entry for /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:22:23::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:22:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:22:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:22:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:22:23::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:22:23::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-26.18:22:23::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-26.18:22:23::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:22:23::SCWMssOS::Completed writing the mss file at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp -TRACE::2026-05-26.18:22:23::SCWMssOS::Forcing BSP Sources regeneration. -KEYINFO::2026-05-26.18:22:24::SCWMssOS::Removing file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system_0.mss -LOG::2026-05-26.18:24:41::SCWPlatform::Started generating the artifacts platform NewInstCal_bsp -TRACE::2026-05-26.18:24:41::SCWPlatform::Sanity checking of platform is completed -LOG::2026-05-26.18:24:41::SCWPlatform::Started generating the artifacts for system configuration NewInstCal_bsp -LOG::2026-05-26.18:24:41::SCWSystem::Checking the domain zynq_fsbl -LOG::2026-05-26.18:24:41::SCWSystem::Doing application build for : zynq_fsbl -TRACE::2026-05-26.18:24:41::SCWBDomain::Not a forced makefile updation, No changes are present. -TRACE::2026-05-26.18:24:41::SCWDomain::Building the domain as part of full build : zynq_fsbl -TRACE::2026-05-26.18:24:41::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:41::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:41::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:41::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:24:41::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:41::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:24:41::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:24:41::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:24:41::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:24:41::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:24:41::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:24:41::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:24:41::SCWBDomain::Completed writing the mss file at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp -TRACE::2026-05-26.18:24:41::SCWBDomain::bsp generated is upto date with the mss file. Skipping bsp generation. -TRACE::2026-05-26.18:24:41::SCWBDomain::Not a forced makefile updation, No changes are present. -TRACE::2026-05-26.18:24:41::SCWBDomain::System Command Ran cd /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl ; bash -c " make -C zynq_fsbl_bsp ; make " -TRACE::2026-05-26.18:24:41::SCWBDomain::make: Entering directory '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp' - -TRACE::2026-05-26.18:24:41::SCWBDomain::make --no-print-directory seq_libs - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm- -TRACE::2026-05-26.18:24:41::SCWBDomain::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a -TRACE::2026-05-26.18:24:41::SCWBDomain::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no -TRACE::2026-05-26.18:24:41::SCWBDomain::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi -TRACE::2026-05-26.18:24:41::SCWBDomain::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-26.18:24:41::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-26.18:24:41::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_8/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:41::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:41::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_9/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-26.18:24:41::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-26.18:24:41::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_19/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:41::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:41::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_12/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:41::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:41::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_11/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:41::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:41::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scugic_v5_2/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:41::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:41::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_5/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea -TRACE::2026-05-26.18:24:41::SCWBDomain::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:41::SCWBDomain:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:41::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:41::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/sdps_v4_2/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:41::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:41::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/standalone_v9_0/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none- -TRACE::2026-05-26.18:24:41::SCWBDomain::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha -TRACE::2026-05-26.18:24:41::SCWBDomain::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_13/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:41::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:41::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_7/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:41::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:41::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilffs_v5_1/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v5_1/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:41::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:41::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_7/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:41::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:41::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/xilrsa_v1_7/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-26.18:24:41::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-26.18:24:41::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Finished building libraries sequentially. - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -j 30 --no-print-directory par_libs - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm- -TRACE::2026-05-26.18:24:41::SCWBDomain::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a -TRACE::2026-05-26.18:24:41::SCWBDomain::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no -TRACE::2026-05-26.18:24:41::SCWBDomain::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi -TRACE::2026-05-26.18:24:41::SCWBDomain::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_8/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-26.18:24:41::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-26.18:24:41::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:41::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:41::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_9/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-26.18:24:41::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-26.18:24:41::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_19/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:41::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:41::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_12/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_11/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:41::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:41::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:41::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:41::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scugic_v5_2/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:41::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:41::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_5/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea -TRACE::2026-05-26.18:24:41::SCWBDomain::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:41::SCWBDomain:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:41::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:41::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/sdps_v4_2/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:41::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:41::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/standalone_v9_0/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none- -TRACE::2026-05-26.18:24:41::SCWBDomain::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha -TRACE::2026-05-26.18:24:41::SCWBDomain::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_7/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:41::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:41::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilffs_v5_1/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v5_1/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:41::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:41::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_7/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:41::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:41::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_13/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:41::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:41::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-non -TRACE::2026-05-26.18:24:41::SCWBDomain::e-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi= -TRACE::2026-05-26.18:24:41::SCWBDomain::hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_2/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none- -TRACE::2026-05-26.18:24:41::SCWBDomain::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha -TRACE::2026-05-26.18:24:41::SCWBDomain::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-26.18:24:41::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-26.18:24:41::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_8/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-26.18:24:41::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-26.18:24:41::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_9/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-26.18:24:41::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-26.18:24:41::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_19/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_12/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:41::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:41::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_11/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:41::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:41::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:41::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:41::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/scugic_v5_2/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_5/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-26.18:24:41::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-26.18:24:41::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-26.18:24:41::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-26.18:24:41::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/sdps_v4_2/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-26.18:24:41::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-26.18:24:41::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-26.18:24:41::SCWBDomain::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-26.18:24:41::SCWBDomain::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/standalone_v9_0/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:41::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:41::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_13/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:41::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:41::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_7/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-26.18:24:41::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-26.18:24:41::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/xilffs_v5_1/src - -TRACE::2026-05-26.18:24:41::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v5_1/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-26.18:24:41::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-26.18:24:41::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:41::SCWBDomain::Finished building libraries parallelly. - -TRACE::2026-05-26.18:24:41::SCWBDomain::make --no-print-directory archive - -TRACE::2026-05-26.18:24:41::SCWBDomain::arm-none-eabi-ar -r ps7_cortexa9_0/lib/libxil.a ps7_cortexa9_0/lib/_exit.o ps7_cortexa9_0/lib/_open.o ps7_cortexa9_0/lib/_sbrk -TRACE::2026-05-26.18:24:41::SCWBDomain::.o ps7_cortexa9_0/lib/abort.o ps7_cortexa9_0/lib/asm_vectors.o ps7_cortexa9_0/lib/boot.o ps7_cortexa9_0/lib/close.o ps7_cortexa -TRACE::2026-05-26.18:24:41::SCWBDomain::9_0/lib/cpputest_time.o ps7_cortexa9_0/lib/cpu_init.o ps7_cortexa9_0/lib/errno.o ps7_cortexa9_0/lib/fcntl.o ps7_cortexa9_0/lib/ -TRACE::2026-05-26.18:24:41::SCWBDomain::fstat.o ps7_cortexa9_0/lib/getentropy.o ps7_cortexa9_0/lib/getpid.o ps7_cortexa9_0/lib/inbyte.o ps7_cortexa9_0/lib/isatty.o ps7 -TRACE::2026-05-26.18:24:41::SCWBDomain::_cortexa9_0/lib/kill.o ps7_cortexa9_0/lib/lseek.o ps7_cortexa9_0/lib/open.o ps7_cortexa9_0/lib/outbyte.o ps7_cortexa9_0/lib/pri -TRACE::2026-05-26.18:24:41::SCWBDomain::nt.o ps7_cortexa9_0/lib/putnum.o ps7_cortexa9_0/lib/read.o ps7_cortexa9_0/lib/sbrk.o ps7_cortexa9_0/lib/sleep.o ps7_cortexa9_0/ -TRACE::2026-05-26.18:24:41::SCWBDomain::lib/time.o ps7_cortexa9_0/lib/translation_table.o ps7_cortexa9_0/lib/unlink.o ps7_cortexa9_0/lib/usleep.o ps7_cortexa9_0/lib/ve -TRACE::2026-05-26.18:24:41::SCWBDomain::ctors.o ps7_cortexa9_0/lib/write.o ps7_cortexa9_0/lib/xadcps.o ps7_cortexa9_0/lib/xadcps_g.o ps7_cortexa9_0/lib/xadcps_intr.o p -TRACE::2026-05-26.18:24:41::SCWBDomain::s7_cortexa9_0/lib/xadcps_selftest.o ps7_cortexa9_0/lib/xadcps_sinit.o ps7_cortexa9_0/lib/xcoresightpsdcc.o ps7_cortexa9_0/lib/x -TRACE::2026-05-26.18:24:41::SCWBDomain::devcfg.o ps7_cortexa9_0/lib/xdevcfg_g.o ps7_cortexa9_0/lib/xdevcfg_hw.o ps7_cortexa9_0/lib/xdevcfg_intr.o ps7_cortexa9_0/lib/xd -TRACE::2026-05-26.18:24:41::SCWBDomain::evcfg_selftest.o ps7_cortexa9_0/lib/xdevcfg_sinit.o ps7_cortexa9_0/lib/xdmaps.o ps7_cortexa9_0/lib/xdmaps_g.o ps7_cortexa9_0/li -TRACE::2026-05-26.18:24:41::SCWBDomain::b/xdmaps_hw.o ps7_cortexa9_0/lib/xdmaps_selftest.o ps7_cortexa9_0/lib/xdmaps_sinit.o ps7_cortexa9_0/lib/xemacps.o ps7_cortexa9_ -TRACE::2026-05-26.18:24:41::SCWBDomain::0/lib/xemacps_bdring.o ps7_cortexa9_0/lib/xemacps_control.o ps7_cortexa9_0/lib/xemacps_g.o ps7_cortexa9_0/lib/xemacps_hw.o ps7_ -TRACE::2026-05-26.18:24:41::SCWBDomain::cortexa9_0/lib/xemacps_intr.o ps7_cortexa9_0/lib/xemacps_sinit.o ps7_cortexa9_0/lib/xgpiops.o ps7_cortexa9_0/lib/xgpiops_g.o ps -TRACE::2026-05-26.18:24:41::SCWBDomain::7_cortexa9_0/lib/xgpiops_hw.o ps7_cortexa9_0/lib/xgpiops_intr.o ps7_cortexa9_0/lib/xgpiops_selftest.o ps7_cortexa9_0/lib/xgpiop -TRACE::2026-05-26.18:24:41::SCWBDomain::s_sinit.o ps7_cortexa9_0/lib/xil-crt0.o ps7_cortexa9_0/lib/xil_assert.o ps7_cortexa9_0/lib/xil_cache.o ps7_cortexa9_0/lib/xil_c -TRACE::2026-05-26.18:24:41::SCWBDomain::locking.o ps7_cortexa9_0/lib/xil_exception.o ps7_cortexa9_0/lib/xil_mem.o ps7_cortexa9_0/lib/xil_misc_psreset_api.o ps7_cortexa -TRACE::2026-05-26.18:24:41::SCWBDomain::9_0/lib/xil_mmu.o ps7_cortexa9_0/lib/xil_printf.o ps7_cortexa9_0/lib/xil_sleepcommon.o ps7_cortexa9_0/lib/xil_sleeptimer.o ps7_ -TRACE::2026-05-26.18:24:41::SCWBDomain::cortexa9_0/lib/xil_spinlock.o ps7_cortexa9_0/lib/xil_testcache.o ps7_cortexa9_0/lib/xil_testio.o ps7_cortexa9_0/lib/xil_testmem -TRACE::2026-05-26.18:24:41::SCWBDomain::.o ps7_cortexa9_0/lib/xil_util.o ps7_cortexa9_0/lib/xinterrupt_wrap.o ps7_cortexa9_0/lib/xl2cc_counter.o ps7_cortexa9_0/lib/xpl -TRACE::2026-05-26.18:24:41::SCWBDomain::atform_info.o ps7_cortexa9_0/lib/xpm_counter.o ps7_cortexa9_0/lib/xpm_init.o ps7_cortexa9_0/lib/xqspips.o ps7_cortexa9_0/lib/xq -TRACE::2026-05-26.18:24:41::SCWBDomain::spips_g.o ps7_cortexa9_0/lib/xqspips_hw.o ps7_cortexa9_0/lib/xqspips_options.o ps7_cortexa9_0/lib/xqspips_selftest.o ps7_cortex -TRACE::2026-05-26.18:24:41::SCWBDomain::a9_0/lib/xqspips_sinit.o ps7_cortexa9_0/lib/xscugic.o ps7_cortexa9_0/lib/xscugic_g.o ps7_cortexa9_0/lib/xscugic_hw.o ps7_cortex -TRACE::2026-05-26.18:24:41::SCWBDomain::a9_0/lib/xscugic_intr.o ps7_cortexa9_0/lib/xscugic_selftest.o ps7_cortexa9_0/lib/xscugic_sinit.o ps7_cortexa9_0/lib/xscutimer.o -TRACE::2026-05-26.18:24:41::SCWBDomain:: ps7_cortexa9_0/lib/xscutimer_g.o ps7_cortexa9_0/lib/xscutimer_selftest.o ps7_cortexa9_0/lib/xscutimer_sinit.o ps7_cortexa9_0/l -TRACE::2026-05-26.18:24:41::SCWBDomain::ib/xscuwdt.o ps7_cortexa9_0/lib/xscuwdt_g.o ps7_cortexa9_0/lib/xscuwdt_selftest.o ps7_cortexa9_0/lib/xscuwdt_sinit.o ps7_cortex -TRACE::2026-05-26.18:24:41::SCWBDomain::a9_0/lib/xsdps.o ps7_cortexa9_0/lib/xsdps_card.o ps7_cortexa9_0/lib/xsdps_g.o ps7_cortexa9_0/lib/xsdps_host.o ps7_cortexa9_0/li -TRACE::2026-05-26.18:24:41::SCWBDomain::b/xsdps_options.o ps7_cortexa9_0/lib/xsdps_sinit.o ps7_cortexa9_0/lib/xtime_l.o ps7_cortexa9_0/lib/xuartps.o ps7_cortexa9_0/lib -TRACE::2026-05-26.18:24:41::SCWBDomain::/xuartps_g.o ps7_cortexa9_0/lib/xuartps_hw.o ps7_cortexa9_0/lib/xuartps_intr.o ps7_cortexa9_0/lib/xuartps_options.o ps7_cortexa -TRACE::2026-05-26.18:24:41::SCWBDomain::9_0/lib/xuartps_selftest.o ps7_cortexa9_0/lib/xuartps_sinit.o - -TRACE::2026-05-26.18:24:41::SCWBDomain::Finished building libraries - -TRACE::2026-05-26.18:24:41::SCWBDomain::make: Leaving directory '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp' - -TRACE::2026-05-26.18:24:41::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c fsbl_hooks.c -o fsbl_hooks.o -Izynq_f -TRACE::2026-05-26.18:24:41::SCWBDomain::sbl_bsp/ps7_cortexa9_0/include -I. - -TRACE::2026-05-26.18:24:42::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c image_mover.c -o image_mover.o -Izynq -TRACE::2026-05-26.18:24:42::SCWBDomain::_fsbl_bsp/ps7_cortexa9_0/include -I. - -TRACE::2026-05-26.18:24:42::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c main.c -o main.o -Izynq_fsbl_bsp/ps7_ -TRACE::2026-05-26.18:24:42::SCWBDomain::cortexa9_0/include -I. - -TRACE::2026-05-26.18:24:42::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c md5.c -o md5.o -Izynq_fsbl_bsp/ps7_co -TRACE::2026-05-26.18:24:42::SCWBDomain::rtexa9_0/include -I. - -TRACE::2026-05-26.18:24:42::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c nand.c -o nand.o -Izynq_fsbl_bsp/ps7_ -TRACE::2026-05-26.18:24:42::SCWBDomain::cortexa9_0/include -I. - -TRACE::2026-05-26.18:24:42::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c nor.c -o nor.o -Izynq_fsbl_bsp/ps7_co -TRACE::2026-05-26.18:24:42::SCWBDomain::rtexa9_0/include -I. - -TRACE::2026-05-26.18:24:42::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c pcap.c -o pcap.o -Izynq_fsbl_bsp/ps7_ -TRACE::2026-05-26.18:24:42::SCWBDomain::cortexa9_0/include -I. - -TRACE::2026-05-26.18:24:42::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c ps7_init.c -o ps7_init.o -Izynq_fsbl_ -TRACE::2026-05-26.18:24:42::SCWBDomain::bsp/ps7_cortexa9_0/include -I. - -TRACE::2026-05-26.18:24:42::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c qspi.c -o qspi.o -Izynq_fsbl_bsp/ps7_ -TRACE::2026-05-26.18:24:42::SCWBDomain::cortexa9_0/include -I. - -TRACE::2026-05-26.18:24:42::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c rsa.c -o rsa.o -Izynq_fsbl_bsp/ps7_co -TRACE::2026-05-26.18:24:42::SCWBDomain::rtexa9_0/include -I. - -TRACE::2026-05-26.18:24:42::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c sd.c -o sd.o -Izynq_fsbl_bsp/ps7_cort -TRACE::2026-05-26.18:24:42::SCWBDomain::exa9_0/include -I. - -TRACE::2026-05-26.18:24:42::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c fsbl_handoff.S -o fsbl_handoff.o -Izy -TRACE::2026-05-26.18:24:42::SCWBDomain::nq_fsbl_bsp/ps7_cortexa9_0/include -I. - -TRACE::2026-05-26.18:24:42::SCWBDomain::arm-none-eabi-gcc -o fsbl.elf fsbl_handoff.o fsbl_hooks.o image_mover.o main.o md5.o nand.o nor.o pcap.o ps7_init.o qspi.o rsa. -TRACE::2026-05-26.18:24:42::SCWBDomain::o sd.o -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id -TRACE::2026-05-26.18:24:42::SCWBDomain::=none -specs=Xilinx.spec -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end- -TRACE::2026-05-26.18:24:42::SCWBDomain::group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group -Wl,--gc-sections -Lzynq_fsbl_bsp/p -TRACE::2026-05-26.18:24:42::SCWBDomain::s7_cortexa9_0/lib -L./ -Tlscript.ld - -LOG::2026-05-26.18:24:42::SCWSystem::Checking the domain standalone_domain -LOG::2026-05-26.18:24:42::SCWSystem::Not a boot domain -LOG::2026-05-26.18:24:42::SCWSystem::Started Processing the domain standalone_domain -TRACE::2026-05-26.18:24:42::SCWDomain::Generating domain artifcats -TRACE::2026-05-26.18:24:42::SCWMssOS::Generating standalone artifcats -TRACE::2026-05-26.18:24:42::SCWMssOS::Copying the qemu file from /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt To /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/qemu/ -TRACE::2026-05-26.18:24:42::SCWMssOS::Copying the qemu file from /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt To /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/qemu/ -TRACE::2026-05-26.18:24:42::SCWMssOS:: Copying the user libraries. -TRACE::2026-05-26.18:24:42::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:42::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:42::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:42::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:24:42::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:42::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:24:42::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:24:42::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:24:42::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:24:42::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:24:42::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:24:42::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:24:42::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:24:42::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:24:42::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-26.18:24:42::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-26.18:24:42::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:24:42::SCWMssOS::Completed writing the mss file at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp -TRACE::2026-05-26.18:24:42::SCWMssOS::Mss edits present, copying mssfile into export location /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:24:42::SCWMssOS::bsp generated is upto date with the mss file. Skipping bsp generation. -TRACE::2026-05-26.18:24:42::SCWMssOS::BSP is already built. skipping the bsp build ... -TRACE::2026-05-26.18:24:42::SCWDomain::Building the domain as part of full build : standalone_domain -TRACE::2026-05-26.18:24:42::SCWMssOS::doing bsp build ... -TRACE::2026-05-26.18:24:42::SCWMssOS::System Command Ran cd /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp ; bash -c "make " -TRACE::2026-05-26.18:24:42::SCWMssOS::make --no-print-directory seq_libs - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm- -TRACE::2026-05-26.18:24:42::SCWMssOS::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a -TRACE::2026-05-26.18:24:42::SCWMssOS::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no -TRACE::2026-05-26.18:24:42::SCWMssOS::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi -TRACE::2026-05-26.18:24:42::SCWMssOS::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-26.18:24:42::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-26.18:24:42::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_8/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:42::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:42::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_9/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-26.18:24:42::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-26.18:24:42::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_19/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:42::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:42::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_12/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:42::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:42::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/lwip213_v1_1/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/lwip213_v1_1/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:42::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:42::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_11/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:42::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:42::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scugic_v5_2/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:42::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:42::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_5/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea -TRACE::2026-05-26.18:24:42::SCWMssOS::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:42::SCWMssOS:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:42::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:42::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/sdps_v4_2/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:42::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:42::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/standalone_v9_0/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none- -TRACE::2026-05-26.18:24:42::SCWMssOS::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha -TRACE::2026-05-26.18:24:42::SCWMssOS::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_13/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:42::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:42::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_7/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:42::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:42::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/lwip213_v1_1/src - -TRACE::2026-05-26.18:24:42::SCWMssOS::make -C ps7_cortexa9_0/libsrc/lwip213_v1_1/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:42::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:42::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:42::SCWMssOS::Compiling lwip src and adapter files - -TRACE::2026-05-26.18:24:45::SCWMssOS::Finished building libraries sequentially. - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -j 30 --no-print-directory par_libs - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm- -TRACE::2026-05-26.18:24:45::SCWMssOS::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a -TRACE::2026-05-26.18:24:45::SCWMssOS::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no -TRACE::2026-05-26.18:24:45::SCWMssOS::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi -TRACE::2026-05-26.18:24:45::SCWMssOS::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-26.18:24:45::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-26.18:24:45::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_8/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:45::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:45::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_9/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_19/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-26.18:24:45::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-26.18:24:45::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:45::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:45::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_12/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:45::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:45::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/lwip213_v1_1/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/lwip213_v1_1/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:45::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:45::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_11/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scugic_v5_2/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:45::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:45::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_5/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:45::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:45::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea -TRACE::2026-05-26.18:24:45::SCWMssOS::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:45::SCWMssOS:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:45::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:45::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/sdps_v4_2/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:45::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:45::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/standalone_v9_0/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none- -TRACE::2026-05-26.18:24:45::SCWMssOS::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha -TRACE::2026-05-26.18:24:45::SCWMssOS::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_13/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:45::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:45::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_7/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-26.18:24:45::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-26.18:24:45::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-non -TRACE::2026-05-26.18:24:45::SCWMssOS::e-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi= -TRACE::2026-05-26.18:24:45::SCWMssOS::hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none- -TRACE::2026-05-26.18:24:45::SCWMssOS::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha -TRACE::2026-05-26.18:24:45::SCWMssOS::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_2/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-26.18:24:45::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-26.18:24:45::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_8/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-26.18:24:45::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-26.18:24:45::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_9/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_19/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-26.18:24:45::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-26.18:24:45::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:45::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:45::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_12/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:45::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:45::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_11/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:45::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:45::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/scugic_v5_2/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-26.18:24:45::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-26.18:24:45::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_5/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-26.18:24:45::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-26.18:24:45::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/sdps_v4_2/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-26.18:24:45::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-26.18:24:45::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-26.18:24:45::SCWMssOS::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-26.18:24:45::SCWMssOS::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/standalone_v9_0/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-26.18:24:45::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-26.18:24:45::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_13/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-26.18:24:45::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-26.18:24:45::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_7/src - -TRACE::2026-05-26.18:24:45::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-26.18:24:45::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-26.18:24:45::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-26.18:24:45::SCWMssOS::Finished building libraries parallelly. - -TRACE::2026-05-26.18:24:45::SCWMssOS::make --no-print-directory archive - -TRACE::2026-05-26.18:24:45::SCWMssOS::arm-none-eabi-ar -r ps7_cortexa9_0/lib/libxil.a ps7_cortexa9_0/lib/_exit.o ps7_cortexa9_0/lib/_open.o ps7_cortexa9_0/lib/_sbrk -TRACE::2026-05-26.18:24:45::SCWMssOS::.o ps7_cortexa9_0/lib/abort.o ps7_cortexa9_0/lib/asm_vectors.o ps7_cortexa9_0/lib/boot.o ps7_cortexa9_0/lib/close.o ps7_cortexa -TRACE::2026-05-26.18:24:45::SCWMssOS::9_0/lib/cpputest_time.o ps7_cortexa9_0/lib/cpu_init.o ps7_cortexa9_0/lib/errno.o ps7_cortexa9_0/lib/fcntl.o ps7_cortexa9_0/lib/ -TRACE::2026-05-26.18:24:45::SCWMssOS::fstat.o ps7_cortexa9_0/lib/getentropy.o ps7_cortexa9_0/lib/getpid.o ps7_cortexa9_0/lib/inbyte.o ps7_cortexa9_0/lib/isatty.o ps7 -TRACE::2026-05-26.18:24:45::SCWMssOS::_cortexa9_0/lib/kill.o ps7_cortexa9_0/lib/lseek.o ps7_cortexa9_0/lib/open.o ps7_cortexa9_0/lib/outbyte.o ps7_cortexa9_0/lib/pri -TRACE::2026-05-26.18:24:45::SCWMssOS::nt.o ps7_cortexa9_0/lib/putnum.o ps7_cortexa9_0/lib/read.o ps7_cortexa9_0/lib/sbrk.o ps7_cortexa9_0/lib/sleep.o ps7_cortexa9_0/ -TRACE::2026-05-26.18:24:45::SCWMssOS::lib/time.o ps7_cortexa9_0/lib/translation_table.o ps7_cortexa9_0/lib/unlink.o ps7_cortexa9_0/lib/usleep.o ps7_cortexa9_0/lib/ve -TRACE::2026-05-26.18:24:45::SCWMssOS::ctors.o ps7_cortexa9_0/lib/write.o ps7_cortexa9_0/lib/xadcps.o ps7_cortexa9_0/lib/xadcps_g.o ps7_cortexa9_0/lib/xadcps_intr.o p -TRACE::2026-05-26.18:24:45::SCWMssOS::s7_cortexa9_0/lib/xadcps_selftest.o ps7_cortexa9_0/lib/xadcps_sinit.o ps7_cortexa9_0/lib/xcoresightpsdcc.o ps7_cortexa9_0/lib/x -TRACE::2026-05-26.18:24:45::SCWMssOS::devcfg.o ps7_cortexa9_0/lib/xdevcfg_g.o ps7_cortexa9_0/lib/xdevcfg_hw.o ps7_cortexa9_0/lib/xdevcfg_intr.o ps7_cortexa9_0/lib/xd -TRACE::2026-05-26.18:24:45::SCWMssOS::evcfg_selftest.o ps7_cortexa9_0/lib/xdevcfg_sinit.o ps7_cortexa9_0/lib/xdmaps.o ps7_cortexa9_0/lib/xdmaps_g.o ps7_cortexa9_0/li -TRACE::2026-05-26.18:24:45::SCWMssOS::b/xdmaps_hw.o ps7_cortexa9_0/lib/xdmaps_selftest.o ps7_cortexa9_0/lib/xdmaps_sinit.o ps7_cortexa9_0/lib/xemacps.o ps7_cortexa9_ -TRACE::2026-05-26.18:24:45::SCWMssOS::0/lib/xemacps_bdring.o ps7_cortexa9_0/lib/xemacps_control.o ps7_cortexa9_0/lib/xemacps_g.o ps7_cortexa9_0/lib/xemacps_hw.o ps7_ -TRACE::2026-05-26.18:24:45::SCWMssOS::cortexa9_0/lib/xemacps_intr.o ps7_cortexa9_0/lib/xemacps_sinit.o ps7_cortexa9_0/lib/xgpiops.o ps7_cortexa9_0/lib/xgpiops_g.o ps -TRACE::2026-05-26.18:24:45::SCWMssOS::7_cortexa9_0/lib/xgpiops_hw.o ps7_cortexa9_0/lib/xgpiops_intr.o ps7_cortexa9_0/lib/xgpiops_selftest.o ps7_cortexa9_0/lib/xgpiop -TRACE::2026-05-26.18:24:45::SCWMssOS::s_sinit.o ps7_cortexa9_0/lib/xil-crt0.o ps7_cortexa9_0/lib/xil_assert.o ps7_cortexa9_0/lib/xil_cache.o ps7_cortexa9_0/lib/xil_c -TRACE::2026-05-26.18:24:45::SCWMssOS::locking.o ps7_cortexa9_0/lib/xil_exception.o ps7_cortexa9_0/lib/xil_mem.o ps7_cortexa9_0/lib/xil_misc_psreset_api.o ps7_cortexa -TRACE::2026-05-26.18:24:45::SCWMssOS::9_0/lib/xil_mmu.o ps7_cortexa9_0/lib/xil_printf.o ps7_cortexa9_0/lib/xil_sleepcommon.o ps7_cortexa9_0/lib/xil_sleeptimer.o ps7_ -TRACE::2026-05-26.18:24:45::SCWMssOS::cortexa9_0/lib/xil_spinlock.o ps7_cortexa9_0/lib/xil_testcache.o ps7_cortexa9_0/lib/xil_testio.o ps7_cortexa9_0/lib/xil_testmem -TRACE::2026-05-26.18:24:45::SCWMssOS::.o ps7_cortexa9_0/lib/xil_util.o ps7_cortexa9_0/lib/xinterrupt_wrap.o ps7_cortexa9_0/lib/xl2cc_counter.o ps7_cortexa9_0/lib/xpl -TRACE::2026-05-26.18:24:45::SCWMssOS::atform_info.o ps7_cortexa9_0/lib/xpm_counter.o ps7_cortexa9_0/lib/xpm_init.o ps7_cortexa9_0/lib/xqspips.o ps7_cortexa9_0/lib/xq -TRACE::2026-05-26.18:24:45::SCWMssOS::spips_g.o ps7_cortexa9_0/lib/xqspips_hw.o ps7_cortexa9_0/lib/xqspips_options.o ps7_cortexa9_0/lib/xqspips_selftest.o ps7_cortex -TRACE::2026-05-26.18:24:45::SCWMssOS::a9_0/lib/xqspips_sinit.o ps7_cortexa9_0/lib/xscugic.o ps7_cortexa9_0/lib/xscugic_g.o ps7_cortexa9_0/lib/xscugic_hw.o ps7_cortex -TRACE::2026-05-26.18:24:45::SCWMssOS::a9_0/lib/xscugic_intr.o ps7_cortexa9_0/lib/xscugic_selftest.o ps7_cortexa9_0/lib/xscugic_sinit.o ps7_cortexa9_0/lib/xscutimer.o -TRACE::2026-05-26.18:24:45::SCWMssOS:: ps7_cortexa9_0/lib/xscutimer_g.o ps7_cortexa9_0/lib/xscutimer_selftest.o ps7_cortexa9_0/lib/xscutimer_sinit.o ps7_cortexa9_0/l -TRACE::2026-05-26.18:24:45::SCWMssOS::ib/xscuwdt.o ps7_cortexa9_0/lib/xscuwdt_g.o ps7_cortexa9_0/lib/xscuwdt_selftest.o ps7_cortexa9_0/lib/xscuwdt_sinit.o ps7_cortex -TRACE::2026-05-26.18:24:45::SCWMssOS::a9_0/lib/xsdps.o ps7_cortexa9_0/lib/xsdps_card.o ps7_cortexa9_0/lib/xsdps_g.o ps7_cortexa9_0/lib/xsdps_host.o ps7_cortexa9_0/li -TRACE::2026-05-26.18:24:45::SCWMssOS::b/xsdps_options.o ps7_cortexa9_0/lib/xsdps_sinit.o ps7_cortexa9_0/lib/xtime_l.o ps7_cortexa9_0/lib/xuartps.o ps7_cortexa9_0/lib -TRACE::2026-05-26.18:24:45::SCWMssOS::/xuartps_g.o ps7_cortexa9_0/lib/xuartps_hw.o ps7_cortexa9_0/lib/xuartps_intr.o ps7_cortexa9_0/lib/xuartps_options.o ps7_cortexa -TRACE::2026-05-26.18:24:45::SCWMssOS::9_0/lib/xuartps_selftest.o ps7_cortexa9_0/lib/xuartps_sinit.o - -TRACE::2026-05-26.18:24:45::SCWMssOS::Finished building libraries - -TRACE::2026-05-26.18:24:45::SCWMssOS::Copying to export directory. -TRACE::2026-05-26.18:24:45::SCWMssOS:: Checking if to create the Supporting Applications -TRACE::2026-05-26.18:24:45::SCWMssOS:: No Linux domain exists, trying to generate FSBL -LOG::2026-05-26.18:24:45::SCWSystem::Completed Processing the domain standalone_domain -LOG::2026-05-26.18:24:45::SCWSystem::Completed Processing the sysconfig NewInstCal_bsp -LOG::2026-05-26.18:24:45::SCWPlatform::Completed generating the artifacts for system configuration NewInstCal_bsp -TRACE::2026-05-26.18:24:45::SCWPlatform::Started preparing the platform -TRACE::2026-05-26.18:24:45::SCWSystem::Writing the bif file for system config NewInstCal_bsp -TRACE::2026-05-26.18:24:45::SCWSystem::dir created -TRACE::2026-05-26.18:24:45::SCWSystem::Writing the bif -TRACE::2026-05-26.18:24:45::SCWPlatform::Started writing the spfm file -TRACE::2026-05-26.18:24:45::SCWPlatform::Started writing the xpfm file -TRACE::2026-05-26.18:24:45::SCWPlatform::Completed generating the platform -TRACE::2026-05-26.18:24:45::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:24:45::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:24:45::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:24:45::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:24:45::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:24:45::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:24:45::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:24:45::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:24:45::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:45::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:45::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:45::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:24:45::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:45::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:24:45::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:24:45::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:24:45::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:24:45::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:24:45::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:24:45::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-26.18:24:45::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:45::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:45::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:45::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:24:45::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:45::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:24:45::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:24:45::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:24:45::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:24:45::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:24:45::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:24:45::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:24:45::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ", - "platPreBuiltFlag": false, - "platformSamplesDir": "", - "platActiveSys": "NewInstCal_bsp", - "systems": [{ - "systemName": "NewInstCal_bsp", - "systemDesc": "NewInstCal_bsp", - "sysIsBootAutoGen": "true", - "systemDispName": "NewInstCal_bsp", - "sysActiveDom": "standalone_domain", - "sysDefaultDom": "standalone_domain", - "domains": [{ - "domainName": "zynq_fsbl", - "domainDispName": "zynq_fsbl", - "domainDesc": "FSBL Application BSP - Auto Generated.", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "debugEnable": "", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "88a630cf45945e27dbb40d72cff1145a", - "compatibleApp": "zynq_fsbl", - "domType": "bootDomain", - "arch": "32-bit", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["xilffs:5.1", "xilrsa:1.7"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }, { - "domainName": "standalone_domain", - "domainDispName": "standalone on ps7_cortexa9_0", - "domainDesc": "standalone_domain", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "qemuArgs": "/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt", - "qemuData": "/resources/NewInstCal_bsp/standalone_domain/qemu", - "debugEnable": "False", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "36df5c3fd5a33f289a56469b013613e2", - "compatibleApp": "", - "domType": "mssDomain", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["lwip213:1.1"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }] - }] -} -KEYINFO::2026-05-26.18:24:45::SCWPlatform::updated the xpfm file. -TRACE::2026-05-26.18:24:45::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:45::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:45::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:45::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:24:45::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:24:45::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:24:45::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:24:45::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:24:45::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:24:45::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:24:45::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:24:45::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:22::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:22::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:22::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:22::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:25:22::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:22::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:25:22::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:25:22::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:25:22::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:25:22::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:22::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:25:22::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:25::SCWMssOS::In reload Mss file. -TRACE::2026-05-26.18:25:25::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:25::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:25::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:25::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:25:25::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:25::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:25:25::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:25:25::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:25:25::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:25:25::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:25::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:25:25::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:25::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:25::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:25::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-26.18:25:25::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-26.18:25:25::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:25::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:25::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:25::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:25::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:25:25::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:25::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:25:25::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:25:25::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:25:25::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:25:25::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:25::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:25:25::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:25::SCWMssOS:: library already available in sw design: lwip213:1.1 -TRACE::2026-05-26.18:25:25::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:25::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-26.18:25:25::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-26.18:25:25::SCWMssOS::Commit changes completed. -TRACE::2026-05-26.18:25:25::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:25::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:25::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:25::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-26.18:25:25::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-26.18:25:25::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-26.18:25:25::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-26.18:25:25::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-26.18:25:25::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-26.18:25:25::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:25::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-26.18:25:25::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-26.18:25:25::SCWMssOS::Removing the swdes entry for /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:26::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:26::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:26::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:26::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:26::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:26::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:26::SCWPlatform::Do not have an existing db opened. -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened new HwDB with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWReader::Active system found as NewInstCal_bsp -TRACE::2026-05-27.15:45:27::SCWReader::Handling sysconfig NewInstCal_bsp -TRACE::2026-05-27.15:45:27::SCWDomain::checking for install qemu data : -TRACE::2026-05-27.15:45:27::SCWDomain:: Using the QEMU Data from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/ -TRACE::2026-05-27.15:45:27::SCWDomain:: Using the QEMU args from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWReader::Boot application domain added for zynq_fsbl -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::DEBUG: swdes dump -TRACE::2026-05-27.15:45:27::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system -TRACE::2026-05-27.15:45:27::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-27.15:45:27::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.15:45:27::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS:: library already available in sw design: xilffs:5.1 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.15:45:27::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS:: library already available in sw design: xilrsa:1.7 -TRACE::2026-05-27.15:45:27::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.15:45:27::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-27.15:45:27::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.15:45:27::SCWReader::Adding prebuilt librarypaths as -TRACE::2026-05-27.15:45:27::SCWReader::Adding prebuilt incpaths as -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.15:45:27::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWReader::No isolation master present -TRACE::2026-05-27.15:45:27::SCWDomain::checking for install qemu data : -TRACE::2026-05-27.15:45:27::SCWDomain:: Using the QEMU Data from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/ -TRACE::2026-05-27.15:45:27::SCWDomain:: Using the QEMU args from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.15:45:27::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-27.15:45:27::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-27.15:45:27::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.15:45:27::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS:: library already available in sw design: lwip213:1.1 -TRACE::2026-05-27.15:45:27::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.15:45:27::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-27.15:45:27::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.15:45:27::SCWReader::Adding prebuilt librarypaths as -TRACE::2026-05-27.15:45:27::SCWReader::Adding prebuilt incpaths as -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.15:45:27::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWReader::No isolation master present -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.15:45:27::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::In reload Mss file. -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.15:45:27::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-27.15:45:27::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-27.15:45:27::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.15:45:27::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS:: library already available in sw design: lwip213:1.1 -TRACE::2026-05-27.15:45:27::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.15:45:27::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-27.15:45:27::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw -TRACE::2026-05-27.15:45:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.15:45:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.15:45:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.15:45:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.15:45:27::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.15:45:27::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.15:45:27::SCWMssOS::Removing the swdes entry for /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/proj_cal/Vitis/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:08::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:08::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:08::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:08::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:08::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:08::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:08::SCWPlatform::Do not have an existing db opened. -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened new HwDB with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWReader::Active system found as NewInstCal_bsp -TRACE::2026-05-27.17:48:09::SCWReader::Handling sysconfig NewInstCal_bsp -TRACE::2026-05-27.17:48:09::SCWDomain::checking for install qemu data : -TRACE::2026-05-27.17:48:09::SCWDomain:: Using the QEMU Data from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/ -TRACE::2026-05-27.17:48:09::SCWDomain:: Using the QEMU args from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:09::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:09::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:09::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:09::SCWReader::Boot application domain added for zynq_fsbl -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:09::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:09::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::DEBUG: swdes dump -TRACE::2026-05-27.17:48:09::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system -TRACE::2026-05-27.17:48:09::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-27.17:48:09::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:09::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:09::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:09::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS:: library already available in sw design: xilffs:5.1 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:09::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:09::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:09::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS:: library already available in sw design: xilrsa:1.7 -TRACE::2026-05-27.17:48:09::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.17:48:09::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-27.17:48:09::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.17:48:09::SCWReader::Adding prebuilt librarypaths as -TRACE::2026-05-27.17:48:09::SCWReader::Adding prebuilt incpaths as -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:09::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:09::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:09::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWReader::No isolation master present -TRACE::2026-05-27.17:48:09::SCWDomain::checking for install qemu data : -TRACE::2026-05-27.17:48:09::SCWDomain:: Using the QEMU Data from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/ -TRACE::2026-05-27.17:48:09::SCWDomain:: Using the QEMU args from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:09::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:09::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:09::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:09::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:09::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-27.17:48:09::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-27.17:48:09::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:09::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:09::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:09::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS:: library already available in sw design: lwip213:1.1 -TRACE::2026-05-27.17:48:09::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.17:48:09::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-27.17:48:09::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.17:48:09::SCWReader::Adding prebuilt librarypaths as -TRACE::2026-05-27.17:48:09::SCWReader::Adding prebuilt incpaths as -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:09::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:09::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:09::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:09::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:09::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:09::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:09::SCWReader::No isolation master present -TRACE::2026-05-27.17:48:27::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa/system_wrapper.xsa -TRACE::2026-05-27.17:48:27::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa/system_wrapper.xsa -TRACE::2026-05-27.17:48:27::SCWPlatform:: Platform location is /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa -TRACE::2026-05-27.17:48:27::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa/system_wrapper.xsa -TRACE::2026-05-27.17:48:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:28::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:28::SCWMssOS::Doing hw sync for the mss in domain: zynq_fsbl -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:28::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:28::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:28::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:28::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:28::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:28::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:28::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:28::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa -TRACE::2026-05-27.17:48:28::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:28::SCWPlatform::update - Opened existing hwdb system_wrapper_0 -TRACE::2026-05-27.17:48:28::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:28::SCWMssOS::Doing hw sync for the mss in domain: standalone_domain -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:28::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:28::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:28::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:28::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.17:48:28::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.17:48:28::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:28::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:28::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa -TRACE::2026-05-27.17:48:28::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/tempdsa/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:28::SCWPlatform::update - Opened existing hwdb system_wrapper_0 -TRACE::2026-05-27.17:48:28::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:28::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.17:48:28::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-27.17:48:28::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.17:48:28::SCWMssOS::Completed hw sync for the mss in domain: zynq_fsbl -TRACE::2026-05-27.17:48:28::SCWMssOS::Removing the swdes entry for /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.17:48:28::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-27.17:48:28::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.17:48:28::SCWMssOS::Completed hw sync for the mss in domain: standalone_domain -TRACE::2026-05-27.17:48:28::SCWMssOS::Removing the swdes entry for /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:28::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:28::SCWPlatform::Do not have an existing db opened. -TRACE::2026-05-27.17:48:28::SCWPlatform::Opened new HwDB with name system_wrapper_1 -TRACE::2026-05-27.17:48:28::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWMssOS::Adding the swdes entry, mss present, able to open swdb /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system -TRACE::2026-05-27.17:48:28::SCWMssOS::Writing the mss file completed /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.17:48:28::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWMssOS::Adding the swdes entry, mss present, able to open swdb /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-27.17:48:28::SCWMssOS::Writing the mss file completed /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:28::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-27.17:48:28::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-27.17:48:28::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:28::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:28::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:28::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:28::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:28::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_1 -TRACE::2026-05-27.17:48:28::SCWPlatform::Opened existing hwdb system_wrapper_1 -TRACE::2026-05-27.17:48:28::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:28::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:28::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:28::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ", - "platPreBuiltFlag": false, - "platformSamplesDir": "", - "platActiveSys": "NewInstCal_bsp", - "systems": [{ - "systemName": "NewInstCal_bsp", - "systemDesc": "NewInstCal_bsp", - "sysIsBootAutoGen": "true", - "systemDispName": "NewInstCal_bsp", - "sysActiveDom": "standalone_domain", - "sysDefaultDom": "standalone_domain", - "domains": [{ - "domainName": "zynq_fsbl", - "domainDispName": "zynq_fsbl", - "domainDesc": "FSBL Application BSP - Auto Generated.", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "debugEnable": "", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "88a630cf45945e27dbb40d72cff1145a1", - "compatibleApp": "zynq_fsbl", - "domType": "bootDomain", - "arch": "32-bit", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["xilffs:5.1", "xilrsa:1.7"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }, { - "domainName": "standalone_domain", - "domainDispName": "standalone on ps7_cortexa9_0", - "domainDesc": "standalone_domain", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "qemuArgs": "/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt", - "qemuData": "/resources/NewInstCal_bsp/standalone_domain/qemu", - "debugEnable": "False", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "36df5c3fd5a33f289a56469b013613e21", - "compatibleApp": "", - "domType": "mssDomain", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["lwip213:1.1"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }] - }] -} -TRACE::2026-05-27.17:48:30::SCWPlatform::Clearing the existing platform -TRACE::2026-05-27.17:48:30::SCWSystem::Clearing the existing sysconfig -TRACE::2026-05-27.17:48:30::SCWBDomain::clearing the fsbl build -TRACE::2026-05-27.17:48:30::SCWMssOS::Removing the swdes entry for /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::Removing the swdes entry for /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWSystem::Clearing the domains completed. -TRACE::2026-05-27.17:48:30::SCWPlatform::Clearing the opened hw db. -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform location is /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Do not have an existing db opened. -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened new HwDB with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWReader::Active system found as NewInstCal_bsp -TRACE::2026-05-27.17:48:30::SCWReader::Handling sysconfig NewInstCal_bsp -TRACE::2026-05-27.17:48:30::SCWDomain::checking for install qemu data : -TRACE::2026-05-27.17:48:30::SCWDomain:: Using the QEMU Data from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/ -TRACE::2026-05-27.17:48:30::SCWDomain:: Using the QEMU args from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:30::SCWReader::Boot application domain added for zynq_fsbl -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:30::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::DEBUG: swdes dump -TRACE::2026-05-27.17:48:30::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system -TRACE::2026-05-27.17:48:30::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-27.17:48:30::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:30::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:30::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS:: library already available in sw design: xilffs:5.1 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:30::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:30::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS:: library already available in sw design: xilrsa:1.7 -TRACE::2026-05-27.17:48:30::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.17:48:30::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-27.17:48:30::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.17:48:30::SCWReader::Adding prebuilt librarypaths as -TRACE::2026-05-27.17:48:30::SCWReader::Adding prebuilt incpaths as -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:30::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:30::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWReader::No isolation master present -TRACE::2026-05-27.17:48:30::SCWDomain::checking for install qemu data : -TRACE::2026-05-27.17:48:30::SCWDomain:: Using the QEMU Data from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/ -TRACE::2026-05-27.17:48:30::SCWDomain:: Using the QEMU args from install at : /data/xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:30::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:30::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-27.17:48:30::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-27.17:48:30::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:30::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:30::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS:: library already available in sw design: lwip213:1.1 -TRACE::2026-05-27.17:48:30::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.17:48:30::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-27.17:48:30::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.17:48:30::SCWReader::Adding prebuilt librarypaths as -TRACE::2026-05-27.17:48:30::SCWReader::Adding prebuilt incpaths as -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:30::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:30::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:30::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:30::SCWReader::No isolation master present -LOG::2026-05-27.17:48:39::SCWPlatform::Started generating the artifacts platform NewInstCal_bsp -TRACE::2026-05-27.17:48:39::SCWPlatform::Sanity checking of platform is completed -LOG::2026-05-27.17:48:39::SCWPlatform::Started generating the artifacts for system configuration NewInstCal_bsp -LOG::2026-05-27.17:48:39::SCWSystem::Checking the domain zynq_fsbl -LOG::2026-05-27.17:48:39::SCWSystem::Doing application build for : zynq_fsbl -TRACE::2026-05-27.17:48:39::SCWBDomain::Not a forced makefile updation, No changes are present. -TRACE::2026-05-27.17:48:39::SCWDomain::Building the domain as part of full build : zynq_fsbl -TRACE::2026-05-27.17:48:39::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:39::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:39::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:39::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:39::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:39::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:39::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:39::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:39::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:39::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:39::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:39::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:39::SCWBDomain::Completed writing the mss file at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp -TRACE::2026-05-27.17:48:39::SCWBDomain::bsp generated is stale removing and regenerating. -TRACE::2026-05-27.17:48:39::SCWBDomain::Updating the makefile used for building the Application zynq_fsbl -TRACE::2026-05-27.17:48:39::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:39::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:39::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:39::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:39::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:39::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:39::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:39::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:39::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:39::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:39::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| - -TRACE::2026-05-27.17:48:39::SCWMssOS::No sw design opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:39::SCWMssOS::mss exists loading the mss file /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:39::SCWMssOS::Opened the sw design from mss /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:39::SCWMssOS::Adding the swdes entry /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system -TRACE::2026-05-27.17:48:39::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-27.17:48:39::SCWMssOS::Opened the sw design. /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:42::SCWBDomain::removing the temporary location in _platform. -TRACE::2026-05-27.17:48:42::SCWBDomain::Makefile is Updated. -TRACE::2026-05-27.17:48:42::SCWBDomain::doing clean. -TRACE::2026-05-27.17:48:42::SCWBDomain::System Command Ran cd /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl ; bash -c "make clean" -TRACE::2026-05-27.17:48:42::SCWBDomain::rm -rf fsbl_hooks.o image_mover.o main.o md5.o nand.o nor.o pcap.o ps7_init.o qspi.o rsa.o sd.o fsbl_handoff.o zynq -TRACE::2026-05-27.17:48:42::SCWBDomain::_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a fsbl.elf *.o - -TRACE::2026-05-27.17:48:42::SCWBDomain::System Command Ran cd /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl ; bash -c " make -C zynq_fsbl_bsp ; make " -TRACE::2026-05-27.17:48:42::SCWBDomain::make: Entering directory '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsb -TRACE::2026-05-27.17:48:42::SCWBDomain::l_bsp' - -TRACE::2026-05-27.17:48:42::SCWBDomain::make --no-print-directory seq_libs - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm- -TRACE::2026-05-27.17:48:42::SCWBDomain::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a -TRACE::2026-05-27.17:48:42::SCWBDomain::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no -TRACE::2026-05-27.17:48:42::SCWBDomain::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi -TRACE::2026-05-27.17:48:42::SCWBDomain::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-27.17:48:42::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-27.17:48:42::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_8/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_9/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-27.17:48:42::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-27.17:48:42::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_19/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:42::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:42::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_12/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:42::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:42::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_11/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:42::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:42::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scugic_v5_2/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_5/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea -TRACE::2026-05-27.17:48:42::SCWBDomain::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:42::SCWBDomain:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/sdps_v4_2/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:42::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:42::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/standalone_v9_0/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none- -TRACE::2026-05-27.17:48:42::SCWBDomain::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha -TRACE::2026-05-27.17:48:42::SCWBDomain::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_13/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:42::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:42::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_7/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilffs_v5_1/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v5_1/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_7/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/xilrsa_v1_7/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.17:48:42::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.17:48:42::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Finished building libraries sequentially. - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -j 30 --no-print-directory par_libs - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm- -TRACE::2026-05-27.17:48:42::SCWBDomain::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a -TRACE::2026-05-27.17:48:42::SCWBDomain::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no -TRACE::2026-05-27.17:48:42::SCWBDomain::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi -TRACE::2026-05-27.17:48:42::SCWBDomain::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-27.17:48:42::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-27.17:48:42::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_8/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_9/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-27.17:48:42::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-27.17:48:42::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_19/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_12/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:42::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:42::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:42::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:42::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_11/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:42::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:42::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scugic_v5_2/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_5/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea -TRACE::2026-05-27.17:48:42::SCWBDomain::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:42::SCWBDomain:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/sdps_v4_2/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:42::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:42::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/standalone_v9_0/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_13/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none- -TRACE::2026-05-27.17:48:42::SCWBDomain::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha -TRACE::2026-05-27.17:48:42::SCWBDomain::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:42::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:42::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_7/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilffs_v5_1/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v5_1/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_7/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-non -TRACE::2026-05-27.17:48:42::SCWBDomain::e-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi= -TRACE::2026-05-27.17:48:42::SCWBDomain::hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none- -TRACE::2026-05-27.17:48:42::SCWBDomain::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha -TRACE::2026-05-27.17:48:42::SCWBDomain::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_2/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.17:48:42::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.17:48:42::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_8/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.17:48:42::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.17:48:42::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_9/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.17:48:42::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.17:48:42::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_19/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:42::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:42::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_12/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:42::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:42::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_11/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:42::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:42::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/scugic_v5_2/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_5/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.17:48:42::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.17:48:42::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-27.17:48:42::SCWBDomain::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-27.17:48:42::SCWBDomain::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.17:48:42::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.17:48:42::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/sdps_v4_2/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.17:48:42::SCWBDomain::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-27.17:48:42::SCWBDomain::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/standalone_v9_0/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:42::SCWBDomain::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:42::SCWBDomain::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_13/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:42::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:42::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_7/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.17:48:42::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.17:48:42::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Running Make libs in ps7_cortexa9_0/libsrc/xilffs_v5_1/src - -TRACE::2026-05-27.17:48:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v5_1/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.17:48:42::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.17:48:42::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:42::SCWBDomain::Finished building libraries parallelly. - -TRACE::2026-05-27.17:48:42::SCWBDomain::make --no-print-directory archive - -TRACE::2026-05-27.17:48:42::SCWBDomain::arm-none-eabi-ar -r ps7_cortexa9_0/lib/libxil.a ps7_cortexa9_0/lib/_exit.o ps7_cortexa9_0/lib/_open.o ps7_cortexa9_0/lib/_sbrk -TRACE::2026-05-27.17:48:42::SCWBDomain::.o ps7_cortexa9_0/lib/abort.o ps7_cortexa9_0/lib/asm_vectors.o ps7_cortexa9_0/lib/boot.o ps7_cortexa9_0/lib/close.o ps7_cortexa -TRACE::2026-05-27.17:48:42::SCWBDomain::9_0/lib/cpputest_time.o ps7_cortexa9_0/lib/cpu_init.o ps7_cortexa9_0/lib/errno.o ps7_cortexa9_0/lib/fcntl.o ps7_cortexa9_0/lib/ -TRACE::2026-05-27.17:48:42::SCWBDomain::fstat.o ps7_cortexa9_0/lib/getentropy.o ps7_cortexa9_0/lib/getpid.o ps7_cortexa9_0/lib/inbyte.o ps7_cortexa9_0/lib/isatty.o ps7 -TRACE::2026-05-27.17:48:42::SCWBDomain::_cortexa9_0/lib/kill.o ps7_cortexa9_0/lib/lseek.o ps7_cortexa9_0/lib/open.o ps7_cortexa9_0/lib/outbyte.o ps7_cortexa9_0/lib/pri -TRACE::2026-05-27.17:48:42::SCWBDomain::nt.o ps7_cortexa9_0/lib/putnum.o ps7_cortexa9_0/lib/read.o ps7_cortexa9_0/lib/sbrk.o ps7_cortexa9_0/lib/sleep.o ps7_cortexa9_0/ -TRACE::2026-05-27.17:48:42::SCWBDomain::lib/time.o ps7_cortexa9_0/lib/translation_table.o ps7_cortexa9_0/lib/unlink.o ps7_cortexa9_0/lib/usleep.o ps7_cortexa9_0/lib/ve -TRACE::2026-05-27.17:48:42::SCWBDomain::ctors.o ps7_cortexa9_0/lib/write.o ps7_cortexa9_0/lib/xadcps.o ps7_cortexa9_0/lib/xadcps_g.o ps7_cortexa9_0/lib/xadcps_intr.o p -TRACE::2026-05-27.17:48:42::SCWBDomain::s7_cortexa9_0/lib/xadcps_selftest.o ps7_cortexa9_0/lib/xadcps_sinit.o ps7_cortexa9_0/lib/xcoresightpsdcc.o ps7_cortexa9_0/lib/x -TRACE::2026-05-27.17:48:42::SCWBDomain::devcfg.o ps7_cortexa9_0/lib/xdevcfg_g.o ps7_cortexa9_0/lib/xdevcfg_hw.o ps7_cortexa9_0/lib/xdevcfg_intr.o ps7_cortexa9_0/lib/xd -TRACE::2026-05-27.17:48:42::SCWBDomain::evcfg_selftest.o ps7_cortexa9_0/lib/xdevcfg_sinit.o ps7_cortexa9_0/lib/xdmaps.o ps7_cortexa9_0/lib/xdmaps_g.o ps7_cortexa9_0/li -TRACE::2026-05-27.17:48:42::SCWBDomain::b/xdmaps_hw.o ps7_cortexa9_0/lib/xdmaps_selftest.o ps7_cortexa9_0/lib/xdmaps_sinit.o ps7_cortexa9_0/lib/xemacps.o ps7_cortexa9_ -TRACE::2026-05-27.17:48:42::SCWBDomain::0/lib/xemacps_bdring.o ps7_cortexa9_0/lib/xemacps_control.o ps7_cortexa9_0/lib/xemacps_g.o ps7_cortexa9_0/lib/xemacps_hw.o ps7_ -TRACE::2026-05-27.17:48:42::SCWBDomain::cortexa9_0/lib/xemacps_intr.o ps7_cortexa9_0/lib/xemacps_sinit.o ps7_cortexa9_0/lib/xgpiops.o ps7_cortexa9_0/lib/xgpiops_g.o ps -TRACE::2026-05-27.17:48:42::SCWBDomain::7_cortexa9_0/lib/xgpiops_hw.o ps7_cortexa9_0/lib/xgpiops_intr.o ps7_cortexa9_0/lib/xgpiops_selftest.o ps7_cortexa9_0/lib/xgpiop -TRACE::2026-05-27.17:48:42::SCWBDomain::s_sinit.o ps7_cortexa9_0/lib/xil-crt0.o ps7_cortexa9_0/lib/xil_assert.o ps7_cortexa9_0/lib/xil_cache.o ps7_cortexa9_0/lib/xil_c -TRACE::2026-05-27.17:48:42::SCWBDomain::locking.o ps7_cortexa9_0/lib/xil_exception.o ps7_cortexa9_0/lib/xil_mem.o ps7_cortexa9_0/lib/xil_misc_psreset_api.o ps7_cortexa -TRACE::2026-05-27.17:48:42::SCWBDomain::9_0/lib/xil_mmu.o ps7_cortexa9_0/lib/xil_printf.o ps7_cortexa9_0/lib/xil_sleepcommon.o ps7_cortexa9_0/lib/xil_sleeptimer.o ps7_ -TRACE::2026-05-27.17:48:42::SCWBDomain::cortexa9_0/lib/xil_spinlock.o ps7_cortexa9_0/lib/xil_testcache.o ps7_cortexa9_0/lib/xil_testio.o ps7_cortexa9_0/lib/xil_testmem -TRACE::2026-05-27.17:48:42::SCWBDomain::.o ps7_cortexa9_0/lib/xil_util.o ps7_cortexa9_0/lib/xinterrupt_wrap.o ps7_cortexa9_0/lib/xl2cc_counter.o ps7_cortexa9_0/lib/xpl -TRACE::2026-05-27.17:48:42::SCWBDomain::atform_info.o ps7_cortexa9_0/lib/xpm_counter.o ps7_cortexa9_0/lib/xpm_init.o ps7_cortexa9_0/lib/xqspips.o ps7_cortexa9_0/lib/xq -TRACE::2026-05-27.17:48:42::SCWBDomain::spips_g.o ps7_cortexa9_0/lib/xqspips_hw.o ps7_cortexa9_0/lib/xqspips_options.o ps7_cortexa9_0/lib/xqspips_selftest.o ps7_cortex -TRACE::2026-05-27.17:48:42::SCWBDomain::a9_0/lib/xqspips_sinit.o ps7_cortexa9_0/lib/xscugic.o ps7_cortexa9_0/lib/xscugic_g.o ps7_cortexa9_0/lib/xscugic_hw.o ps7_cortex -TRACE::2026-05-27.17:48:42::SCWBDomain::a9_0/lib/xscugic_intr.o ps7_cortexa9_0/lib/xscugic_selftest.o ps7_cortexa9_0/lib/xscugic_sinit.o ps7_cortexa9_0/lib/xscutimer.o -TRACE::2026-05-27.17:48:42::SCWBDomain:: ps7_cortexa9_0/lib/xscutimer_g.o ps7_cortexa9_0/lib/xscutimer_selftest.o ps7_cortexa9_0/lib/xscutimer_sinit.o ps7_cortexa9_0/l -TRACE::2026-05-27.17:48:42::SCWBDomain::ib/xscuwdt.o ps7_cortexa9_0/lib/xscuwdt_g.o ps7_cortexa9_0/lib/xscuwdt_selftest.o ps7_cortexa9_0/lib/xscuwdt_sinit.o ps7_cortex -TRACE::2026-05-27.17:48:42::SCWBDomain::a9_0/lib/xsdps.o ps7_cortexa9_0/lib/xsdps_card.o ps7_cortexa9_0/lib/xsdps_g.o ps7_cortexa9_0/lib/xsdps_host.o ps7_cortexa9_0/li -TRACE::2026-05-27.17:48:42::SCWBDomain::b/xsdps_options.o ps7_cortexa9_0/lib/xsdps_sinit.o ps7_cortexa9_0/lib/xtime_l.o ps7_cortexa9_0/lib/xuartps.o ps7_cortexa9_0/lib -TRACE::2026-05-27.17:48:42::SCWBDomain::/xuartps_g.o ps7_cortexa9_0/lib/xuartps_hw.o ps7_cortexa9_0/lib/xuartps_intr.o ps7_cortexa9_0/lib/xuartps_options.o ps7_cortexa -TRACE::2026-05-27.17:48:42::SCWBDomain::9_0/lib/xuartps_selftest.o ps7_cortexa9_0/lib/xuartps_sinit.o - -TRACE::2026-05-27.17:48:43::SCWBDomain::Finished building libraries - -TRACE::2026-05-27.17:48:43::SCWBDomain::make: Leaving directory '/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl -TRACE::2026-05-27.17:48:43::SCWBDomain::_bsp' - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c fsbl_hooks.c -o fsbl_hooks.o -Izynq_f -TRACE::2026-05-27.17:48:43::SCWBDomain::sbl_bsp/ps7_cortexa9_0/include -I. - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c image_mover.c -o image_mover.o -Izynq -TRACE::2026-05-27.17:48:43::SCWBDomain::_fsbl_bsp/ps7_cortexa9_0/include -I. - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c main.c -o main.o -Izynq_fsbl_bsp/ps7_ -TRACE::2026-05-27.17:48:43::SCWBDomain::cortexa9_0/include -I. - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c md5.c -o md5.o -Izynq_fsbl_bsp/ps7_co -TRACE::2026-05-27.17:48:43::SCWBDomain::rtexa9_0/include -I. - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c nand.c -o nand.o -Izynq_fsbl_bsp/ps7_ -TRACE::2026-05-27.17:48:43::SCWBDomain::cortexa9_0/include -I. - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c nor.c -o nor.o -Izynq_fsbl_bsp/ps7_co -TRACE::2026-05-27.17:48:43::SCWBDomain::rtexa9_0/include -I. - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c pcap.c -o pcap.o -Izynq_fsbl_bsp/ps7_ -TRACE::2026-05-27.17:48:43::SCWBDomain::cortexa9_0/include -I. - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c ps7_init.c -o ps7_init.o -Izynq_fsbl_ -TRACE::2026-05-27.17:48:43::SCWBDomain::bsp/ps7_cortexa9_0/include -I. - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c qspi.c -o qspi.o -Izynq_fsbl_bsp/ps7_ -TRACE::2026-05-27.17:48:43::SCWBDomain::cortexa9_0/include -I. - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c rsa.c -o rsa.o -Izynq_fsbl_bsp/ps7_co -TRACE::2026-05-27.17:48:43::SCWBDomain::rtexa9_0/include -I. - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c sd.c -o sd.o -Izynq_fsbl_bsp/ps7_cort -TRACE::2026-05-27.17:48:43::SCWBDomain::exa9_0/include -I. - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c fsbl_handoff.S -o fsbl_handoff.o -Izy -TRACE::2026-05-27.17:48:43::SCWBDomain::nq_fsbl_bsp/ps7_cortexa9_0/include -I. - -TRACE::2026-05-27.17:48:43::SCWBDomain::arm-none-eabi-gcc -o fsbl.elf fsbl_handoff.o fsbl_hooks.o image_mover.o main.o md5.o nand.o nor.o pcap.o ps7_init.o qspi.o rsa. -TRACE::2026-05-27.17:48:43::SCWBDomain::o sd.o -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id -TRACE::2026-05-27.17:48:43::SCWBDomain::=none -specs=Xilinx.spec -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end- -TRACE::2026-05-27.17:48:43::SCWBDomain::group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group -Wl,--gc-sections -Lzynq_fsbl_bsp/p -TRACE::2026-05-27.17:48:43::SCWBDomain::s7_cortexa9_0/lib -L./ -Tlscript.ld - -LOG::2026-05-27.17:48:43::SCWSystem::Checking the domain standalone_domain -LOG::2026-05-27.17:48:43::SCWSystem::Not a boot domain -LOG::2026-05-27.17:48:43::SCWSystem::Started Processing the domain standalone_domain -TRACE::2026-05-27.17:48:43::SCWDomain::Generating domain artifcats -TRACE::2026-05-27.17:48:43::SCWMssOS::Generating standalone artifcats -TRACE::2026-05-27.17:48:43::SCWMssOS::Copying the qemu file from /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt To /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/qemu/ -TRACE::2026-05-27.17:48:43::SCWMssOS::Copying the qemu file from /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt To /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/qemu/ -TRACE::2026-05-27.17:48:43::SCWMssOS:: Copying the user libraries. -TRACE::2026-05-27.17:48:43::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:43::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:43::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:43::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:43::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:43::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:43::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:43::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:43::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:43::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:43::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:43::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:43::SCWMssOS::Completed writing the mss file at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp -TRACE::2026-05-27.17:48:43::SCWMssOS::Mss edits present, copying mssfile into export location /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:43::SCWMssOS::bsp generated is stale removing and regenerating. -TRACE::2026-05-27.17:48:43::SCWMssOS::doing bsp build ... -TRACE::2026-05-27.17:48:43::SCWMssOS::System Command Ran cd /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp ; bash -c "make " -TRACE::2026-05-27.17:48:43::SCWMssOS::make --no-print-directory seq_libs - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm- -TRACE::2026-05-27.17:48:43::SCWMssOS::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a -TRACE::2026-05-27.17:48:43::SCWMssOS::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no -TRACE::2026-05-27.17:48:43::SCWMssOS::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi -TRACE::2026-05-27.17:48:43::SCWMssOS::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-27.17:48:43::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-27.17:48:43::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_8/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:43::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:43::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_9/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-27.17:48:43::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-27.17:48:43::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_19/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:43::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:43::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_12/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:43::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:43::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/lwip213_v1_1/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/lwip213_v1_1/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:43::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:43::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_11/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:43::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:43::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scugic_v5_2/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:43::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:43::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_5/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea -TRACE::2026-05-27.17:48:43::SCWMssOS::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:43::SCWMssOS:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:43::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:43::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/sdps_v4_2/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:43::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:43::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/standalone_v9_0/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none- -TRACE::2026-05-27.17:48:43::SCWMssOS::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha -TRACE::2026-05-27.17:48:43::SCWMssOS::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_13/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:43::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:43::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_7/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:43::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:43::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/lwip213_v1_1/src - -TRACE::2026-05-27.17:48:43::SCWMssOS::make -C ps7_cortexa9_0/libsrc/lwip213_v1_1/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:43::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:43::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:43::SCWMssOS::Compiling lwip src and adapter files - -TRACE::2026-05-27.17:48:46::SCWMssOS::Finished building libraries sequentially. - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -j 30 --no-print-directory par_libs - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm- -TRACE::2026-05-27.17:48:46::SCWMssOS::none-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-a -TRACE::2026-05-27.17:48:46::SCWMssOS::bi=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-no -TRACE::2026-05-27.17:48:46::SCWMssOS::ne-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi -TRACE::2026-05-27.17:48:46::SCWMssOS::=hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-27.17:48:46::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-27.17:48:46::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_8/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:46::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:46::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_9/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-27.17:48:46::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-27.17:48:46::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_19/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:46::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:46::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_12/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:46::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:46::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/lwip213_v1_1/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/lwip213_v1_1/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:46::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:46::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_11/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:46::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:46::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scugic_v5_2/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_5/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:46::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:46::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea -TRACE::2026-05-27.17:48:46::SCWMssOS::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:46::SCWMssOS:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:46::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:46::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/sdps_v4_2/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:46::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:46::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/standalone_v9_0/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none- -TRACE::2026-05-27.17:48:46::SCWMssOS::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha -TRACE::2026-05-27.17:48:46::SCWMssOS::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_13/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:46::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:46::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_7/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s include "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.17:48:46::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.17:48:46::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-non -TRACE::2026-05-27.17:48:46::SCWMssOS::e-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi= -TRACE::2026-05-27.17:48:46::SCWMssOS::hard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_2/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none- -TRACE::2026-05-27.17:48:46::SCWMssOS::eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=ha -TRACE::2026-05-27.17:48:46::SCWMssOS::rd -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.17:48:46::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.17:48:46::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_8/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.17:48:46::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.17:48:46::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_9/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_19/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.17:48:46::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.17:48:46::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:46::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:46::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_12/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:46::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:46::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_11/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:46::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:46::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/scugic_v5_2/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.17:48:46::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.17:48:46::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_5/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi- -TRACE::2026-05-27.17:48:46::SCWMssOS::as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -n -TRACE::2026-05-27.17:48:46::SCWMssOS::ostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.17:48:46::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.17:48:46::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/sdps_v4_2/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.17:48:46::SCWMssOS::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-27.17:48:46::SCWMssOS::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/standalone_v9_0/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eab -TRACE::2026-05-27.17:48:46::SCWMssOS::i-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.17:48:46::SCWMssOS::-nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_13/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.17:48:46::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.17:48:46::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_7/src - -TRACE::2026-05-27.17:48:46::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s libs "SHELL=/bin/sh" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.17:48:46::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.17:48:46::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.17:48:46::SCWMssOS::Finished building libraries parallelly. - -TRACE::2026-05-27.17:48:46::SCWMssOS::make --no-print-directory archive - -TRACE::2026-05-27.17:48:46::SCWMssOS::arm-none-eabi-ar -r ps7_cortexa9_0/lib/libxil.a ps7_cortexa9_0/lib/_exit.o ps7_cortexa9_0/lib/_open.o ps7_cortexa9_0/lib/_sbrk -TRACE::2026-05-27.17:48:46::SCWMssOS::.o ps7_cortexa9_0/lib/abort.o ps7_cortexa9_0/lib/asm_vectors.o ps7_cortexa9_0/lib/boot.o ps7_cortexa9_0/lib/close.o ps7_cortexa -TRACE::2026-05-27.17:48:46::SCWMssOS::9_0/lib/cpputest_time.o ps7_cortexa9_0/lib/cpu_init.o ps7_cortexa9_0/lib/errno.o ps7_cortexa9_0/lib/fcntl.o ps7_cortexa9_0/lib/ -TRACE::2026-05-27.17:48:46::SCWMssOS::fstat.o ps7_cortexa9_0/lib/getentropy.o ps7_cortexa9_0/lib/getpid.o ps7_cortexa9_0/lib/inbyte.o ps7_cortexa9_0/lib/isatty.o ps7 -TRACE::2026-05-27.17:48:46::SCWMssOS::_cortexa9_0/lib/kill.o ps7_cortexa9_0/lib/lseek.o ps7_cortexa9_0/lib/open.o ps7_cortexa9_0/lib/outbyte.o ps7_cortexa9_0/lib/pri -TRACE::2026-05-27.17:48:46::SCWMssOS::nt.o ps7_cortexa9_0/lib/putnum.o ps7_cortexa9_0/lib/read.o ps7_cortexa9_0/lib/sbrk.o ps7_cortexa9_0/lib/sleep.o ps7_cortexa9_0/ -TRACE::2026-05-27.17:48:46::SCWMssOS::lib/time.o ps7_cortexa9_0/lib/translation_table.o ps7_cortexa9_0/lib/unlink.o ps7_cortexa9_0/lib/usleep.o ps7_cortexa9_0/lib/ve -TRACE::2026-05-27.17:48:46::SCWMssOS::ctors.o ps7_cortexa9_0/lib/write.o ps7_cortexa9_0/lib/xadcps.o ps7_cortexa9_0/lib/xadcps_g.o ps7_cortexa9_0/lib/xadcps_intr.o p -TRACE::2026-05-27.17:48:46::SCWMssOS::s7_cortexa9_0/lib/xadcps_selftest.o ps7_cortexa9_0/lib/xadcps_sinit.o ps7_cortexa9_0/lib/xcoresightpsdcc.o ps7_cortexa9_0/lib/x -TRACE::2026-05-27.17:48:46::SCWMssOS::devcfg.o ps7_cortexa9_0/lib/xdevcfg_g.o ps7_cortexa9_0/lib/xdevcfg_hw.o ps7_cortexa9_0/lib/xdevcfg_intr.o ps7_cortexa9_0/lib/xd -TRACE::2026-05-27.17:48:46::SCWMssOS::evcfg_selftest.o ps7_cortexa9_0/lib/xdevcfg_sinit.o ps7_cortexa9_0/lib/xdmaps.o ps7_cortexa9_0/lib/xdmaps_g.o ps7_cortexa9_0/li -TRACE::2026-05-27.17:48:46::SCWMssOS::b/xdmaps_hw.o ps7_cortexa9_0/lib/xdmaps_selftest.o ps7_cortexa9_0/lib/xdmaps_sinit.o ps7_cortexa9_0/lib/xemacps.o ps7_cortexa9_ -TRACE::2026-05-27.17:48:46::SCWMssOS::0/lib/xemacps_bdring.o ps7_cortexa9_0/lib/xemacps_control.o ps7_cortexa9_0/lib/xemacps_g.o ps7_cortexa9_0/lib/xemacps_hw.o ps7_ -TRACE::2026-05-27.17:48:46::SCWMssOS::cortexa9_0/lib/xemacps_intr.o ps7_cortexa9_0/lib/xemacps_sinit.o ps7_cortexa9_0/lib/xgpiops.o ps7_cortexa9_0/lib/xgpiops_g.o ps -TRACE::2026-05-27.17:48:46::SCWMssOS::7_cortexa9_0/lib/xgpiops_hw.o ps7_cortexa9_0/lib/xgpiops_intr.o ps7_cortexa9_0/lib/xgpiops_selftest.o ps7_cortexa9_0/lib/xgpiop -TRACE::2026-05-27.17:48:46::SCWMssOS::s_sinit.o ps7_cortexa9_0/lib/xil-crt0.o ps7_cortexa9_0/lib/xil_assert.o ps7_cortexa9_0/lib/xil_cache.o ps7_cortexa9_0/lib/xil_c -TRACE::2026-05-27.17:48:46::SCWMssOS::locking.o ps7_cortexa9_0/lib/xil_exception.o ps7_cortexa9_0/lib/xil_mem.o ps7_cortexa9_0/lib/xil_misc_psreset_api.o ps7_cortexa -TRACE::2026-05-27.17:48:46::SCWMssOS::9_0/lib/xil_mmu.o ps7_cortexa9_0/lib/xil_printf.o ps7_cortexa9_0/lib/xil_sleepcommon.o ps7_cortexa9_0/lib/xil_sleeptimer.o ps7_ -TRACE::2026-05-27.17:48:46::SCWMssOS::cortexa9_0/lib/xil_spinlock.o ps7_cortexa9_0/lib/xil_testcache.o ps7_cortexa9_0/lib/xil_testio.o ps7_cortexa9_0/lib/xil_testmem -TRACE::2026-05-27.17:48:46::SCWMssOS::.o ps7_cortexa9_0/lib/xil_util.o ps7_cortexa9_0/lib/xinterrupt_wrap.o ps7_cortexa9_0/lib/xl2cc_counter.o ps7_cortexa9_0/lib/xpl -TRACE::2026-05-27.17:48:46::SCWMssOS::atform_info.o ps7_cortexa9_0/lib/xpm_counter.o ps7_cortexa9_0/lib/xpm_init.o ps7_cortexa9_0/lib/xqspips.o ps7_cortexa9_0/lib/xq -TRACE::2026-05-27.17:48:46::SCWMssOS::spips_g.o ps7_cortexa9_0/lib/xqspips_hw.o ps7_cortexa9_0/lib/xqspips_options.o ps7_cortexa9_0/lib/xqspips_selftest.o ps7_cortex -TRACE::2026-05-27.17:48:46::SCWMssOS::a9_0/lib/xqspips_sinit.o ps7_cortexa9_0/lib/xscugic.o ps7_cortexa9_0/lib/xscugic_g.o ps7_cortexa9_0/lib/xscugic_hw.o ps7_cortex -TRACE::2026-05-27.17:48:46::SCWMssOS::a9_0/lib/xscugic_intr.o ps7_cortexa9_0/lib/xscugic_selftest.o ps7_cortexa9_0/lib/xscugic_sinit.o ps7_cortexa9_0/lib/xscutimer.o -TRACE::2026-05-27.17:48:46::SCWMssOS:: ps7_cortexa9_0/lib/xscutimer_g.o ps7_cortexa9_0/lib/xscutimer_selftest.o ps7_cortexa9_0/lib/xscutimer_sinit.o ps7_cortexa9_0/l -TRACE::2026-05-27.17:48:46::SCWMssOS::ib/xscuwdt.o ps7_cortexa9_0/lib/xscuwdt_g.o ps7_cortexa9_0/lib/xscuwdt_selftest.o ps7_cortexa9_0/lib/xscuwdt_sinit.o ps7_cortex -TRACE::2026-05-27.17:48:46::SCWMssOS::a9_0/lib/xsdps.o ps7_cortexa9_0/lib/xsdps_card.o ps7_cortexa9_0/lib/xsdps_g.o ps7_cortexa9_0/lib/xsdps_host.o ps7_cortexa9_0/li -TRACE::2026-05-27.17:48:46::SCWMssOS::b/xsdps_options.o ps7_cortexa9_0/lib/xsdps_sinit.o ps7_cortexa9_0/lib/xtime_l.o ps7_cortexa9_0/lib/xuartps.o ps7_cortexa9_0/lib -TRACE::2026-05-27.17:48:46::SCWMssOS::/xuartps_g.o ps7_cortexa9_0/lib/xuartps_hw.o ps7_cortexa9_0/lib/xuartps_intr.o ps7_cortexa9_0/lib/xuartps_options.o ps7_cortexa -TRACE::2026-05-27.17:48:46::SCWMssOS::9_0/lib/xuartps_selftest.o ps7_cortexa9_0/lib/xuartps_sinit.o - -TRACE::2026-05-27.17:48:46::SCWMssOS::Finished building libraries - -TRACE::2026-05-27.17:48:46::SCWMssOS:: Checking if to create the Supporting Applications -TRACE::2026-05-27.17:48:46::SCWMssOS:: No Linux domain exists, trying to generate FSBL -LOG::2026-05-27.17:48:46::SCWSystem::Completed Processing the domain standalone_domain -LOG::2026-05-27.17:48:46::SCWSystem::Completed Processing the sysconfig NewInstCal_bsp -LOG::2026-05-27.17:48:46::SCWPlatform::Completed generating the artifacts for system configuration NewInstCal_bsp -TRACE::2026-05-27.17:48:46::SCWPlatform::Started preparing the platform -TRACE::2026-05-27.17:48:46::SCWSystem::Writing the bif file for system config NewInstCal_bsp -TRACE::2026-05-27.17:48:46::SCWSystem::dir created -TRACE::2026-05-27.17:48:46::SCWSystem::Writing the bif -TRACE::2026-05-27.17:48:46::SCWPlatform::Started writing the spfm file -TRACE::2026-05-27.17:48:46::SCWPlatform::Started writing the xpfm file -TRACE::2026-05-27.17:48:46::SCWPlatform::Completed generating the platform -TRACE::2026-05-27.17:48:46::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:46::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.17:48:46::SCWMssOS::Running validate of swdbs. -KEYINFO::2026-05-27.17:48:46::SCWMssOS::Could not open the swdb for system -KEYINFO::2026-05-27.17:48:46::SCWMssOS::Could not open the sw design at system -ERROR: [Hsi 55-1558] Software Design system is not found - -TRACE::2026-05-27.17:48:46::SCWMssOS::Cleared the swdb table entry -TRACE::2026-05-27.17:48:46::SCWMssOS::Adding the swdes entry, mss present, able to open swdb /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system -TRACE::2026-05-27.17:48:46::SCWMssOS::Writing the mss file completed /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:46::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.17:48:46::SCWMssOS::Saving the mss changes /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:46::SCWMssOS::Adding the swdes entry, mss present, able to open swdb /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-27.17:48:46::SCWMssOS::Writing the mss file completed /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:46::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.17:48:46::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:46::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:46::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:46::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:46::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:46::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:46::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:46::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:46::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:46::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:46::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:46::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.17:48:46::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:46::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:46::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:46::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:46::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:46::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:46::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:46::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:46::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:46::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:46::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:46::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:46::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ", - "platPreBuiltFlag": false, - "platformSamplesDir": "", - "platActiveSys": "NewInstCal_bsp", - "systems": [{ - "systemName": "NewInstCal_bsp", - "systemDesc": "NewInstCal_bsp", - "sysIsBootAutoGen": "true", - "systemDispName": "NewInstCal_bsp", - "sysActiveDom": "standalone_domain", - "sysDefaultDom": "standalone_domain", - "domains": [{ - "domainName": "zynq_fsbl", - "domainDispName": "zynq_fsbl", - "domainDesc": "FSBL Application BSP - Auto Generated.", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "debugEnable": "", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "88a630cf45945e27dbb40d72cff1145a", - "compatibleApp": "zynq_fsbl", - "domType": "bootDomain", - "arch": "32-bit", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["xilffs:5.1", "xilrsa:1.7"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }, { - "domainName": "standalone_domain", - "domainDispName": "standalone on ps7_cortexa9_0", - "domainDesc": "standalone_domain", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "qemuArgs": "/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt", - "qemuData": "/resources/NewInstCal_bsp/standalone_domain/qemu", - "debugEnable": "False", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "36df5c3fd5a33f289a56469b013613e2", - "compatibleApp": "", - "domType": "mssDomain", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["lwip213:1.1"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }] - }] -} -KEYINFO::2026-05-27.17:48:46::SCWPlatform::updated the xpfm file. -TRACE::2026-05-27.17:48:46::SCWPlatform::Trying to open the hw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:46::SCWPlatform::DSA given /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:46::SCWPlatform::DSA absoulate path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:46::SCWPlatform::DSA directory /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.17:48:46::SCWPlatform:: Platform Path /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.17:48:46::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.17:48:46::SCWPlatform::Trying to set the existing hwdb with name system_wrapper_2 -TRACE::2026-05-27.17:48:46::SCWPlatform::Opened existing hwdb system_wrapper_2 -TRACE::2026-05-27.17:48:46::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.17:48:46::SCWMssOS::Checking the sw design at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.17:48:46::SCWMssOS::DEBUG: swdes dump /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.17:48:46::SCWMssOS::Sw design exists and opened at /home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:02:20::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:20::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:20::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:20::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:20::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:20::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:20::SCWPlatform::Do not have an existing db opened. -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened new HwDB with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWReader::Active system found as NewInstCal_bsp -TRACE::2026-05-27.18:02:23::SCWReader::Handling sysconfig NewInstCal_bsp -TRACE::2026-05-27.18:02:23::SCWDomain::checking for install qemu data : -TRACE::2026-05-27.18:02:23::SCWDomain:: Using the QEMU Data from install at : C:/Xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/ -TRACE::2026-05-27.18:02:23::SCWDomain:: Using the QEMU args from install at : C:/Xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:23::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:23::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:23::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:02:23::SCWReader::Boot application domain added for zynq_fsbl -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:23::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:02:23::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::DEBUG: swdes dump -TRACE::2026-05-27.18:02:23::SCWMssOS::No sw design opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::mss exists loading the mss file C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::Opened the sw design from mss C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::Adding the swdes entry C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system -TRACE::2026-05-27.18:02:23::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-27.18:02:23::SCWMssOS::Opened the sw design. C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:23::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:02:23::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::DEBUG: swdes dump C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.18:02:23::SCWMssOS::Sw design exists and opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS:: library already available in sw design: xilffs:5.1 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:23::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:02:23::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::DEBUG: swdes dump C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.18:02:23::SCWMssOS::Sw design exists and opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS:: library already available in sw design: xilrsa:1.7 -TRACE::2026-05-27.18:02:23::SCWMssOS::Saving the mss changes C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.18:02:23::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-27.18:02:23::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.18:02:23::SCWReader::Adding prebuilt librarypaths as -TRACE::2026-05-27.18:02:23::SCWReader::Adding prebuilt incpaths as -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:23::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:02:23::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::DEBUG: swdes dump C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.18:02:23::SCWMssOS::Sw design exists and opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWReader::No isolation master present -TRACE::2026-05-27.18:02:23::SCWDomain::checking for install qemu data : -TRACE::2026-05-27.18:02:23::SCWDomain:: Using the QEMU Data from install at : C:/Xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/ -TRACE::2026-05-27.18:02:23::SCWDomain:: Using the QEMU args from install at : C:/Xilinx/Vitis/2023.2/data/emulation/platforms/zynq/sw/a9_standalone/qemu/qemu_args.txt -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:23::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:23::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:23::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:02:23::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::DEBUG: swdes dump C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.18:02:23::SCWMssOS::No sw design opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::mss exists loading the mss file C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::Opened the sw design from mss C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::Adding the swdes entry C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-27.18:02:23::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-27.18:02:23::SCWMssOS::Opened the sw design. C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:23::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:02:23::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::DEBUG: swdes dump C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.18:02:23::SCWMssOS::Sw design exists and opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS:: library already available in sw design: lwip213:1.1 -TRACE::2026-05-27.18:02:23::SCWMssOS::Saving the mss changes C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.18:02:23::SCWMssOS::Completed writemss as part of save. -TRACE::2026-05-27.18:02:23::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.18:02:23::SCWReader::Adding prebuilt librarypaths as -TRACE::2026-05-27.18:02:23::SCWReader::Adding prebuilt incpaths as -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:02:23::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:02:23::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:02:23::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:02:23::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:02:23::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWMssOS::DEBUG: swdes dump C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.18:02:23::SCWMssOS::Sw design exists and opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:02:23::SCWReader::No isolation master present -LOG::2026-05-27.18:03:27::SCWPlatform::Started generating the artifacts platform NewInstCal_bsp -TRACE::2026-05-27.18:03:27::SCWPlatform::Sanity checking of platform is completed -LOG::2026-05-27.18:03:27::SCWPlatform::Started generating the artifacts for system configuration NewInstCal_bsp -LOG::2026-05-27.18:03:27::SCWSystem::Checking the domain zynq_fsbl -LOG::2026-05-27.18:03:27::SCWSystem::Doing application build for : zynq_fsbl -TRACE::2026-05-27.18:03:27::SCWBDomain::Not a forced makefile updation, No changes are present. -TRACE::2026-05-27.18:03:27::SCWDomain::Building the domain as part of full build : zynq_fsbl -TRACE::2026-05-27.18:03:27::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:03:27::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:03:27::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:03:27::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:03:27::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:03:27::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:03:27::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:03:27::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:03:27::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:03:27::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:03:27::SCWMssOS::DEBUG: swdes dump C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.18:03:27::SCWMssOS::Sw design exists and opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:03:27::SCWBDomain::Completed writing the mss file at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp -TRACE::2026-05-27.18:03:28::SCWBDomain::bsp generated is stale removing and regenerating. -TRACE::2026-05-27.18:03:30::SCWBDomain::Updating the makefile used for building the Application zynq_fsbl -TRACE::2026-05-27.18:03:30::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:03:30::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:03:30::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:03:30::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:03:30::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:03:30::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:03:30::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:03:30::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:03:30::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:03:30::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:03:30::SCWMssOS::DEBUG: swdes dump C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| - -TRACE::2026-05-27.18:03:30::SCWMssOS::No sw design opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:03:30::SCWMssOS::mss exists loading the mss file C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:03:30::SCWMssOS::Opened the sw design from mss C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:03:30::SCWMssOS::Adding the swdes entry C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system -TRACE::2026-05-27.18:03:30::SCWMssOS::updating the scw layer about changes -TRACE::2026-05-27.18:03:30::SCWMssOS::Opened the sw design. C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:03:38::SCWBDomain::removing the temporary location in _platform. -TRACE::2026-05-27.18:03:38::SCWBDomain::Makefile is Updated. -TRACE::2026-05-27.18:03:38::SCWBDomain::doing clean. -TRACE::2026-05-27.18:03:38::SCWBDomain::System Command Ran C:& cd C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl & make clean -TRACE::2026-05-27.18:03:39::SCWBDomain::rm -rf sd.o nand.o nor.o image_mover.o md5.o fsbl_hooks.o main.o rsa.o qspi.o ps7_init.o pcap.o fsbl_handoff.o zynq -TRACE::2026-05-27.18:03:39::SCWBDomain::_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a fsbl.elf *.o - -TRACE::2026-05-27.18:03:39::SCWBDomain::System Command Ran C:& cd C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl& make -C zynq_fsbl_bsp & make -TRACE::2026-05-27.18:03:39::SCWBDomain::make: Entering directory 'C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zyn -TRACE::2026-05-27.18:03:39::SCWBDomain::q_fsbl/zynq_fsbl_bsp' - -TRACE::2026-05-27.18:03:39::SCWBDomain::make --no-print-directory seq_libs - -TRACE::2026-05-27.18:03:39::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src" - -TRACE::2026-05-27.18:03:39::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none -TRACE::2026-05-27.18:03:39::SCWBDomain::-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=h -TRACE::2026-05-27.18:03:39::SCWBDomain::ard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:39::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src" - -TRACE::2026-05-27.18:03:39::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-e -TRACE::2026-05-27.18:03:39::SCWBDomain::abi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=har -TRACE::2026-05-27.18:03:39::SCWBDomain::d -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:39::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src" - -TRACE::2026-05-27.18:03:39::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:39::SCWBDomain::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-27.18:03:39::SCWBDomain::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:39::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_8/src" - -TRACE::2026-05-27.18:03:39::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:39::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:39::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:39::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_9/src" - -TRACE::2026-05-27.18:03:39::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:39::SCWBDomain::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-27.18:03:39::SCWBDomain::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:39::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_19/src" - -TRACE::2026-05-27.18:03:39::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:39::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:39::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:40::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_12/src" - -TRACE::2026-05-27.18:03:40::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:40::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:40::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:40::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_11/src" - -TRACE::2026-05-27.18:03:40::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:40::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:40::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:40::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/scugic_v5_2/src" - -TRACE::2026-05-27.18:03:40::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:40::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:40::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:40::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_5/src" - -TRACE::2026-05-27.18:03:40::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.18:03:40::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.18:03:40::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:40::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src" - -TRACE::2026-05-27.18:03:40::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:40::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:40::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:40::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/sdps_v4_2/src" - -TRACE::2026-05-27.18:03:40::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:03:40::SCWBDomain::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:03:40::SCWBDomain::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:40::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/standalone_v9_0/src" - -TRACE::2026-05-27.18:03:40::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.18:03:40::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.18:03:40::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:41::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_13/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:42::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:42::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_7/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:42::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:42::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/xilffs_v5_1/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v5_1/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:42::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:42::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_7/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:42::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:42::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/xilrsa_v1_7/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "A -TRACE::2026-05-27.18:03:42::SCWBDomain::RCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostart -TRACE::2026-05-27.18:03:42::SCWBDomain::files -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::'Finished building libraries sequentially.' - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -j 6 --no-print-directory par_libs - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none -TRACE::2026-05-27.18:03:42::SCWBDomain::-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=h -TRACE::2026-05-27.18:03:42::SCWBDomain::ard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-e -TRACE::2026-05-27.18:03:42::SCWBDomain::abi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=har -TRACE::2026-05-27.18:03:42::SCWBDomain::d -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:42::SCWBDomain::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-27.18:03:42::SCWBDomain::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_8/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:42::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:42::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_9/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:42::SCWBDomain::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-27.18:03:42::SCWBDomain::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_19/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:42::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:42::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_12/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:42::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:42::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_11/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:42::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:42::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/scugic_v5_2/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:42::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:42::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_5/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.18:03:42::SCWBDomain::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.18:03:42::SCWBDomain::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:42::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:42::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/sdps_v4_2/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:03:42::SCWBDomain::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:03:42::SCWBDomain::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/standalone_v9_0/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.18:03:42::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.18:03:42::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_13/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:42::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:42::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_7/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:42::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:42::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/xilffs_v5_1/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v5_1/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:42::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:42::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:42::SCWBDomain::"Running Make include in ps7_cortexa9_0/libsrc/xilrsa_v1_7/src" - -TRACE::2026-05-27.18:03:42::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilrsa_v1_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:42::SCWBDomain:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:42::SCWBDomain::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:43::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src" - -TRACE::2026-05-27.18:03:43::SCWBDomain::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea -TRACE::2026-05-27.18:03:43::SCWBDomain::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.18:03:43::SCWBDomain:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:43::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src" - -TRACE::2026-05-27.18:03:43::SCWBDomain::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.18:03:43::SCWBDomain::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.18:03:43::SCWBDomain::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:43::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_2/src" - -TRACE::2026-05-27.18:03:43::SCWBDomain::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "AR -TRACE::2026-05-27.18:03:43::SCWBDomain::CHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartf -TRACE::2026-05-27.18:03:43::SCWBDomain::iles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:43::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_8/src" - -TRACE::2026-05-27.18:03:43::SCWBDomain::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "A -TRACE::2026-05-27.18:03:43::SCWBDomain::RCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostart -TRACE::2026-05-27.18:03:43::SCWBDomain::files -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:43::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_9/src" - -TRACE::2026-05-27.18:03:43::SCWBDomain::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "AR -TRACE::2026-05-27.18:03:43::SCWBDomain::CHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartf -TRACE::2026-05-27.18:03:43::SCWBDomain::iles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:43::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_19/src" - -TRACE::2026-05-27.18:03:43::SCWBDomain::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:03:43::SCWBDomain::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:03:43::SCWBDomain::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:43::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_12/src" - -TRACE::2026-05-27.18:03:43::SCWBDomain::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:03:43::SCWBDomain::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:03:43::SCWBDomain::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:44::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_11/src" - -TRACE::2026-05-27.18:03:44::SCWBDomain::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:03:44::SCWBDomain::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:03:44::SCWBDomain::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:44::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/scugic_v5_2/src" - -TRACE::2026-05-27.18:03:44::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "A -TRACE::2026-05-27.18:03:44::SCWBDomain::RCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostart -TRACE::2026-05-27.18:03:44::SCWBDomain::files -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:44::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_5/src" - -TRACE::2026-05-27.18:03:45::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:45::SCWBDomain::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-27.18:03:45::SCWBDomain::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:45::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src" - -TRACE::2026-05-27.18:03:45::SCWBDomain::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "A -TRACE::2026-05-27.18:03:45::SCWBDomain::RCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostart -TRACE::2026-05-27.18:03:45::SCWBDomain::files -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:45::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/sdps_v4_2/src" - -TRACE::2026-05-27.18:03:45::SCWBDomain::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARC -TRACE::2026-05-27.18:03:45::SCWBDomain::HIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfi -TRACE::2026-05-27.18:03:45::SCWBDomain::les -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:45::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/standalone_v9_0/src" - -TRACE::2026-05-27.18:03:45::SCWBDomain::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:45::SCWBDomain::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:45::SCWBDomain::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:45::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_13/src" - -TRACE::2026-05-27.18:03:45::SCWBDomain::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:03:45::SCWBDomain::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:03:45::SCWBDomain::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:45::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_7/src" - -TRACE::2026-05-27.18:03:45::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "A -TRACE::2026-05-27.18:03:45::SCWBDomain::RCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostart -TRACE::2026-05-27.18:03:45::SCWBDomain::files -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:46::SCWBDomain::"Running Make libs in ps7_cortexa9_0/libsrc/xilffs_v5_1/src" - -TRACE::2026-05-27.18:03:46::SCWBDomain::make -C ps7_cortexa9_0/libsrc/xilffs_v5_1/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "A -TRACE::2026-05-27.18:03:46::SCWBDomain::RCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostart -TRACE::2026-05-27.18:03:46::SCWBDomain::files -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:48::SCWBDomain::'Finished building libraries parallelly.' - -TRACE::2026-05-27.18:03:48::SCWBDomain::make --no-print-directory archive - -TRACE::2026-05-27.18:03:48::SCWBDomain::arm-none-eabi-ar -r ps7_cortexa9_0/lib/libxil.a ps7_cortexa9_0/lib/_exit.o ps7_cortexa9_0/lib/_open.o ps7_cortexa9_0/lib/_sbrk -TRACE::2026-05-27.18:03:48::SCWBDomain::.o ps7_cortexa9_0/lib/abort.o ps7_cortexa9_0/lib/asm_vectors.o ps7_cortexa9_0/lib/boot.o ps7_cortexa9_0/lib/close.o ps7_cortexa -TRACE::2026-05-27.18:03:48::SCWBDomain::9_0/lib/cpputest_time.o ps7_cortexa9_0/lib/cpu_init.o ps7_cortexa9_0/lib/errno.o ps7_cortexa9_0/lib/fcntl.o ps7_cortexa9_0/lib/ -TRACE::2026-05-27.18:03:48::SCWBDomain::fstat.o ps7_cortexa9_0/lib/getentropy.o ps7_cortexa9_0/lib/getpid.o ps7_cortexa9_0/lib/inbyte.o ps7_cortexa9_0/lib/isatty.o ps7 -TRACE::2026-05-27.18:03:48::SCWBDomain::_cortexa9_0/lib/kill.o ps7_cortexa9_0/lib/lseek.o ps7_cortexa9_0/lib/open.o ps7_cortexa9_0/lib/outbyte.o ps7_cortexa9_0/lib/pri -TRACE::2026-05-27.18:03:48::SCWBDomain::nt.o ps7_cortexa9_0/lib/putnum.o ps7_cortexa9_0/lib/read.o ps7_cortexa9_0/lib/sbrk.o ps7_cortexa9_0/lib/sleep.o ps7_cortexa9_0/ -TRACE::2026-05-27.18:03:48::SCWBDomain::lib/time.o ps7_cortexa9_0/lib/translation_table.o ps7_cortexa9_0/lib/unlink.o ps7_cortexa9_0/lib/usleep.o ps7_cortexa9_0/lib/ve -TRACE::2026-05-27.18:03:48::SCWBDomain::ctors.o ps7_cortexa9_0/lib/write.o ps7_cortexa9_0/lib/xadcps.o ps7_cortexa9_0/lib/xadcps_g.o ps7_cortexa9_0/lib/xadcps_intr.o p -TRACE::2026-05-27.18:03:48::SCWBDomain::s7_cortexa9_0/lib/xadcps_selftest.o ps7_cortexa9_0/lib/xadcps_sinit.o ps7_cortexa9_0/lib/xcoresightpsdcc.o ps7_cortexa9_0/lib/x -TRACE::2026-05-27.18:03:48::SCWBDomain::devcfg.o ps7_cortexa9_0/lib/xdevcfg_g.o ps7_cortexa9_0/lib/xdevcfg_hw.o ps7_cortexa9_0/lib/xdevcfg_intr.o ps7_cortexa9_0/lib/xd -TRACE::2026-05-27.18:03:48::SCWBDomain::evcfg_selftest.o ps7_cortexa9_0/lib/xdevcfg_sinit.o ps7_cortexa9_0/lib/xdmaps.o ps7_cortexa9_0/lib/xdmaps_g.o ps7_cortexa9_0/li -TRACE::2026-05-27.18:03:48::SCWBDomain::b/xdmaps_hw.o ps7_cortexa9_0/lib/xdmaps_selftest.o ps7_cortexa9_0/lib/xdmaps_sinit.o ps7_cortexa9_0/lib/xemacps.o ps7_cortexa9_ -TRACE::2026-05-27.18:03:48::SCWBDomain::0/lib/xemacps_bdring.o ps7_cortexa9_0/lib/xemacps_control.o ps7_cortexa9_0/lib/xemacps_g.o ps7_cortexa9_0/lib/xemacps_hw.o ps7_ -TRACE::2026-05-27.18:03:48::SCWBDomain::cortexa9_0/lib/xemacps_intr.o ps7_cortexa9_0/lib/xemacps_sinit.o ps7_cortexa9_0/lib/xgpiops.o ps7_cortexa9_0/lib/xgpiops_g.o ps -TRACE::2026-05-27.18:03:48::SCWBDomain::7_cortexa9_0/lib/xgpiops_hw.o ps7_cortexa9_0/lib/xgpiops_intr.o ps7_cortexa9_0/lib/xgpiops_selftest.o ps7_cortexa9_0/lib/xgpiop -TRACE::2026-05-27.18:03:48::SCWBDomain::s_sinit.o ps7_cortexa9_0/lib/xil-crt0.o ps7_cortexa9_0/lib/xil_assert.o ps7_cortexa9_0/lib/xil_cache.o ps7_cortexa9_0/lib/xil_c -TRACE::2026-05-27.18:03:48::SCWBDomain::locking.o ps7_cortexa9_0/lib/xil_exception.o ps7_cortexa9_0/lib/xil_mem.o ps7_cortexa9_0/lib/xil_misc_psreset_api.o ps7_cortexa -TRACE::2026-05-27.18:03:48::SCWBDomain::9_0/lib/xil_mmu.o ps7_cortexa9_0/lib/xil_printf.o ps7_cortexa9_0/lib/xil_sleepcommon.o ps7_cortexa9_0/lib/xil_sleeptimer.o ps7_ -TRACE::2026-05-27.18:03:48::SCWBDomain::cortexa9_0/lib/xil_spinlock.o ps7_cortexa9_0/lib/xil_testcache.o ps7_cortexa9_0/lib/xil_testio.o ps7_cortexa9_0/lib/xil_testmem -TRACE::2026-05-27.18:03:48::SCWBDomain::.o ps7_cortexa9_0/lib/xil_util.o ps7_cortexa9_0/lib/xinterrupt_wrap.o ps7_cortexa9_0/lib/xl2cc_counter.o ps7_cortexa9_0/lib/xpl -TRACE::2026-05-27.18:03:48::SCWBDomain::atform_info.o ps7_cortexa9_0/lib/xpm_counter.o ps7_cortexa9_0/lib/xpm_init.o ps7_cortexa9_0/lib/xqspips.o ps7_cortexa9_0/lib/xq -TRACE::2026-05-27.18:03:48::SCWBDomain::spips_g.o ps7_cortexa9_0/lib/xqspips_hw.o ps7_cortexa9_0/lib/xqspips_options.o ps7_cortexa9_0/lib/xqspips_selftest.o ps7_cortex -TRACE::2026-05-27.18:03:48::SCWBDomain::a9_0/lib/xqspips_sinit.o ps7_cortexa9_0/lib/xscugic.o ps7_cortexa9_0/lib/xscugic_g.o ps7_cortexa9_0/lib/xscugic_hw.o ps7_cortex -TRACE::2026-05-27.18:03:48::SCWBDomain::a9_0/lib/xscugic_intr.o ps7_cortexa9_0/lib/xscugic_selftest.o ps7_cortexa9_0/lib/xscugic_sinit.o ps7_cortexa9_0/lib/xscutimer.o -TRACE::2026-05-27.18:03:48::SCWBDomain:: ps7_cortexa9_0/lib/xscutimer_g.o ps7_cortexa9_0/lib/xscutimer_selftest.o ps7_cortexa9_0/lib/xscutimer_sinit.o ps7_cortexa9_0/l -TRACE::2026-05-27.18:03:48::SCWBDomain::ib/xscuwdt.o ps7_cortexa9_0/lib/xscuwdt_g.o ps7_cortexa9_0/lib/xscuwdt_selftest.o ps7_cortexa9_0/lib/xscuwdt_sinit.o ps7_cortex -TRACE::2026-05-27.18:03:48::SCWBDomain::a9_0/lib/xsdps.o ps7_cortexa9_0/lib/xsdps_card.o ps7_cortexa9_0/lib/xsdps_g.o ps7_cortexa9_0/lib/xsdps_host.o ps7_cortexa9_0/li -TRACE::2026-05-27.18:03:48::SCWBDomain::b/xsdps_options.o ps7_cortexa9_0/lib/xsdps_sinit.o ps7_cortexa9_0/lib/xtime_l.o ps7_cortexa9_0/lib/xuartps.o ps7_cortexa9_0/lib -TRACE::2026-05-27.18:03:48::SCWBDomain::/xuartps_g.o ps7_cortexa9_0/lib/xuartps_hw.o ps7_cortexa9_0/lib/xuartps_intr.o ps7_cortexa9_0/lib/xuartps_options.o ps7_cortexa -TRACE::2026-05-27.18:03:48::SCWBDomain::9_0/lib/xuartps_selftest.o ps7_cortexa9_0/lib/xuartps_sinit.o - -TRACE::2026-05-27.18:03:49::SCWBDomain::'Finished building libraries' - -TRACE::2026-05-27.18:03:49::SCWBDomain::make: Leaving directory 'C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq -TRACE::2026-05-27.18:03:49::SCWBDomain::_fsbl/zynq_fsbl_bsp' - -TRACE::2026-05-27.18:03:49::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c sd.c -o sd.o -Izynq_fsbl_bsp/ps7_cort -TRACE::2026-05-27.18:03:49::SCWBDomain::exa9_0/include -I. - -TRACE::2026-05-27.18:03:49::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c nand.c -o nand.o -Izynq_fsbl_bsp/ps7_ -TRACE::2026-05-27.18:03:49::SCWBDomain::cortexa9_0/include -I. - -TRACE::2026-05-27.18:03:49::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c nor.c -o nor.o -Izynq_fsbl_bsp/ps7_co -TRACE::2026-05-27.18:03:49::SCWBDomain::rtexa9_0/include -I. - -TRACE::2026-05-27.18:03:49::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c image_mover.c -o image_mover.o -Izynq -TRACE::2026-05-27.18:03:49::SCWBDomain::_fsbl_bsp/ps7_cortexa9_0/include -I. - -TRACE::2026-05-27.18:03:49::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c md5.c -o md5.o -Izynq_fsbl_bsp/ps7_co -TRACE::2026-05-27.18:03:49::SCWBDomain::rtexa9_0/include -I. - -TRACE::2026-05-27.18:03:49::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c fsbl_hooks.c -o fsbl_hooks.o -Izynq_f -TRACE::2026-05-27.18:03:49::SCWBDomain::sbl_bsp/ps7_cortexa9_0/include -I. - -TRACE::2026-05-27.18:03:50::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c main.c -o main.o -Izynq_fsbl_bsp/ps7_ -TRACE::2026-05-27.18:03:50::SCWBDomain::cortexa9_0/include -I. - -TRACE::2026-05-27.18:03:50::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c rsa.c -o rsa.o -Izynq_fsbl_bsp/ps7_co -TRACE::2026-05-27.18:03:50::SCWBDomain::rtexa9_0/include -I. - -TRACE::2026-05-27.18:03:50::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c qspi.c -o qspi.o -Izynq_fsbl_bsp/ps7_ -TRACE::2026-05-27.18:03:50::SCWBDomain::cortexa9_0/include -I. - -TRACE::2026-05-27.18:03:50::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c ps7_init.c -o ps7_init.o -Izynq_fsbl_ -TRACE::2026-05-27.18:03:50::SCWBDomain::bsp/ps7_cortexa9_0/include -I. - -TRACE::2026-05-27.18:03:50::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c pcap.c -o pcap.o -Izynq_fsbl_bsp/ps7_ -TRACE::2026-05-27.18:03:50::SCWBDomain::cortexa9_0/include -I. - -TRACE::2026-05-27.18:03:50::SCWBDomain::arm-none-eabi-gcc -O2 -c -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -c fsbl_handoff.S -o fsbl_handoff.o -Izy -TRACE::2026-05-27.18:03:50::SCWBDomain::nq_fsbl_bsp/ps7_cortexa9_0/include -I. - -TRACE::2026-05-27.18:03:50::SCWBDomain::arm-none-eabi-gcc -o fsbl.elf fsbl_handoff.o fsbl_hooks.o image_mover.o main.o md5.o nand.o nor.o pcap.o ps7_init.o qspi.o rsa. -TRACE::2026-05-27.18:03:50::SCWBDomain::o sd.o -MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id -TRACE::2026-05-27.18:03:50::SCWBDomain::=none -specs=Xilinx.spec -lrsa -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end- -TRACE::2026-05-27.18:03:50::SCWBDomain::group -Wl,--start-group,-lrsa,-lxil,-lgcc,-lc,--end-group -Wl,--gc-sections -Lzynq_fsbl_bsp/p -TRACE::2026-05-27.18:03:50::SCWBDomain::s7_cortexa9_0/lib -L./ -Tlscript.ld - -LOG::2026-05-27.18:03:51::SCWSystem::Checking the domain standalone_domain -LOG::2026-05-27.18:03:51::SCWSystem::Not a boot domain -LOG::2026-05-27.18:03:51::SCWSystem::Started Processing the domain standalone_domain -TRACE::2026-05-27.18:03:51::SCWDomain::Generating domain artifcats -TRACE::2026-05-27.18:03:51::SCWMssOS::Generating standalone artifcats -TRACE::2026-05-27.18:03:51::SCWMssOS::Copying the qemu file from C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt To C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/qemu/ -TRACE::2026-05-27.18:03:51::SCWMssOS::Copying the qemu file from C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt To C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/export/NewInstCal_bsp/sw/NewInstCal_bsp/standalone_domain/qemu/ -TRACE::2026-05-27.18:03:51::SCWMssOS:: Copying the user libraries. -TRACE::2026-05-27.18:03:51::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:03:51::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:03:51::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:03:51::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:03:51::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:03:51::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:03:51::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:03:51::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:03:51::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:03:51::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:03:51::SCWMssOS::DEBUG: swdes dump C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.18:03:51::SCWMssOS::Sw design exists and opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:03:51::SCWMssOS::Completed writing the mss file at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp -TRACE::2026-05-27.18:03:51::SCWMssOS::Mss edits present, copying mssfile into export location C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:03:51::SCWMssOS::bsp generated is stale removing and regenerating. -TRACE::2026-05-27.18:03:53::SCWMssOS::doing bsp build ... -TRACE::2026-05-27.18:03:53::SCWMssOS::System Command Ran C: & cd C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp & make -TRACE::2026-05-27.18:03:53::SCWMssOS::make --no-print-directory seq_libs - -TRACE::2026-05-27.18:03:53::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src" - -TRACE::2026-05-27.18:03:53::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none -TRACE::2026-05-27.18:03:53::SCWMssOS::-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=h -TRACE::2026-05-27.18:03:53::SCWMssOS::ard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:53::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src" - -TRACE::2026-05-27.18:03:53::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-e -TRACE::2026-05-27.18:03:53::SCWMssOS::abi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=har -TRACE::2026-05-27.18:03:53::SCWMssOS::d -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:53::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src" - -TRACE::2026-05-27.18:03:54::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:54::SCWMssOS::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-27.18:03:54::SCWMssOS::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:54::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_8/src" - -TRACE::2026-05-27.18:03:54::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:54::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:54::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:54::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_9/src" - -TRACE::2026-05-27.18:03:54::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:54::SCWMssOS::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-27.18:03:54::SCWMssOS::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:54::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_19/src" - -TRACE::2026-05-27.18:03:54::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:54::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:54::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:54::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_12/src" - -TRACE::2026-05-27.18:03:54::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:54::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:54::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:54::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/lwip213_v1_1/src" - -TRACE::2026-05-27.18:03:54::SCWMssOS::make -C ps7_cortexa9_0/libsrc/lwip213_v1_1/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:54::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:54::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:56::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_11/src" - -TRACE::2026-05-27.18:03:56::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:56::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:56::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:56::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/scugic_v5_2/src" - -TRACE::2026-05-27.18:03:56::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:56::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:56::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:56::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_5/src" - -TRACE::2026-05-27.18:03:56::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.18:03:56::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.18:03:56::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:56::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src" - -TRACE::2026-05-27.18:03:56::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:56::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:56::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:57::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/sdps_v4_2/src" - -TRACE::2026-05-27.18:03:57::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:03:57::SCWMssOS::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:03:57::SCWMssOS::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:57::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/standalone_v9_0/src" - -TRACE::2026-05-27.18:03:57::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.18:03:57::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.18:03:57::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:58::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_13/src" - -TRACE::2026-05-27.18:03:58::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:03:58::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:03:58::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:58::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_7/src" - -TRACE::2026-05-27.18:03:58::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:03:58::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:03:58::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:58::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/lwip213_v1_1/src" - -TRACE::2026-05-27.18:03:58::SCWMssOS::make -C ps7_cortexa9_0/libsrc/lwip213_v1_1/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:03:58::SCWMssOS::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:03:58::SCWMssOS::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:03:58::SCWMssOS::"Compiling lwip src and adapter files" - -TRACE::2026-05-27.18:04:06::SCWMssOS::'Finished building libraries sequentially.' - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -j 6 --no-print-directory par_libs - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none -TRACE::2026-05-27.18:04:06::SCWMssOS::-eabi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=h -TRACE::2026-05-27.18:04:06::SCWMssOS::ard -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-e -TRACE::2026-05-27.18:04:06::SCWMssOS::abi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=har -TRACE::2026-05-27.18:04:06::SCWMssOS::d -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/ddrps_v1_2/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:04:06::SCWMssOS::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-27.18:04:06::SCWMssOS::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/devcfg_v3_8/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:04:06::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:04:06::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/dmaps_v2_9/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:04:06::SCWMssOS::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-27.18:04:06::SCWMssOS::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/emacps_v3_19/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:04:06::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:04:06::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/gpiops_v3_12/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:04:06::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:04:06::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/lwip213_v1_1/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/lwip213_v1_1/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:04:06::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:04:06::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/qspips_v3_11/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:04:06::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:04:06::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/scugic_v5_2/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:04:06::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:04:06::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/scutimer_v2_5/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-a -TRACE::2026-05-27.18:04:06::SCWMssOS::s" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -no -TRACE::2026-05-27.18:04:06::SCWMssOS::startfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:04:06::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:04:06::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/sdps_v4_2/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:04:06::SCWMssOS::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:04:06::SCWMssOS::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/standalone_v9_0/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.18:04:06::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.18:04:06::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/uartps_v3_13/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:04:06::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:04:06::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:06::SCWMssOS::"Running Make include in ps7_cortexa9_0/libsrc/xadcps_v2_7/src" - -TRACE::2026-05-27.18:04:06::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s include "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:04:06::SCWMssOS:: "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nost -TRACE::2026-05-27.18:04:06::SCWMssOS::artfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:07::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src" - -TRACE::2026-05-27.18:04:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/coresightps_dcc_v1_9/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-ea -TRACE::2026-05-27.18:04:07::SCWMssOS::bi-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -TRACE::2026-05-27.18:04:07::SCWMssOS:: -nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:07::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src" - -TRACE::2026-05-27.18:04:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi -TRACE::2026-05-27.18:04:07::SCWMssOS::-as" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard - -TRACE::2026-05-27.18:04:07::SCWMssOS::nostartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:07::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/ddrps_v1_2/src" - -TRACE::2026-05-27.18:04:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/ddrps_v1_2/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "AR -TRACE::2026-05-27.18:04:07::SCWMssOS::CHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartf -TRACE::2026-05-27.18:04:07::SCWMssOS::iles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:07::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/devcfg_v3_8/src" - -TRACE::2026-05-27.18:04:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/devcfg_v3_8/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "A -TRACE::2026-05-27.18:04:07::SCWMssOS::RCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostart -TRACE::2026-05-27.18:04:07::SCWMssOS::files -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:07::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/dmaps_v2_9/src" - -TRACE::2026-05-27.18:04:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/dmaps_v2_9/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "AR -TRACE::2026-05-27.18:04:07::SCWMssOS::CHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartf -TRACE::2026-05-27.18:04:07::SCWMssOS::iles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:07::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/emacps_v3_19/src" - -TRACE::2026-05-27.18:04:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/emacps_v3_19/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:04:07::SCWMssOS::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:04:07::SCWMssOS::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:07::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/gpiops_v3_12/src" - -TRACE::2026-05-27.18:04:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/gpiops_v3_12/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:04:07::SCWMssOS::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:04:07::SCWMssOS::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:07::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/qspips_v3_11/src" - -TRACE::2026-05-27.18:04:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/qspips_v3_11/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:04:07::SCWMssOS::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:04:07::SCWMssOS::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:07::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/scugic_v5_2/src" - -TRACE::2026-05-27.18:04:07::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scugic_v5_2/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "A -TRACE::2026-05-27.18:04:07::SCWMssOS::RCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostart -TRACE::2026-05-27.18:04:07::SCWMssOS::files -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:08::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/scutimer_v2_5/src" - -TRACE::2026-05-27.18:04:08::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scutimer_v2_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" -TRACE::2026-05-27.18:04:08::SCWMssOS::"ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nosta -TRACE::2026-05-27.18:04:08::SCWMssOS::rtfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:09::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/scuwdt_v2_5/src" - -TRACE::2026-05-27.18:04:09::SCWMssOS::make -C ps7_cortexa9_0/libsrc/scuwdt_v2_5/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "A -TRACE::2026-05-27.18:04:09::SCWMssOS::RCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostart -TRACE::2026-05-27.18:04:09::SCWMssOS::files -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:09::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/sdps_v4_2/src" - -TRACE::2026-05-27.18:04:09::SCWMssOS::make -C ps7_cortexa9_0/libsrc/sdps_v4_2/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "ARC -TRACE::2026-05-27.18:04:09::SCWMssOS::HIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfi -TRACE::2026-05-27.18:04:09::SCWMssOS::les -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:09::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/standalone_v9_0/src" - -TRACE::2026-05-27.18:04:09::SCWMssOS::make -C ps7_cortexa9_0/libsrc/standalone_v9_0/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as -TRACE::2026-05-27.18:04:09::SCWMssOS::" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nos -TRACE::2026-05-27.18:04:09::SCWMssOS::tartfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:09::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/uartps_v3_13/src" - -TRACE::2026-05-27.18:04:09::SCWMssOS::make -C ps7_cortexa9_0/libsrc/uartps_v3_13/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" " -TRACE::2026-05-27.18:04:09::SCWMssOS::ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostar -TRACE::2026-05-27.18:04:09::SCWMssOS::tfiles -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:09::SCWMssOS::"Running Make libs in ps7_cortexa9_0/libsrc/xadcps_v2_7/src" - -TRACE::2026-05-27.18:04:09::SCWMssOS::make -C ps7_cortexa9_0/libsrc/xadcps_v2_7/src -s libs "SHELL=CMD" "COMPILER=arm-none-eabi-gcc" "ASSEMBLER=arm-none-eabi-as" "A -TRACE::2026-05-27.18:04:09::SCWMssOS::RCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostart -TRACE::2026-05-27.18:04:09::SCWMssOS::files -g -Wall -Wextra -fno-tree-loop-distribute-patterns" - -TRACE::2026-05-27.18:04:11::SCWMssOS::'Finished building libraries parallelly.' - -TRACE::2026-05-27.18:04:11::SCWMssOS::make --no-print-directory archive - -TRACE::2026-05-27.18:04:11::SCWMssOS::arm-none-eabi-ar -r ps7_cortexa9_0/lib/libxil.a ps7_cortexa9_0/lib/_exit.o ps7_cortexa9_0/lib/_open.o ps7_cortexa9_0/lib/_sbrk -TRACE::2026-05-27.18:04:11::SCWMssOS::.o ps7_cortexa9_0/lib/abort.o ps7_cortexa9_0/lib/asm_vectors.o ps7_cortexa9_0/lib/boot.o ps7_cortexa9_0/lib/close.o ps7_cortexa -TRACE::2026-05-27.18:04:11::SCWMssOS::9_0/lib/cpputest_time.o ps7_cortexa9_0/lib/cpu_init.o ps7_cortexa9_0/lib/errno.o ps7_cortexa9_0/lib/fcntl.o ps7_cortexa9_0/lib/ -TRACE::2026-05-27.18:04:11::SCWMssOS::fstat.o ps7_cortexa9_0/lib/getentropy.o ps7_cortexa9_0/lib/getpid.o ps7_cortexa9_0/lib/inbyte.o ps7_cortexa9_0/lib/isatty.o ps7 -TRACE::2026-05-27.18:04:11::SCWMssOS::_cortexa9_0/lib/kill.o ps7_cortexa9_0/lib/lseek.o ps7_cortexa9_0/lib/open.o ps7_cortexa9_0/lib/outbyte.o ps7_cortexa9_0/lib/pri -TRACE::2026-05-27.18:04:11::SCWMssOS::nt.o ps7_cortexa9_0/lib/putnum.o ps7_cortexa9_0/lib/read.o ps7_cortexa9_0/lib/sbrk.o ps7_cortexa9_0/lib/sleep.o ps7_cortexa9_0/ -TRACE::2026-05-27.18:04:11::SCWMssOS::lib/time.o ps7_cortexa9_0/lib/translation_table.o ps7_cortexa9_0/lib/unlink.o ps7_cortexa9_0/lib/usleep.o ps7_cortexa9_0/lib/ve -TRACE::2026-05-27.18:04:11::SCWMssOS::ctors.o ps7_cortexa9_0/lib/write.o ps7_cortexa9_0/lib/xadcps.o ps7_cortexa9_0/lib/xadcps_g.o ps7_cortexa9_0/lib/xadcps_intr.o p -TRACE::2026-05-27.18:04:11::SCWMssOS::s7_cortexa9_0/lib/xadcps_selftest.o ps7_cortexa9_0/lib/xadcps_sinit.o ps7_cortexa9_0/lib/xcoresightpsdcc.o ps7_cortexa9_0/lib/x -TRACE::2026-05-27.18:04:11::SCWMssOS::devcfg.o ps7_cortexa9_0/lib/xdevcfg_g.o ps7_cortexa9_0/lib/xdevcfg_hw.o ps7_cortexa9_0/lib/xdevcfg_intr.o ps7_cortexa9_0/lib/xd -TRACE::2026-05-27.18:04:11::SCWMssOS::evcfg_selftest.o ps7_cortexa9_0/lib/xdevcfg_sinit.o ps7_cortexa9_0/lib/xdmaps.o ps7_cortexa9_0/lib/xdmaps_g.o ps7_cortexa9_0/li -TRACE::2026-05-27.18:04:11::SCWMssOS::b/xdmaps_hw.o ps7_cortexa9_0/lib/xdmaps_selftest.o ps7_cortexa9_0/lib/xdmaps_sinit.o ps7_cortexa9_0/lib/xemacps.o ps7_cortexa9_ -TRACE::2026-05-27.18:04:11::SCWMssOS::0/lib/xemacps_bdring.o ps7_cortexa9_0/lib/xemacps_control.o ps7_cortexa9_0/lib/xemacps_g.o ps7_cortexa9_0/lib/xemacps_hw.o ps7_ -TRACE::2026-05-27.18:04:11::SCWMssOS::cortexa9_0/lib/xemacps_intr.o ps7_cortexa9_0/lib/xemacps_sinit.o ps7_cortexa9_0/lib/xgpiops.o ps7_cortexa9_0/lib/xgpiops_g.o ps -TRACE::2026-05-27.18:04:11::SCWMssOS::7_cortexa9_0/lib/xgpiops_hw.o ps7_cortexa9_0/lib/xgpiops_intr.o ps7_cortexa9_0/lib/xgpiops_selftest.o ps7_cortexa9_0/lib/xgpiop -TRACE::2026-05-27.18:04:11::SCWMssOS::s_sinit.o ps7_cortexa9_0/lib/xil-crt0.o ps7_cortexa9_0/lib/xil_assert.o ps7_cortexa9_0/lib/xil_cache.o ps7_cortexa9_0/lib/xil_c -TRACE::2026-05-27.18:04:11::SCWMssOS::locking.o ps7_cortexa9_0/lib/xil_exception.o ps7_cortexa9_0/lib/xil_mem.o ps7_cortexa9_0/lib/xil_misc_psreset_api.o ps7_cortexa -TRACE::2026-05-27.18:04:11::SCWMssOS::9_0/lib/xil_mmu.o ps7_cortexa9_0/lib/xil_printf.o ps7_cortexa9_0/lib/xil_sleepcommon.o ps7_cortexa9_0/lib/xil_sleeptimer.o ps7_ -TRACE::2026-05-27.18:04:11::SCWMssOS::cortexa9_0/lib/xil_spinlock.o ps7_cortexa9_0/lib/xil_testcache.o ps7_cortexa9_0/lib/xil_testio.o ps7_cortexa9_0/lib/xil_testmem -TRACE::2026-05-27.18:04:11::SCWMssOS::.o ps7_cortexa9_0/lib/xil_util.o ps7_cortexa9_0/lib/xinterrupt_wrap.o ps7_cortexa9_0/lib/xl2cc_counter.o ps7_cortexa9_0/lib/xpl -TRACE::2026-05-27.18:04:11::SCWMssOS::atform_info.o ps7_cortexa9_0/lib/xpm_counter.o ps7_cortexa9_0/lib/xpm_init.o ps7_cortexa9_0/lib/xqspips.o ps7_cortexa9_0/lib/xq -TRACE::2026-05-27.18:04:11::SCWMssOS::spips_g.o ps7_cortexa9_0/lib/xqspips_hw.o ps7_cortexa9_0/lib/xqspips_options.o ps7_cortexa9_0/lib/xqspips_selftest.o ps7_cortex -TRACE::2026-05-27.18:04:11::SCWMssOS::a9_0/lib/xqspips_sinit.o ps7_cortexa9_0/lib/xscugic.o ps7_cortexa9_0/lib/xscugic_g.o ps7_cortexa9_0/lib/xscugic_hw.o ps7_cortex -TRACE::2026-05-27.18:04:11::SCWMssOS::a9_0/lib/xscugic_intr.o ps7_cortexa9_0/lib/xscugic_selftest.o ps7_cortexa9_0/lib/xscugic_sinit.o ps7_cortexa9_0/lib/xscutimer.o -TRACE::2026-05-27.18:04:11::SCWMssOS:: ps7_cortexa9_0/lib/xscutimer_g.o ps7_cortexa9_0/lib/xscutimer_selftest.o ps7_cortexa9_0/lib/xscutimer_sinit.o ps7_cortexa9_0/l -TRACE::2026-05-27.18:04:11::SCWMssOS::ib/xscuwdt.o ps7_cortexa9_0/lib/xscuwdt_g.o ps7_cortexa9_0/lib/xscuwdt_selftest.o ps7_cortexa9_0/lib/xscuwdt_sinit.o ps7_cortex -TRACE::2026-05-27.18:04:11::SCWMssOS::a9_0/lib/xsdps.o ps7_cortexa9_0/lib/xsdps_card.o ps7_cortexa9_0/lib/xsdps_g.o ps7_cortexa9_0/lib/xsdps_host.o ps7_cortexa9_0/li -TRACE::2026-05-27.18:04:11::SCWMssOS::b/xsdps_options.o ps7_cortexa9_0/lib/xsdps_sinit.o ps7_cortexa9_0/lib/xtime_l.o ps7_cortexa9_0/lib/xuartps.o ps7_cortexa9_0/lib -TRACE::2026-05-27.18:04:11::SCWMssOS::/xuartps_g.o ps7_cortexa9_0/lib/xuartps_hw.o ps7_cortexa9_0/lib/xuartps_intr.o ps7_cortexa9_0/lib/xuartps_options.o ps7_cortexa -TRACE::2026-05-27.18:04:11::SCWMssOS::9_0/lib/xuartps_selftest.o ps7_cortexa9_0/lib/xuartps_sinit.o - -TRACE::2026-05-27.18:04:12::SCWMssOS::'Finished building libraries' - -TRACE::2026-05-27.18:04:12::SCWMssOS:: Checking if to create the Supporting Applications -TRACE::2026-05-27.18:04:12::SCWMssOS:: No Linux domain exists, trying to generate FSBL -LOG::2026-05-27.18:04:12::SCWSystem::Completed Processing the domain standalone_domain -LOG::2026-05-27.18:04:12::SCWSystem::Completed Processing the sysconfig NewInstCal_bsp -LOG::2026-05-27.18:04:12::SCWPlatform::Completed generating the artifacts for system configuration NewInstCal_bsp -TRACE::2026-05-27.18:04:12::SCWPlatform::Started preparing the platform -TRACE::2026-05-27.18:04:12::SCWSystem::Writing the bif file for system config NewInstCal_bsp -TRACE::2026-05-27.18:04:12::SCWSystem::dir created -TRACE::2026-05-27.18:04:12::SCWSystem::Writing the bif -TRACE::2026-05-27.18:04:12::SCWPlatform::Started writing the spfm file -TRACE::2026-05-27.18:04:12::SCWPlatform::Started writing the xpfm file -TRACE::2026-05-27.18:04:12::SCWPlatform::Completed generating the platform -TRACE::2026-05-27.18:04:12::SCWMssOS::Saving the mss changes C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:04:12::SCWMssOS::Found a swdesign opened with the mssfile. -TRACE::2026-05-27.18:04:12::SCWMssOS::Running validate of swdbs. -KEYINFO::2026-05-27.18:04:12::SCWMssOS::Could not open the swdb for system -KEYINFO::2026-05-27.18:04:12::SCWMssOS::Could not open the sw design at system -ERROR: [Hsi 55-1558] Software Design system is not found - -TRACE::2026-05-27.18:04:12::SCWMssOS::Cleared the swdb table entry -TRACE::2026-05-27.18:04:12::SCWMssOS::Adding the swdes entry, mss present, able to open swdb C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss with des name system -TRACE::2026-05-27.18:04:12::SCWMssOS::Writing the mss file completed C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:04:12::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.18:04:12::SCWMssOS::Saving the mss changes C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:04:12::SCWMssOS::Adding the swdes entry, mss present, able to open swdb C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss with des name system_0 -TRACE::2026-05-27.18:04:12::SCWMssOS::Writing the mss file completed C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:04:12::SCWMssOS::Commit changes completed. -TRACE::2026-05-27.18:04:12::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:04:12::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:04:12::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:04:12::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:04:12::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:04:12::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:04:12::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:04:12::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:04:12::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:04:12::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:04:12::SCWMssOS::DEBUG: swdes dump C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.18:04:12::SCWMssOS::Sw design exists and opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss -TRACE::2026-05-27.18:04:12::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:04:12::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:04:12::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:04:12::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:04:12::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:04:12::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:04:12::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:04:12::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:04:12::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:04:12::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:04:12::SCWMssOS::DEBUG: swdes dump C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.18:04:12::SCWMssOS::Sw design exists and opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:04:12::SCWWriter::formatted JSON is { - "platformName": "NewInstCal_bsp", - "sprVersion": "2.0", - "mode": "gui", - "dsaType": "Fixed", - "platformDesc": "NewInstCal_bsp", - "platHandOff": "/home/ly0kos/work/prj/New_CalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/system_wrapper.xsa", - "platIntHandOff": "/hw/system_wrapper.xsa", - "deviceType": "zynq", - "platIsPrebuiltAutogen": "false", - "platIsNoBootBsp": "false", - "hasFsblMakeHasChanges": "false", - "hasPmufwMakeHasChanges": "false", - "fsblExtraCompilerFlags": "-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ", - "platPreBuiltFlag": false, - "platformSamplesDir": "", - "platActiveSys": "NewInstCal_bsp", - "systems": [{ - "systemName": "NewInstCal_bsp", - "systemDesc": "NewInstCal_bsp", - "sysIsBootAutoGen": "true", - "systemDispName": "NewInstCal_bsp", - "sysActiveDom": "standalone_domain", - "sysDefaultDom": "standalone_domain", - "domains": [{ - "domainName": "zynq_fsbl", - "domainDispName": "zynq_fsbl", - "domainDesc": "FSBL Application BSP - Auto Generated.", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "debugEnable": "", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "3243e54020e3af7b58d483729f3822a1", - "compatibleApp": "zynq_fsbl", - "domType": "bootDomain", - "arch": "32-bit", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["xilffs:5.1", "xilrsa:1.7"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }, { - "domainName": "standalone_domain", - "domainDispName": "standalone on ps7_cortexa9_0", - "domainDesc": "standalone_domain", - "processors": "ps7_cortexa9_0", - "os": "standalone", - "sdxOs": "standalone", - "qemuArgs": "/resources/NewInstCal_bsp/standalone_domain/qemu_args.txt", - "qemuData": "/resources/NewInstCal_bsp/standalone_domain/qemu", - "debugEnable": "False", - "domRuntimes": ["cpp"], - "swRepo": "", - "mssOsVer": "9.0", - "mssFile": "", - "md5Digest": "1422839dbecb6fdfcf744dce689d156a", - "compatibleApp": "", - "domType": "mssDomain", - "appSettings": { - "appCompilerFlags": "", - "appLinkerFlags": "" - }, - "addedLibs": ["lwip213:1.1"], - "libOptions": { - "libsContainingOptions": [] - }, - "prebuiltLibs": { - "prebuiltIncPath": [], - "prebuiltLibPath": [] - }, - "isolation": { - } - }] - }] -} -KEYINFO::2026-05-27.18:04:12::SCWPlatform::updated the xpfm file. -TRACE::2026-05-27.18:04:13::SCWPlatform::Trying to open the hw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:04:13::SCWPlatform::DSA given C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:04:13::SCWPlatform::DSA absoulate path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:04:13::SCWPlatform::DSA directory C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw -TRACE::2026-05-27.18:04:13::SCWPlatform:: Platform Path C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/hw/system_wrapper.xsa -TRACE::2026-05-27.18:04:13::SCWPlatform:: Unique name xilinx:::0.0 -TRACE::2026-05-27.18:04:13::SCWPlatform::Trying to set the existing hwdb with name system_wrapper -TRACE::2026-05-27.18:04:13::SCWPlatform::Opened existing hwdb system_wrapper -TRACE::2026-05-27.18:04:13::SCWPlatform::Found the Hw Db part of the input DSA -TRACE::2026-05-27.18:04:13::SCWMssOS::Checking the sw design at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss -TRACE::2026-05-27.18:04:13::SCWMssOS::DEBUG: swdes dump C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss|system_0|| -C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/zynq_fsbl/zynq_fsbl_bsp/system.mss|system|| - -TRACE::2026-05-27.18:04:13::SCWMssOS::Sw design exists and opened at C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/Zynq/Debug_FW/Vitis_Classic/NewInstCal_bsp/ps7_cortexa9_0/standalone_domain/bsp/system.mss