yuysh/NewInstrCalBoard_Zynq
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Add UART Debugging code

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yuysh
2026-05-28 17:02:45 +08:00
parent d744efedf0
commit 480f680726
4 changed files with 203 additions and 8 deletions
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Vitis_Classic/NewInstrCalBoard/src/main.c
+26 -7
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@@ -40,26 +40,44 @@
#include "GPIO_Driv.h"
#include "SPI_Driv.h"
#include "cal_meas.h"
#include "uart_IO.h"
u8 recvbuffer[1024] = {0};
int main()
{
init_platform();
xil_printf("=====================\r\n[I] System Init Done!\r\n");
xil_printf("[D] Start EMIO Config\r\n");
EMIO_config();
xil_printf("[D] End of EMIO Config\r\n");
interface_initial(CPLD_U1);
interface_initial(CPLD_U2);
interface_initial(CPLD_U3);
xil_printf("[D] Start CPLD Reset\r\n");
rst_CPLD(CPLD_U1,4);
rst_CPLD(CPLD_U2,4);
rst_CPLD(CPLD_U3,4);
xil_printf("[D] End of CPLD Reset\r\n");
xil_printf("[D] Config CPLD SPI to known state\r\n");
interface_initial(CPLD_U1);
interface_initial(CPLD_U2);
interface_initial(CPLD_U3);
/* receive and process packets */
while (1) {
xil_printf("[I] Board Init Complete!\r\n[I] Waiting for Command...\r\n");
/* receive and process Instructions */
int len = 0;
while (1)
{
int Status = -255;
Status = UART_RecvInstr(recvbuffer);
if (Status < 0)
{
xil_printf("[E] UART Receive ERROR!!! Check PrintOut Ahead\r\n");
}
}
/* never reached */
@@ -67,3 +85,4 @@ int main()
return 0;
}