/*******************************************************************************
* Copyright (c) 2018 - 2021 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/


#ifndef __XPMC_XIOU_SLCR_H__
#define __XPMC_XIOU_SLCR_H__


#ifdef __cplusplus
extern "C" {
#endif

/**
 *@cond nocomments
 */

/**
 * XpmcXiouSlcr Base Address
 */
#define XPMC_XIOU_SLCR_BASEADDR      0xF1060000UL

/**
 * Register: XpmcXiouSlcrMioPin0
 */
#define XPMC_XIOU_SLCR_MIO_PIN_0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000000UL )
#define XPMC_XIOU_SLCR_MIO_PIN_0_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_0_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_0_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_0_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_0_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_0_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_0_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_0_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_0_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin1
 */
#define XPMC_XIOU_SLCR_MIO_PIN_1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000004UL )
#define XPMC_XIOU_SLCR_MIO_PIN_1_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_1_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_1_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_1_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_1_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_1_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_1_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_1_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_1_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin2
 */
#define XPMC_XIOU_SLCR_MIO_PIN_2    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000008UL )
#define XPMC_XIOU_SLCR_MIO_PIN_2_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_2_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_2_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_2_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_2_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_2_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_2_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_2_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_2_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin3
 */
#define XPMC_XIOU_SLCR_MIO_PIN_3    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000000CUL )
#define XPMC_XIOU_SLCR_MIO_PIN_3_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_3_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_3_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_3_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_3_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_3_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_3_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_3_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_3_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin4
 */
#define XPMC_XIOU_SLCR_MIO_PIN_4    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000010UL )
#define XPMC_XIOU_SLCR_MIO_PIN_4_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_4_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_4_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_4_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_4_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_4_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_4_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_4_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_4_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin5
 */
#define XPMC_XIOU_SLCR_MIO_PIN_5    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000014UL )
#define XPMC_XIOU_SLCR_MIO_PIN_5_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_5_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_5_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_5_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_5_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_5_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_5_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_5_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_5_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin6
 */
#define XPMC_XIOU_SLCR_MIO_PIN_6    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000018UL )
#define XPMC_XIOU_SLCR_MIO_PIN_6_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_6_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_6_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_6_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_6_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_6_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_6_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_6_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_6_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin7
 */
#define XPMC_XIOU_SLCR_MIO_PIN_7    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000001CUL )
#define XPMC_XIOU_SLCR_MIO_PIN_7_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_7_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_7_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_7_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_7_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_7_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_7_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_7_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_7_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin8
 */
#define XPMC_XIOU_SLCR_MIO_PIN_8    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000020UL )
#define XPMC_XIOU_SLCR_MIO_PIN_8_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_8_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_8_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_8_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_8_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_8_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_8_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_8_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_8_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin9
 */
#define XPMC_XIOU_SLCR_MIO_PIN_9    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000024UL )
#define XPMC_XIOU_SLCR_MIO_PIN_9_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_9_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_9_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_9_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_9_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_9_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_9_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_9_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_9_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin10
 */
#define XPMC_XIOU_SLCR_MIO_PIN_10    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000028UL )
#define XPMC_XIOU_SLCR_MIO_PIN_10_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_10_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_10_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_10_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_10_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_10_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_10_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_10_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_10_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin11
 */
#define XPMC_XIOU_SLCR_MIO_PIN_11    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000002CUL )
#define XPMC_XIOU_SLCR_MIO_PIN_11_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_11_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_11_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_11_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_11_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_11_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_11_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_11_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_11_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin12
 */
#define XPMC_XIOU_SLCR_MIO_PIN_12    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000030UL )
#define XPMC_XIOU_SLCR_MIO_PIN_12_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_12_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_12_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_12_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_12_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_12_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_12_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_12_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_12_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin13
 */
#define XPMC_XIOU_SLCR_MIO_PIN_13    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000034UL )
#define XPMC_XIOU_SLCR_MIO_PIN_13_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_13_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_13_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_13_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_13_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_13_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_13_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_13_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_13_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin14
 */
#define XPMC_XIOU_SLCR_MIO_PIN_14    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000038UL )
#define XPMC_XIOU_SLCR_MIO_PIN_14_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_14_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_14_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_14_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_14_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_14_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_14_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_14_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_14_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin15
 */
#define XPMC_XIOU_SLCR_MIO_PIN_15    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000003CUL )
#define XPMC_XIOU_SLCR_MIO_PIN_15_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_15_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_15_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_15_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_15_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_15_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_15_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_15_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_15_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin16
 */
#define XPMC_XIOU_SLCR_MIO_PIN_16    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000040UL )
#define XPMC_XIOU_SLCR_MIO_PIN_16_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_16_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_16_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_16_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_16_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_16_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_16_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_16_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_16_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin17
 */
#define XPMC_XIOU_SLCR_MIO_PIN_17    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000044UL )
#define XPMC_XIOU_SLCR_MIO_PIN_17_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_17_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_17_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_17_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_17_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_17_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_17_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_17_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_17_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin18
 */
#define XPMC_XIOU_SLCR_MIO_PIN_18    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000048UL )
#define XPMC_XIOU_SLCR_MIO_PIN_18_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_18_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_18_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_18_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_18_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_18_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_18_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_18_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_18_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin19
 */
#define XPMC_XIOU_SLCR_MIO_PIN_19    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000004CUL )
#define XPMC_XIOU_SLCR_MIO_PIN_19_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_19_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_19_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_19_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_19_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_19_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_19_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_19_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_19_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin20
 */
#define XPMC_XIOU_SLCR_MIO_PIN_20    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000050UL )
#define XPMC_XIOU_SLCR_MIO_PIN_20_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_20_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_20_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_20_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_20_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_20_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_20_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_20_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_20_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin21
 */
#define XPMC_XIOU_SLCR_MIO_PIN_21    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000054UL )
#define XPMC_XIOU_SLCR_MIO_PIN_21_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_21_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_21_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_21_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_21_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_21_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_21_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_21_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_21_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin22
 */
#define XPMC_XIOU_SLCR_MIO_PIN_22    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000058UL )
#define XPMC_XIOU_SLCR_MIO_PIN_22_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_22_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_22_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_22_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_22_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_22_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_22_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_22_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_22_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin23
 */
#define XPMC_XIOU_SLCR_MIO_PIN_23    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000005CUL )
#define XPMC_XIOU_SLCR_MIO_PIN_23_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_23_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_23_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_23_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_23_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_23_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_23_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_23_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_23_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin24
 */
#define XPMC_XIOU_SLCR_MIO_PIN_24    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000060UL )
#define XPMC_XIOU_SLCR_MIO_PIN_24_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_24_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_24_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_24_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_24_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_24_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_24_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_24_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_24_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin25
 */
#define XPMC_XIOU_SLCR_MIO_PIN_25    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000064UL )
#define XPMC_XIOU_SLCR_MIO_PIN_25_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_25_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_25_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_25_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_25_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_25_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_25_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_25_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_25_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin26
 */
#define XPMC_XIOU_SLCR_MIO_PIN_26    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000068UL )
#define XPMC_XIOU_SLCR_MIO_PIN_26_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_26_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_26_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_26_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_26_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_26_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_26_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_26_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_26_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin27
 */
#define XPMC_XIOU_SLCR_MIO_PIN_27    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000006CUL )
#define XPMC_XIOU_SLCR_MIO_PIN_27_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_27_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_27_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_27_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_27_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_27_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_27_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_27_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_27_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin28
 */
#define XPMC_XIOU_SLCR_MIO_PIN_28    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000070UL )
#define XPMC_XIOU_SLCR_MIO_PIN_28_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_28_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_28_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_28_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_28_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_28_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_28_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_28_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_28_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin29
 */
#define XPMC_XIOU_SLCR_MIO_PIN_29    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000074UL )
#define XPMC_XIOU_SLCR_MIO_PIN_29_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_29_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_29_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_29_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_29_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_29_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_29_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_29_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_29_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin30
 */
#define XPMC_XIOU_SLCR_MIO_PIN_30    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000078UL )
#define XPMC_XIOU_SLCR_MIO_PIN_30_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_30_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_30_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_30_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_30_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_30_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_30_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_30_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_30_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin31
 */
#define XPMC_XIOU_SLCR_MIO_PIN_31    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000007CUL )
#define XPMC_XIOU_SLCR_MIO_PIN_31_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_31_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_31_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_31_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_31_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_31_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_31_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_31_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_31_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin32
 */
#define XPMC_XIOU_SLCR_MIO_PIN_32    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000080UL )
#define XPMC_XIOU_SLCR_MIO_PIN_32_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_32_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_32_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_32_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_32_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_32_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_32_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_32_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_32_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin33
 */
#define XPMC_XIOU_SLCR_MIO_PIN_33    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000084UL )
#define XPMC_XIOU_SLCR_MIO_PIN_33_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_33_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_33_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_33_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_33_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_33_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_33_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_33_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_33_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin34
 */
#define XPMC_XIOU_SLCR_MIO_PIN_34    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000088UL )
#define XPMC_XIOU_SLCR_MIO_PIN_34_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_34_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_34_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_34_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_34_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_34_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_34_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_34_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_34_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin35
 */
#define XPMC_XIOU_SLCR_MIO_PIN_35    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000008CUL )
#define XPMC_XIOU_SLCR_MIO_PIN_35_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_35_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_35_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_35_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_35_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_35_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_35_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_35_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_35_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin36
 */
#define XPMC_XIOU_SLCR_MIO_PIN_36    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000090UL )
#define XPMC_XIOU_SLCR_MIO_PIN_36_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_36_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_36_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_36_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_36_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_36_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_36_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_36_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_36_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin37
 */
#define XPMC_XIOU_SLCR_MIO_PIN_37    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000094UL )
#define XPMC_XIOU_SLCR_MIO_PIN_37_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_37_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_37_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_37_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_37_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_37_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_37_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_37_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_37_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin38
 */
#define XPMC_XIOU_SLCR_MIO_PIN_38    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000098UL )
#define XPMC_XIOU_SLCR_MIO_PIN_38_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_38_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_38_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_38_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_38_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_38_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_38_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_38_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_38_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin39
 */
#define XPMC_XIOU_SLCR_MIO_PIN_39    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000009CUL )
#define XPMC_XIOU_SLCR_MIO_PIN_39_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_39_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_39_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_39_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_39_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_39_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_39_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_39_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_39_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin40
 */
#define XPMC_XIOU_SLCR_MIO_PIN_40    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000000A0UL )
#define XPMC_XIOU_SLCR_MIO_PIN_40_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_40_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_40_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_40_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_40_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_40_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_40_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_40_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_40_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin41
 */
#define XPMC_XIOU_SLCR_MIO_PIN_41    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000000A4UL )
#define XPMC_XIOU_SLCR_MIO_PIN_41_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_41_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_41_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_41_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_41_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_41_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_41_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_41_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_41_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin42
 */
#define XPMC_XIOU_SLCR_MIO_PIN_42    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000000A8UL )
#define XPMC_XIOU_SLCR_MIO_PIN_42_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_42_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_42_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_42_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_42_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_42_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_42_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_42_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_42_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin43
 */
#define XPMC_XIOU_SLCR_MIO_PIN_43    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000000ACUL )
#define XPMC_XIOU_SLCR_MIO_PIN_43_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_43_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_43_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_43_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_43_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_43_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_43_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_43_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_43_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin44
 */
#define XPMC_XIOU_SLCR_MIO_PIN_44    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000000B0UL )
#define XPMC_XIOU_SLCR_MIO_PIN_44_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_44_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_44_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_44_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_44_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_44_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_44_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_44_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_44_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin45
 */
#define XPMC_XIOU_SLCR_MIO_PIN_45    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000000B4UL )
#define XPMC_XIOU_SLCR_MIO_PIN_45_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_45_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_45_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_45_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_45_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_45_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_45_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_45_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_45_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin46
 */
#define XPMC_XIOU_SLCR_MIO_PIN_46    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000000B8UL )
#define XPMC_XIOU_SLCR_MIO_PIN_46_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_46_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_46_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_46_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_46_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_46_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_46_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_46_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_46_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin47
 */
#define XPMC_XIOU_SLCR_MIO_PIN_47    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000000BCUL )
#define XPMC_XIOU_SLCR_MIO_PIN_47_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_47_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_47_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_47_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_47_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_47_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_47_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_47_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_47_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin48
 */
#define XPMC_XIOU_SLCR_MIO_PIN_48    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000000C0UL )
#define XPMC_XIOU_SLCR_MIO_PIN_48_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_48_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_48_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_48_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_48_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_48_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_48_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_48_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_48_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin49
 */
#define XPMC_XIOU_SLCR_MIO_PIN_49    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000000C4UL )
#define XPMC_XIOU_SLCR_MIO_PIN_49_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_49_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_49_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_49_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_49_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_49_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_49_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_49_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_49_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin50
 */
#define XPMC_XIOU_SLCR_MIO_PIN_50    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000000C8UL )
#define XPMC_XIOU_SLCR_MIO_PIN_50_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_50_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_50_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_50_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_50_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_50_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_50_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_50_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_50_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioPin51
 */
#define XPMC_XIOU_SLCR_MIO_PIN_51    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000000CCUL )
#define XPMC_XIOU_SLCR_MIO_PIN_51_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_PIN_51_L3_SEL_WIDTH   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_51_L3_SEL_MASK    0x00000380UL
#define XPMC_XIOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_PIN_51_L2_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_51_L2_SEL_MASK    0x00000060UL
#define XPMC_XIOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_PIN_51_L1_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_51_L1_SEL_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_PIN_51_L0_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_MIO_PIN_51_L0_SEL_MASK    0x00000006UL
#define XPMC_XIOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0EnRx
 */
#define XPMC_XIOU_SLCR_BNK0_EN_RX    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000100UL )
#define XPMC_XIOU_SLCR_BNK0_EN_RX_RSTVAL   0x03ffffffUL

#define XPMC_XIOU_SLCR_BNK0_EN_RX_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_EN_RX_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK0_EN_RX_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK0_EN_RX_DEFVAL  0x3ffffffUL

/**
 * Register: XpmcXiouSlcrBnk0SelRx0
 */
#define XPMC_XIOU_SLCR_BNK0_SEL_RX0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000104UL )
#define XPMC_XIOU_SLCR_BNK0_SEL_RX0_RSTVAL   0xffffffffUL

#define XPMC_XIOU_SLCR_BNK0_SEL_RX0_RX_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_SEL_RX0_RX_WIDTH   32UL
#define XPMC_XIOU_SLCR_BNK0_SEL_RX0_RX_MASK    0xffffffffUL
#define XPMC_XIOU_SLCR_BNK0_SEL_RX0_RX_DEFVAL  0xffffffffUL

/**
 * Register: XpmcXiouSlcrBnk0SelRx1
 */
#define XPMC_XIOU_SLCR_BNK0_SEL_RX1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000108UL )
#define XPMC_XIOU_SLCR_BNK0_SEL_RX1_RSTVAL   0x000fffffUL

#define XPMC_XIOU_SLCR_BNK0_SEL_RX1_RX_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_SEL_RX1_RX_WIDTH   20UL
#define XPMC_XIOU_SLCR_BNK0_SEL_RX1_RX_MASK    0x000fffffUL
#define XPMC_XIOU_SLCR_BNK0_SEL_RX1_RX_DEFVAL  0xfffffUL

/**
 * Register: XpmcXiouSlcrBnk0EnRxSchmittHyst
 */
#define XPMC_XIOU_SLCR_BNK0_EN_RX_SCHMITT_HYST    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000010CUL )
#define XPMC_XIOU_SLCR_BNK0_EN_RX_SCHMITT_HYST_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_EN_RX_SCHMITT_HYST_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_EN_RX_SCHMITT_HYST_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK0_EN_RX_SCHMITT_HYST_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK0_EN_RX_SCHMITT_HYST_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0EnWkPd
 */
#define XPMC_XIOU_SLCR_BNK0_EN_WK_PD    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000110UL )
#define XPMC_XIOU_SLCR_BNK0_EN_WK_PD_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_EN_WK_PD_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_EN_WK_PD_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK0_EN_WK_PD_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK0_EN_WK_PD_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0EnWkPu
 */
#define XPMC_XIOU_SLCR_BNK0_EN_WK_PU    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000114UL )
#define XPMC_XIOU_SLCR_BNK0_EN_WK_PU_RSTVAL   0x03ffffffUL

#define XPMC_XIOU_SLCR_BNK0_EN_WK_PU_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_EN_WK_PU_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK0_EN_WK_PU_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK0_EN_WK_PU_DEFVAL  0x3ffffffUL

/**
 * Register: XpmcXiouSlcrBnk0SelDrv0
 */
#define XPMC_XIOU_SLCR_BNK0_SEL_DRV0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000118UL )
#define XPMC_XIOU_SLCR_BNK0_SEL_DRV0_RSTVAL   0xaaaaaaaaUL

#define XPMC_XIOU_SLCR_BNK0_SEL_DRV0_DRV_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_SEL_DRV0_DRV_WIDTH   32UL
#define XPMC_XIOU_SLCR_BNK0_SEL_DRV0_DRV_MASK    0xffffffffUL
#define XPMC_XIOU_SLCR_BNK0_SEL_DRV0_DRV_DEFVAL  0xaaaaaaaaUL

/**
 * Register: XpmcXiouSlcrBnk0SelDrv1
 */
#define XPMC_XIOU_SLCR_BNK0_SEL_DRV1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000011CUL )
#define XPMC_XIOU_SLCR_BNK0_SEL_DRV1_RSTVAL   0x000aaaaaUL

#define XPMC_XIOU_SLCR_BNK0_SEL_DRV1_DRV_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_SEL_DRV1_DRV_WIDTH   20UL
#define XPMC_XIOU_SLCR_BNK0_SEL_DRV1_DRV_MASK    0x000fffffUL
#define XPMC_XIOU_SLCR_BNK0_SEL_DRV1_DRV_DEFVAL  0xaaaaaUL

/**
 * Register: XpmcXiouSlcrBnk0SelSlew
 */
#define XPMC_XIOU_SLCR_BNK0_SEL_SLEW    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000120UL )
#define XPMC_XIOU_SLCR_BNK0_SEL_SLEW_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_SEL_SLEW_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_SEL_SLEW_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK0_SEL_SLEW_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK0_SEL_SLEW_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0EnDftOptInv
 */
#define XPMC_XIOU_SLCR_BNK0_EN_DFT_OPT_INV    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000124UL )
#define XPMC_XIOU_SLCR_BNK0_EN_DFT_OPT_INV_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_EN_DFT_OPT_INV_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_EN_DFT_OPT_INV_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK0_EN_DFT_OPT_INV_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK0_EN_DFT_OPT_INV_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0EnPad2padLpbck
 */
#define XPMC_XIOU_SLCR_BNK0_EN_PAD2PAD_LPBCK    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000128UL )
#define XPMC_XIOU_SLCR_BNK0_EN_PAD2PAD_LPBCK_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_EN_PAD2PAD_LPBCK_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_EN_PAD2PAD_LPBCK_WIDTH   13UL
#define XPMC_XIOU_SLCR_BNK0_EN_PAD2PAD_LPBCK_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_BNK0_EN_PAD2PAD_LPBCK_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0RxSpr0
 */
#define XPMC_XIOU_SLCR_BNK0_RX_SPR0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000012CUL )
#define XPMC_XIOU_SLCR_BNK0_RX_SPR0_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_RX_SPR0_SPR_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_RX_SPR0_SPR_WIDTH   32UL
#define XPMC_XIOU_SLCR_BNK0_RX_SPR0_SPR_MASK    0xffffffffUL
#define XPMC_XIOU_SLCR_BNK0_RX_SPR0_SPR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0RxSpr1
 */
#define XPMC_XIOU_SLCR_BNK0_RX_SPR1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000130UL )
#define XPMC_XIOU_SLCR_BNK0_RX_SPR1_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_RX_SPR1_SPR_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_RX_SPR1_SPR_WIDTH   20UL
#define XPMC_XIOU_SLCR_BNK0_RX_SPR1_SPR_MASK    0x000fffffUL
#define XPMC_XIOU_SLCR_BNK0_RX_SPR1_SPR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0TxSpr0
 */
#define XPMC_XIOU_SLCR_BNK0_TX_SPR0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000134UL )
#define XPMC_XIOU_SLCR_BNK0_TX_SPR0_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_TX_SPR0_SPR_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_TX_SPR0_SPR_WIDTH   32UL
#define XPMC_XIOU_SLCR_BNK0_TX_SPR0_SPR_MASK    0xffffffffUL
#define XPMC_XIOU_SLCR_BNK0_TX_SPR0_SPR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0TxSpr1
 */
#define XPMC_XIOU_SLCR_BNK0_TX_SPR1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000138UL )
#define XPMC_XIOU_SLCR_BNK0_TX_SPR1_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_TX_SPR1_SPR_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_TX_SPR1_SPR_WIDTH   20UL
#define XPMC_XIOU_SLCR_BNK0_TX_SPR1_SPR_MASK    0x000fffffUL
#define XPMC_XIOU_SLCR_BNK0_TX_SPR1_SPR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0SelEn1p8
 */
#define XPMC_XIOU_SLCR_BNK0_SEL_EN1P8    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000013CUL )
#define XPMC_XIOU_SLCR_BNK0_SEL_EN1P8_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_SEL_EN1P8_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_SEL_EN1P8_WIDTH   1UL
#define XPMC_XIOU_SLCR_BNK0_SEL_EN1P8_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_BNK0_SEL_EN1P8_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0EnBPorDetect
 */
#define XPMC_XIOU_SLCR_BNK0_EN_B_POR_DETECT    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000140UL )
#define XPMC_XIOU_SLCR_BNK0_EN_B_POR_DETECT_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_EN_B_POR_DETECT_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_EN_B_POR_DETECT_WIDTH   1UL
#define XPMC_XIOU_SLCR_BNK0_EN_B_POR_DETECT_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_BNK0_EN_B_POR_DETECT_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0LpfBypPorDetect
 */
#define XPMC_XIOU_SLCR_BNK0_LPF_BYP_POR_DETECT    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000144UL )
#define XPMC_XIOU_SLCR_BNK0_LPF_BYP_POR_DETECT_RSTVAL   0x00000001UL

#define XPMC_XIOU_SLCR_BNK0_LPF_BYP_POR_DETECT_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_LPF_BYP_POR_DETECT_WIDTH   1UL
#define XPMC_XIOU_SLCR_BNK0_LPF_BYP_POR_DETECT_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_BNK0_LPF_BYP_POR_DETECT_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrBnk0EnLatch
 */
#define XPMC_XIOU_SLCR_BNK0_EN_LATCH    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000148UL )
#define XPMC_XIOU_SLCR_BNK0_EN_LATCH_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_EN_LATCH_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_EN_LATCH_WIDTH   1UL
#define XPMC_XIOU_SLCR_BNK0_EN_LATCH_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_BNK0_EN_LATCH_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0VbgLpfBypB
 */
#define XPMC_XIOU_SLCR_BNK0_VBG_LPF_BYP_B    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000014CUL )
#define XPMC_XIOU_SLCR_BNK0_VBG_LPF_BYP_B_RSTVAL   0x00000001UL

#define XPMC_XIOU_SLCR_BNK0_VBG_LPF_BYP_B_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_VBG_LPF_BYP_B_WIDTH   1UL
#define XPMC_XIOU_SLCR_BNK0_VBG_LPF_BYP_B_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_BNK0_VBG_LPF_BYP_B_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrBnk0EnAmpB
 */
#define XPMC_XIOU_SLCR_BNK0_EN_AMP_B    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000150UL )
#define XPMC_XIOU_SLCR_BNK0_EN_AMP_B_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_EN_AMP_B_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_EN_AMP_B_WIDTH   2UL
#define XPMC_XIOU_SLCR_BNK0_EN_AMP_B_MASK    0x00000003UL
#define XPMC_XIOU_SLCR_BNK0_EN_AMP_B_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0SprBias
 */
#define XPMC_XIOU_SLCR_BNK0_SPR_BIAS    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000154UL )
#define XPMC_XIOU_SLCR_BNK0_SPR_BIAS_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_SPR_BIAS_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_SPR_BIAS_WIDTH   4UL
#define XPMC_XIOU_SLCR_BNK0_SPR_BIAS_MASK    0x0000000fUL
#define XPMC_XIOU_SLCR_BNK0_SPR_BIAS_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0DriverBias
 */
#define XPMC_XIOU_SLCR_BNK0_DRIVER_BIAS    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000158UL )
#define XPMC_XIOU_SLCR_BNK0_DRIVER_BIAS_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_DRIVER_BIAS_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_DRIVER_BIAS_WIDTH   15UL
#define XPMC_XIOU_SLCR_BNK0_DRIVER_BIAS_MASK    0x00007fffUL
#define XPMC_XIOU_SLCR_BNK0_DRIVER_BIAS_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0Vmode
 */
#define XPMC_XIOU_SLCR_BNK0_VMODE    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000015CUL )
#define XPMC_XIOU_SLCR_BNK0_VMODE_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_VMODE_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_VMODE_WIDTH   1UL
#define XPMC_XIOU_SLCR_BNK0_VMODE_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_BNK0_VMODE_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0SelAuxIoRx
 */
#define XPMC_XIOU_SLCR_BNK0_SEL_AUX_IO_RX    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000160UL )
#define XPMC_XIOU_SLCR_BNK0_SEL_AUX_IO_RX_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_SEL_AUX_IO_RX_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_SEL_AUX_IO_RX_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK0_SEL_AUX_IO_RX_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK0_SEL_AUX_IO_RX_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk0EnTxHsMode
 */
#define XPMC_XIOU_SLCR_BNK0_EN_TX_HS_MODE    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000164UL )
#define XPMC_XIOU_SLCR_BNK0_EN_TX_HS_MODE_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK0_EN_TX_HS_MODE_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK0_EN_TX_HS_MODE_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK0_EN_TX_HS_MODE_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK0_EN_TX_HS_MODE_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrMioMstTri0
 */
#define XPMC_XIOU_SLCR_MIO_MST_TRI0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000200UL )
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_RSTVAL   0x03ffffffUL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT   25UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK    0x02000000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT   24UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK    0x01000000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT   23UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK    0x00800000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT   22UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK    0x00400000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT   21UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK    0x00200000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT   20UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK    0x00100000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT   19UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK    0x00080000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT   18UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK    0x00040000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT   17UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK    0x00020000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT   16UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK    0x00010000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT   15UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK    0x00008000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT   14UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK    0x00004000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT   13UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK    0x00002000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT   12UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK    0x00001000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT   11UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK    0x00000800UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT   10UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK    0x00000400UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT   9UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK    0x00000200UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT   8UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK    0x00000100UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK    0x00000080UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT   6UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK    0x00000040UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK    0x00000020UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT   4UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT   2UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT   0UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrMioMstTri1
 */
#define XPMC_XIOU_SLCR_MIO_MST_TRI1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000204UL )
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_RSTVAL   0x03ffffffUL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT   25UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK    0x02000000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT   24UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK    0x01000000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT   23UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK    0x00800000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT   22UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK    0x00400000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT   21UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK    0x00200000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT   20UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK    0x00100000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT   19UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK    0x00080000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT   18UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK    0x00040000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT   17UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK    0x00020000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT   16UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK    0x00010000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT   15UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK    0x00008000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT   14UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK    0x00004000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT   13UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK    0x00002000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT   12UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK    0x00001000UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT   11UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK    0x00000800UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT   10UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK    0x00000400UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT   9UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK    0x00000200UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT   8UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK    0x00000100UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT   7UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK    0x00000080UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT   6UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK    0x00000040UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_31_TRI_SHIFT   5UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_31_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_31_TRI_MASK    0x00000020UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_31_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_30_TRI_SHIFT   4UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_30_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_30_TRI_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_30_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_29_TRI_SHIFT   3UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_29_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_29_TRI_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_29_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_28_TRI_SHIFT   2UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_28_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_28_TRI_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_28_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_27_TRI_SHIFT   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_27_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_27_TRI_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_27_TRI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_26_TRI_SHIFT   0UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_26_TRI_WIDTH   1UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_26_TRI_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_MIO_MST_TRI1_PIN_26_TRI_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrBnk1EnRx
 */
#define XPMC_XIOU_SLCR_BNK1_EN_RX    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000300UL )
#define XPMC_XIOU_SLCR_BNK1_EN_RX_RSTVAL   0x03ffffffUL

#define XPMC_XIOU_SLCR_BNK1_EN_RX_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_EN_RX_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK1_EN_RX_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK1_EN_RX_DEFVAL  0x3ffffffUL

/**
 * Register: XpmcXiouSlcrBnk1SelRx0
 */
#define XPMC_XIOU_SLCR_BNK1_SEL_RX0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000304UL )
#define XPMC_XIOU_SLCR_BNK1_SEL_RX0_RSTVAL   0xffffffffUL

#define XPMC_XIOU_SLCR_BNK1_SEL_RX0_RX_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_SEL_RX0_RX_WIDTH   32UL
#define XPMC_XIOU_SLCR_BNK1_SEL_RX0_RX_MASK    0xffffffffUL
#define XPMC_XIOU_SLCR_BNK1_SEL_RX0_RX_DEFVAL  0xffffffffUL

/**
 * Register: XpmcXiouSlcrBnk1SelRx1
 */
#define XPMC_XIOU_SLCR_BNK1_SEL_RX1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000308UL )
#define XPMC_XIOU_SLCR_BNK1_SEL_RX1_RSTVAL   0x000fffffUL

#define XPMC_XIOU_SLCR_BNK1_SEL_RX1_RX_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_SEL_RX1_RX_WIDTH   20UL
#define XPMC_XIOU_SLCR_BNK1_SEL_RX1_RX_MASK    0x000fffffUL
#define XPMC_XIOU_SLCR_BNK1_SEL_RX1_RX_DEFVAL  0xfffffUL

/**
 * Register: XpmcXiouSlcrBnk1EnRxSchmittHyst
 */
#define XPMC_XIOU_SLCR_BNK1_EN_RX_SCHMITT_HYST    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000030CUL )
#define XPMC_XIOU_SLCR_BNK1_EN_RX_SCHMITT_HYST_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_EN_RX_SCHMITT_HYST_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_EN_RX_SCHMITT_HYST_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK1_EN_RX_SCHMITT_HYST_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK1_EN_RX_SCHMITT_HYST_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1EnWkPd
 */
#define XPMC_XIOU_SLCR_BNK1_EN_WK_PD    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000310UL )
#define XPMC_XIOU_SLCR_BNK1_EN_WK_PD_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_EN_WK_PD_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_EN_WK_PD_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK1_EN_WK_PD_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK1_EN_WK_PD_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1EnWkPu
 */
#define XPMC_XIOU_SLCR_BNK1_EN_WK_PU    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000314UL )
#define XPMC_XIOU_SLCR_BNK1_EN_WK_PU_RSTVAL   0x03ffffffUL

#define XPMC_XIOU_SLCR_BNK1_EN_WK_PU_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_EN_WK_PU_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK1_EN_WK_PU_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK1_EN_WK_PU_DEFVAL  0x3ffffffUL

/**
 * Register: XpmcXiouSlcrBnk1SelDrv0
 */
#define XPMC_XIOU_SLCR_BNK1_SEL_DRV0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000318UL )
#define XPMC_XIOU_SLCR_BNK1_SEL_DRV0_RSTVAL   0xaaaaaaaaUL

#define XPMC_XIOU_SLCR_BNK1_SEL_DRV0_DRV_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_SEL_DRV0_DRV_WIDTH   32UL
#define XPMC_XIOU_SLCR_BNK1_SEL_DRV0_DRV_MASK    0xffffffffUL
#define XPMC_XIOU_SLCR_BNK1_SEL_DRV0_DRV_DEFVAL  0xaaaaaaaaUL

/**
 * Register: XpmcXiouSlcrBnk1SelDrv1
 */
#define XPMC_XIOU_SLCR_BNK1_SEL_DRV1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000031CUL )
#define XPMC_XIOU_SLCR_BNK1_SEL_DRV1_RSTVAL   0x000aaaaaUL

#define XPMC_XIOU_SLCR_BNK1_SEL_DRV1_DRV_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_SEL_DRV1_DRV_WIDTH   20UL
#define XPMC_XIOU_SLCR_BNK1_SEL_DRV1_DRV_MASK    0x000fffffUL
#define XPMC_XIOU_SLCR_BNK1_SEL_DRV1_DRV_DEFVAL  0xaaaaaUL

/**
 * Register: XpmcXiouSlcrBnk1SelSlew
 */
#define XPMC_XIOU_SLCR_BNK1_SEL_SLEW    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000320UL )
#define XPMC_XIOU_SLCR_BNK1_SEL_SLEW_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_SEL_SLEW_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_SEL_SLEW_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK1_SEL_SLEW_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK1_SEL_SLEW_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1EnDftOptInv
 */
#define XPMC_XIOU_SLCR_BNK1_EN_DFT_OPT_INV    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000324UL )
#define XPMC_XIOU_SLCR_BNK1_EN_DFT_OPT_INV_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_EN_DFT_OPT_INV_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_EN_DFT_OPT_INV_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK1_EN_DFT_OPT_INV_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK1_EN_DFT_OPT_INV_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1EnPad2padLpbck
 */
#define XPMC_XIOU_SLCR_BNK1_EN_PAD2PAD_LPBCK    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000328UL )
#define XPMC_XIOU_SLCR_BNK1_EN_PAD2PAD_LPBCK_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_EN_PAD2PAD_LPBCK_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_EN_PAD2PAD_LPBCK_WIDTH   13UL
#define XPMC_XIOU_SLCR_BNK1_EN_PAD2PAD_LPBCK_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_BNK1_EN_PAD2PAD_LPBCK_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1RxSpr0
 */
#define XPMC_XIOU_SLCR_BNK1_RX_SPR0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000032CUL )
#define XPMC_XIOU_SLCR_BNK1_RX_SPR0_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_RX_SPR0_SPR_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_RX_SPR0_SPR_WIDTH   32UL
#define XPMC_XIOU_SLCR_BNK1_RX_SPR0_SPR_MASK    0xffffffffUL
#define XPMC_XIOU_SLCR_BNK1_RX_SPR0_SPR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1RxSpr1
 */
#define XPMC_XIOU_SLCR_BNK1_RX_SPR1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000330UL )
#define XPMC_XIOU_SLCR_BNK1_RX_SPR1_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_RX_SPR1_SPR_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_RX_SPR1_SPR_WIDTH   20UL
#define XPMC_XIOU_SLCR_BNK1_RX_SPR1_SPR_MASK    0x000fffffUL
#define XPMC_XIOU_SLCR_BNK1_RX_SPR1_SPR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1TxSpr0
 */
#define XPMC_XIOU_SLCR_BNK1_TX_SPR0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000334UL )
#define XPMC_XIOU_SLCR_BNK1_TX_SPR0_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_TX_SPR0_SPR_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_TX_SPR0_SPR_WIDTH   32UL
#define XPMC_XIOU_SLCR_BNK1_TX_SPR0_SPR_MASK    0xffffffffUL
#define XPMC_XIOU_SLCR_BNK1_TX_SPR0_SPR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1TxSpr1
 */
#define XPMC_XIOU_SLCR_BNK1_TX_SPR1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000338UL )
#define XPMC_XIOU_SLCR_BNK1_TX_SPR1_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_TX_SPR1_SPR_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_TX_SPR1_SPR_WIDTH   20UL
#define XPMC_XIOU_SLCR_BNK1_TX_SPR1_SPR_MASK    0x000fffffUL
#define XPMC_XIOU_SLCR_BNK1_TX_SPR1_SPR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1SelEn1p8
 */
#define XPMC_XIOU_SLCR_BNK1_SEL_EN1P8    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000033CUL )
#define XPMC_XIOU_SLCR_BNK1_SEL_EN1P8_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_SEL_EN1P8_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_SEL_EN1P8_WIDTH   1UL
#define XPMC_XIOU_SLCR_BNK1_SEL_EN1P8_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_BNK1_SEL_EN1P8_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1EnBPorDetect
 */
#define XPMC_XIOU_SLCR_BNK1_EN_B_POR_DETECT    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000340UL )
#define XPMC_XIOU_SLCR_BNK1_EN_B_POR_DETECT_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_EN_B_POR_DETECT_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_EN_B_POR_DETECT_WIDTH   1UL
#define XPMC_XIOU_SLCR_BNK1_EN_B_POR_DETECT_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_BNK1_EN_B_POR_DETECT_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1LpfBypPorDetect
 */
#define XPMC_XIOU_SLCR_BNK1_LPF_BYP_POR_DETECT    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000344UL )
#define XPMC_XIOU_SLCR_BNK1_LPF_BYP_POR_DETECT_RSTVAL   0x00000001UL

#define XPMC_XIOU_SLCR_BNK1_LPF_BYP_POR_DETECT_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_LPF_BYP_POR_DETECT_WIDTH   1UL
#define XPMC_XIOU_SLCR_BNK1_LPF_BYP_POR_DETECT_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_BNK1_LPF_BYP_POR_DETECT_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrBnk1EnLatch
 */
#define XPMC_XIOU_SLCR_BNK1_EN_LATCH    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000348UL )
#define XPMC_XIOU_SLCR_BNK1_EN_LATCH_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_EN_LATCH_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_EN_LATCH_WIDTH   1UL
#define XPMC_XIOU_SLCR_BNK1_EN_LATCH_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_BNK1_EN_LATCH_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1VbgLpfBypB
 */
#define XPMC_XIOU_SLCR_BNK1_VBG_LPF_BYP_B    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000034CUL )
#define XPMC_XIOU_SLCR_BNK1_VBG_LPF_BYP_B_RSTVAL   0x00000001UL

#define XPMC_XIOU_SLCR_BNK1_VBG_LPF_BYP_B_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_VBG_LPF_BYP_B_WIDTH   1UL
#define XPMC_XIOU_SLCR_BNK1_VBG_LPF_BYP_B_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_BNK1_VBG_LPF_BYP_B_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrBnk1EnAmpB
 */
#define XPMC_XIOU_SLCR_BNK1_EN_AMP_B    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000350UL )
#define XPMC_XIOU_SLCR_BNK1_EN_AMP_B_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_EN_AMP_B_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_EN_AMP_B_WIDTH   2UL
#define XPMC_XIOU_SLCR_BNK1_EN_AMP_B_MASK    0x00000003UL
#define XPMC_XIOU_SLCR_BNK1_EN_AMP_B_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1SprBias
 */
#define XPMC_XIOU_SLCR_BNK1_SPR_BIAS    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000354UL )
#define XPMC_XIOU_SLCR_BNK1_SPR_BIAS_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_SPR_BIAS_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_SPR_BIAS_WIDTH   4UL
#define XPMC_XIOU_SLCR_BNK1_SPR_BIAS_MASK    0x0000000fUL
#define XPMC_XIOU_SLCR_BNK1_SPR_BIAS_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1DriverBias
 */
#define XPMC_XIOU_SLCR_BNK1_DRIVER_BIAS    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000358UL )
#define XPMC_XIOU_SLCR_BNK1_DRIVER_BIAS_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_DRIVER_BIAS_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_DRIVER_BIAS_WIDTH   15UL
#define XPMC_XIOU_SLCR_BNK1_DRIVER_BIAS_MASK    0x00007fffUL
#define XPMC_XIOU_SLCR_BNK1_DRIVER_BIAS_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1Vmode
 */
#define XPMC_XIOU_SLCR_BNK1_VMODE    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000035CUL )
#define XPMC_XIOU_SLCR_BNK1_VMODE_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_VMODE_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_VMODE_WIDTH   1UL
#define XPMC_XIOU_SLCR_BNK1_VMODE_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_BNK1_VMODE_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1SelAuxIoRx
 */
#define XPMC_XIOU_SLCR_BNK1_SEL_AUX_IO_RX    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000360UL )
#define XPMC_XIOU_SLCR_BNK1_SEL_AUX_IO_RX_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_SEL_AUX_IO_RX_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_SEL_AUX_IO_RX_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK1_SEL_AUX_IO_RX_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK1_SEL_AUX_IO_RX_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrBnk1EnTxHsMode
 */
#define XPMC_XIOU_SLCR_BNK1_EN_TX_HS_MODE    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000364UL )
#define XPMC_XIOU_SLCR_BNK1_EN_TX_HS_MODE_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_BNK1_EN_TX_HS_MODE_SHIFT   0UL
#define XPMC_XIOU_SLCR_BNK1_EN_TX_HS_MODE_WIDTH   26UL
#define XPMC_XIOU_SLCR_BNK1_EN_TX_HS_MODE_MASK    0x03ffffffUL
#define XPMC_XIOU_SLCR_BNK1_EN_TX_HS_MODE_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0ClkCtrl
 */
#define XPMC_XIOU_SLCR_SD0_CLK_CTRL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000400UL )
#define XPMC_XIOU_SLCR_SD0_CLK_CTRL_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD0_CLK_CTRL_SDIO0_FBCLK_SEL_SHIFT   2UL
#define XPMC_XIOU_SLCR_SD0_CLK_CTRL_SDIO0_FBCLK_SEL_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CLK_CTRL_SDIO0_FBCLK_SEL_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_SD0_CLK_CTRL_SDIO0_FBCLK_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_CLK_CTRL_SDIO0_RX_SRC_SEL_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_CLK_CTRL_SDIO0_RX_SRC_SEL_WIDTH   2UL
#define XPMC_XIOU_SLCR_SD0_CLK_CTRL_SDIO0_RX_SRC_SEL_MASK    0x00000003UL
#define XPMC_XIOU_SLCR_SD0_CLK_CTRL_SDIO0_RX_SRC_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0CtrlReg
 */
#define XPMC_XIOU_SLCR_SD0_CTRL_REG    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000404UL )
#define XPMC_XIOU_SLCR_SD0_CTRL_REG_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD0_CTRL_REG_EMMC_SEL_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_CTRL_REG_EMMC_SEL_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CTRL_REG_EMMC_SEL_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD0_CTRL_REG_EMMC_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0CfgReg1
 */
#define XPMC_XIOU_SLCR_SD0_CFG_REG1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000410UL )
#define XPMC_XIOU_SLCR_SD0_CFG_REG1_RSTVAL   0x00003250UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG1_BASECLK_SHIFT   7UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG1_BASECLK_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG1_BASECLK_MASK    0x00007f80UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG1_BASECLK_DEFVAL  0x64UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG1_TUNIGCOUNT_SHIFT   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG1_TUNIGCOUNT_WIDTH   6UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG1_TUNIGCOUNT_MASK    0x0000007eUL
#define XPMC_XIOU_SLCR_SD0_CFG_REG1_TUNIGCOUNT_DEFVAL  0x28UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG1_ASYNCWKPENA_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG1_ASYNCWKPENA_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG1_ASYNCWKPENA_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG1_ASYNCWKPENA_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0CfgReg2
 */
#define XPMC_XIOU_SLCR_SD0_CFG_REG2    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000414UL )
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_RSTVAL   0x00000ffcUL

#define XPMC_XIOU_SLCR_SD0_CFG_REG2_SLOTTYPE_SHIFT   12UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_SLOTTYPE_WIDTH   2UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_SLOTTYPE_MASK    0x00003000UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_SLOTTYPE_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG2_ASYCINTR_SHIFT   11UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_ASYCINTR_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_ASYCINTR_MASK    0x00000800UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_ASYCINTR_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG2_64BIT_SHIFT   10UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_64BIT_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_64BIT_MASK    0x00000400UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_64BIT_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG2_1P8V_SHIFT   9UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_1P8V_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_1P8V_MASK    0x00000200UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_1P8V_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG2_3P0V_SHIFT   8UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_3P0V_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_3P0V_MASK    0x00000100UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_3P0V_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG2_3P3V_SHIFT   7UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_3P3V_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_3P3V_MASK    0x00000080UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_3P3V_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG2_SUSPRES_SHIFT   6UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_SUSPRES_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_SUSPRES_MASK    0x00000040UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_SUSPRES_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG2_SDMA_SHIFT   5UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_SDMA_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_SDMA_MASK    0x00000020UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_SDMA_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG2_HIGHSPEED_SHIFT   4UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_HIGHSPEED_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_HIGHSPEED_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_HIGHSPEED_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG2_ADMA2_SHIFT   3UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_ADMA2_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_ADMA2_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_ADMA2_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG2_8BIT_SHIFT   2UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_8BIT_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_8BIT_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_8BIT_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG2_MAXBLK_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_MAXBLK_WIDTH   2UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_MAXBLK_MASK    0x00000003UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG2_MAXBLK_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0CfgReg3
 */
#define XPMC_XIOU_SLCR_SD0_CFG_REG3    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000418UL )
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_RSTVAL   0x00000407UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG3_TUNINGSDR50_SHIFT   10UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_TUNINGSDR50_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_TUNINGSDR50_MASK    0x00000400UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_TUNINGSDR50_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG3_RETUNETMR_SHIFT   6UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_RETUNETMR_WIDTH   4UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_RETUNETMR_MASK    0x000003c0UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_RETUNETMR_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG3_DDRIVER_SHIFT   5UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_DDRIVER_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_DDRIVER_MASK    0x00000020UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_DDRIVER_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG3_CDRIVER_SHIFT   4UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_CDRIVER_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_CDRIVER_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_CDRIVER_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG3_ADRIVER_SHIFT   3UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_ADRIVER_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_ADRIVER_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_ADRIVER_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG3_DDR50_SHIFT   2UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_DDR50_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_DDR50_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_DDR50_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG3_SDR104_SHIFT   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_SDR104_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_SDR104_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_SDR104_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD0_CFG_REG3_SDR50_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_SDR50_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_SDR50_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD0_CFG_REG3_SDR50_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrSd0Initpreset
 */
#define XPMC_XIOU_SLCR_SD0_INITPRESET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000041CUL )
#define XPMC_XIOU_SLCR_SD0_INITPRESET_RSTVAL   0x00000100UL

#define XPMC_XIOU_SLCR_SD0_INITPRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_INITPRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD0_INITPRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD0_INITPRESET_DEFVAL  0x100UL

/**
 * Register: XpmcXiouSlcrSd0Dsppreset
 */
#define XPMC_XIOU_SLCR_SD0_DSPPRESET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000420UL )
#define XPMC_XIOU_SLCR_SD0_DSPPRESET_RSTVAL   0x00000004UL

#define XPMC_XIOU_SLCR_SD0_DSPPRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_DSPPRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD0_DSPPRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD0_DSPPRESET_DEFVAL  0x4UL

/**
 * Register: XpmcXiouSlcrSd0Hspdpreset
 */
#define XPMC_XIOU_SLCR_SD0_HSPDPRESET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000424UL )
#define XPMC_XIOU_SLCR_SD0_HSPDPRESET_RSTVAL   0x00000002UL

#define XPMC_XIOU_SLCR_SD0_HSPDPRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_HSPDPRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD0_HSPDPRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD0_HSPDPRESET_DEFVAL  0x2UL

/**
 * Register: XpmcXiouSlcrSd0Sdr12preset
 */
#define XPMC_XIOU_SLCR_SD0_SDR12PRESET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000428UL )
#define XPMC_XIOU_SLCR_SD0_SDR12PRESET_RSTVAL   0x00000004UL

#define XPMC_XIOU_SLCR_SD0_SDR12PRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_SDR12PRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD0_SDR12PRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD0_SDR12PRESET_DEFVAL  0x4UL

/**
 * Register: XpmcXiouSlcrSd0Sdr25preset
 */
#define XPMC_XIOU_SLCR_SD0_SDR25PRESET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000042CUL )
#define XPMC_XIOU_SLCR_SD0_SDR25PRESET_RSTVAL   0x00000002UL

#define XPMC_XIOU_SLCR_SD0_SDR25PRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_SDR25PRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD0_SDR25PRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD0_SDR25PRESET_DEFVAL  0x2UL

/**
 * Register: XpmcXiouSlcrSd0Sdr50prset
 */
#define XPMC_XIOU_SLCR_SD0_SDR50PRSET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000430UL )
#define XPMC_XIOU_SLCR_SD0_SDR50PRSET_RSTVAL   0x00000001UL

#define XPMC_XIOU_SLCR_SD0_SDR50PRSET_SDR50PRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_SDR50PRSET_SDR50PRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD0_SDR50PRSET_SDR50PRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD0_SDR50PRSET_SDR50PRESET_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrSd0Sdr104prst
 */
#define XPMC_XIOU_SLCR_SD0_SDR104PRST    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000434UL )
#define XPMC_XIOU_SLCR_SD0_SDR104PRST_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD0_SDR104PRST_SDR104PRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_SDR104PRST_SDR104PRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD0_SDR104PRST_SDR104PRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD0_SDR104PRST_SDR104PRESET_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0Ddr50preset
 */
#define XPMC_XIOU_SLCR_SD0_DDR50PRESET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000438UL )
#define XPMC_XIOU_SLCR_SD0_DDR50PRESET_RSTVAL   0x00000002UL

#define XPMC_XIOU_SLCR_SD0_DDR50PRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_DDR50PRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD0_DDR50PRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD0_DDR50PRESET_DEFVAL  0x2UL

/**
 * Register: XpmcXiouSlcrSd0Maxcur1p8
 */
#define XPMC_XIOU_SLCR_SD0_MAXCUR1P8    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000043CUL )
#define XPMC_XIOU_SLCR_SD0_MAXCUR1P8_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD0_MAXCUR1P8_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_MAXCUR1P8_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_MAXCUR1P8_MASK    0x000000ffUL
#define XPMC_XIOU_SLCR_SD0_MAXCUR1P8_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0Maxcur3p0
 */
#define XPMC_XIOU_SLCR_SD0_MAXCUR3P0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000440UL )
#define XPMC_XIOU_SLCR_SD0_MAXCUR3P0_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD0_MAXCUR3P0_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_MAXCUR3P0_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_MAXCUR3P0_MASK    0x000000ffUL
#define XPMC_XIOU_SLCR_SD0_MAXCUR3P0_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0Maxcur3p3
 */
#define XPMC_XIOU_SLCR_SD0_MAXCUR3P3    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000444UL )
#define XPMC_XIOU_SLCR_SD0_MAXCUR3P3_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD0_MAXCUR3P3_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_MAXCUR3P3_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_MAXCUR3P3_MASK    0x000000ffUL
#define XPMC_XIOU_SLCR_SD0_MAXCUR3P3_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0DllCtrl
 */
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000448UL )
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_RSTVAL   0x00000001UL

#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_CLKSTABLE_CFG_SHIFT   9UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_CLKSTABLE_CFG_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_CLKSTABLE_CFG_MASK    0x00000200UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_CLKSTABLE_CFG_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_CFG_SHIFT   5UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_CFG_WIDTH   4UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_CFG_MASK    0x000001e0UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_CFG_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_PSDONE_SHIFT   4UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_PSDONE_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_PSDONE_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_PSDONE_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_OVF_SHIFT   3UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_OVF_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_OVF_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_OVF_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_RST_SHIFT   2UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_RST_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_RST_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_RST_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_TESTMODE_SHIFT   1UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_TESTMODE_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_TESTMODE_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_TESTMODE_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_LOCK_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_LOCK_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_LOCK_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD0_DLL_CTRL_LOCK_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrSd0CdnCtrl
 */
#define XPMC_XIOU_SLCR_SD0_CDN_CTRL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000044CUL )
#define XPMC_XIOU_SLCR_SD0_CDN_CTRL_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD0_CDN_CTRL_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_CDN_CTRL_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_CDN_CTRL_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD0_CDN_CTRL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0DllTest
 */
#define XPMC_XIOU_SLCR_SD0_DLL_TEST    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000450UL )
#define XPMC_XIOU_SLCR_SD0_DLL_TEST_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD0_DLL_TEST_DIV_SHIFT   16UL
#define XPMC_XIOU_SLCR_SD0_DLL_TEST_DIV_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_DLL_TEST_DIV_MASK    0x00ff0000UL
#define XPMC_XIOU_SLCR_SD0_DLL_TEST_DIV_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_DLL_TEST_TX_SEL_SHIFT   9UL
#define XPMC_XIOU_SLCR_SD0_DLL_TEST_TX_SEL_WIDTH   7UL
#define XPMC_XIOU_SLCR_SD0_DLL_TEST_TX_SEL_MASK    0x0000fe00UL
#define XPMC_XIOU_SLCR_SD0_DLL_TEST_TX_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD0_DLL_TEST_RX_SEL_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_DLL_TEST_RX_SEL_WIDTH   9UL
#define XPMC_XIOU_SLCR_SD0_DLL_TEST_RX_SEL_MASK    0x000001ffUL
#define XPMC_XIOU_SLCR_SD0_DLL_TEST_RX_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0RxTuningSel
 */
#define XPMC_XIOU_SLCR_SD0_RX_TUNING_SEL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000454UL )
#define XPMC_XIOU_SLCR_SD0_RX_TUNING_SEL_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD0_RX_TUNING_SEL_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_RX_TUNING_SEL_WIDTH   9UL
#define XPMC_XIOU_SLCR_SD0_RX_TUNING_SEL_MASK    0x000001ffUL
#define XPMC_XIOU_SLCR_SD0_RX_TUNING_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0DllDivMap0
 */
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000458UL )
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_RSTVAL   0x50505050UL

#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_3_SHIFT   24UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_3_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_3_MASK    0xff000000UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_3_DEFVAL  0x50UL

#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_2_SHIFT   16UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_2_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_2_MASK    0x00ff0000UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_2_DEFVAL  0x50UL

#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_1_SHIFT   8UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_1_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_1_MASK    0x0000ff00UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_1_DEFVAL  0x50UL

#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_0_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_0_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_0_MASK    0x000000ffUL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP0_0_DEFVAL  0x50UL

/**
 * Register: XpmcXiouSlcrSd0DllDivMap1
 */
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000045CUL )
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_RSTVAL   0x50505050UL

#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_7_SHIFT   24UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_7_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_7_MASK    0xff000000UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_7_DEFVAL  0x50UL

#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_6_SHIFT   16UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_6_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_6_MASK    0x00ff0000UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_6_DEFVAL  0x50UL

#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_5_SHIFT   8UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_5_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_5_MASK    0x0000ff00UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_5_DEFVAL  0x50UL

#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_4_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_4_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_4_MASK    0x000000ffUL
#define XPMC_XIOU_SLCR_SD0_DLL_DIV_MAP1_4_DEFVAL  0x50UL

/**
 * Register: XpmcXiouSlcrSd0CoherentCtrl
 */
#define XPMC_XIOU_SLCR_SD0_COHERENT_CTRL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000460UL )
#define XPMC_XIOU_SLCR_SD0_COHERENT_CTRL_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD0_COHERENT_CTRL_AXI_COH_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_COHERENT_CTRL_AXI_COH_WIDTH   4UL
#define XPMC_XIOU_SLCR_SD0_COHERENT_CTRL_AXI_COH_MASK    0x0000000fUL
#define XPMC_XIOU_SLCR_SD0_COHERENT_CTRL_AXI_COH_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0InterconnectRoute
 */
#define XPMC_XIOU_SLCR_SD0_INTERCONNECT_ROUTE    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000464UL )
#define XPMC_XIOU_SLCR_SD0_INTERCONNECT_ROUTE_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD0_INTERCONNECT_ROUTE_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_INTERCONNECT_ROUTE_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD0_INTERCONNECT_ROUTE_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD0_INTERCONNECT_ROUTE_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd0Ram
 */
#define XPMC_XIOU_SLCR_SD0_RAM    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000468UL )
#define XPMC_XIOU_SLCR_SD0_RAM_RSTVAL   0x0000001bUL

/**
 * Register: XpmcXiouSlcrSd0InterconnectQos
 */
#define XPMC_XIOU_SLCR_SD0_INTERCONNECT_QOS    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000046CUL )
#define XPMC_XIOU_SLCR_SD0_INTERCONNECT_QOS_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD0_INTERCONNECT_QOS_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD0_INTERCONNECT_QOS_WIDTH   4UL
#define XPMC_XIOU_SLCR_SD0_INTERCONNECT_QOS_MASK    0x0000000fUL
#define XPMC_XIOU_SLCR_SD0_INTERCONNECT_QOS_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1ClkCtrl
 */
#define XPMC_XIOU_SLCR_SD1_CLK_CTRL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000480UL )
#define XPMC_XIOU_SLCR_SD1_CLK_CTRL_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD1_CLK_CTRL_SDIO1_FBCLK_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_SD1_CLK_CTRL_SDIO1_FBCLK_SEL_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CLK_CTRL_SDIO1_FBCLK_SEL_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_SD1_CLK_CTRL_SDIO1_FBCLK_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_CLK_CTRL_SDIO1_RX_SRC_SEL_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD1_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1CtrlReg
 */
#define XPMC_XIOU_SLCR_SD1_CTRL_REG    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000484UL )
#define XPMC_XIOU_SLCR_SD1_CTRL_REG_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD1_CTRL_REG_EMMC_SEL_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_CTRL_REG_EMMC_SEL_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CTRL_REG_EMMC_SEL_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD1_CTRL_REG_EMMC_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1CfgReg1
 */
#define XPMC_XIOU_SLCR_SD1_CFG_REG1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000490UL )
#define XPMC_XIOU_SLCR_SD1_CFG_REG1_RSTVAL   0x00003250UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG1_BASECLK_SHIFT   7UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG1_BASECLK_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG1_BASECLK_MASK    0x00007f80UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG1_BASECLK_DEFVAL  0x64UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG1_TUNIGCOUNT_SHIFT   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG1_TUNIGCOUNT_WIDTH   6UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG1_TUNIGCOUNT_MASK    0x0000007eUL
#define XPMC_XIOU_SLCR_SD1_CFG_REG1_TUNIGCOUNT_DEFVAL  0x28UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG1_ASYNCWKPENA_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG1_ASYNCWKPENA_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG1_ASYNCWKPENA_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG1_ASYNCWKPENA_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1CfgReg2
 */
#define XPMC_XIOU_SLCR_SD1_CFG_REG2    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000494UL )
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_RSTVAL   0x00000ffcUL

#define XPMC_XIOU_SLCR_SD1_CFG_REG2_SLOTTYPE_SHIFT   12UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_SLOTTYPE_WIDTH   2UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_SLOTTYPE_MASK    0x00003000UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_SLOTTYPE_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG2_ASYCINTR_SHIFT   11UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_ASYCINTR_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_ASYCINTR_MASK    0x00000800UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_ASYCINTR_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG2_64BIT_SHIFT   10UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_64BIT_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_64BIT_MASK    0x00000400UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_64BIT_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG2_1P8V_SHIFT   9UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_1P8V_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_1P8V_MASK    0x00000200UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_1P8V_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG2_3P0V_SHIFT   8UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_3P0V_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_3P0V_MASK    0x00000100UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_3P0V_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG2_3P3V_SHIFT   7UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_3P3V_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_3P3V_MASK    0x00000080UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_3P3V_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG2_SUSPRES_SHIFT   6UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_SUSPRES_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_SUSPRES_MASK    0x00000040UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_SUSPRES_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG2_SDMA_SHIFT   5UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_SDMA_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_SDMA_MASK    0x00000020UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_SDMA_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG2_HIGHSPEED_SHIFT   4UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_HIGHSPEED_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_HIGHSPEED_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_HIGHSPEED_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG2_ADMA2_SHIFT   3UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_ADMA2_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_ADMA2_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_ADMA2_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG2_8BIT_SHIFT   2UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_8BIT_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_8BIT_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_8BIT_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG2_MAXBLK_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_MAXBLK_WIDTH   2UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_MAXBLK_MASK    0x00000003UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG2_MAXBLK_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1CfgReg3
 */
#define XPMC_XIOU_SLCR_SD1_CFG_REG3    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000498UL )
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_RSTVAL   0x00000407UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG3_TUNINGSDR50_SHIFT   10UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_TUNINGSDR50_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_TUNINGSDR50_MASK    0x00000400UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_TUNINGSDR50_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG3_RETUNETMR_SHIFT   6UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_RETUNETMR_WIDTH   4UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_RETUNETMR_MASK    0x000003c0UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_RETUNETMR_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG3_DDRIVER_SHIFT   5UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_DDRIVER_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_DDRIVER_MASK    0x00000020UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_DDRIVER_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG3_CDRIVER_SHIFT   4UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_CDRIVER_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_CDRIVER_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_CDRIVER_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG3_ADRIVER_SHIFT   3UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_ADRIVER_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_ADRIVER_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_ADRIVER_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG3_DDR50_SHIFT   2UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_DDR50_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_DDR50_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_DDR50_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG3_SDR104_SHIFT   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_SDR104_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_SDR104_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_SDR104_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_SD1_CFG_REG3_SDR50_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_SDR50_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_SDR50_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD1_CFG_REG3_SDR50_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrSd1Initpreset
 */
#define XPMC_XIOU_SLCR_SD1_INITPRESET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000049CUL )
#define XPMC_XIOU_SLCR_SD1_INITPRESET_RSTVAL   0x00000100UL

#define XPMC_XIOU_SLCR_SD1_INITPRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_INITPRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD1_INITPRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD1_INITPRESET_DEFVAL  0x100UL

/**
 * Register: XpmcXiouSlcrSd1Dsppreset
 */
#define XPMC_XIOU_SLCR_SD1_DSPPRESET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004A0UL )
#define XPMC_XIOU_SLCR_SD1_DSPPRESET_RSTVAL   0x00000004UL

#define XPMC_XIOU_SLCR_SD1_DSPPRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_DSPPRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD1_DSPPRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD1_DSPPRESET_DEFVAL  0x4UL

/**
 * Register: XpmcXiouSlcrSd1Hspdpreset
 */
#define XPMC_XIOU_SLCR_SD1_HSPDPRESET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004A4UL )
#define XPMC_XIOU_SLCR_SD1_HSPDPRESET_RSTVAL   0x00000002UL

#define XPMC_XIOU_SLCR_SD1_HSPDPRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_HSPDPRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD1_HSPDPRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD1_HSPDPRESET_DEFVAL  0x2UL

/**
 * Register: XpmcXiouSlcrSd1Sdr12preset
 */
#define XPMC_XIOU_SLCR_SD1_SDR12PRESET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004A8UL )
#define XPMC_XIOU_SLCR_SD1_SDR12PRESET_RSTVAL   0x00000004UL

#define XPMC_XIOU_SLCR_SD1_SDR12PRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_SDR12PRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD1_SDR12PRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD1_SDR12PRESET_DEFVAL  0x4UL

/**
 * Register: XpmcXiouSlcrSd1Sdr25preset
 */
#define XPMC_XIOU_SLCR_SD1_SDR25PRESET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004ACUL )
#define XPMC_XIOU_SLCR_SD1_SDR25PRESET_RSTVAL   0x00000002UL

#define XPMC_XIOU_SLCR_SD1_SDR25PRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_SDR25PRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD1_SDR25PRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD1_SDR25PRESET_DEFVAL  0x2UL

/**
 * Register: XpmcXiouSlcrSd1Sdr50prset
 */
#define XPMC_XIOU_SLCR_SD1_SDR50PRSET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004B0UL )
#define XPMC_XIOU_SLCR_SD1_SDR50PRSET_RSTVAL   0x00000001UL

#define XPMC_XIOU_SLCR_SD1_SDR50PRSET_SDR50PRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_SDR50PRSET_SDR50PRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD1_SDR50PRSET_SDR50PRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD1_SDR50PRSET_SDR50PRESET_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrSd1Sdr104prst
 */
#define XPMC_XIOU_SLCR_SD1_SDR104PRST    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004B4UL )
#define XPMC_XIOU_SLCR_SD1_SDR104PRST_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD1_SDR104PRST_SDR104PRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_SDR104PRST_SDR104PRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD1_SDR104PRST_SDR104PRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD1_SDR104PRST_SDR104PRESET_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1Ddr50preset
 */
#define XPMC_XIOU_SLCR_SD1_DDR50PRESET    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004B8UL )
#define XPMC_XIOU_SLCR_SD1_DDR50PRESET_RSTVAL   0x00000002UL

#define XPMC_XIOU_SLCR_SD1_DDR50PRESET_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_DDR50PRESET_WIDTH   13UL
#define XPMC_XIOU_SLCR_SD1_DDR50PRESET_MASK    0x00001fffUL
#define XPMC_XIOU_SLCR_SD1_DDR50PRESET_DEFVAL  0x2UL

/**
 * Register: XpmcXiouSlcrSd1Maxcur1p8
 */
#define XPMC_XIOU_SLCR_SD1_MAXCUR1P8    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004BCUL )
#define XPMC_XIOU_SLCR_SD1_MAXCUR1P8_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD1_MAXCUR1P8_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_MAXCUR1P8_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_MAXCUR1P8_MASK    0x000000ffUL
#define XPMC_XIOU_SLCR_SD1_MAXCUR1P8_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1Maxcur3p0
 */
#define XPMC_XIOU_SLCR_SD1_MAXCUR3P0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004C0UL )
#define XPMC_XIOU_SLCR_SD1_MAXCUR3P0_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD1_MAXCUR3P0_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_MAXCUR3P0_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_MAXCUR3P0_MASK    0x000000ffUL
#define XPMC_XIOU_SLCR_SD1_MAXCUR3P0_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1Maxcur3p3
 */
#define XPMC_XIOU_SLCR_SD1_MAXCUR3P3    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004C4UL )
#define XPMC_XIOU_SLCR_SD1_MAXCUR3P3_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD1_MAXCUR3P3_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_MAXCUR3P3_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_MAXCUR3P3_MASK    0x000000ffUL
#define XPMC_XIOU_SLCR_SD1_MAXCUR3P3_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1DllCtrl
 */
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004C8UL )
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_RSTVAL   0x00000001UL

#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_CLKSTABLE_CFG_SHIFT   9UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_CLKSTABLE_CFG_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_CLKSTABLE_CFG_MASK    0x00000200UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_CLKSTABLE_CFG_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_CFG_SHIFT   5UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_CFG_WIDTH   4UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_CFG_MASK    0x000001e0UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_CFG_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_PSDONE_SHIFT   4UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_PSDONE_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_PSDONE_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_PSDONE_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_OVF_SHIFT   3UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_OVF_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_OVF_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_OVF_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_RST_SHIFT   2UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_RST_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_RST_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_RST_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_TESTMODE_SHIFT   1UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_TESTMODE_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_TESTMODE_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_TESTMODE_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_LOCK_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_LOCK_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_LOCK_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD1_DLL_CTRL_LOCK_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrSd1CdnCtrl
 */
#define XPMC_XIOU_SLCR_SD1_CDN_CTRL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004CCUL )
#define XPMC_XIOU_SLCR_SD1_CDN_CTRL_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD1_CDN_CTRL_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_CDN_CTRL_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_CDN_CTRL_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD1_CDN_CTRL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1DllTest
 */
#define XPMC_XIOU_SLCR_SD1_DLL_TEST    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004D0UL )
#define XPMC_XIOU_SLCR_SD1_DLL_TEST_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD1_DLL_TEST_DIV_SHIFT   16UL
#define XPMC_XIOU_SLCR_SD1_DLL_TEST_DIV_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_DLL_TEST_DIV_MASK    0x00ff0000UL
#define XPMC_XIOU_SLCR_SD1_DLL_TEST_DIV_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_DLL_TEST_TX_SEL_SHIFT   9UL
#define XPMC_XIOU_SLCR_SD1_DLL_TEST_TX_SEL_WIDTH   7UL
#define XPMC_XIOU_SLCR_SD1_DLL_TEST_TX_SEL_MASK    0x0000fe00UL
#define XPMC_XIOU_SLCR_SD1_DLL_TEST_TX_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_SD1_DLL_TEST_RX_SEL_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_DLL_TEST_RX_SEL_WIDTH   9UL
#define XPMC_XIOU_SLCR_SD1_DLL_TEST_RX_SEL_MASK    0x000001ffUL
#define XPMC_XIOU_SLCR_SD1_DLL_TEST_RX_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1RxTuningSel
 */
#define XPMC_XIOU_SLCR_SD1_RX_TUNING_SEL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004D4UL )
#define XPMC_XIOU_SLCR_SD1_RX_TUNING_SEL_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD1_RX_TUNING_SEL_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_RX_TUNING_SEL_WIDTH   9UL
#define XPMC_XIOU_SLCR_SD1_RX_TUNING_SEL_MASK    0x000001ffUL
#define XPMC_XIOU_SLCR_SD1_RX_TUNING_SEL_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1DllDivMap0
 */
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004D8UL )
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_RSTVAL   0x50505050UL

#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_3_SHIFT   24UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_3_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_3_MASK    0xff000000UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_3_DEFVAL  0x50UL

#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_2_SHIFT   16UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_2_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_2_MASK    0x00ff0000UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_2_DEFVAL  0x50UL

#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_1_SHIFT   8UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_1_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_1_MASK    0x0000ff00UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_1_DEFVAL  0x50UL

#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_0_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_0_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_0_MASK    0x000000ffUL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP0_0_DEFVAL  0x50UL

/**
 * Register: XpmcXiouSlcrSd1DllDivMap1
 */
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004DCUL )
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_RSTVAL   0x50505050UL

#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_7_SHIFT   24UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_7_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_7_MASK    0xff000000UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_7_DEFVAL  0x50UL

#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_6_SHIFT   16UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_6_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_6_MASK    0x00ff0000UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_6_DEFVAL  0x50UL

#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_5_SHIFT   8UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_5_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_5_MASK    0x0000ff00UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_5_DEFVAL  0x50UL

#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_4_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_4_WIDTH   8UL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_4_MASK    0x000000ffUL
#define XPMC_XIOU_SLCR_SD1_DLL_DIV_MAP1_4_DEFVAL  0x50UL

/**
 * Register: XpmcXiouSlcrSd1CoherentCtrl
 */
#define XPMC_XIOU_SLCR_SD1_COHERENT_CTRL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004E0UL )
#define XPMC_XIOU_SLCR_SD1_COHERENT_CTRL_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD1_COHERENT_CTRL_AXI_COH_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_COHERENT_CTRL_AXI_COH_WIDTH   4UL
#define XPMC_XIOU_SLCR_SD1_COHERENT_CTRL_AXI_COH_MASK    0x0000000fUL
#define XPMC_XIOU_SLCR_SD1_COHERENT_CTRL_AXI_COH_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1InterconnectRoute
 */
#define XPMC_XIOU_SLCR_SD1_INTERCONNECT_ROUTE    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004E4UL )
#define XPMC_XIOU_SLCR_SD1_INTERCONNECT_ROUTE_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD1_INTERCONNECT_ROUTE_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_INTERCONNECT_ROUTE_WIDTH   1UL
#define XPMC_XIOU_SLCR_SD1_INTERCONNECT_ROUTE_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_SD1_INTERCONNECT_ROUTE_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrSd1Ram
 */
#define XPMC_XIOU_SLCR_SD1_RAM    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004E8UL )
#define XPMC_XIOU_SLCR_SD1_RAM_RSTVAL   0x0000001bUL

/**
 * Register: XpmcXiouSlcrSd1InterconnectQos
 */
#define XPMC_XIOU_SLCR_SD1_INTERCONNECT_QOS    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x000004ECUL )
#define XPMC_XIOU_SLCR_SD1_INTERCONNECT_QOS_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_SD1_INTERCONNECT_QOS_SHIFT   0UL
#define XPMC_XIOU_SLCR_SD1_INTERCONNECT_QOS_WIDTH   4UL
#define XPMC_XIOU_SLCR_SD1_INTERCONNECT_QOS_MASK    0x0000000fUL
#define XPMC_XIOU_SLCR_SD1_INTERCONNECT_QOS_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrOspiQspiAxiMuxSel
 */
#define XPMC_XIOU_SLCR_OSPI_QSPI_AXI_MUX_SEL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000504UL )
#define XPMC_XIOU_SLCR_OSPI_QSPI_AXI_MUX_SEL_RSTVAL   0x00000001UL

#define XPMC_XIOU_SLCR_OSPI_QSPI_AXI_MUX_SEL_SHIFT   1UL
#define XPMC_XIOU_SLCR_OSPI_QSPI_AXI_MUX_SEL_WIDTH   1UL
#define XPMC_XIOU_SLCR_OSPI_QSPI_AXI_MUX_SEL_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_OSPI_QSPI_AXI_MUX_SEL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_OSPI_QSPI_AXI_MUX_SEL_XQSPIPSOSPI_SHIFT   0UL
#define XPMC_XIOU_SLCR_OSPI_QSPI_AXI_MUX_SEL_XQSPIPSOSPI_WIDTH   1UL
#define XPMC_XIOU_SLCR_OSPI_QSPI_AXI_MUX_SEL_XQSPIPSOSPI_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_OSPI_QSPI_AXI_MUX_SEL_XQSPIPSOSPI_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrXqspipsiouCoherentCtrl
 */
#define XPMC_XIOU_SLCR_XQSPIPSIOU_COHERENT_CTRL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000508UL )
#define XPMC_XIOU_SLCR_XQSPIPSIOU_COHERENT_CTRL_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_XQSPIPSIOU_COHERENT_CTRL_XQSPIPSAXI_COH_SHIFT   0UL
#define XPMC_XIOU_SLCR_XQSPIPSIOU_COHERENT_CTRL_XQSPIPSAXI_COH_WIDTH   4UL
#define XPMC_XIOU_SLCR_XQSPIPSIOU_COHERENT_CTRL_XQSPIPSAXI_COH_MASK    0x0000000fUL
#define XPMC_XIOU_SLCR_XQSPIPSIOU_COHERENT_CTRL_XQSPIPSAXI_COH_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrXqspipsiouInterconnectRoute
 */
#define XPMC_XIOU_SLCR_XQSPIPSIOU_INTERCONNECT_ROUTE    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000050CUL )
#define XPMC_XIOU_SLCR_XQSPIPSIOU_INTERCONNECT_ROUTE_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_XQSPIPSIOU_INTERCONNECT_ROUTE_QSPI_SHIFT   0UL
#define XPMC_XIOU_SLCR_XQSPIPSIOU_INTERCONNECT_ROUTE_QSPI_WIDTH   1UL
#define XPMC_XIOU_SLCR_XQSPIPSIOU_INTERCONNECT_ROUTE_QSPI_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_XQSPIPSIOU_INTERCONNECT_ROUTE_QSPI_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrXqspipsiouRam
 */
#define XPMC_XIOU_SLCR_XQSPIPSIOU_RAM    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000510UL )
#define XPMC_XIOU_SLCR_XQSPIPSIOU_RAM_RSTVAL   0x00000d9bUL

/**
 * Register: XpmcXiouSlcrXqspipsiouInterconnectQos
 */
#define XPMC_XIOU_SLCR_XQSPIPSIOU_INTERCONNECT_QOS    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000514UL )
#define XPMC_XIOU_SLCR_XQSPIPSIOU_INTERCONNECT_QOS_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_XQSPIPSIOU_INTERCONNECT_QOS_XQSPIPSQOS_SHIFT   0UL
#define XPMC_XIOU_SLCR_XQSPIPSIOU_INTERCONNECT_QOS_XQSPIPSQOS_WIDTH   4UL
#define XPMC_XIOU_SLCR_XQSPIPSIOU_INTERCONNECT_QOS_XQSPIPSQOS_MASK    0x0000000fUL
#define XPMC_XIOU_SLCR_XQSPIPSIOU_INTERCONNECT_QOS_XQSPIPSQOS_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrOspiCoherentCtrl
 */
#define XPMC_XIOU_SLCR_OSPI_COHERENT_CTRL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000530UL )
#define XPMC_XIOU_SLCR_OSPI_COHERENT_CTRL_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_OSPI_COHERENT_CTRL_AXI_COH_SHIFT   0UL
#define XPMC_XIOU_SLCR_OSPI_COHERENT_CTRL_AXI_COH_WIDTH   4UL
#define XPMC_XIOU_SLCR_OSPI_COHERENT_CTRL_AXI_COH_MASK    0x0000000fUL
#define XPMC_XIOU_SLCR_OSPI_COHERENT_CTRL_AXI_COH_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrOspiInterconnectRoute
 */
#define XPMC_XIOU_SLCR_OSPI_INTERCONNECT_ROUTE    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000534UL )
#define XPMC_XIOU_SLCR_OSPI_INTERCONNECT_ROUTE_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_OSPI_INTERCONNECT_ROUTE_SHIFT   0UL
#define XPMC_XIOU_SLCR_OSPI_INTERCONNECT_ROUTE_WIDTH   1UL
#define XPMC_XIOU_SLCR_OSPI_INTERCONNECT_ROUTE_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_OSPI_INTERCONNECT_ROUTE_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrOspiRam
 */
#define XPMC_XIOU_SLCR_OSPI_RAM    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000538UL )
#define XPMC_XIOU_SLCR_OSPI_RAM_RSTVAL   0x0000000bUL

/**
 * Register: XpmcXiouSlcrOspiInterconnectQos
 */
#define XPMC_XIOU_SLCR_OSPI_INTERCONNECT_QOS    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000053CUL )
#define XPMC_XIOU_SLCR_OSPI_INTERCONNECT_QOS_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_OSPI_INTERCONNECT_QOS_SHIFT   0UL
#define XPMC_XIOU_SLCR_OSPI_INTERCONNECT_QOS_WIDTH   4UL
#define XPMC_XIOU_SLCR_OSPI_INTERCONNECT_QOS_MASK    0x0000000fUL
#define XPMC_XIOU_SLCR_OSPI_INTERCONNECT_QOS_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrOspiRefclkDlyCtrl
 */
#define XPMC_XIOU_SLCR_OSPI_REFCLK_DLY_CTRL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000540UL )
#define XPMC_XIOU_SLCR_OSPI_REFCLK_DLY_CTRL_RSTVAL   0x00000013UL

#define XPMC_XIOU_SLCR_OSPI_REFCLK_DLY_CTRL_DLY1_SHIFT   3UL
#define XPMC_XIOU_SLCR_OSPI_REFCLK_DLY_CTRL_DLY1_WIDTH   2UL
#define XPMC_XIOU_SLCR_OSPI_REFCLK_DLY_CTRL_DLY1_MASK    0x00000018UL
#define XPMC_XIOU_SLCR_OSPI_REFCLK_DLY_CTRL_DLY1_DEFVAL  0x2UL

#define XPMC_XIOU_SLCR_OSPI_REFCLK_DLY_CTRL_DLY0_SHIFT   0UL
#define XPMC_XIOU_SLCR_OSPI_REFCLK_DLY_CTRL_DLY0_WIDTH   3UL
#define XPMC_XIOU_SLCR_OSPI_REFCLK_DLY_CTRL_DLY0_MASK    0x00000007UL
#define XPMC_XIOU_SLCR_OSPI_REFCLK_DLY_CTRL_DLY0_DEFVAL  0x3UL

/**
 * Register: XpmcXiouSlcrCurPwrSt
 */
#define XPMC_XIOU_SLCR_CUR_PWR_ST    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000600UL )
#define XPMC_XIOU_SLCR_CUR_PWR_ST_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_CUR_PWR_ST_U2PMU_SHIFT   0UL
#define XPMC_XIOU_SLCR_CUR_PWR_ST_U2PMU_WIDTH   2UL
#define XPMC_XIOU_SLCR_CUR_PWR_ST_U2PMU_MASK    0x00000003UL
#define XPMC_XIOU_SLCR_CUR_PWR_ST_U2PMU_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrConnectSt
 */
#define XPMC_XIOU_SLCR_CONNECT_ST    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000604UL )
#define XPMC_XIOU_SLCR_CONNECT_ST_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_CONNECT_ST_U2PMU_SHIFT   0UL
#define XPMC_XIOU_SLCR_CONNECT_ST_U2PMU_WIDTH   1UL
#define XPMC_XIOU_SLCR_CONNECT_ST_U2PMU_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_CONNECT_ST_U2PMU_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrPwStateReq
 */
#define XPMC_XIOU_SLCR_PW_STATE_REQ    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000608UL )
#define XPMC_XIOU_SLCR_PW_STATE_REQ_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_PW_STATE_REQ_BIT_1_0_SHIFT   0UL
#define XPMC_XIOU_SLCR_PW_STATE_REQ_BIT_1_0_WIDTH   2UL
#define XPMC_XIOU_SLCR_PW_STATE_REQ_BIT_1_0_MASK    0x00000003UL
#define XPMC_XIOU_SLCR_PW_STATE_REQ_BIT_1_0_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrHostU2PortDis
 */
#define XPMC_XIOU_SLCR_HOST_U2_PORT_DIS    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000060CUL )
#define XPMC_XIOU_SLCR_HOST_U2_PORT_DIS_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_HOST_U2_PORT_DIS_BIT_0_SHIFT   0UL
#define XPMC_XIOU_SLCR_HOST_U2_PORT_DIS_BIT_0_WIDTH   1UL
#define XPMC_XIOU_SLCR_HOST_U2_PORT_DIS_BIT_0_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_HOST_U2_PORT_DIS_BIT_0_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrDbgU2pmu
 */
#define XPMC_XIOU_SLCR_DBG_U2PMU    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000610UL )
#define XPMC_XIOU_SLCR_DBG_U2PMU_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_DBG_U2PMU_BIT_31_0_SHIFT   0UL
#define XPMC_XIOU_SLCR_DBG_U2PMU_BIT_31_0_WIDTH   32UL
#define XPMC_XIOU_SLCR_DBG_U2PMU_BIT_31_0_MASK    0xffffffffUL
#define XPMC_XIOU_SLCR_DBG_U2PMU_BIT_31_0_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrDbgU2pmuExt1
 */
#define XPMC_XIOU_SLCR_DBG_U2PMU_EXT1    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000614UL )
#define XPMC_XIOU_SLCR_DBG_U2PMU_EXT1_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_DBG_U2PMU_EXT1_BIT_63_32_SHIFT   0UL
#define XPMC_XIOU_SLCR_DBG_U2PMU_EXT1_BIT_63_32_WIDTH   32UL
#define XPMC_XIOU_SLCR_DBG_U2PMU_EXT1_BIT_63_32_MASK    0xffffffffUL
#define XPMC_XIOU_SLCR_DBG_U2PMU_EXT1_BIT_63_32_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrDbgU2pmuExt2
 */
#define XPMC_XIOU_SLCR_DBG_U2PMU_EXT2    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000618UL )
#define XPMC_XIOU_SLCR_DBG_U2PMU_EXT2_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_DBG_U2PMU_EXT2_BIT_67_64_SHIFT   0UL
#define XPMC_XIOU_SLCR_DBG_U2PMU_EXT2_BIT_67_64_WIDTH   4UL
#define XPMC_XIOU_SLCR_DBG_U2PMU_EXT2_BIT_67_64_MASK    0x0000000fUL
#define XPMC_XIOU_SLCR_DBG_U2PMU_EXT2_BIT_67_64_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrPmeGenU2pmu
 */
#define XPMC_XIOU_SLCR_PME_GEN_U2PMU    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000061CUL )
#define XPMC_XIOU_SLCR_PME_GEN_U2PMU_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_PME_GEN_U2PMU_BIT_0_SHIFT   0UL
#define XPMC_XIOU_SLCR_PME_GEN_U2PMU_BIT_0_WIDTH   1UL
#define XPMC_XIOU_SLCR_PME_GEN_U2PMU_BIT_0_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_PME_GEN_U2PMU_BIT_0_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrPwrCfgUsb2
 */
#define XPMC_XIOU_SLCR_PWR_CFG_USB2    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000620UL )
#define XPMC_XIOU_SLCR_PWR_CFG_USB2_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_PWR_CFG_USB2_STRAP_SHIFT   0UL
#define XPMC_XIOU_SLCR_PWR_CFG_USB2_STRAP_WIDTH   30UL
#define XPMC_XIOU_SLCR_PWR_CFG_USB2_STRAP_MASK    0x3fffffffUL
#define XPMC_XIOU_SLCR_PWR_CFG_USB2_STRAP_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrPhyHub
 */
#define XPMC_XIOU_SLCR_PHY_HUB    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000624UL )
#define XPMC_XIOU_SLCR_PHY_HUB_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_PHY_HUB_VBUS_CTRL_SHIFT   1UL
#define XPMC_XIOU_SLCR_PHY_HUB_VBUS_CTRL_WIDTH   1UL
#define XPMC_XIOU_SLCR_PHY_HUB_VBUS_CTRL_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_PHY_HUB_VBUS_CTRL_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PHY_HUB_OVER_CURRENT_SHIFT   0UL
#define XPMC_XIOU_SLCR_PHY_HUB_OVER_CURRENT_WIDTH   1UL
#define XPMC_XIOU_SLCR_PHY_HUB_OVER_CURRENT_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_PHY_HUB_OVER_CURRENT_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrCtrl
 */
#define XPMC_XIOU_SLCR_CTRL    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000700UL )
#define XPMC_XIOU_SLCR_CTRL_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
#define XPMC_XIOU_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
#define XPMC_XIOU_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrIsr
 */
#define XPMC_XIOU_SLCR_ISR    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000800UL )
#define XPMC_XIOU_SLCR_ISR_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_ISR_ADDR_DECODE_ERR_SHIFT   0UL
#define XPMC_XIOU_SLCR_ISR_ADDR_DECODE_ERR_WIDTH   1UL
#define XPMC_XIOU_SLCR_ISR_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_ISR_ADDR_DECODE_ERR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrImr
 */
#define XPMC_XIOU_SLCR_IMR    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000804UL )
#define XPMC_XIOU_SLCR_IMR_RSTVAL   0x00000001UL

#define XPMC_XIOU_SLCR_IMR_ADDR_DECODE_ERR_SHIFT   0UL
#define XPMC_XIOU_SLCR_IMR_ADDR_DECODE_ERR_WIDTH   1UL
#define XPMC_XIOU_SLCR_IMR_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_IMR_ADDR_DECODE_ERR_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrIer
 */
#define XPMC_XIOU_SLCR_IER    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000808UL )
#define XPMC_XIOU_SLCR_IER_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_IER_ADDR_DECODE_ERR_SHIFT   0UL
#define XPMC_XIOU_SLCR_IER_ADDR_DECODE_ERR_WIDTH   1UL
#define XPMC_XIOU_SLCR_IER_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_IER_ADDR_DECODE_ERR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrIdr
 */
#define XPMC_XIOU_SLCR_IDR    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000080CUL )
#define XPMC_XIOU_SLCR_IDR_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_IDR_ADDR_DECODE_ERR_SHIFT   0UL
#define XPMC_XIOU_SLCR_IDR_ADDR_DECODE_ERR_WIDTH   1UL
#define XPMC_XIOU_SLCR_IDR_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_IDR_ADDR_DECODE_ERR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrItr
 */
#define XPMC_XIOU_SLCR_ITR    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000810UL )
#define XPMC_XIOU_SLCR_ITR_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_ITR_ADDR_DECODE_ERR_SHIFT   0UL
#define XPMC_XIOU_SLCR_ITR_ADDR_DECODE_ERR_WIDTH   1UL
#define XPMC_XIOU_SLCR_ITR_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_ITR_ADDR_DECODE_ERR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrParityIsr
 */
#define XPMC_XIOU_SLCR_PARITY_ISR    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000814UL )
#define XPMC_XIOU_SLCR_PARITY_ISR_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_SD1_SHIFT   12UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_SD1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_SD1_MASK    0x00001000UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_SD1_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_SD0_SHIFT   11UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_SD0_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_SD0_MASK    0x00000800UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_SD0_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_QSPI_SHIFT   10UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_QSPI_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_QSPI_MASK    0x00000400UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_QSPI_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_OSPI_SHIFT   9UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_OSPI_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_OSPI_MASK    0x00000200UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_AXI_OSPI_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_SD1_SHIFT   8UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_SD1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_SD1_MASK    0x00000100UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_SD1_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_SD0_SHIFT   7UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_SD0_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_SD0_MASK    0x00000080UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_SD0_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_QSPI1_SHIFT   6UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_QSPI1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_QSPI1_MASK    0x00000040UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_QSPI1_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_SECURE_APB_SHIFT   5UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_SECURE_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_SECURE_APB_MASK    0x00000020UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_SECURE_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_APB_SHIFT   4UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_APB_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_XIOUSLCR_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_QSPI0_APB_SHIFT   3UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_QSPI0_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_QSPI0_APB_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_QSPI0_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_OSPI_APB_SHIFT   2UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_OSPI_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_OSPI_APB_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_OSPI_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_I2C_APB_SHIFT   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_I2C_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_I2C_APB_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_I2C_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_GPIO_APB_SHIFT   0UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_GPIO_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_GPIO_APB_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_PARITY_ISR_PERR_GPIO_APB_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrParityImr
 */
#define XPMC_XIOU_SLCR_PARITY_IMR    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000818UL )
#define XPMC_XIOU_SLCR_PARITY_IMR_RSTVAL   0x00001fffUL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_SD1_SHIFT   12UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_SD1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_SD1_MASK    0x00001000UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_SD1_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_SD0_SHIFT   11UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_SD0_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_SD0_MASK    0x00000800UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_SD0_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_QSPI_SHIFT   10UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_QSPI_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_QSPI_MASK    0x00000400UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_QSPI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_OSPI_SHIFT   9UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_OSPI_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_OSPI_MASK    0x00000200UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_AXI_OSPI_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_SD1_SHIFT   8UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_SD1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_SD1_MASK    0x00000100UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_SD1_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_SD0_SHIFT   7UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_SD0_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_SD0_MASK    0x00000080UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_SD0_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_QSPI1_SHIFT   6UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_QSPI1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_QSPI1_MASK    0x00000040UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_QSPI1_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_SECURE_APB_SHIFT   5UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_SECURE_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_SECURE_APB_MASK    0x00000020UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_SECURE_APB_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_APB_SHIFT   4UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_APB_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_XIOUSLCR_APB_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_QSPI0_APB_SHIFT   3UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_QSPI0_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_QSPI0_APB_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_QSPI0_APB_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_OSPI_APB_SHIFT   2UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_OSPI_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_OSPI_APB_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_OSPI_APB_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_I2C_APB_SHIFT   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_I2C_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_I2C_APB_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_I2C_APB_DEFVAL  0x1UL

#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_GPIO_APB_SHIFT   0UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_GPIO_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_GPIO_APB_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_PARITY_IMR_PERR_GPIO_APB_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSlcrParityIer
 */
#define XPMC_XIOU_SLCR_PARITY_IER    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x0000081CUL )
#define XPMC_XIOU_SLCR_PARITY_IER_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_SD1_SHIFT   12UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_SD1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_SD1_MASK    0x00001000UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_SD1_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_SD0_SHIFT   11UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_SD0_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_SD0_MASK    0x00000800UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_SD0_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_QSPI_SHIFT   10UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_QSPI_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_QSPI_MASK    0x00000400UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_QSPI_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_OSPI_SHIFT   9UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_OSPI_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_OSPI_MASK    0x00000200UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_AXI_OSPI_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_SD1_SHIFT   8UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_SD1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_SD1_MASK    0x00000100UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_SD1_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_SD0_SHIFT   7UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_SD0_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_SD0_MASK    0x00000080UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_SD0_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_QSPI1_SHIFT   6UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_QSPI1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_QSPI1_MASK    0x00000040UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_QSPI1_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_SECURE_APB_SHIFT   5UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_SECURE_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_SECURE_APB_MASK    0x00000020UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_SECURE_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_APB_SHIFT   4UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_APB_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_XIOUSLCR_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_QSPI0_APB_SHIFT   3UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_QSPI0_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_QSPI0_APB_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_QSPI0_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_OSPI_APB_SHIFT   2UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_OSPI_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_OSPI_APB_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_OSPI_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_I2C_APB_SHIFT   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_I2C_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_I2C_APB_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_I2C_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IER_PERR_GPIO_APB_SHIFT   0UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_GPIO_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_GPIO_APB_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_PARITY_IER_PERR_GPIO_APB_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrParityIdr
 */
#define XPMC_XIOU_SLCR_PARITY_IDR    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000820UL )
#define XPMC_XIOU_SLCR_PARITY_IDR_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_SD1_SHIFT   12UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_SD1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_SD1_MASK    0x00001000UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_SD1_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_SD0_SHIFT   11UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_SD0_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_SD0_MASK    0x00000800UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_SD0_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_QSPI_SHIFT   10UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_QSPI_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_QSPI_MASK    0x00000400UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_QSPI_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_OSPI_SHIFT   9UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_OSPI_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_OSPI_MASK    0x00000200UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_AXI_OSPI_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_SD1_SHIFT   8UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_SD1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_SD1_MASK    0x00000100UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_SD1_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_SD0_SHIFT   7UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_SD0_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_SD0_MASK    0x00000080UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_SD0_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_QSPI1_SHIFT   6UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_QSPI1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_QSPI1_MASK    0x00000040UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_QSPI1_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_SECURE_APB_SHIFT   5UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_SECURE_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_SECURE_APB_MASK    0x00000020UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_SECURE_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_APB_SHIFT   4UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_APB_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_XIOUSLCR_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_QSPI0_APB_SHIFT   3UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_QSPI0_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_QSPI0_APB_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_QSPI0_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_OSPI_APB_SHIFT   2UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_OSPI_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_OSPI_APB_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_OSPI_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_I2C_APB_SHIFT   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_I2C_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_I2C_APB_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_I2C_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_GPIO_APB_SHIFT   0UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_GPIO_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_GPIO_APB_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_PARITY_IDR_PERR_GPIO_APB_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrParityItr
 */
#define XPMC_XIOU_SLCR_PARITY_ITR    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000824UL )
#define XPMC_XIOU_SLCR_PARITY_ITR_RSTVAL   0x00000000UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_SD1_SHIFT   12UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_SD1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_SD1_MASK    0x00001000UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_SD1_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_SD0_SHIFT   11UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_SD0_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_SD0_MASK    0x00000800UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_SD0_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_QSPI_SHIFT   10UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_QSPI_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_QSPI_MASK    0x00000400UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_QSPI_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_OSPI_SHIFT   9UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_OSPI_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_OSPI_MASK    0x00000200UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_AXI_OSPI_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_SD1_SHIFT   8UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_SD1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_SD1_MASK    0x00000100UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_SD1_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_SD0_SHIFT   7UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_SD0_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_SD0_MASK    0x00000080UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_SD0_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_QSPI1_SHIFT   6UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_QSPI1_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_QSPI1_MASK    0x00000040UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_QSPI1_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_SECURE_APB_SHIFT   5UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_SECURE_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_SECURE_APB_MASK    0x00000020UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_SECURE_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_APB_SHIFT   4UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_APB_MASK    0x00000010UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_XIOUSLCR_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_QSPI0_APB_SHIFT   3UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_QSPI0_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_QSPI0_APB_MASK    0x00000008UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_QSPI0_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_OSPI_APB_SHIFT   2UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_OSPI_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_OSPI_APB_MASK    0x00000004UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_OSPI_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_I2C_APB_SHIFT   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_I2C_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_I2C_APB_MASK    0x00000002UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_I2C_APB_DEFVAL  0x0UL

#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_GPIO_APB_SHIFT   0UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_GPIO_APB_WIDTH   1UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_GPIO_APB_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_PARITY_ITR_PERR_GPIO_APB_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSlcrWprot0
 */
#define XPMC_XIOU_SLCR_WPROT0    ( ( XPMC_XIOU_SLCR_BASEADDR ) + 0x00000828UL )
#define XPMC_XIOU_SLCR_WPROT0_RSTVAL   0x00000001UL

#define XPMC_XIOU_SLCR_WPROT0_ACT_SHIFT   0UL
#define XPMC_XIOU_SLCR_WPROT0_ACT_WIDTH   1UL
#define XPMC_XIOU_SLCR_WPROT0_ACT_MASK    0x00000001UL
#define XPMC_XIOU_SLCR_WPROT0_ACT_DEFVAL  0x1UL

/**
 *@endcond
 */

#ifdef __cplusplus
}
#endif

#endif /* __XPMC_XIOU_SLCR_H__ */
