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// IP VLNV: xilinx.com:module_ref:dna_port_read:1.0
// IP Revision: 1

(* X_CORE_INFO = "dna_port_read,Vivado 2023.2" *)
(* CHECK_LICENSE_TYPE = "system_dna_port_read_0_0,dna_port_read,{}" *)
(* CORE_GENERATION_INFO = "system_dna_port_read_0_0,dna_port_read,{x_ipProduct=Vivado 2023.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=dna_port_read,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *)
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_dna_port_read_0_0 (
  clk,
  rst_n,
  start_vld,
  read_vld,
  dna_port
);

(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN system_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst_n RST" *)
input wire rst_n;
input wire start_vld;
output wire read_vld;
output wire [56 : 0] dna_port;

  dna_port_read inst (
    .clk(clk),
    .rst_n(rst_n),
    .start_vld(start_vld),
    .read_vld(read_vld),
    .dna_port(dna_port)
  );
endmodule
