`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/01/29 15:52:48
// Design Name: 
// Module Name: dna_port_read
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module dna_port_read(
		input 				clk,
		input 				rst_n,
		input 				start_vld,
		output 			  read_vld,
		output[56:0]	dna_port
    );
    
    	localparam CNT0 = 90;
	
	wire 						read_vld;
	reg[56:0]				dna_port;
	
	reg[7:0] 				cnt0;
	wire 						add_cnt0;
	wire 						end_cnt0;
	reg 						start_flag;
	
	wire 						dna_out;
  wire 						dna_read;
  wire 						dna_shift;
	
	 DNA_PORT #(
      .SIM_DNA_VALUE(57'h000000000000000)  // Specifies a sample 57-bit DNA value for simulation
   )
   DNA_PORT_inst (
      .DOUT(dna_out),   // 1-bit output: DNA output data.
      .CLK(clk),     // 1-bit input: Clock input.
      .DIN(1'b0),     // 1-bit input: User data input pin.
      .READ(dna_read),   // 1-bit input: Active high load DNA, active low read input.
      .SHIFT(dna_shift)  // 1-bit input: Active high shift enable input.
   );
   
   always @(posedge clk or negedge rst_n)begin
   		if(rst_n == 1'b0)begin
   			start_flag <= 0;
   		end	
   		else if(start_vld == 1'b1)begin
   			start_flag <= 1;
   		end
   		else if(end_cnt0)begin
   			start_flag <= 0;
   		end
   end
   
   always @(posedge clk or negedge rst_n)begin
   		if(rst_n == 1'b0)begin
				 cnt0 <= 8'd0;   			
   		end
   		else if(add_cnt0)begin
   			 if(end_cnt0)begin
   			 	 cnt0 <= 8'd0; 
   			 end
   			 else begin
   			 	 cnt0 <= cnt0 + 1'd1; 
   			 end
   		end
   end
   
   assign add_cnt0 = start_flag;
 	 assign end_cnt0 = add_cnt0 && cnt0 == CNT0 -1;
   
   assign dna_read = (cnt0 > 8'd0 && cnt0 <= 8'd9) ? 1'b1 : 1'b0;
   assign dna_shift = (cnt0 > 8'd9 && cnt0 <= 8'd66) ? 1'b1 : 1'b0;
   
   assign read_vld = (cnt0 > 8'd85 && cnt0 <= 8'd89) ? 1'b1 : 1'b0;
   
   always @(posedge clk or negedge rst_n)begin
   		if(rst_n == 1'b0)begin
   			dna_port <= 57'd0;
   		end
   		else if(dna_shift)begin
   			dna_port <= {dna_port[55:0],dna_out};
   		end
   end
    
endmodule
