/*******************************************************************************
* Copyright (c) 2018 - 2021 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
*******************************************************************************/


#ifndef __XPMC_XIOU_SECURE_SLCR_H__
#define __XPMC_XIOU_SECURE_SLCR_H__


#ifdef __cplusplus
extern "C" {
#endif

/**
 *@cond nocomments
 */

/**
 * XpmcXiouSecureSlcr Base Address
 */
#define XPMC_XIOU_SECURE_SLCR_BASEADDR      0xF1070000UL

/**
 * Register: XpmcXiouSecureSlcrAxiWprtcnSd0
 */
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_RSTVAL   0x00000000UL

#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_AWPROT_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_AWPROT_WIDTH   3UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_AWPROT_MASK    0x00000007UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD0_AWPROT_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSecureSlcrAxiRprtcnSd0
 */
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_RSTVAL   0x00000000UL

#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_ARPROT_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_ARPROT_WIDTH   3UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_ARPROT_MASK    0x00000007UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD0_ARPROT_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSecureSlcrAxiWprtcnSd1
 */
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000010UL )
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_RSTVAL   0x00000000UL

#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_AWPROT_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_AWPROT_WIDTH   3UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_AWPROT_MASK    0x00000007UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_SD1_AWPROT_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSecureSlcrAxiRprtcnSd1
 */
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000014UL )
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_RSTVAL   0x00000000UL

#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_ARPROT_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_ARPROT_WIDTH   3UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_ARPROT_MASK    0x00000007UL
#define XPMC_XIOU_SECURE_SLCR_AXI_RPRTCN_SD1_ARPROT_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSecureSlcrAxiWprtcnQspi
 */
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000020UL )
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_RSTVAL   0x00000000UL

#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_XQSPIPSAXI_AWPROT_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_XQSPIPSAXI_AWPROT_WIDTH   3UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_XQSPIPSAXI_AWPROT_MASK    0x00000007UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_QSPI_XQSPIPSAXI_AWPROT_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSecureSlcrAxiWprtcnOspi
 */
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000030UL )
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_RSTVAL   0x00000000UL

#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_AWPROT_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_AWPROT_WIDTH   3UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_AWPROT_MASK    0x00000007UL
#define XPMC_XIOU_SECURE_SLCR_AXI_WPRTCN_OSPI_AWPROT_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSecureSlcrCtrl
 */
#define XPMC_XIOU_SECURE_SLCR_CTRL    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
#define XPMC_XIOU_SECURE_SLCR_CTRL_RSTVAL   0x00000000UL

#define XPMC_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
#define XPMC_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSecureSlcrIsr
 */
#define XPMC_XIOU_SECURE_SLCR_ISR    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
#define XPMC_XIOU_SECURE_SLCR_ISR_RSTVAL   0x00000000UL

#define XPMC_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_WIDTH   1UL
#define XPMC_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_ISR_ADDR_DECODE_ERR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSecureSlcrImr
 */
#define XPMC_XIOU_SECURE_SLCR_IMR    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
#define XPMC_XIOU_SECURE_SLCR_IMR_RSTVAL   0x00000001UL

#define XPMC_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_WIDTH   1UL
#define XPMC_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_IMR_ADDR_DECODE_ERR_DEFVAL  0x1UL

/**
 * Register: XpmcXiouSecureSlcrIer
 */
#define XPMC_XIOU_SECURE_SLCR_IER    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
#define XPMC_XIOU_SECURE_SLCR_IER_RSTVAL   0x00000000UL

#define XPMC_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_WIDTH   1UL
#define XPMC_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_IER_ADDR_DECODE_ERR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSecureSlcrIdr
 */
#define XPMC_XIOU_SECURE_SLCR_IDR    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
#define XPMC_XIOU_SECURE_SLCR_IDR_RSTVAL   0x00000000UL

#define XPMC_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_WIDTH   1UL
#define XPMC_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_IDR_ADDR_DECODE_ERR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSecureSlcrItr
 */
#define XPMC_XIOU_SECURE_SLCR_ITR    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
#define XPMC_XIOU_SECURE_SLCR_ITR_RSTVAL   0x00000000UL

#define XPMC_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_WIDTH   1UL
#define XPMC_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_MASK    0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_ITR_ADDR_DECODE_ERR_DEFVAL  0x0UL

/**
 * Register: XpmcXiouSecureSlcrTzprot
 */
#define XPMC_XIOU_SECURE_SLCR_TZPROT    ( ( XPMC_XIOU_SECURE_SLCR_BASEADDR ) + 0x0000006CUL )
#define XPMC_XIOU_SECURE_SLCR_TZPROT_RSTVAL   0x00000000UL

#define XPMC_XIOU_SECURE_SLCR_TZPROT_ACT_SHIFT   0UL
#define XPMC_XIOU_SECURE_SLCR_TZPROT_ACT_WIDTH   1UL
#define XPMC_XIOU_SECURE_SLCR_TZPROT_ACT_MASK    0x00000001UL
#define XPMC_XIOU_SECURE_SLCR_TZPROT_ACT_DEFVAL  0x0UL

/**
 *@endcond
 */

#ifdef __cplusplus
}
#endif

#endif /* __XPMC_XIOU_SECURE_SLCR_H__ */
