128 lines
6.8 KiB
Plaintext
128 lines
6.8 KiB
Plaintext
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-06-09">
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<IP Version="1_6_042617"/>
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<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/>
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<Core InsertDataset="0" Insert="1" Reveal_sig="697491828" Name="RelayConTop_LA0" ID="0">
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<Setting>
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<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
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<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
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<Capture Mode="0" MinSamplesPerTrig="8"/>
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<Event CntEnable="0" MaxEventCnt="8"/>
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<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
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<DistRAM Disable="0"/>
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</Setting>
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<Dataset Name="Base">
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<Trace>
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<Sig Type="SIG" Name="con_exec"/>
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<Sig Type="SIG" Name="con_done"/>
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<Bus Name="RC_RLSel">
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<Sig Type="SIG" Name="RC_RLSel:0"/>
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<Sig Type="SIG" Name="RC_RLSel:1"/>
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<Sig Type="SIG" Name="RC_RLSel:2"/>
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<Sig Type="SIG" Name="RC_RLSel:3"/>
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<Sig Type="SIG" Name="RC_RLSel:4"/>
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<Sig Type="SIG" Name="RC_RLSel:5"/>
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<Sig Type="SIG" Name="RC_RLSel:6"/>
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<Sig Type="SIG" Name="RC_RLSel:7"/>
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<Sig Type="SIG" Name="RC_RLSel:8"/>
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<Sig Type="SIG" Name="RC_RLSel:9"/>
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<Sig Type="SIG" Name="RC_RLSel:10"/>
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<Sig Type="SIG" Name="RC_RLSel:11"/>
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<Sig Type="SIG" Name="RC_RLSel:12"/>
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<Sig Type="SIG" Name="RC_RLSel:13"/>
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<Sig Type="SIG" Name="RC_RLSel:14"/>
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<Sig Type="SIG" Name="RC_RLSel:15"/>
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<Sig Type="SIG" Name="RC_RLSel:16"/>
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<Sig Type="SIG" Name="RC_RLSel:17"/>
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</Bus>
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<Bus Name="DC_Con3">
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<Sig Type="SIG" Name="DC_Con3:0"/>
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<Sig Type="SIG" Name="DC_Con3:1"/>
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<Sig Type="SIG" Name="DC_Con3:2"/>
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<Sig Type="SIG" Name="DC_Con3:3"/>
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<Sig Type="SIG" Name="DC_Con3:4"/>
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<Sig Type="SIG" Name="DC_Con3:5"/>
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<Sig Type="SIG" Name="DC_Con3:6"/>
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<Sig Type="SIG" Name="DC_Con3:7"/>
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<Sig Type="SIG" Name="DC_Con3:8"/>
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<Sig Type="SIG" Name="DC_Con3:9"/>
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<Sig Type="SIG" Name="DC_Con3:10"/>
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<Sig Type="SIG" Name="DC_Con3:11"/>
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<Sig Type="SIG" Name="DC_Con3:12"/>
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<Sig Type="SIG" Name="DC_Con3:13"/>
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<Sig Type="SIG" Name="DC_Con3:14"/>
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<Sig Type="SIG" Name="DC_Con3:15"/>
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<Sig Type="SIG" Name="DC_Con3:16"/>
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<Sig Type="SIG" Name="DC_Con3:17"/>
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<Sig Type="SIG" Name="DC_Con3:18"/>
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<Sig Type="SIG" Name="DC_Con3:19"/>
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<Sig Type="SIG" Name="DC_Con3:20"/>
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<Sig Type="SIG" Name="DC_Con3:21"/>
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<Sig Type="SIG" Name="DC_Con3:22"/>
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<Sig Type="SIG" Name="DC_Con3:23"/>
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</Bus>
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<Bus Name="o_PMU_OC_3">
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<Sig Type="SIG" Name="o_PMU_OC_3:0"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:1"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:2"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:3"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:4"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:5"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:6"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:7"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:8"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:9"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:10"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:11"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:12"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:13"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:14"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:15"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:16"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:17"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:18"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:19"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:20"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:21"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:22"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:23"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:24"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:25"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:26"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:27"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:28"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:29"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:30"/>
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<Sig Type="SIG" Name="o_PMU_OC_3:31"/>
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</Bus>
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<Bus Name="o_DMM_EN">
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<Sig Type="SIG" Name="o_DMM_EN:0"/>
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<Sig Type="SIG" Name="o_DMM_EN:1"/>
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<Sig Type="SIG" Name="o_DMM_EN:2"/>
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<Sig Type="SIG" Name="o_DMM_EN:3"/>
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<Sig Type="SIG" Name="o_DMM_EN:4"/>
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<Sig Type="SIG" Name="o_DMM_EN:5"/>
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<Sig Type="SIG" Name="o_DMM_EN:6"/>
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<Sig Type="SIG" Name="o_DMM_EN:7"/>
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<Sig Type="SIG" Name="o_DMM_EN:8"/>
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<Sig Type="SIG" Name="o_DMM_EN:9"/>
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<Sig Type="SIG" Name="o_DMM_EN:10"/>
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<Sig Type="SIG" Name="o_DMM_EN:11"/>
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<Sig Type="SIG" Name="o_DMM_EN:12"/>
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<Sig Type="SIG" Name="o_DMM_EN:13"/>
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<Sig Type="SIG" Name="o_DMM_EN:14"/>
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<Sig Type="SIG" Name="o_DMM_EN:15"/>
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<Sig Type="SIG" Name="o_DMM_EN:16"/>
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<Sig Type="SIG" Name="o_DMM_EN:17"/>
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<Sig Type="SIG" Name="o_DMM_EN:18"/>
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</Bus>
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</Trace>
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<Trigger>
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<TU Serialbits="0" Type="0" ID="1" Sig="i_rst_n,"/>
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<TU Serialbits="0" Type="0" ID="2" Sig="i_cs,"/>
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<TU Serialbits="0" Type="0" ID="3" Sig="con_exec,"/>
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<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
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</Trigger>
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</Dataset>
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</Core>
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</Project>
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