yuysh/NewInstrCalBoard_CPLD
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NewInstrCalBoard_CPLD/CPLD1/debug.rvl
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yuysh 54a64ec222 Bug fixes for all CPLDs
2026-05-29 18:31:27 +08:00

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<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/debug.rvl" Date="2026-05-29">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD1"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="695935105" Name="RelayConTop_LA0" ID="0">
<Setting>
<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
<DistRAM Disable="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Type="SIG" Name="i_rst_n"/>
<Sig Type="SIG" Name="BUS_Con_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Reg_1/err_flag"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_con_exec"/>
<Bus Name="CPLD_Con_1/i_DC_Con1">
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:0"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:1"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:2"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:3"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:4"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:5"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:6"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:7"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:8"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:9"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:10"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:11"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:12"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:13"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:14"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:15"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:16"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:17"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:18"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:19"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:20"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:21"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:22"/>
<Sig Type="SIG" Name="CPLD_Con_1/i_DC_Con1:23"/>
</Bus>
<Bus Name="o_RC_RLSel">
<Sig Type="SIG" Name="o_RC_RLSel:0"/>
<Sig Type="SIG" Name="o_RC_RLSel:1"/>
<Sig Type="SIG" Name="o_RC_RLSel:2"/>
<Sig Type="SIG" Name="o_RC_RLSel:3"/>
<Sig Type="SIG" Name="o_RC_RLSel:4"/>
<Sig Type="SIG" Name="o_RC_RLSel:5"/>
<Sig Type="SIG" Name="o_RC_RLSel:6"/>
<Sig Type="SIG" Name="o_RC_RLSel:7"/>
<Sig Type="SIG" Name="o_RC_RLSel:8"/>
<Sig Type="SIG" Name="o_RC_RLSel:9"/>
<Sig Type="SIG" Name="o_RC_RLSel:10"/>
<Sig Type="SIG" Name="o_RC_RLSel:11"/>
<Sig Type="SIG" Name="o_RC_RLSel:12"/>
<Sig Type="SIG" Name="o_RC_RLSel:13"/>
<Sig Type="SIG" Name="o_RC_RLSel:14"/>
<Sig Type="SIG" Name="o_RC_RLSel:15"/>
<Sig Type="SIG" Name="o_RC_RLSel:16"/>
<Sig Type="SIG" Name="o_RC_RLSel:17"/>
</Bus>
<Bus Name="o_PMU_OC_1">
<Sig Type="SIG" Name="o_PMU_OC_1:0"/>
<Sig Type="SIG" Name="o_PMU_OC_1:1"/>
<Sig Type="SIG" Name="o_PMU_OC_1:2"/>
<Sig Type="SIG" Name="o_PMU_OC_1:3"/>
<Sig Type="SIG" Name="o_PMU_OC_1:4"/>
<Sig Type="SIG" Name="o_PMU_OC_1:5"/>
<Sig Type="SIG" Name="o_PMU_OC_1:6"/>
<Sig Type="SIG" Name="o_PMU_OC_1:7"/>
<Sig Type="SIG" Name="o_PMU_OC_1:8"/>
<Sig Type="SIG" Name="o_PMU_OC_1:9"/>
<Sig Type="SIG" Name="o_PMU_OC_1:10"/>
<Sig Type="SIG" Name="o_PMU_OC_1:11"/>
<Sig Type="SIG" Name="o_PMU_OC_1:12"/>
<Sig Type="SIG" Name="o_PMU_OC_1:13"/>
<Sig Type="SIG" Name="o_PMU_OC_1:14"/>
<Sig Type="SIG" Name="o_PMU_OC_1:15"/>
<Sig Type="SIG" Name="o_PMU_OC_1:16"/>
<Sig Type="SIG" Name="o_PMU_OC_1:17"/>
<Sig Type="SIG" Name="o_PMU_OC_1:18"/>
<Sig Type="SIG" Name="o_PMU_OC_1:19"/>
<Sig Type="SIG" Name="o_PMU_OC_1:20"/>
<Sig Type="SIG" Name="o_PMU_OC_1:21"/>
<Sig Type="SIG" Name="o_PMU_OC_1:22"/>
<Sig Type="SIG" Name="o_PMU_OC_1:23"/>
<Sig Type="SIG" Name="o_PMU_OC_1:24"/>
<Sig Type="SIG" Name="o_PMU_OC_1:25"/>
<Sig Type="SIG" Name="o_PMU_OC_1:26"/>
<Sig Type="SIG" Name="o_PMU_OC_1:27"/>
<Sig Type="SIG" Name="o_PMU_OC_1:28"/>
<Sig Type="SIG" Name="o_PMU_OC_1:29"/>
<Sig Type="SIG" Name="o_PMU_OC_1:30"/>
<Sig Type="SIG" Name="o_PMU_OC_1:31"/>
</Bus>
<Bus Name="o_DMM_EN">
<Sig Type="SIG" Name="o_DMM_EN:0"/>
<Sig Type="SIG" Name="o_DMM_EN:1"/>
<Sig Type="SIG" Name="o_DMM_EN:2"/>
<Sig Type="SIG" Name="o_DMM_EN:3"/>
<Sig Type="SIG" Name="o_DMM_EN:4"/>
<Sig Type="SIG" Name="o_DMM_EN:5"/>
<Sig Type="SIG" Name="o_DMM_EN:6"/>
<Sig Type="SIG" Name="o_DMM_EN:7"/>
<Sig Type="SIG" Name="o_DMM_EN:8"/>
<Sig Type="SIG" Name="o_DMM_EN:9"/>
<Sig Type="SIG" Name="o_DMM_EN:10"/>
<Sig Type="SIG" Name="o_DMM_EN:11"/>
<Sig Type="SIG" Name="o_DMM_EN:12"/>
<Sig Type="SIG" Name="o_DMM_EN:13"/>
<Sig Type="SIG" Name="o_DMM_EN:14"/>
<Sig Type="SIG" Name="o_DMM_EN:15"/>
<Sig Type="SIG" Name="o_DMM_EN:16"/>
<Sig Type="SIG" Name="o_DMM_EN:17"/>
<Sig Type="SIG" Name="o_DMM_EN:18"/>
</Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="i_rst_n,"/>
<TU Serialbits="0" Type="0" ID="2" Sig="CPLD_Con_1/i_con_exec,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
</Trigger>
</Dataset>
</Core>
</Project>
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