162 lines
2.1 KiB
Plaintext
162 lines
2.1 KiB
Plaintext
# ============================================================
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# Lattice Diamond .gitignore
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#
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# Strategy:
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# 1. Ignore all junk with broad glob patterns
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# 2. Negate ONLY the files Lattice Diamond needs to open a project
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# ============================================================
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# ---------- Build output ----------
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*_tcr.dir/
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#Others
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.vscode
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.recovery
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*.edn
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*.cam
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*.areasrr
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*.pt
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*.hrr
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*.sym
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pmi_*
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# ---------- Synthesis (Synplify Pro / Synplify) ----------
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synlog/
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synwork/
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syntmp/
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*.srp
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*.srm
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*.srd
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*.srs
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*.srr
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*.rt.csv
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*.fdep
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*.szr
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# ---------- Implementation (Place & Route) ----------
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*.ncd
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*.par
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*.ngd
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*.pad
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*.fse
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*.twr
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*.tw1
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*.t2b
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*.p2t
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*.p3t
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*.mrp
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*.mt
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*.drc
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*.prf
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*.prs
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*.plg
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*.bgn
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*.alt
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*.gcr
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*.fdepxmr
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*.schmap
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# ---------- Auto-generated junk ----------
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*.lst
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*.naf
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*.log
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*.tlg
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*.tgl
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*.CML
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*.tcl
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# ---------- QuestaSim / VCS simulation junk ----------
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*.ado
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*.adf
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*.cr.mti
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*.mdo
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*.mpf
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*.tops
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*.dmp
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*.vcd
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*.wlf
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vsim.wlf
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transcript
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hdlparser.log
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*.qdb
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*.qtl
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*.qpg
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*.ngo
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*.vmake
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*_info
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work/
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# ---------- HTML / XML reports ----------
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*.html
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*.htm
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*.xml
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*.csv
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*.txt
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# ---------- Generated / intermediate files ----------
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promote.xml
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reportview.xml
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*.asd
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*.rptmap
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*.rpt
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*.tcr
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# ---------- Reveal debug workspace (re-generatable) ----------
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reveal_workspace/
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*.rvp
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# ---------- Bitstream / programming intermediates ----------
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*.srf
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*.sdf
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*.ibs
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*.lpc
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*.duruntime
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*.xdm
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*.edi
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# ---------- Backup / temp ----------
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*.bak
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# ---------- Per-project sub-directories ----------
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# Diamond GUI configs
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*.ini
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*.cfg
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# ---------- Lattice GUI state ----------
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*.sort
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*.db
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# ---------- Negate: Lattice Diamond opens project ONLY with these ----------
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# Verilog / SystemVerilog / VHDL source
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!*.v
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!*.sv
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!*.vhd
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# Lattice project definition
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!*.lpf
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!*.ldf
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!*.sty
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!*.ccl
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!*.tfi
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# Bitstream and programming
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!*.bit
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!*.jed
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!*.svf
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!*.xcf
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# Simulation project files (.spf is needed by Diamond's sim engine)
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!*.spf
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# Debug / trace
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!*.hub
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!*.rvl
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# ---------- Catch-alls (after negations — last matching rule wins) ----------
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# IEEE stdlib VHDL (auto-generated by sim tool, not project source)
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*_math_real*
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*.log.bak.*
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.build_status
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