12 lines
749 B
Plaintext
12 lines
749 B
Plaintext
<BaliSimProject version="1.3" path="." stage="0" language="-1" name="tb_RelayConTop" simType="QuestaSim">
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<Source worklib="work" path="CPLD_Con.v" type="VERILOG" langstandard="" include="none"/>
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<Source worklib="work" path="Reg_file.v" type="VERILOG" langstandard="" include="none"/>
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<Source worklib="work" path="BUS_Con.v" type="VERILOG" langstandard="" include="none"/>
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<Source worklib="work" path="RelayConTop.v" type="VERILOG" langstandard="" include="none"/>
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<Source worklib="work" path="tb_RelayConTop.sv" type="VERILOG" langstandard="" include="none"/>
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<SimLib value="pmi_work ovi_machxo2"/>
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<GlbInc value=""/>
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<Macro value=""/>
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<TopModule instance="" language="" name="tb_RelayConTop"/>
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</BaliSimProject>
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