93 lines
1.8 KiB
Verilog
93 lines
1.8 KiB
Verilog
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// TOOL: vlog2tf
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// DATE: Fri May 15 17:23:27 2026
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// TITLE: Lattice Semiconductor Corporation
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// MODULE: RelayConTop
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// DESIGN: RelayConTop
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// FILENAME: RelayConTop_tf.v
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// PROJECT: NewExtIns_CPLD1
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// VERSION: 2.0
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// This file is auto generated by Diamond
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`timescale 1 ns / 1 ps
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// Define Module for Test Fixture
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module RelayConTop_tf();
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// Inputs
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reg i_sys_clk;
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reg i_rst_n;
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reg i_sclk;
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reg i_mosi;
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reg i_cs;
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reg i_rready;
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reg i_wvalid;
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// Outputs
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wire o_miso;
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wire o_rvalid;
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wire o_wready;
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wire o_err;
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wire o_con_done;
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wire [18:0] o_DMM_EN;
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wire o_IO_RC1;
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wire o_RC_T27;
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wire o_RC_T28;
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wire o_RC_T29;
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wire o_RC_T30;
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wire o_RC_T31;
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wire [31:0] o_OC_1;
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wire [31:0] o_OC_2;
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wire [31:0] o_OC_3;
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wire [31:0] o_OC_4;
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// Bidirs
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// Instantiate the UUT
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// Please check and add your parameters manually
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RelayConTop UUT (
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.i_sys_clk(i_sys_clk),
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.i_rst_n(i_rst_n),
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.i_sclk(i_sclk),
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.i_mosi(i_mosi),
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.i_cs(i_cs),
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.o_miso(o_miso),
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.o_rvalid(o_rvalid),
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.i_rready(i_rready),
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.i_wvalid(i_wvalid),
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.o_wready(o_wready),
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.o_err(o_err),
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.o_con_done(o_con_done),
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.o_DMM_EN(o_DMM_EN),
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.o_IO_RC1(o_IO_RC1),
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.o_RC_T27(o_RC_T27),
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.o_RC_T28(o_RC_T28),
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.o_RC_T29(o_RC_T29),
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.o_RC_T30(o_RC_T30),
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.o_RC_T31(o_RC_T31),
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.o_OC_1(o_OC_1),
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.o_OC_2(o_OC_2),
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.o_OC_3(o_OC_3),
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.o_OC_4(o_OC_4)
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);
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// Initialize Inputs
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// You can add your stimulus here
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initial begin
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i_sys_clk = 0;
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i_rst_n = 0;
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i_sclk = 0;
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i_mosi = 0;
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i_cs = 0;
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i_rready = 0;
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i_wvalid = 0;
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end
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endmodule // RelayConTop_tf
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