36 lines
1.9 KiB
Plaintext
36 lines
1.9 KiB
Plaintext
<Project ModBy="Inserter" SigType="0" Name="C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD3/debug.rvl" Date="2026-05-29">
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<IP Version="1_6_042617"/>
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<Design DesignEntry="Schematic/Verilog HDL" Synthesis="synplify" DeviceFamily="MachXO2" DesignName="NewExtIns_CPLD3"/>
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<Core InsertDataset="0" Insert="1" Reveal_sig="695936675" Name="RelayConTop_LA0" ID="0">
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<Setting>
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<Clock SampleClk="i_sys_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
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<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="0" BufferDepth="2048"/>
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<Capture Mode="0" MinSamplesPerTrig="8"/>
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<Event CntEnable="0" MaxEventCnt="8"/>
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<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_RelayConTop_LA0_net"/>
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<DistRAM Disable="0"/>
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</Setting>
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<Dataset Name="Base">
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<Trace>
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<Sig Type="SIG" Name="i_rst_n"/>
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<Sig Type="SIG" Name="Bus_Con_3/err_flag"/>
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<Sig Type="SIG" Name="CPLD_Con_3/err_flag"/>
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<Sig Type="SIG" Name="CPLD_Reg_3/err_flag"/>
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<Sig Type="SIG" Name="CPLD_Con_3/i_con_exec"/>
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<Bus Name="o_PMU_RC">
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<Sig Type="SIG" Name="o_PMU_RC:0"/>
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<Sig Type="SIG" Name="o_PMU_RC:1"/>
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<Sig Type="SIG" Name="o_PMU_RC:2"/>
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<Sig Type="SIG" Name="o_PMU_RC:3"/>
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</Bus>
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</Trace>
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<Trigger>
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<TU Serialbits="0" Type="0" ID="1" Sig="i_rst_n,"/>
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<TU Serialbits="0" Type="0" ID="2" Sig="CPLD_Con_3/i_con_exec,"/>
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<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
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<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
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</Trigger>
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</Dataset>
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</Core>
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</Project>
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