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NewInstrCalBoard_CPLD/CPLD2/impl1/NewExtIns_CPLD2_impl1_synplify.lpf
T
2026-05-28 09:30:38 +08:00

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#
# Logical Preferences generated for Lattice by Synplify map202309lat, Build 191R.
#
# Period Constraints
#FREQUENCY NET "RelayConTop_reveal_coretop_instance/jtck[0]" 200.0 MHz;
#FREQUENCY PORT "i_sys_clk" 200.0 MHz;
# Output Constraints
# Input Constraints
# Point-to-point Delay Constraints
# Block Path Constraints
#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]";
#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c";
#BLOCK PATH FROM CLKNET "i_sys_clk_c" TO CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]";
#BLOCK PATH FROM CLKNET "RelayConTop_reveal_coretop_instance/jtck[0]" TO CLKNET "i_sys_clk_c";
BLOCK ASYNCPATHS;
# End of generated Logical Preferences.