20 lines
346 B
Verilog
20 lines
346 B
Verilog
module AD5522_Con (
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input i_sys_clk,
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input i_rst_n,
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output o_AD5522_Reset
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);
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reg AD5522_Reset;
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always @(posedge i_sys_clk) begin
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if (!i_rst_n) begin
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AD5522_Reset <= 'd0;
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end else begin
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AD5522_Reset <= 'd1;
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end
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end
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assign o_AD5522_Reset = AD5522_Reset;
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endmodule |