169 lines
3.9 KiB
Verilog
169 lines
3.9 KiB
Verilog
module RelayConTop (
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input i_sys_clk,
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input i_rst_n,
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input i_sclk,
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input i_mosi,
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input i_cs,
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output o_miso,
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output o_rvalid,
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input i_rready,
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input i_wvalid,
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output o_wready,
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output o_err,
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output [7:0]o_RC_F, //Ref: Schematic
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output [15:0]o_RC_S,
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output [25:0]o_RC_T, //Actually ONLY 25 pin(rest is on CPLD1)
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//PMU OC Control
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output [15:0]o_PMU_OC_1 ,
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output [15:0]o_PMU_OC_2 ,
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output [15:0]o_PMU_OC_3 ,
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output [15:0]o_PMU_OC_4 ,
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//DPS OC Control
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output [15:0]o_DPS_F_1 ,
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output [15:0]o_DPS_S_1 ,
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output [15:0]o_DPS_F_2 ,
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output [15:0]o_DPS_S_2 ,
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output [15:0]o_DPS_F_3 ,
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output [15:0]o_DPS_S_3 ,
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output [15:0]o_DPS_F_4 ,
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output [15:0]o_DPS_S_4
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);
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wire [7:0] RC_F;
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wire [15:0] RC_S;
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wire [31:0] RC_T;
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wire [23:0]r_data ;
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wire [23:0]w_data ;
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wire [6:0]reg_addr ;
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wire cmd_valid;
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wire reg_busy;
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wire wr_flag; //1=write,0=read
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wire bus_err_flag;
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wire reg_err_flag;
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wire cpld_err_flag;
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wire con_exec;
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wire [23:0]freq1_relay ;
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wire [23:0]freq2_relay ;
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wire [23:0]freq3_relay ;
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wire [23:0]freq4_relay ;
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//DC Control Reg output
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wire [23:0]DC_Con1 ;
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wire [23:0]DC_Con2 ;
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wire [23:0]DC_Con3 ;
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wire [23:0]DC_Con4 ;
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//PMU OC Control
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wire [31:0]PMU_OC_1 ;
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wire [31:0]PMU_OC_2 ;
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wire [31:0]PMU_OC_3 ;
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wire [31:0]PMU_OC_4 ;
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//DPS PerChannel Force/Sense Control
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wire [15:0]DPS_FS_1 ;
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wire [15:0]DPS_FS_2 ;
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wire [15:0]DPS_FS_3 ;
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wire [15:0]DPS_FS_4 ;
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wire con_rvalid;
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wire con_done;
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BUS_Con BUS_Con_2(
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.i_sys_clk(i_sys_clk),
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.i_rst_n(i_rst_n),
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.i_sclk(i_sclk),
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.i_mosi(i_mosi),
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.i_cs(i_cs),
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.i_rvalid(con_rvalid),
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.i_wvalid(i_wvalid),
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.i_reg_busy(reg_busy),
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.i_rdata(r_data),
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.o_cmd_valid(cmd_valid),
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.o_wr(wr_flag),
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.o_miso(o_miso),
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.o_rvalid(o_rvalid),
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.o_wready(o_wready),
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.o_data(w_data),
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.o_addr(reg_addr),
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.o_err(bus_err_flag)
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);
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Reg_file CPLD_Reg_2(
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.i_sys_clk(i_sys_clk),
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.i_rst_n(i_rst_n),
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.i_wr_req(cmd_valid),
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.i_wr(wr_flag),
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.i_addr(reg_addr),
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.i_wdata(w_data),
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.i_con_done(con_done), //Controller Exec Done
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.o_freq1(freq1_relay), //Freq_Slot1
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.o_freq2(freq2_relay), //Freq_Slot2
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.o_freq3(freq3_relay), //Freq_Slot3
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.o_freq4(freq4_relay), //Freq_Slot4
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.o_DC1(DC_Con1),
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.o_DC2(DC_Con2),
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.o_DC3(DC_Con3),
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.o_DC4(DC_Con4),
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.o_rvalid(con_rvalid),
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.o_rdata(r_data),
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.o_exec(con_exec), //Exec cmd
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.o_busy(reg_busy),
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.o_err(reg_err_flag)
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);
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CPLD_Con CPLD_Con_2(
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.i_sys_clk(i_sys_clk),
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.i_rst_n(i_rst_n),
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.i_con_exec(con_exec),
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.i_freq_relay1(freq1_relay),
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.i_freq_relay2(freq2_relay),
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.i_freq_relay3(freq3_relay),
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.i_freq_relay4(freq4_relay),
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.i_DC_Con1(DC_Con1),
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.i_DC_Con2(DC_Con2),
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.i_DC_Con3(DC_Con3),
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.i_DC_Con4(DC_Con4),
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.o_PMU_OC_1(PMU_OC_1),
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.o_PMU_OC_2(PMU_OC_2),
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.o_PMU_OC_3(PMU_OC_3),
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.o_PMU_OC_4(PMU_OC_4),
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.o_DPS_FS_1(DPS_FS_1),
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.o_DPS_FS_2(DPS_FS_2),
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.o_DPS_FS_3(DPS_FS_3),
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.o_DPS_FS_4(DPS_FS_4),
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.o_con_done(con_done),
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.o_RC_F(RC_F),
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.o_RC_S(RC_S),
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.o_RC_T(RC_T),
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.o_err(cpld_err_flag)
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);
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assign o_RC_F = RC_F;
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assign o_RC_S = RC_S;
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assign o_RC_T = RC_T[25:0];
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assign o_PMU_OC_1 = {PMU_OC_1[31:24],PMU_OC_1[15:8]} ;
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assign o_PMU_OC_2 = {PMU_OC_2[31:24],PMU_OC_2[15:8]} ;
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assign o_PMU_OC_3 = {PMU_OC_3[31:24],PMU_OC_3[15:8]} ;
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assign o_PMU_OC_4 = {PMU_OC_4[31:24],PMU_OC_4[15:8]} ;
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assign o_DPS_F_1 = DPS_FS_1;
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assign o_DPS_S_1 = DPS_FS_1;
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assign o_DPS_F_2 = DPS_FS_2;
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assign o_DPS_S_2 = DPS_FS_2;
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assign o_DPS_F_3 = DPS_FS_3;
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assign o_DPS_S_3 = DPS_FS_3;
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assign o_DPS_F_4 = DPS_FS_4;
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assign o_DPS_S_4 = DPS_FS_4;
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assign o_err = bus_err_flag || reg_err_flag || cpld_err_flag;
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endmodule
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