module RelayConTop (
	input i_sys_clk,
	input i_rst_n,
	
	input i_sclk,
	input i_mosi,
	input i_cs,
	output o_miso,
	output o_rvalid,
	input i_rready,
	input i_wvalid,
	output o_wready,
	output o_err,
	output [7:0]o_RC_F,           //Ref: Schematic
    output [15:0]o_RC_S,
    output [25:0]o_RC_T,		  //Actually ONLY 25 pin(rest is on CPLD1)
	//PMU OC Control
	output [15:0]o_PMU_OC_1 ,
    output [15:0]o_PMU_OC_2 ,
    output [15:0]o_PMU_OC_3 ,
    output [15:0]o_PMU_OC_4 ,
	//DPS OC Control
	output [15:0]o_DPS_F_1 ,
	output [15:0]o_DPS_S_1 ,
	output [15:0]o_DPS_F_2 ,
	output [15:0]o_DPS_S_2 ,
	output [15:0]o_DPS_F_3 ,
	output [15:0]o_DPS_S_3 ,
	output [15:0]o_DPS_F_4 ,
	output [15:0]o_DPS_S_4 
);

	wire [7:0] RC_F;
	wire [15:0] RC_S;
	wire [31:0] RC_T;

	wire [23:0]r_data ;
	wire [23:0]w_data ;
	wire [6:0]reg_addr ;

	wire cmd_valid;
	wire reg_busy;
	wire wr_flag;						//1=write,0=read
	wire bus_err_flag;
	wire reg_err_flag;
	wire cpld_err_flag;

	wire con_exec;
	wire [23:0]freq1_relay ;
	wire [23:0]freq2_relay ;
	wire [23:0]freq3_relay ;
	wire [23:0]freq4_relay ;

	//DC Control Reg output
	wire [23:0]DC_Con1 ;
	wire [23:0]DC_Con2 ;
	wire [23:0]DC_Con3 ;
	wire [23:0]DC_Con4 ;

	//PMU OC Control
	wire [31:0]PMU_OC_1 ;
	wire [31:0]PMU_OC_2 ;
	wire [31:0]PMU_OC_3 ;
	wire [31:0]PMU_OC_4 ;

	//DPS PerChannel Force/Sense Control
	wire [15:0]DPS_FS_1	;
	wire [15:0]DPS_FS_2	;
	wire [15:0]DPS_FS_3	;
	wire [15:0]DPS_FS_4	;

	wire con_rvalid;

	wire con_done;

BUS_Con BUS_Con_2(
		.i_sys_clk(i_sys_clk),
		.i_rst_n(i_rst_n),
		.i_sclk(i_sclk),
		.i_mosi(i_mosi),
		.i_cs(i_cs),
		.i_rvalid(con_rvalid),
		.i_wvalid(i_wvalid),
		.i_reg_busy(reg_busy),
		.i_rdata(r_data),
		.o_cmd_valid(cmd_valid),
		.o_wr(wr_flag),
 		.o_miso(o_miso),
		.o_rvalid(o_rvalid),
		.o_wready(o_wready),
		.o_data(w_data),
		.o_addr(reg_addr),
		.o_err(bus_err_flag)
	);

	Reg_file CPLD_Reg_2(
		.i_sys_clk(i_sys_clk),
		.i_rst_n(i_rst_n),
		.i_wr_req(cmd_valid),
		.i_wr(wr_flag),
		.i_addr(reg_addr),
		.i_wdata(w_data),
		.i_con_done(con_done),                               	//Controller Exec Done
		.o_freq1(freq1_relay),                            		//Freq_Slot1
		.o_freq2(freq2_relay),                            		//Freq_Slot2
		.o_freq3(freq3_relay),                            		//Freq_Slot3 
		.o_freq4(freq4_relay),									//Freq_Slot4
		.o_DC1(DC_Con1),
		.o_DC2(DC_Con2),
		.o_DC3(DC_Con3),
		.o_DC4(DC_Con4),
		.o_rvalid(con_rvalid),
		.o_rdata(r_data),
		.o_exec(con_exec),										//Exec cmd
		.o_busy(reg_busy),
		.o_err(reg_err_flag)
	);
	
	CPLD_Con CPLD_Con_2(
		.i_sys_clk(i_sys_clk),
		.i_rst_n(i_rst_n),
		.i_con_exec(con_exec),
		.i_freq_relay1(freq1_relay),
		.i_freq_relay2(freq2_relay),
		.i_freq_relay3(freq3_relay),
		.i_freq_relay4(freq4_relay),
		.i_DC_Con1(DC_Con1),
		.i_DC_Con2(DC_Con2),
		.i_DC_Con3(DC_Con3),
		.i_DC_Con4(DC_Con4),
		.o_PMU_OC_1(PMU_OC_1),
		.o_PMU_OC_2(PMU_OC_2),
		.o_PMU_OC_3(PMU_OC_3),
		.o_PMU_OC_4(PMU_OC_4),
		.o_DPS_FS_1(DPS_FS_1),
		.o_DPS_FS_2(DPS_FS_2),
		.o_DPS_FS_3(DPS_FS_3),
		.o_DPS_FS_4(DPS_FS_4),
		.o_con_done(con_done),
		.o_RC_F(RC_F),
		.o_RC_S(RC_S),
		.o_RC_T(RC_T),
		.o_err(cpld_err_flag)
	);


	assign o_RC_F = RC_F;
    assign o_RC_S = RC_S;
    assign o_RC_T = RC_T[25:0];
	
	assign o_PMU_OC_1 = {PMU_OC_1[31:24],PMU_OC_1[15:8]} ;
	assign o_PMU_OC_2 = {PMU_OC_2[31:24],PMU_OC_2[15:8]} ;
	assign o_PMU_OC_3 = {PMU_OC_3[31:24],PMU_OC_3[15:8]} ;
	assign o_PMU_OC_4 = {PMU_OC_4[31:24],PMU_OC_4[15:8]} ;

	assign o_DPS_F_1 = DPS_FS_1;
	assign o_DPS_S_1 = DPS_FS_1;
	assign o_DPS_F_2 = DPS_FS_2;
	assign o_DPS_S_2 = DPS_FS_2;
	assign o_DPS_F_3 = DPS_FS_3;
	assign o_DPS_S_3 = DPS_FS_3;
	assign o_DPS_F_4 = DPS_FS_4;
	assign o_DPS_S_4 = DPS_FS_4;

	assign o_err = bus_err_flag || reg_err_flag ||  cpld_err_flag;
	
	
endmodule