// TOOL:     vlog2tf
// DATE:     Fri May 15 17:23:34 2026
 
// TITLE:    Lattice Semiconductor Corporation
// MODULE:   RelayConTop
// DESIGN:   RelayConTop
// FILENAME: RelayConTop.tfi
// PROJECT:  NewExtIns_CPLD1
// VERSION:  2.0
// NOTE: DO NOT EDIT THIS FILE
//
// This file is generated by the Verilog Test Fixture Declarations process and 
// contains an I/O and instance declarations of the Verilog source file
// you selected from the Sources in Project list.
// Notes:
// 1) This include file (.tfi) should be referenced by your text fixture using
// the `include compile directive using the syntax:  `include "<file_name>.tfi"
// 2) If your design I/O changes, rerun the process to obtain new I/O and 
// instance declarations.
// 3) Verilog simulations will produce errors if there are Lattice FPGA library 
// elements in your design that require the instantiation of GSR, PUR, and TSALL
// and they are not present in the test fixture. For more information see the 
// How To section of online help. 



// Inputs
	reg i_sys_clk;
	reg i_rst_n;
	reg i_sclk;
	reg i_mosi;
	reg i_cs;
	reg i_rready;
	reg i_wvalid;


// Outputs
	wire o_miso;
	wire o_rvalid;
	wire o_wready;
	wire o_err;
	wire o_con_done;
	wire [18:0] o_DMM_EN;
	wire o_IO_RC1;
	wire o_RC_T27;
	wire o_RC_T28;
	wire o_RC_T29;
	wire o_RC_T30;
	wire o_RC_T31;
	wire [31:0] o_OC_1;
	wire [31:0] o_OC_2;
	wire [31:0] o_OC_3;
	wire [31:0] o_OC_4;


// Bidirs


// Instantiate the UUT
	RelayConTop UUT (
		.i_sys_clk(i_sys_clk), 
		.i_rst_n(i_rst_n), 
		.i_sclk(i_sclk), 
		.i_mosi(i_mosi), 
		.i_cs(i_cs), 
		.o_miso(o_miso), 
		.o_rvalid(o_rvalid), 
		.i_rready(i_rready), 
		.i_wvalid(i_wvalid), 
		.o_wready(o_wready), 
		.o_err(o_err), 
		.o_con_done(o_con_done), 
		.o_DMM_EN(o_DMM_EN), 
		.o_IO_RC1(o_IO_RC1), 
		.o_RC_T27(o_RC_T27), 
		.o_RC_T28(o_RC_T28), 
		.o_RC_T29(o_RC_T29), 
		.o_RC_T30(o_RC_T30), 
		.o_RC_T31(o_RC_T31), 
		.o_OC_1(o_OC_1), 
		.o_OC_2(o_OC_2), 
		.o_OC_3(o_OC_3), 
		.o_OC_4(o_OC_4)
	);


// Initialize Inputs
`ifdef auto_init

	initial begin
		i_sys_clk = 0;
		i_rst_n = 0;
		i_sclk = 0;
		i_mosi = 0;
		i_cs = 0;
		i_rready = 0;
		i_wvalid = 0;
	end

`endif