---------------------------------------------------------------------- Report for cell RelayConTop.verilog Register bits: 769 of 6864 (11%) PIC Latch: 0 I/O cells: 187 Cell usage: cell count Res Usage(%) FD1P3AX 419 100.0 FD1P3AY 4 100.0 FD1P3IX 148 100.0 FD1P3JX 1 100.0 FD1S3AX 16 100.0 FD1S3IX 14 100.0 FD1S3JX 1 100.0 GSR 1 100.0 IB 5 100.0 IFS1P3IX 3 100.0 IFS1P3JX 1 100.0 INV 2 100.0 L6MUX21 72 100.0 OB 181 100.0 OBZ 1 100.0 OFS1P3DX 36 100.0 OFS1P3IX 126 100.0 ORCALUT4 747 100.0 PFUMX 104 100.0 PUR 1 100.0 VHI 4 100.0 VLO 4 100.0 SUB MODULES BUS_Con 1 100.0 CPLD_Con 1 100.0 Reg_file 1 100.0 TOTAL 1894 ---------------------------------------------------------------------- Report for cell CPLD_Con.netlist Instance path: CPLD_Con_1 Cell usage: cell count Res Usage(%) FD1P3IX 18 12.2 FD1P3JX 1 100.0 FD1S3AX 12 75.0 FD1S3IX 5 35.7 INV 1 50.0 ORCALUT4 441 59.0 PFUMX 8 7.7 VHI 1 25.0 VLO 1 25.0 TOTAL 488 ---------------------------------------------------------------------- Report for cell Reg_file.netlist Instance path: CPLD_Reg_1 Cell usage: cell count Res Usage(%) FD1P3AX 419 100.0 FD1P3AY 4 100.0 FD1S3AX 2 12.5 L6MUX21 72 100.0 ORCALUT4 239 32.0 PFUMX 96 92.3 VHI 1 25.0 VLO 1 25.0 TOTAL 834 ---------------------------------------------------------------------- Report for cell BUS_Con.netlist Instance path: BUS_Con_1 Cell usage: cell count Res Usage(%) FD1P3IX 130 87.8 FD1S3AX 2 12.5 FD1S3IX 9 64.3 FD1S3JX 1 100.0 ORCALUT4 67 9.0 VHI 1 25.0 VLO 1 25.0 TOTAL 211