module AD5522_Con (
    input i_sys_clk,
    input i_rst_n,
    
    output o_AD5522_Reset
);

    reg AD5522_Reset;

    always @(posedge i_sys_clk) begin
        if (!i_rst_n) begin
            AD5522_Reset <= 'd0;
        end else begin
            AD5522_Reset <= 'd1;
        end
    end

    assign o_AD5522_Reset = AD5522_Reset;

endmodule