# ============================================================
# Lattice Diamond .gitignore
#
# Strategy:
#   1. Ignore all junk with broad glob patterns
#   2. Negate ONLY the files Lattice Diamond needs to open a project
# ============================================================

# ---------- Build output ----------
*_tcr.dir/

#Others
.vscode
.recovery
*.edn
*.cam
*.areasrr
*.pt
*.hrr
*.sym
pmi_*
*._cml

# ---------- Synthesis (Synplify Pro / Synplify) ----------
synlog/
synwork/
syntmp/
*.srp
*.srm
*.srd
*.srs
*.srr
*.rt.csv
*.fdep
*.szr

# ---------- Implementation (Place & Route) ----------
*.ncd
*.par
*.ngd
*.pad
*.fse
*.twr
*.tw1
*.t2b
*.p2t
*.p3t
*.mrp
*.mt
*.drc
*.prf
*.prs
*.plg
*.bgn
*.alt
*.gcr
*.fdepxmr
*.schmap

# ---------- Auto-generated junk ----------
*.lst
*.naf
*.log
*.tlg
*.tgl
*.CML
*.tcl

# ---------- QuestaSim / VCS simulation junk ----------
*.ado
*.adf
*.cr.mti
*.mdo
*.mpf
*.tops
*.dmp
*.vcd
*.wlf
vsim.wlf
transcript
hdlparser.log
*.qdb
*.qtl
*.qpg
*.ngo
*.vmake
*_info
work/

# ---------- HTML / XML reports ----------
*.html
*.htm
*.xml
*.csv
*.txt

# ---------- Generated / intermediate files ----------
promote.xml
reportview.xml
*.asd
*.rptmap
*.rpt
*.tcr

# ---------- Reveal debug workspace (re-generatable) ----------
reveal_workspace/
*.rvp

# ---------- Bitstream / programming intermediates ----------
*.srf
*.sdf
*.ibs
*.lpc
*.duruntime
*.xdm
*.edi

# ---------- Backup / temp ----------
*.bak

# ---------- Per-project sub-directories ----------
# Diamond GUI configs
*.ini
*.cfg

# ---------- Lattice GUI state ----------
*.sort
*.db

# ---------- Negate: Lattice Diamond opens project ONLY with these ----------

# Verilog / SystemVerilog / VHDL source
!*.v
!*.sv
!*.vhd

# Lattice project definition
!*.lpf
!*.ldf
!*.sty
!*.ccl
!*.tfi

# Bitstream and programming
!*.bit
!*.jed
!*.svf
!*.xcf

# Simulation project files (.spf is needed by Diamond's sim engine)
!*.spf

# Debug / trace
!*.hub
!*.rvl

# ---------- Catch-alls (after negations — last matching rule wins) ----------

# IEEE stdlib VHDL (auto-generated by sim tool, not project source)
*_math_real*
*.log.bak.*
.build_status