module CPLD_Con ( input i_sys_clk, input i_rst_n, input i_con_exec, // Freq Relay Control input [23:0]i_freq_relay1, input [23:0]i_freq_relay2, input [23:0]i_freq_relay3, input [23:0]i_freq_relay4, // DC related Control input [23:0]i_DC_Con1, input [23:0]i_DC_Con2, input [23:0]i_DC_Con3, input [23:0]i_DC_Con4, //Output RELAYs output [7:0]o_RC_F, //Ref: Schematic output [15:0]o_RC_S, output [31:0]o_RC_T, output [3:0] o_OC_x09, output [3:0] o_OC_x25, output [31:0]o_PMU_OC_1 , output [31:0]o_PMU_OC_2 , output [31:0]o_PMU_OC_3 , output [31:0]o_PMU_OC_4, //Output FLAGs output o_err, output o_con_done ); //Output Relay Reg reg [3:0] OC_x09; reg [3:0] OC_x25; //Condition Tester reg [3:0]en_t ; reg [3:0]freq_t; reg [3:0]dc_t; //Relay Reg reg [7:0]relay_l1; reg [15:0]relay_l2 ; reg [31:0]relay_l3 ; reg [31:0]PMU_OC_1 ; reg [31:0]PMU_OC_2 ; reg [31:0]PMU_OC_3 ; reg [31:0]PMU_OC_4 ; //Flags reg exec_done_flag; reg exec_flag; reg [3:0]freq_slot_flag; reg [3:0]dc_slot_flag ; reg err_flag; //Counter reg [15:0]delay_cnt; //Shift Counter wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8 wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8 wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8 wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8 //Channels wire [8:0]Channel_1 = i_DC_Con1[9:1] ; wire [8:0]Channel_2 = i_DC_Con2[9:1] ; wire [8:0]Channel_3 = i_DC_Con3[9:1] ; wire [8:0]Channel_4 = i_DC_Con4[9:1] ; wire [8:0] freq_relay1 = i_freq_relay1[9:1]; wire [8:0] freq_relay2 = i_freq_relay2[9:1]; wire [8:0] freq_relay3 = i_freq_relay3[9:1]; wire [8:0] freq_relay4 = i_freq_relay4[9:1]; always @(posedge i_sys_clk) begin if (i_rst_n == 1'b0) begin delay_cnt <= 'd0; end else begin if (exec_flag == 1'b1) begin delay_cnt <= delay_cnt + 1'd1; end else begin delay_cnt <= 'd0; end end end //Function Identify always @(posedge i_sys_clk) begin if (i_rst_n == 1'b0) begin en_t <= 'd0; freq_t <= 'd0; dc_t <= 'd0; end else begin en_t <= (i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]) + (i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0] ); freq_t <= i_freq_relay1[0] + i_freq_relay2[0] + i_freq_relay3[0] + i_freq_relay4[0]; dc_t <= i_DC_Con1[0] +i_DC_Con2[0] +i_DC_Con3[0] +i_DC_Con4[0]; end end // Main Controller Function always @(posedge i_sys_clk) begin if (i_rst_n == 1'b0) begin relay_l1 <= 'd0; relay_l2 <= 'd0; relay_l3 <= 'd0; exec_flag <= 1'b0; exec_done_flag <= 1'b1; freq_slot_flag <= 'd0; PMU_OC_1 <= 'd0; PMU_OC_2 <= 'd0; PMU_OC_3 <= 'd0; PMU_OC_4 <= 'd0; dc_slot_flag<='d0; err_flag <= 'd0; end else begin if ((i_con_exec == 1'b1) & (exec_flag == 1'b0)) begin //To DO: More Sanity Check? if (en_t > 'd1) begin //Only ONE Enable bit should be set! err_flag <= 1'b1; end else begin exec_done_flag <= 'd0; exec_flag <= 1'b1; freq_slot_flag[0] <= i_freq_relay1[0]; freq_slot_flag[1] <= i_freq_relay2[0]; freq_slot_flag[2] <= i_freq_relay3[0]; freq_slot_flag[3] <= i_freq_relay4[0]; dc_slot_flag[0] <= i_DC_Con1[0]; dc_slot_flag[1] <= i_DC_Con2[0]; dc_slot_flag[2] <= i_DC_Con3[0]; dc_slot_flag[3] <= i_DC_Con4[0]; end end else if (exec_flag == 1'b1) begin //Output Relay if (freq_t == 1'b1) begin case (freq_slot_flag) 4'b0001: begin relay_l1 <= {'d0,i_freq_relay1[22],i_freq_relay1[23]}; if (delay_cnt == 'd500) begin relay_l2 <= {'d0,i_freq_relay1[18],i_freq_relay1[19],i_freq_relay1[20],i_freq_relay1[21]}; end else if (delay_cnt == 'd1000) begin relay_l3 <= {'d0,i_freq_relay1[10],i_freq_relay1[11],i_freq_relay1[12],i_freq_relay1[13],i_freq_relay1[14],i_freq_relay1[15],i_freq_relay1[16],i_freq_relay1[17]}; end else if (delay_cnt == 'd1080) begin exec_flag <= 'd0; exec_done_flag <= 1'b1; end if ((freq_relay1 > 64) & (freq_relay1 < 73)) begin OC_x09 <= 4'b0001; end else if ((freq_relay1 > 192) & (freq_relay1 < 201)) begin OC_x25 <= 4'b0001; end else begin OC_x09 <= 'd0; OC_x25 <= 'd0; end end 4'b0010: begin relay_l1 <= {4'd0,i_freq_relay2[22],i_freq_relay2[23],2'd0}; if (delay_cnt == 'd500) begin relay_l2 <= {8'd0,i_freq_relay2[18],i_freq_relay2[19],i_freq_relay2[20],i_freq_relay2[21],4'd0}; end else if (delay_cnt == 'd1000) begin relay_l3 <= {16'd0,i_freq_relay2[10],i_freq_relay2[11],i_freq_relay2[12],i_freq_relay2[13],i_freq_relay2[14],i_freq_relay2[15],i_freq_relay2[16],i_freq_relay2[17],8'd0}; end else if (delay_cnt == 'd1080) begin exec_flag <= 'd0; exec_done_flag <= 1'b1; end if ((freq_relay2 > 64) & (freq_relay2 < 73)) begin OC_x09 <= 4'b0010; end else if ((freq_relay2 > 192) & (freq_relay2 < 201)) begin OC_x25 <= 4'b0010; end else begin OC_x09 <= 'd0; OC_x25 <= 'd0; end end 4'b0100: begin relay_l1 <= {2'd0,i_freq_relay3[22],i_freq_relay3[23],4'd0}; if (delay_cnt == 'd500) begin relay_l2 <= {4'd0,i_freq_relay3[18],i_freq_relay3[19],i_freq_relay3[20],i_freq_relay3[21],8'd0}; end else if (delay_cnt == 'd1000) begin relay_l3 <= {8'd0,i_freq_relay3[12],i_freq_relay3[13],i_freq_relay3[10],i_freq_relay3[11],i_freq_relay3[16],i_freq_relay3[17],i_freq_relay3[14],i_freq_relay3[15],16'd0}; end else if (delay_cnt == 'd1080) begin exec_flag <= 'd0; exec_done_flag <= 1'b1; end if ((freq_relay3 > 64) &(freq_relay3 <73)) begin OC_x09 <= 4'b0100; end else if ((freq_relay3 > 192) & (freq_relay3 < 201)) begin OC_x25 <= 4'b0100; end else begin OC_x09 <= 'd0; OC_x25 <= 'd0; end end 4'b1000: begin relay_l1 <= {i_freq_relay4[22],i_freq_relay4[23],6'd0}; if (delay_cnt == 'd500) begin relay_l2 <= {i_freq_relay4[18],i_freq_relay4[19],i_freq_relay4[20],i_freq_relay4[21],12'd0}; end else if (delay_cnt == 'd1000) begin relay_l3 <= {i_freq_relay4[10],i_freq_relay4[11],i_freq_relay4[12],i_freq_relay4[13],i_freq_relay4[14],i_freq_relay4[15],i_freq_relay4[16],i_freq_relay4[17],24'd0}; end else if (delay_cnt == 'd1080) begin exec_flag <= 'd0; exec_done_flag <= 1'b1; end if ((freq_relay4 > 64) & (freq_relay4 < 73)) begin OC_x09 <= 4'b1000; end else if ((freq_relay4 > 192) & (freq_relay4 < 201)) begin OC_x25 <= 4'b1000; end else begin OC_x09 <= 'd0; OC_x25 <= 'd0; end end default: begin OC_x09 <= 4'b0000; OC_x25 <= 4'b0000; end endcase end else if (dc_t == 1'b1) begin case (dc_slot_flag) 4'b0001: begin //Sanity Check if ((i_DC_Con1[21:17] < 1) || (i_DC_Con1[21:17] > 18) || (i_DC_Con1[9:1] < 1) || (i_DC_Con1[9:1] > 256)) begin err_flag <= 1'b1; end else begin if (i_DC_Con1[23] == 1'b0) begin //Select PMU //Parsing Channel //We need Speacial Handling for tthe "freq" channels PMU_OC_1 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)< 18) || (i_DC_Con2[9:1] < 1) || (i_DC_Con2[9:1] > 256)) begin err_flag <= 1'b1; end else begin if (i_DC_Con2[23] == 1'b0) begin //Select PMU PMU_OC_2 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)< 18) || (i_DC_Con3[9:1] < 1) || (i_DC_Con3[9:1] > 256)) begin err_flag <= 1'b1; end else begin if (i_DC_Con3[23] == 1'b0) begin //Select PMU PMU_OC_3 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)< 18) || (i_DC_Con4[9:1] < 1) || (i_DC_Con4[9:1] > 256)) begin err_flag <= 1'b1; end else begin if (i_DC_Con4[23] == 1'b0) begin //Select PMU PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<