// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.13.0.56.2 // ldbanno -n Verilog -o NewExtIns_CPLD1_impl1_mapvo.vo -w -neg -gui -msgset C:/Users/testrong/Documents/Work/NewInstrCalBoard/2.FW/CPLD/CPLD1/promote.xml NewExtIns_CPLD1_impl1_map.ncd // Netlist created on Thu Jun 18 10:43:06 2026 // Netlist written on Thu Jun 18 10:43:15 2026 // Design is for device LCMXO2-7000HC // Design is for package FPBGA484 // Design is for performance grade 4 `timescale 1 ns / 1 ps module RelayConTop ( i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, o_miso, i_rready, i_wvalid, o_wready, o_err, o_con_done, o_DMM_EN, o_IO_RC1, o_RC_T27, o_RC_T28, o_RC_T29, o_RC_T30, o_RC_T31, o_RC_T32, o_RC_RLSel, o_RC_VSel, o_RC_ISel, o_RC_LOF, o_RC_LOS, o_FMC, o_SMC, o_FMMC, o_SMMC, o_DPSF_RC1, o_DPSS_RC1, o_PMU_OC_1, o_PMU_OC_2, o_PMU_OC_3, o_PMU_OC_4, o_DPS_F_1, o_DPS_S_1, o_DPS_F_2, o_DPS_S_2, o_DPS_F_3, o_DPS_S_3, o_DPS_F_4, o_DPS_S_4 ); input i_sys_clk, i_rst_n, i_sclk, i_mosi, i_cs, i_rready, i_wvalid; output o_miso, o_wready, o_err, o_con_done; output [18:0] o_DMM_EN; output o_IO_RC1, o_RC_T27, o_RC_T28, o_RC_T29, o_RC_T30, o_RC_T31, o_RC_T32; output [17:0] o_RC_RLSel; output o_RC_VSel, o_RC_ISel; output [1:0] o_RC_LOF; output [1:0] o_RC_LOS; output [3:0] o_FMC; output [3:0] o_SMC; output [5:0] o_FMMC; output [5:0] o_SMMC; output o_DPSF_RC1, o_DPSS_RC1; output [15:0] o_PMU_OC_1; output [15:0] o_PMU_OC_2; output [15:0] o_PMU_OC_3; output [15:0] o_PMU_OC_4; output [15:0] o_DPS_F_1; output [15:0] o_DPS_S_1; output [15:0] o_DPS_F_2; output [15:0] o_DPS_S_2; output [15:0] o_DPS_F_3; output [15:0] o_DPS_S_3; output [15:0] o_DPS_F_4; output [15:0] o_DPS_S_4; wire \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[157] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[156] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i , jtaghub16_jtck, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[156] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[157] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[146] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[145] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[145] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[146] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[144] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[143] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[143] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[144] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[155] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[154] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[154] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[155] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[153] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[152] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[152] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[153] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[151] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[150] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[150] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[151] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[149] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[149] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[148] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[147] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[147] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[148] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[142] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[141] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[141] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[142] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] , \w_data[16] , \w_data[15] , \CPLD_Reg_1/regtable[7]_1_sqmuxa , i_rst_n_c, i_sys_clk_c, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[7] , \DC_Con2[15] , \DC_Con2[16] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] , \w_data[14] , \w_data[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[5] , \DC_Con2[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[6] , \DC_Con2[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] , \w_data[12] , \w_data[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[3] , \DC_Con2[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[4] , \DC_Con2[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] , \w_data[10] , \w_data[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[1] , \DC_Con2[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[2] , \DC_Con2[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] , \w_data[9] , \w_data[8] , \CPLD_Reg_1/regtable[6]_1_sqmuxa , \DC_Con1[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[0] , \DC_Con1[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] , \CPLD_Reg_1/regtable[9]_1_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[9] , \DC_Con4[13] , \DC_Con4[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[7] , \DC_Con4[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[8] , \DC_Con4[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[5] , \DC_Con4[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[6] , \DC_Con4[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] , \CPLD_Reg_1/regtable[8]_1_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[3] , \DC_Con3[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[4] , \DC_Con3[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] , \w_data[7] , \w_data[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[1] , \DC_Con3[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[2] , \DC_Con3[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] , \w_data[5] , \w_data[4] , \DC_Con3[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[0] , \DC_Con3[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] , \w_data[3] , \w_data[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[9] , \DC_Con4[2] , \DC_Con4[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] , \w_data[23] , \w_data[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[7] , \DC_Con4[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[8] , \DC_Con4[23] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] , \w_data[21] , \w_data[20] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[5] , \DC_Con4[20] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[6] , \DC_Con4[21] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] , \w_data[1] , \w_data[19] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[3] , \DC_Con4[19] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[4] , \DC_Con4[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] , \w_data[18] , \w_data[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[1] , \DC_Con4[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[2] , \DC_Con4[18] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] , \DC_Con4[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[0] , \DC_Con4[16] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] , \xo2chub/bit_count[0] , \xo2chub/bit_count15 , \xo2chub/bit_count , \xo2chub/bit_count_s[0] , jtaghub16_jrstn, \xo2chub/bit_count_cry[0] , \xo2chub/id_enable , \xo2chub/rom_dout , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[18] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[189] , \xo2chub/jtdo2_int_prm_2_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[189] , \xo2chub/jtdo2_int , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] , jtaghub16_ip_enable0, jtaghub16_er2_tdo0, \xo2chub/ip_enable[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[191] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[190] , \xo2chub/jtdo2_int_prm_4_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[190] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[191] , \xo2chub/ip_enable[2] , \xo2chub/ip_enable[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[193] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[192] , \xo2chub/jtdo2_int_prm_6_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[192] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[193] , \xo2chub/ip_enable[4] , \xo2chub/ip_enable[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[195] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[194] , \xo2chub/jtdo2_int_prm_8_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[194] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[195] , \xo2chub/ip_enable[6] , \xo2chub/ip_enable[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[197] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[196] , \xo2chub/jtdo2_int_prm_10_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[196] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[197] , \xo2chub/ip_enable[8] , \xo2chub/ip_enable[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[182] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[181] , \xo2chub/jtdo2_int_prm_12_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[181] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[182] , \xo2chub/ip_enable[10] , \xo2chub/ip_enable[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[184] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[183] , \xo2chub/jtdo2_int_prm_14_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[183] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[184] , \xo2chub/ip_enable[12] , \xo2chub/ip_enable[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[186] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[185] , \xo2chub/jtdo2_int_prm_16_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[185] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[186] , \xo2chub/ip_enable[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[188] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[187] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[187] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[188] , \xo2chub/rom_rd_addr[7] , jtaghub16_jshift, \xo2chub/rom_rd_addr_s[7] , \xo2chub/rom_rd_addr_cry[6] , \xo2chub/rom_rd_addr[6] , \xo2chub/rom_rd_addr[5] , \xo2chub/rom_rd_addr_s[6] , \xo2chub/rom_rd_addr_s[5] , \xo2chub/rom_rd_addr_cry[4] , \xo2chub/rom_rd_addr[4] , \xo2chub/rom_rd_addr[3] , \xo2chub/rom_rd_addr_s[4] , \xo2chub/rom_rd_addr_s[3] , \xo2chub/rom_rd_addr_cry[2] , \xo2chub/rom_rd_addr[2] , \xo2chub/rom_rd_addr[1] , \xo2chub/rom_rd_addr_s[2] , \xo2chub/rom_rd_addr_s[1] , \xo2chub/rom_rd_addr_cry[0] , \xo2chub/rom_rd_addr[0] , \xo2chub/rom_rd_addr_s[0] , \xo2chub/bit_count[4] , \xo2chub/bit_count[3] , \xo2chub/bit_count_s[4] , \xo2chub/bit_count_s[3] , \xo2chub/bit_count_cry[2] , \xo2chub/bit_count[2] , \xo2chub/bit_count[1] , \xo2chub/bit_count_s[2] , \xo2chub/bit_count_s[1] , \CPLD_Con_1/N_374 , \CPLD_Con_1/g1_0 , \CPLD_Con_1/g0_0_1 , \CPLD_Con_1/PMU_OC_1_4_sqmuxa , \BUS_Con_1.cs_sync[0] , i_rst_n_c_i_set, \BUS_Con_1.cs_sync_rep0[1] , io_RC9_RNID445E, \BUS_Con_1.sclk_sync[0] , \BUS_Con_1/sclk_sync[1] , \BUS_Con_1/bit_cnt[0] , \BUS_Con_1/bit_cnt[1] , \BUS_Con_1/bit_cnt_6[1] , \BUS_Con_1/bit_cnt_6[0] , \BUS_Con_1/cs_sync_RNI4H6C_0[1] , \BUS_Con_1/un1_bit_cnt_7_c3 , \BUS_Con_1/bit_cnt[3] , \BUS_Con_1/sclk_rise , \BUS_Con_1/bit_cnt[2] , \BUS_Con_1/bit_cnt_6[3] , \BUS_Con_1/bit_cnt_6[2] , \BUS_Con_1/bit_cnt[5] , \BUS_Con_1/bit_cnt[4] , \BUS_Con_1/bit_cnt_6[5] , \BUS_Con_1/bit_cnt_6[4] , \BUS_Con_1/state[1] , \BUS_Con_1/state[0] , \BUS_Con_1/data_ready_0_sqmuxa_1 , \BUS_Con_1/cs_sync[1] , \BUS_Con_1/un1_err_flag8 , \BUS_Con_1/data_ready_en_0 , \BUS_Con_1/data_ready , \BUS_Con_1/miso_shift17lt3 , \BUS_Con_1/miso_shift9_2 , \BUS_Con_1/miso_shift9_1 , \BUS_Con_1/miso_loaded , \BUS_Con_1/miso_loaded_0_sqmuxa , \BUS_Con_1/fb_0 , \r_data[1] , \BUS_Con_1/miso_shift17lto5_i_o2 , \BUS_Con_1/miso_shift[8] , \r_data[0] , \BUS_Con_1/miso_shift_8[9] , \BUS_Con_1/miso_shift_8[8] , \BUS_Con_1/miso_shift_1_sqmuxa_i_0 , \BUS_Con_1/miso_shift[9] , \r_data[3] , \BUS_Con_1/miso_shift[10] , \r_data[2] , \BUS_Con_1/miso_shift_8[11] , \BUS_Con_1/miso_shift_8[10] , \BUS_Con_1/miso_shift[11] , \r_data[5] , \BUS_Con_1/miso_shift[12] , \r_data[4] , \BUS_Con_1/miso_shift_8[13] , \BUS_Con_1/miso_shift_8[12] , \BUS_Con_1/miso_shift[13] , \r_data[7] , \BUS_Con_1/miso_shift[14] , \r_data[6] , \BUS_Con_1/miso_shift_8[15] , \BUS_Con_1/miso_shift_8[14] , \BUS_Con_1/miso_shift[15] , \r_data[9] , \BUS_Con_1/miso_shift[16] , \r_data[8] , \BUS_Con_1/miso_shift_8[17] , \BUS_Con_1/miso_shift_8[16] , \BUS_Con_1/miso_shift[17] , \r_data[11] , \BUS_Con_1/miso_shift[18] , \r_data[10] , \BUS_Con_1/miso_shift_8[19] , \BUS_Con_1/miso_shift_8[18] , \BUS_Con_1/miso_shift[19] , \r_data[13] , \BUS_Con_1/miso_shift[20] , \r_data[12] , \BUS_Con_1/miso_shift_8[21] , \BUS_Con_1/miso_shift_8[20] , \BUS_Con_1/miso_shift[21] , \r_data[15] , \BUS_Con_1/miso_shift[22] , \r_data[14] , \BUS_Con_1/miso_shift_8[23] , \BUS_Con_1/miso_shift_8[22] , \BUS_Con_1/miso_shift[23] , \r_data[17] , \BUS_Con_1/miso_shift[24] , \r_data[16] , \BUS_Con_1/miso_shift_8[25] , \BUS_Con_1/miso_shift_8[24] , \BUS_Con_1/miso_shift[25] , \r_data[19] , \BUS_Con_1/miso_shift[26] , \r_data[18] , \BUS_Con_1/miso_shift_8[27] , \BUS_Con_1/miso_shift_8[26] , \BUS_Con_1/miso_shift[27] , \r_data[21] , \BUS_Con_1/miso_shift[28] , \r_data[20] , \BUS_Con_1/miso_shift_8[29] , \BUS_Con_1/miso_shift_8[28] , \BUS_Con_1/miso_shift[29] , \r_data[22] , \BUS_Con_1/miso_shift_8[30] , \BUS_Con_1/miso_shift[30] , \BUS_Con_1/N_497 , reg_busy, \BUS_Con_1/N_504 , \BUS_Con_1/N_495 , \BUS_Con_1/state_nss[1] , \BUS_Con_1/state_nss[0] , \DC_Con3[0] , \DC_Con1[0] , \CPLD_Con_1/SUM1_0 , \CPLD_Con_1/SUM0_0 , \CPLD_Con_1/dc_t[0] , \CPLD_Con_1/dc_t[1] , \CPLD_Con_1/un1_en_t_c2 , \CPLD_Con_1/CO1_0 , \CPLD_Con_1/CO1 , \CPLD_Con_1/SUM1 , \CPLD_Con_1/SUM0 , \CPLD_Con_1/un1_en_t[2] , \CPLD_Con_1/un1_en_t[1] , \CPLD_Con_1/en_t[1] , \CPLD_Con_1/en_t[2] , \CPLD_Con_1/un1_en_t[3] , \CPLD_Con_1/en_t[3] , \CPLD_Con_1/RC_VSel40 , \CPLD_Con_1/dc_slot_flag_1_sqmuxa , \CPLD_Con_1/RC_Tx_1_sqmuxa , \CPLD_Con_1/N_247 , o_con_done_c, \CPLD_Con_1/exec_flag , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_a2_3_0 , \CPLD_Con_1/un1_i_DC_Con1_2 , \CPLD_Con_1/PMU_OC_1_0_sqmuxa , \CPLD_Con_1/RC_Tx_1_sqmuxa_fast , \CPLD_Con_1/exec_flag_fast , \CPLD_Con_1/N_331 , \CPLD_Con_1/un4_DPS_FS_4_axbxc7 , \CPLD_Con_1/un4_DPS_FS_4_axbxc6 , \CPLD_Con_1/RC_Tx_1_sqmuxa_1 , \CPLD_Con_1/RC_Tx_1_sqmuxa_rep1 , \CPLD_Con_1/exec_flag_rep1 , \CPLD_Con_1/N_122 , \freq4_relay[0] , \freq3_relay[0] , \freq2_relay[0] , \freq1_relay[0] , \CPLD_Con_1/freq_t[0] , \CPLD_Con_1/freq_t[1] , \reg_addr[6] , \reg_addr[5] , \reg_addr[4] , \CPLD_Reg_1/N_1133 , con_exec, cmd_valid, \CPLD_Reg_1/state[0] , \CPLD_Reg_1/err_flag8 , \CPLD_Reg_1/N_814 , \CPLD_Reg_1/un9_0 , \CPLD_Reg_1/reg_err_flag , \CPLD_Reg_1/state[1] , \CPLD_Reg_1/regtable[1][23] , \CPLD_Reg_1/N_1059_i , \CPLD_Reg_1/un10_i_0 , \CPLD_Reg_1/N_26 , \CPLD_Reg_1/N_23 , \CPLD_Reg_1/N_22 , \CPLD_Reg_1/state_ns[1] , \CPLD_Reg_1/state_ns[0] , \CPLD_Con_1/N_332 , \CPLD_Con_1/N_249 , \CPLD_Con_1/DMM_en_26_0_a3_0_3[1] , \CPLD_Con_1/un1_i_DC_Con1[1] , \CPLD_Con_1/PMU_OC_1_cnst[0] , \CPLD_Con_1/N_1_11 , \CPLD_Con_1/DMM_en_26[1] , \CPLD_Con_1/DMM_en_26[0] , \CPLD_Con_1/DMM_en_0_sqmuxa_5_i , \DMM_EN[0] , \DMM_EN[1] , \CPLD_Con_1/DMM_en_26_0_a3_0_0[3] , \CPLD_Con_1/DMM_en_cnst[2] , \CPLD_Con_1/DMM_en_26[3] , \CPLD_Con_1/DMM_en_26[2] , \DMM_EN[2] , \DMM_EN[3] , \CPLD_Con_1/N_5_11 , \CPLD_Con_1/DMM_en_cnst[6] , \CPLD_Con_1/DMM_en_cnst[4] , \CPLD_Con_1/DMM_en_26[6] , \CPLD_Con_1/DMM_en_26[4] , \DMM_EN[4] , \DMM_EN[6] , \DC_Con2[9] , \CPLD_Con_1/un1_i_DC_Con2_1_0 , \CPLD_Con_1/PMU_OC_212 , \CPLD_Con_1/PMU_OC_2_cnst_1[16] , \CPLD_Con_1/un1_i_DC_Con1[0] , \CPLD_Con_1/dc_slot_flag[1] , \CPLD_Con_1/DMM_en_26[5] , \DMM_EN[5] , \CPLD_Con_1/un1_i_DC_Con2_1lt8 , \CPLD_Con_1/DMM_en_26[7] , \DMM_EN[7] , \CPLD_Con_1/N_416 , \CPLD_Con_1/PMU_OC_313 , \CPLD_Con_1/DMM_en_26_0_a2_0[9] , \CPLD_Con_1/N_351 , \CPLD_Con_1/DMM_en_26_0_a2_0[8] , \CPLD_Con_1/DMM_en_26[9] , \CPLD_Con_1/DMM_en_26[8] , \DMM_EN[8] , \DMM_EN[9] , \CPLD_Con_1/N_354 , \CPLD_Con_1/DMM_en_26_0_a2_0[11] , \CPLD_Con_1/N_349 , \CPLD_Con_1/DMM_en_26_0_a2_0[10] , \CPLD_Con_1/DMM_en_26[11] , \CPLD_Con_1/DMM_en_26[10] , \DMM_EN[10] , \DMM_EN[11] , \CPLD_Con_1/N_51 , \CPLD_Con_1/DMM_en_26_0_a3_1_0[14] , \CPLD_Con_1/N_134 , \CPLD_Con_1/DMM_en_26_0_a3_2[12] , \CPLD_Con_1/DMM_en_26[14] , \CPLD_Con_1/DMM_en_26[12] , \DMM_EN[12] , \DMM_EN[14] , \CPLD_Con_1/dc_slot_flag[3] , \CPLD_Con_1/DMM_en_26_0_a4_0[13] , \CPLD_Con_1/DMM_en_26_0_a4_1_1_0[13] , \CPLD_Con_1/PMU_OC_4_1_sqmuxa , \CPLD_Con_1/N_59 , \CPLD_Con_1/DMM_en_26[13] , \CPLD_Con_1/N_274 , \DMM_EN[13] , \CPLD_Con_1/DMM_en_26_i_1[15] , \CPLD_Con_1/N_273 , \CPLD_Con_1/N_46_i , \DMM_EN[15] , DPSFS_RC1, \CPLD_Con_1/un1_RC_VSel41_1_0_a2 , \CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1 , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_0 , \CPLD_Con_1/DPSFS_RC1e_1 , \CPLD_Con_1/DPSFS_RC1e_0 , \BUS_Con_1.mosi_sync[0] , \BUS_Con_1/mosi_sync[1] , \CPLD_Con_1/N_153 , \DC_Con1[1] , \CPLD_Con_1/un3_DPS_FS_1_axbxc3 , \CPLD_Con_1/un3_DPS_FS_1_axbxc2 , \DC_Con1[4] , \CPLD_Con_1/N_146_i , \CPLD_Con_1/N_145_i , \CPLD_Con_1/N_28 , \DPS_FS_1[0] , \DPS_FS_1[1] , \CPLD_Con_1/N_154 , \CPLD_Con_1/N_138_i , \CPLD_Con_1/N_137_i , \DPS_FS_1[2] , \DPS_FS_1[3] , \CPLD_Con_1/N_140_i , \CPLD_Con_1/N_139_i , \DPS_FS_1[4] , \DPS_FS_1[5] , \CPLD_Con_1/N_142_i , \CPLD_Con_1/N_141_i , \DPS_FS_1[6] , \DPS_FS_1[7] , \CPLD_Con_1/N_144_i , \CPLD_Con_1/N_143_i , \DPS_FS_1[8] , \DPS_FS_1[9] , \CPLD_Con_1/N_124_i , \CPLD_Con_1/N_120_i , \DPS_FS_1[10] , \DPS_FS_1[11] , \CPLD_Con_1/N_129_i , \CPLD_Con_1/N_125_i , \DPS_FS_1[12] , \DPS_FS_1[13] , \CPLD_Con_1/N_136_i , \CPLD_Con_1/N_130_i , \DPS_FS_1[14] , \DPS_FS_1[15] , \CPLD_Con_1/N_406 , \DC_Con2[3] , \DC_Con2[2] , \DC_Con2[1] , \CPLD_Con_1/N_291_i , \CPLD_Con_1/N_290_i , \CPLD_Con_1/N_26 , \DPS_FS_2[0] , \DPS_FS_2[1] , \CPLD_Con_1/N_293_i , \CPLD_Con_1/N_292_i , \DPS_FS_2[2] , \DPS_FS_2[3] , \CPLD_Con_1/N_279_i , \CPLD_Con_1/N_294_i , \DPS_FS_2[4] , \DPS_FS_2[5] , \CPLD_Con_1/N_281_i , \CPLD_Con_1/N_280_i , \DPS_FS_2[6] , \DPS_FS_2[7] , \CPLD_Con_1/N_407 , \CPLD_Con_1/N_283_i , \CPLD_Con_1/N_282_i , \DPS_FS_2[8] , \DPS_FS_2[9] , \CPLD_Con_1/N_285_i , \CPLD_Con_1/N_284_i , \DPS_FS_2[10] , \DPS_FS_2[11] , \CPLD_Con_1/N_287_i , \CPLD_Con_1/N_286_i , \DPS_FS_2[12] , \DPS_FS_2[13] , \CPLD_Con_1/N_289_i , \CPLD_Con_1/N_288_i , \DPS_FS_2[14] , \DPS_FS_2[15] , \CPLD_Con_1/N_392 , \CPLD_Con_1/N_220 , \CPLD_Con_1/N_169 , \CPLD_Con_1/un4_DPS_FS_3_axbxc3 , \CPLD_Con_1/DPS_FS_3_9_i_a2_4[0] , \CPLD_Con_1/DPS_FS_3_9_i_a2_1[0] , \CPLD_Con_1/N_329_i , \CPLD_Con_1/N_183_i , \CPLD_Con_1/N_24 , \DPS_FS_3[0] , \DPS_FS_3[1] , \CPLD_Con_1/N_240 , \CPLD_Con_1/N_67_0 , \CPLD_Con_1/N_312_i , \CPLD_Con_1/N_330_i , \DPS_FS_3[2] , \DPS_FS_3[3] , \CPLD_Con_1/N_219 , \CPLD_Con_1/N_69_0 , \CPLD_Con_1/N_315_i , \CPLD_Con_1/N_314_i , \DPS_FS_3[4] , \DPS_FS_3[5] , \CPLD_Con_1/N_241 , \CPLD_Con_1/N_71_0 , \CPLD_Con_1/N_317_i , \CPLD_Con_1/N_316_i , \DPS_FS_3[6] , \DPS_FS_3[7] , \CPLD_Con_1/DPS_FS_3_9_i_a2_0[8] , \CPLD_Con_1/N_178_i , \CPLD_Con_1/N_176_i , \DPS_FS_3[8] , \DPS_FS_3[9] , \CPLD_Con_1/N_180_i , \CPLD_Con_1/N_318_i , \DPS_FS_3[10] , \DPS_FS_3[11] , \CPLD_Con_1/N_173_i , \CPLD_Con_1/N_319_i , \DPS_FS_3[12] , \DPS_FS_3[13] , \CPLD_Con_1/N_174_i , \CPLD_Con_1/N_305_i , \DPS_FS_3[14] , \DPS_FS_3[15] , \CPLD_Con_1/N_408 , \CPLD_Con_1/un4_DPS_FS_4_axbxc3 , \CPLD_Con_1/un4_DPS_FS_4_axbxc2 , \DC_Con4[4] , \CPLD_Con_1/N_307_i , \CPLD_Con_1/N_306_i , \CPLD_Con_1/un1_exec_flag_10_i_0 , \DPS_FS_4[0] , \DPS_FS_4[1] , \CPLD_Con_1/N_409 , \CPLD_Con_1/N_309_i , \CPLD_Con_1/N_308_i , \DPS_FS_4[2] , \DPS_FS_4[3] , \CPLD_Con_1/N_311_i , \CPLD_Con_1/N_310_i , \DPS_FS_4[4] , \DPS_FS_4[5] , \CPLD_Con_1/N_296_i , \CPLD_Con_1/N_295_i , \DPS_FS_4[6] , \DPS_FS_4[7] , \CPLD_Con_1/N_298_i , \CPLD_Con_1/N_297_i , \DPS_FS_4[8] , \DPS_FS_4[9] , \CPLD_Con_1/N_300_i , \CPLD_Con_1/N_299_i , \DPS_FS_4[10] , \DPS_FS_4[11] , \CPLD_Con_1/N_302_i , \CPLD_Con_1/N_301_i , \DPS_FS_4[12] , \DPS_FS_4[13] , \CPLD_Con_1/N_304_i , \CPLD_Con_1/N_303_i , \DPS_FS_4[14] , \DPS_FS_4[15] , \FSMC[1] , \CPLD_Con_1/RC_VSel39 , \CPLD_Con_1/DPS_FSMMCe_1_0[5] , \FSMC[0] , \CPLD_Con_1/RC_VSel38 , \CPLD_Con_1/DPS_FSMCd_0[1] , \CPLD_Con_1/DPS_FSMCd_0[0] , \FSMC[3] , \CPLD_Con_1/DPS_FSMC_RNO_0[3] , \FSMC[2] , \CPLD_Con_1/DPS_FSMCd_0[3] , \CPLD_Con_1/DPS_FSMCd_0[2] , \FSMMC[5] , \CPLD_Con_1/DPS_FSMMCe_N_2L1 , \FSMMC[4] , \CPLD_Con_1/DPS_FSMMCe_1[4] , \CPLD_Con_1/DPS_FSMMCe_0[5] , \CPLD_Con_1/DPS_FSMMCe_0[4] , \CPLD_Con_1/N_65 , \CPLD_Con_1/N_41 , \CPLD_Con_1/RC_RLSel_13_0_iv_1[1] , \CPLD_Con_1/N_80 , \CPLD_Con_1/N_73 , \CPLD_Con_1/un20_RC_RLSel_m[0] , \CPLD_Con_1/RC_RLSel_13_0_iv_i_1[0] , \CPLD_Con_1/RC_RLSel_13_0_iv_i[1] , \CPLD_Con_1/RC_RLSel_13_0_iv_i[0] , \CPLD_Con_1/un1_exec_flag_1_i , \RC_RLSel[0] , \RC_RLSel[1] , \CPLD_Con_1/N_45 , \CPLD_Con_1/un20_RC_RLSel_m[3] , \CPLD_Con_1/RC_RLSel_13_0_iv_0[3] , \CPLD_Con_1/un95_RC_RLSel_m[2] , \CPLD_Con_1/un70_RC_RLSel_m[2] , \CPLD_Con_1/un45_RC_RLSel_m[2] , \CPLD_Con_1/un20_RC_RLSel_m[2] , \CPLD_Con_1/RC_RLSel_13_0_iv_i[3] , \CPLD_Con_1/RC_RLSel_13_0_iv_i[2] , \RC_RLSel[2] , \RC_RLSel[3] , \CPLD_Con_1/un70_RC_RLSel_m[5] , \CPLD_Con_1/un20_RC_RLSel_m[5] , \CPLD_Con_1/RC_RLSel_13_iv_1[5] , \CPLD_Con_1/N_48 , \CPLD_Con_1/N_43 , \CPLD_Con_1/un20_RC_RLSel_m[4] , \CPLD_Con_1/RC_RLSel_13_iv_1[4] , \CPLD_Con_1/RC_RLSel_13_iv_i[5] , \CPLD_Con_1/RC_RLSel_13_iv_i[4] , \RC_RLSel[4] , \RC_RLSel[5] , \CPLD_Con_1/N_64 , \CPLD_Con_1/un20_RC_RLSel_m[7] , \CPLD_Con_1/RC_RLSel_13_iv_1[7] , \CPLD_Con_1/N_81 , \CPLD_Con_1/un95_RC_RLSel_m[6] , \CPLD_Con_1/RC_RLSel_13_iv_i_1[6] , \CPLD_Con_1/RC_RLSel_13_iv_i[7] , \CPLD_Con_1/RC_RLSel_13_iv_i[6] , \RC_RLSel[6] , \RC_RLSel[7] , \CPLD_Con_1/N_47 , \CPLD_Con_1/un20_RC_RLSel_m[9] , \CPLD_Con_1/RC_RLSel_13_iv_1[9] , \CPLD_Con_1/N_66 , \CPLD_Con_1/un20_RC_RLSel_m[8] , \CPLD_Con_1/RC_RLSel_13_iv_1[8] , \CPLD_Con_1/RC_RLSel_13_iv_i[9] , \CPLD_Con_1/RC_RLSel_13_iv_i[8] , \RC_RLSel[8] , \RC_RLSel[9] , \CPLD_Con_1/un20_RC_RLSel_m[11] , \CPLD_Con_1/RC_RLSel_13_iv_1[11] , \CPLD_Con_1/un20_RC_RLSel_m[10] , \CPLD_Con_1/RC_RLSel_13_iv_1[10] , \CPLD_Con_1/RC_RLSel_13_iv_i[11] , \CPLD_Con_1/RC_RLSel_13_iv_i[10] , \RC_RLSel[10] , \RC_RLSel[11] , \CPLD_Con_1/un20_RC_RLSel_m[13] , \CPLD_Con_1/RC_RLSel_13_iv_1[13] , \CPLD_Con_1/un20_RC_RLSel_m[12] , \CPLD_Con_1/RC_RLSel_13_iv_1[12] , \CPLD_Con_1/RC_RLSel_13_iv_i[13] , \CPLD_Con_1/RC_RLSel_13_iv_i[12] , \RC_RLSel[12] , \RC_RLSel[13] , \CPLD_Con_1/un20_RC_RLSel_m[15] , \CPLD_Con_1/RC_RLSel_13_iv_1[15] , \CPLD_Con_1/un20_RC_RLSel_m[14] , \CPLD_Con_1/RC_RLSel_13_iv_1[14] , \CPLD_Con_1/RC_RLSel_13_iv_i[15] , \CPLD_Con_1/RC_RLSel_13_iv_i[14] , \RC_RLSel[14] , \RC_RLSel[15] , \CPLD_Con_1/un70_RC_RLSel_m[17] , \CPLD_Con_1/un45_RC_RLSel_m[17] , \CPLD_Con_1/RC_RLSel_13_iv_1[17] , \CPLD_Con_1/un70_RC_RLSel_m[16] , \CPLD_Con_1/un45_RC_RLSel_m[16] , \CPLD_Con_1/RC_RLSel_13_iv_1[16] , \CPLD_Con_1/RC_RLSel_13_iv_i[17] , \CPLD_Con_1/RC_RLSel_13_iv_i[16] , \RC_RLSel[16] , \RC_RLSel[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_65 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast , jtaghub16_jce2, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4360 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk_3[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_57 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3_1[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_2_m_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker , jtaghub16_jtdi, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4323_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_48_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_909 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_893 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_941 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_925 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_973 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_957 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1005 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_989 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1037 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1021 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1069 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1053 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1101 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1085 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1133 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1117 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1165 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1149 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1197 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1181 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1229 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1213 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1261 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1245 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1293 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1277 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1325 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1309 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1357 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1341 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1389 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1373 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1421 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1405 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1453 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1437 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1485 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1469 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1517 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1501 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1549 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1533 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1581 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1565 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1613 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1597 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1645 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1629 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[47] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1677 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1661 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[49] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[48] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1709 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1693 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[51] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[50] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1741 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1725 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[53] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[52] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1773 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1757 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[55] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[54] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1805 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1789 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[57] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[56] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1837 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1821 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[59] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[58] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1869 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1853 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[61] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[60] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1901 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1885 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[63] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[62] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1933 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1917 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[65] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[64] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1965 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1949 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[67] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[66] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1997 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1981 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[69] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[68] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[69] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2029 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2013 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[71] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[70] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2061 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2045 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[73] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[72] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2093 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2077 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[75] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[74] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2125 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2109 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[77] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[76] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2157 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2141 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[79] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[78] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2189 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2173 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[81] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[80] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2221 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2205 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[83] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[82] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2253 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2237 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[85] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[84] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2285 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2269 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[87] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[86] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2317 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2301 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[89] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[88] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2349 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2333 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[91] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[90] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2381 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2365 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[93] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[92] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2413 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2397 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[95] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[94] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2445 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2429 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[97] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[96] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2477 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2461 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[99] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[98] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2509 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2493 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[101] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[100] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2541 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2525 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[103] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[102] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2573 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2557 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[105] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[104] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2605 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2589 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[107] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[106] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2637 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2621 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[109] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[108] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2669 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2653 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[111] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[110] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2701 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2685 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[113] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[112] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2733 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2717 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[115] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[114] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2765 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2749 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[117] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[116] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2797 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2781 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[119] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[118] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2829 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2813 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[121] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[120] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2861 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2845 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[123] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[122] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2893 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2877 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[125] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[124] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2925 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2909 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[127] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[126] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2957 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2941 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[129] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[128] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2989 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2973 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[131] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[130] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3021 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3005 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[133] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[132] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3053 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3037 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[135] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[134] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3085 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3069 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[137] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[136] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[140] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3117 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[139] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3101 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[139] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[139] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3149 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3133 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[141] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[140] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[140] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[141] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3181 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3165 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[143] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[142] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[142] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[143] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3213 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3197 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[145] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[144] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[144] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[145] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3245 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3229 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[147] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[146] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[146] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[147] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3277 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3261 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[149] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[148] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[148] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[149] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3309 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3293 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[151] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[150] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[150] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[151] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3341 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3325 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[153] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[152] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[152] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[153] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3373 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3357 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[155] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[154] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[154] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[155] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[158] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3405 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3389 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[157] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[156] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[156] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[157] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[160] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3437 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[159] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3421 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[159] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[158] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[158] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[159] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[162] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3469 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[161] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3453 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[161] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[160] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[160] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[161] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[164] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3501 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[163] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3485 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[163] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[162] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[162] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[163] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[166] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3533 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[165] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3517 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[165] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[164] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[164] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[165] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[168] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3565 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[167] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3549 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[167] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[166] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[166] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[167] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[170] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3597 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[169] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3581 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[169] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[168] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[168] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[169] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[172] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3629 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[171] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3613 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[171] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[170] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[170] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[171] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[174] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3661 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[173] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3645 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[173] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[172] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[172] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[173] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[176] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3693 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[175] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3677 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[175] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[174] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[174] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[175] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[178] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3725 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[177] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3709 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[177] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[176] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[176] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[177] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[180] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3757 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[179] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3741 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[179] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[178] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[178] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[179] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3789 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3773 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[181] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[180] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[180] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[181] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3821 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3805 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[183] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[182] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[182] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[183] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3853 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3837 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[185] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[184] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[184] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[185] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3885 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3869 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[187] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[186] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[186] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[187] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3917 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3901 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[189] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[188] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[188] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[189] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3949 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3933 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[191] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[190] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[190] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[191] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3981 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3965 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[193] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[192] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[192] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[193] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4013 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3997 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[195] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[194] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[194] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[195] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[198] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4045 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4029 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[197] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[196] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[196] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[197] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[200] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4077 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[199] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4061 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[199] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[198] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[198] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[199] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[202] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4109 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[201] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4093 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[201] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[200] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[200] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[201] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[204] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4141 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[203] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4125 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[203] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[202] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[202] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[203] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[206] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4173 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[205] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4157 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[205] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[204] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[204] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[205] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[208] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4205 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[207] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4189 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[207] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[206] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[206] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[207] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_213_3774_i_m2_i_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[210] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[209] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_74 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4322_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_73 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[208] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[209] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_211_3810_i_m2_i_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[212] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_212_3792_i_m2_i_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[211] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4320_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4321_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[212] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[211] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4319_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_1[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_123_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_122_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_120_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_121_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4378_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_118_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnte , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc19_i_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_125 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_105 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_792 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_804 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_353_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_i[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_2_1_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_846 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_4 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_a2_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_388 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_380_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_1_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_844_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_843 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_1_1_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_878 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_830 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_427 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_407 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_1_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_826 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_481_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_448 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_282_1_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_253_1_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_840 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_510 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_489 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_801 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_551 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_539 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_880 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_27_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_7_i_0_a2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_655_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_39 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_a2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_649_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_9 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_0_0_a2_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_648_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_7 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_6 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_654_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/VCC\000/BUF1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen_jtck , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_653_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_652_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_651_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_8[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_27 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_26 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_39 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_90_i , \DC_Con4[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_88_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_89_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_4[2] , \DC_Con4[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_10 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_9 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_8 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_96_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_cnt_init_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_98 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_out[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4 , \DC_Con4[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_out[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_5_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_18 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_15 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_out[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] , \DC_Con1[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_end_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4370 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4368 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4412_mux , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4326_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_1[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4330 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4325_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_528 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_529 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_530 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4344 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_554 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_539 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14] , \BUS_Con_1/N_16_i , \BUS_Con_1/N_493_i , \CPLD_Reg_1/regtable[1]_RNO[0] , wr_flag, reg_addr_1_rep1, reg_addr_0_rep1, \CPLD_Reg_1/un34_regtable_1[1] , \CPLD_Reg_1/N_1067 , \CPLD_Reg_1/N_45_i , con_rvalid, \CPLD_Con_1/N_383 , \CPLD_Con_1/N_362 , \CPLD_Con_1/N_385 , \CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0_1 , \CPLD_Con_1/err_flag_en_0_o2_2 , \CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0 , \CPLD_Con_1/err_flag_en_0_a2_6_mb_mb , cpld_err_flag, \o_PMU_OC_3_c[5] , \CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 , \CPLD_Con_1/N_454 , \CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i , \o_PMU_OC_3_c[1] , \CPLD_Con_1/N_426 , \CPLD_Con_1/PMU_OC_3d_0[5] , \CPLD_Con_1/PMU_OC_3d_0[1] , \o_PMU_OC_3_c[13] , \CPLD_Con_1/N_457 , \o_PMU_OC_3_c[9] , \CPLD_Con_1/N_437 , \CPLD_Con_1/PMU_OC_3d_0[21] , \CPLD_Con_1/PMU_OC_3d_0[17] , \DC_Con3[22] , \DC_Con2[22] , \CPLD_Con_1/N_189 , \DC_Con1[22] , \CPLD_Con_1/m16_0_1 , \CPLD_Con_1/N_17_i , \CPLD_Con_1/N_205_i , o_RC_ISel_c, \CPLD_Con_1/N_193 , \CPLD_Con_1/m9_0_1 , \CPLD_Con_1/N_10_i , o_RC_VSel_c, reg_addr_3_rep1, \CPLD_Reg_1/regtable[14][0] , reg_addr_3_rep2, \CPLD_Reg_1/regtable[10][0] , \CPLD_Reg_1/rdata_reg_2[0] , \reg_addr[1] , \reg_addr_fast[2] , \CPLD_Reg_1/N_352 , \CPLD_Reg_1/N_328 , \CPLD_Reg_1/rdata_reg_1_sqmuxa , \CPLD_Reg_1/N_232 , \CPLD_Reg_1/regtable[14][1] , \CPLD_Reg_1/regtable[10][1] , \CPLD_Reg_1/regtable[2][1] , \CPLD_Reg_1/rdata_reg_2[1] , \CPLD_Reg_1/N_353 , \CPLD_Reg_1/N_329 , \CPLD_Reg_1/N_233 , \DC_Con1[2] , \CPLD_Reg_1/regtable[14][2] , \CPLD_Reg_1/regtable[10][2] , \CPLD_Reg_1/regtable[2][2] , \CPLD_Reg_1/rdata_reg_2[2] , \CPLD_Reg_1/N_354 , \CPLD_Reg_1/N_330 , \CPLD_Reg_1/N_234 , \DC_Con1[3] , \CPLD_Reg_1/regtable[14][3] , \CPLD_Reg_1/regtable[10][3] , \CPLD_Reg_1/regtable[2][3] , \CPLD_Reg_1/rdata_reg_2[3] , \CPLD_Reg_1/N_355 , \CPLD_Reg_1/N_331 , \CPLD_Reg_1/N_235 , \CPLD_Reg_1/regtable[14][4] , \CPLD_Reg_1/regtable[10][4] , \CPLD_Reg_1/regtable[2][4] , \CPLD_Reg_1/rdata_reg_2[4] , \CPLD_Reg_1/N_356 , \CPLD_Reg_1/N_332 , \CPLD_Reg_1/N_236 , \DC_Con1[5] , \CPLD_Reg_1/regtable[14][5] , \CPLD_Reg_1/regtable[10][5] , \CPLD_Reg_1/regtable[2][5] , \CPLD_Reg_1/rdata_reg_2[5] , \CPLD_Reg_1/N_357 , \CPLD_Reg_1/N_333 , \CPLD_Reg_1/N_237 , \DC_Con1[6] , \CPLD_Reg_1/regtable[14][6] , \CPLD_Reg_1/regtable[10][6] , \CPLD_Reg_1/regtable[2][6] , \CPLD_Reg_1/rdata_reg_2[6] , reg_addr_2_rep1, \CPLD_Reg_1/N_358 , \CPLD_Reg_1/N_334 , \CPLD_Reg_1/N_238 , \DC_Con1[7] , \CPLD_Reg_1/regtable[14][7] , \CPLD_Reg_1/regtable[10][7] , \CPLD_Reg_1/regtable[2][7] , \CPLD_Reg_1/rdata_reg_2[7] , \CPLD_Reg_1/N_359 , \CPLD_Reg_1/N_335 , \CPLD_Reg_1/N_239 , \CPLD_Reg_1/regtable[14][8] , \CPLD_Reg_1/regtable[10][8] , \CPLD_Reg_1/regtable[2][8] , \CPLD_Reg_1/rdata_reg_2[8] , \CPLD_Reg_1/N_360 , \CPLD_Reg_1/N_336 , \CPLD_Reg_1/N_240 , \CPLD_Reg_1/regtable[14][9] , \reg_addr[3] , \CPLD_Reg_1/regtable[10][9] , \CPLD_Reg_1/regtable[2][9] , \CPLD_Reg_1/rdata_reg_2[9] , \CPLD_Reg_1/N_361 , \CPLD_Reg_1/N_337 , \CPLD_Reg_1/N_241 , \DC_Con1[10] , \CPLD_Reg_1/regtable[14][10] , \CPLD_Reg_1/regtable[10][10] , \CPLD_Reg_1/regtable[2][10] , \CPLD_Reg_1/rdata_reg_2[10] , \CPLD_Reg_1/N_362 , \CPLD_Reg_1/N_338 , \CPLD_Reg_1/N_242 , \DC_Con1[11] , \CPLD_Reg_1/regtable[14][11] , \CPLD_Reg_1/regtable[10][11] , \CPLD_Reg_1/regtable[2][11] , \CPLD_Reg_1/rdata_reg_2[11] , \CPLD_Reg_1/N_363 , \CPLD_Reg_1/N_339 , \CPLD_Reg_1/N_243 , \DC_Con1[12] , \CPLD_Reg_1/regtable[14][12] , \CPLD_Reg_1/regtable[10][12] , \CPLD_Reg_1/regtable[2][12] , \CPLD_Reg_1/rdata_reg_2[12] , \CPLD_Reg_1/N_364 , \CPLD_Reg_1/N_340 , \CPLD_Reg_1/N_244 , \DC_Con1[13] , \CPLD_Reg_1/regtable[14][13] , \CPLD_Reg_1/regtable[10][13] , \CPLD_Reg_1/regtable[2][13] , \CPLD_Reg_1/rdata_reg_2[13] , \CPLD_Reg_1/N_365 , \CPLD_Reg_1/N_341 , \CPLD_Reg_1/N_245 , \DC_Con1[14] , \CPLD_Reg_1/regtable[14][14] , \CPLD_Reg_1/regtable[10][14] , \CPLD_Reg_1/regtable[2][14] , \CPLD_Reg_1/rdata_reg_2[14] , \CPLD_Reg_1/N_366 , \CPLD_Reg_1/N_342 , \CPLD_Reg_1/N_246 , \DC_Con1[15] , \CPLD_Reg_1/regtable[14][15] , \CPLD_Reg_1/regtable[10][15] , \CPLD_Reg_1/regtable[2][15] , \CPLD_Reg_1/rdata_reg_2[15] , \CPLD_Reg_1/N_367 , \CPLD_Reg_1/N_343 , \CPLD_Reg_1/N_247 , \DC_Con1[16] , \CPLD_Reg_1/regtable[14][16] , \CPLD_Reg_1/regtable[10][16] , \CPLD_Reg_1/regtable[2][16] , \CPLD_Reg_1/rdata_reg_2[16] , \CPLD_Reg_1/N_368 , \CPLD_Reg_1/N_344 , \CPLD_Reg_1/N_248 , \CPLD_Reg_1/regtable[14][17] , \CPLD_Reg_1/regtable[10][17] , \CPLD_Reg_1/regtable[2][17] , \CPLD_Reg_1/rdata_reg_2[17] , \CPLD_Reg_1/N_369 , \CPLD_Reg_1/N_345 , \CPLD_Reg_1/N_249 , \DC_Con1[18] , \CPLD_Reg_1/regtable[14][18] , \CPLD_Reg_1/regtable[10][18] , \CPLD_Reg_1/regtable[2][18] , \CPLD_Reg_1/rdata_reg_2[18] , \CPLD_Reg_1/N_370 , \CPLD_Reg_1/N_346 , \CPLD_Reg_1/N_250 , \DC_Con1[19] , \CPLD_Reg_1/regtable[14][19] , \CPLD_Reg_1/regtable[10][19] , \CPLD_Reg_1/regtable[2][19] , \CPLD_Reg_1/rdata_reg_2[19] , \CPLD_Reg_1/N_371 , \CPLD_Reg_1/N_347 , \CPLD_Reg_1/N_251 , \DC_Con1[20] , \CPLD_Reg_1/regtable[14][20] , \CPLD_Reg_1/regtable[10][20] , \CPLD_Reg_1/regtable[2][20] , \CPLD_Reg_1/rdata_reg_2[20] , \CPLD_Reg_1/N_372 , \CPLD_Reg_1/N_348 , \CPLD_Reg_1/N_252 , \DC_Con1[21] , \CPLD_Reg_1/regtable[14][21] , \CPLD_Reg_1/regtable[10][21] , \CPLD_Reg_1/regtable[2][21] , \CPLD_Reg_1/rdata_reg_2[21] , \CPLD_Reg_1/N_373 , \CPLD_Reg_1/N_349 , \CPLD_Reg_1/N_253 , \CPLD_Reg_1/regtable[14][22] , \CPLD_Reg_1/regtable[10][22] , \CPLD_Reg_1/regtable[2][22] , \CPLD_Reg_1/rdata_reg_2[22] , \CPLD_Reg_1/N_374 , \CPLD_Reg_1/N_350 , \CPLD_Reg_1/N_254 , \DC_Con1[23] , \CPLD_Reg_1/regtable[14][23] , \CPLD_Reg_1/regtable[10][23] , \CPLD_Reg_1/regtable[2][23] , \CPLD_Reg_1/rdata_reg_2[23] , \CPLD_Reg_1/N_375 , \CPLD_Reg_1/N_351 , \CPLD_Reg_1/N_255 , \r_data[23] , \BUS_Con_1/recv_reg[25] , \BUS_Con_1/recv_reg[1] , \BUS_Con_1/addr_out_1_sqmuxa_1 , \BUS_Con_1/recv_reg[24] , \BUS_Con_1/recv_reg[0] , \BUS_Con_1/N_479_i , \BUS_Con_1/N_480_i , \BUS_Con_1/un1_state_2_0 , \reg_addr[0] , \BUS_Con_1/recv_reg[27] , \BUS_Con_1/recv_reg[3] , \BUS_Con_1/recv_reg[26] , \BUS_Con_1/recv_reg[2] , \BUS_Con_1/N_477_i , \BUS_Con_1/N_478_i , \reg_addr[2] , \BUS_Con_1/recv_reg[29] , \BUS_Con_1/recv_reg[5] , \BUS_Con_1/recv_reg[28] , \BUS_Con_1/recv_reg[4] , \BUS_Con_1/N_475_i , \BUS_Con_1/N_476_i , \BUS_Con_1/recv_reg[30] , \BUS_Con_1/recv_reg[6] , \BUS_Con_1/N_474_i , \BUS_Con_1/N_480_i_rep2 , \BUS_Con_1/N_480_i_rep1 , reg_addr_0_rep2, \BUS_Con_1/N_479_i_rep1 , \BUS_Con_1/N_478_i_rep2 , \BUS_Con_1/N_478_i_rep1 , reg_addr_2_rep2, \BUS_Con_1/N_477_i_rep2 , \BUS_Con_1/N_477_i_rep1 , \BUS_Con_1/N_479_i_fast , \BUS_Con_1/N_480_i_fast , \reg_addr_fast[0] , \reg_addr_fast[1] , \BUS_Con_1/N_477_i_fast , \BUS_Con_1/N_478_i_fast , \reg_addr_fast[3] , \CPLD_Reg_1/busy_flag_1_i_a3_0_0 , \CPLD_Reg_1/N_44_i , \CPLD_Reg_1/state_6_d_i , \BUS_Con_1/wr_flag , \BUS_Con_1/recv_reg[31] , \BUS_Con_1/recv_reg[7] , \BUS_Con_1/data_out_0_sqmuxa , \BUS_Con_1/wr_out_8 , \xo2chub/er1_shift_reg[1] , \xo2chub/er1_shift_reg[14] , \xo2chub/er1_shift_reg[13] , jtaghub16_jupdate, \xo2chub/jtdo1_1_0 , \xo2chub/jce1_d1 , \xo2chub/er1_shift_reg[16] , \xo2chub/er1_shift_reg[15] , \xo2chub/er1_shift_reg8 , \xo2chub/id_enable_0_sqmuxa , \xo2chub/er1_shift_reg[18] , \xo2chub/er1_shift_reg[17] , GND, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat , \xo2chub/jce1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_m2_0 , \CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf1_1 , \CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf0_1 , \CPLD_Con_1/un16lto5_4_i_a2_0_0 , \CPLD_Con_1/un1_i_DC_Con3_2lto8_d , \CPLD_Reg_1/regtable[13][20] , \DC_Con3[20] , \CPLD_Reg_1/regtable[12][20] , \CPLD_Reg_1/N_324 , \CPLD_Reg_1/N_276 , \DC_Con2[20] , \CPLD_Reg_1/regtable[15][20] , \CPLD_Reg_1/regtable[11][20] , \CPLD_Reg_1/regtable[3][20] , \CPLD_Reg_1/N_300 , \CPLD_Reg_1/regtable[5][20] , \CPLD_Reg_1/regtable[4][20] , \CPLD_Reg_1/regtable[1][20] , \CPLD_Reg_1/regtable[0][20] , \CPLD_Reg_1/regtable[0][0] , \CPLD_Reg_1/N_256 , \CPLD_Reg_1/regtable[15][0] , \CPLD_Reg_1/regtable[11][0] , \CPLD_Reg_1/N_280 , \CPLD_Reg_1/regtable[13][0] , \CPLD_Reg_1/regtable[12][0] , \CPLD_Reg_1/N_304 , \CPLD_Reg_1/regtable[5][1] , \CPLD_Reg_1/regtable[4][1] , \CPLD_Reg_1/regtable[1][1] , \CPLD_Reg_1/regtable[0][1] , \CPLD_Reg_1/N_257 , \CPLD_Reg_1/regtable[15][1] , \CPLD_Reg_1/regtable[11][1] , \CPLD_Reg_1/regtable[3][1] , \CPLD_Reg_1/N_281 , \CPLD_Reg_1/regtable[13][1] , \DC_Con3[1] , \CPLD_Reg_1/regtable[12][1] , \CPLD_Reg_1/N_305 , \CPLD_Reg_1/regtable[5][2] , \CPLD_Reg_1/regtable[4][2] , \CPLD_Reg_1/regtable[1][2] , \CPLD_Reg_1/regtable[0][2] , \CPLD_Reg_1/N_258 , \CPLD_Reg_1/regtable[15][2] , \CPLD_Reg_1/regtable[11][2] , \CPLD_Reg_1/regtable[3][2] , \CPLD_Reg_1/N_282 , \CPLD_Reg_1/regtable[13][2] , \DC_Con3[2] , \CPLD_Reg_1/regtable[12][2] , \CPLD_Reg_1/N_306 , \CPLD_Reg_1/regtable[5][3] , \CPLD_Reg_1/regtable[4][3] , \CPLD_Reg_1/regtable[1][3] , \CPLD_Reg_1/regtable[0][3] , \CPLD_Reg_1/N_259 , \CPLD_Reg_1/regtable[15][3] , \CPLD_Reg_1/regtable[11][3] , \CPLD_Reg_1/regtable[3][3] , \CPLD_Reg_1/N_283 , \CPLD_Reg_1/regtable[13][3] , \DC_Con3[3] , \CPLD_Reg_1/regtable[12][3] , \CPLD_Reg_1/N_307 , \CPLD_Reg_1/regtable[5][4] , \CPLD_Reg_1/regtable[4][4] , \CPLD_Reg_1/regtable[1][4] , \CPLD_Reg_1/regtable[0][4] , \CPLD_Reg_1/N_260 , \DC_Con2[4] , \CPLD_Reg_1/regtable[15][4] , \CPLD_Reg_1/regtable[11][4] , \CPLD_Reg_1/regtable[3][4] , \CPLD_Reg_1/N_284 , \CPLD_Reg_1/regtable[13][4] , \CPLD_Reg_1/regtable[12][4] , \CPLD_Reg_1/N_308 , \CPLD_Reg_1/regtable[5][5] , \CPLD_Reg_1/regtable[4][5] , \CPLD_Reg_1/regtable[1][5] , \CPLD_Reg_1/regtable[0][5] , \CPLD_Reg_1/N_261 , \DC_Con2[5] , \CPLD_Reg_1/regtable[15][5] , \CPLD_Reg_1/regtable[11][5] , \CPLD_Reg_1/regtable[3][5] , \CPLD_Reg_1/N_285 , \CPLD_Reg_1/regtable[13][5] , \CPLD_Reg_1/regtable[12][5] , \CPLD_Reg_1/N_309 , \CPLD_Reg_1/regtable[5][6] , \CPLD_Reg_1/regtable[4][6] , \CPLD_Reg_1/regtable[1][6] , \CPLD_Reg_1/regtable[0][6] , \CPLD_Reg_1/N_262 , \DC_Con2[6] , \CPLD_Reg_1/regtable[15][6] , \CPLD_Reg_1/regtable[11][6] , \CPLD_Reg_1/regtable[3][6] , \CPLD_Reg_1/N_286 , \CPLD_Reg_1/regtable[13][6] , \CPLD_Reg_1/regtable[12][6] , \CPLD_Reg_1/N_310 , \CPLD_Reg_1/regtable[5][7] , \CPLD_Reg_1/regtable[4][7] , \CPLD_Reg_1/regtable[1][7] , \CPLD_Reg_1/regtable[0][7] , \CPLD_Reg_1/N_263 , \DC_Con2[7] , \CPLD_Reg_1/regtable[15][7] , \CPLD_Reg_1/regtable[11][7] , \CPLD_Reg_1/regtable[3][7] , \CPLD_Reg_1/N_287 , \CPLD_Reg_1/regtable[13][7] , \CPLD_Reg_1/regtable[12][7] , \CPLD_Reg_1/N_311 , \CPLD_Reg_1/regtable[5][8] , \CPLD_Reg_1/regtable[4][8] , \CPLD_Reg_1/regtable[1][8] , \CPLD_Reg_1/regtable[0][8] , \CPLD_Reg_1/N_264 , \DC_Con2[8] , \CPLD_Reg_1/regtable[15][8] , \CPLD_Reg_1/regtable[11][8] , \CPLD_Reg_1/regtable[3][8] , \CPLD_Reg_1/N_288 , \DC_Con4[8] , \CPLD_Reg_1/regtable[13][8] , \CPLD_Reg_1/regtable[12][8] , \CPLD_Reg_1/N_312 , \CPLD_Reg_1/regtable[5][9] , \CPLD_Reg_1/regtable[4][9] , \CPLD_Reg_1/regtable[1][9] , \CPLD_Reg_1/regtable[0][9] , \CPLD_Reg_1/N_265 , \CPLD_Reg_1/regtable[15][9] , \CPLD_Reg_1/regtable[11][9] , \CPLD_Reg_1/regtable[3][9] , \CPLD_Reg_1/N_289 , \DC_Con4[9] , \CPLD_Reg_1/regtable[13][9] , \CPLD_Reg_1/regtable[12][9] , \CPLD_Reg_1/N_313 , \CPLD_Reg_1/regtable[5][10] , \CPLD_Reg_1/regtable[4][10] , \CPLD_Reg_1/regtable[1][10] , \CPLD_Reg_1/regtable[0][10] , \CPLD_Reg_1/N_266 , \CPLD_Reg_1/regtable[15][10] , \CPLD_Reg_1/regtable[11][10] , \CPLD_Reg_1/regtable[3][10] , \CPLD_Reg_1/N_290 , \CPLD_Reg_1/regtable[13][10] , \DC_Con3[10] , \CPLD_Reg_1/regtable[12][10] , \CPLD_Reg_1/N_314 , \CPLD_Reg_1/regtable[5][11] , \CPLD_Reg_1/regtable[4][11] , \CPLD_Reg_1/regtable[1][11] , \CPLD_Reg_1/regtable[0][11] , \CPLD_Reg_1/N_267 , \CPLD_Reg_1/regtable[15][11] , \CPLD_Reg_1/regtable[11][11] , \CPLD_Reg_1/regtable[3][11] , \CPLD_Reg_1/N_291 , \CPLD_Reg_1/regtable[13][11] , \DC_Con3[11] , \CPLD_Reg_1/regtable[12][11] , \CPLD_Reg_1/N_315 , \freq4_relay[12] , \CPLD_Reg_1/regtable[4][12] , \CPLD_Reg_1/regtable[1][12] , \CPLD_Reg_1/regtable[0][12] , \CPLD_Reg_1/N_268 , \CPLD_Reg_1/regtable[15][12] , \CPLD_Reg_1/regtable[11][12] , \CPLD_Reg_1/regtable[3][12] , \CPLD_Reg_1/N_292 , \CPLD_Reg_1/regtable[13][12] , \DC_Con3[12] , \CPLD_Reg_1/regtable[12][12] , \CPLD_Reg_1/N_316 , \freq4_relay[13] , \CPLD_Reg_1/regtable[4][13] , \CPLD_Reg_1/regtable[1][13] , \CPLD_Reg_1/regtable[0][13] , \CPLD_Reg_1/N_269 , \CPLD_Reg_1/regtable[15][13] , \CPLD_Reg_1/regtable[11][13] , \CPLD_Reg_1/regtable[3][13] , \CPLD_Reg_1/N_293 , \CPLD_Reg_1/regtable[13][13] , \DC_Con3[13] , \CPLD_Reg_1/regtable[12][13] , \CPLD_Reg_1/N_317 , \freq4_relay[14] , \CPLD_Reg_1/regtable[4][14] , \CPLD_Reg_1/regtable[1][14] , \CPLD_Reg_1/regtable[0][14] , \CPLD_Reg_1/N_270 , \CPLD_Reg_1/regtable[15][14] , \CPLD_Reg_1/regtable[11][14] , \CPLD_Reg_1/regtable[3][14] , \CPLD_Reg_1/N_294 , \CPLD_Reg_1/regtable[13][14] , \DC_Con3[14] , \CPLD_Reg_1/regtable[12][14] , \CPLD_Reg_1/N_318 , \freq4_relay[15] , \CPLD_Reg_1/regtable[4][15] , \CPLD_Reg_1/regtable[1][15] , \CPLD_Reg_1/regtable[0][15] , \CPLD_Reg_1/N_271 , \CPLD_Reg_1/regtable[15][15] , \CPLD_Reg_1/regtable[11][15] , \CPLD_Reg_1/regtable[3][15] , \CPLD_Reg_1/N_295 , \CPLD_Reg_1/regtable[13][15] , \DC_Con3[15] , \CPLD_Reg_1/regtable[12][15] , \CPLD_Reg_1/N_319 , \freq4_relay[16] , \CPLD_Reg_1/regtable[4][16] , \CPLD_Reg_1/regtable[1][16] , \CPLD_Reg_1/regtable[0][16] , \CPLD_Reg_1/N_272 , \CPLD_Reg_1/regtable[15][16] , \CPLD_Reg_1/regtable[11][16] , \CPLD_Reg_1/regtable[3][16] , \CPLD_Reg_1/N_296 , \CPLD_Reg_1/regtable[13][16] , \DC_Con3[16] , \CPLD_Reg_1/regtable[12][16] , \CPLD_Reg_1/N_320 , \freq4_relay[17] , \CPLD_Reg_1/regtable[4][17] , \CPLD_Reg_1/regtable[1][17] , \CPLD_Reg_1/regtable[0][17] , \CPLD_Reg_1/N_273 , \DC_Con2[17] , \CPLD_Reg_1/regtable[15][17] , \CPLD_Reg_1/regtable[11][17] , \CPLD_Reg_1/regtable[3][17] , \CPLD_Reg_1/N_297 , \CPLD_Reg_1/regtable[13][17] , \DC_Con3[17] , \CPLD_Reg_1/regtable[12][17] , \CPLD_Reg_1/N_321 , \CPLD_Reg_1/regtable[5][18] , \CPLD_Reg_1/regtable[4][18] , \CPLD_Reg_1/regtable[1][18] , \CPLD_Reg_1/regtable[0][18] , \CPLD_Reg_1/N_274 , \DC_Con2[18] , \CPLD_Reg_1/regtable[15][18] , \CPLD_Reg_1/regtable[11][18] , \CPLD_Reg_1/regtable[3][18] , \CPLD_Reg_1/N_298 , \CPLD_Reg_1/regtable[13][18] , \DC_Con3[18] , \CPLD_Reg_1/regtable[12][18] , \CPLD_Reg_1/N_322 , \CPLD_Reg_1/regtable[5][19] , \CPLD_Reg_1/regtable[4][19] , \CPLD_Reg_1/regtable[1][19] , \CPLD_Reg_1/regtable[0][19] , \CPLD_Reg_1/N_275 , \DC_Con2[19] , \CPLD_Reg_1/regtable[15][19] , \CPLD_Reg_1/regtable[11][19] , \CPLD_Reg_1/regtable[3][19] , \CPLD_Reg_1/N_299 , \CPLD_Reg_1/regtable[13][19] , \DC_Con3[19] , \CPLD_Reg_1/regtable[12][19] , \CPLD_Reg_1/N_323 , \CPLD_Reg_1/regtable[5][21] , \CPLD_Reg_1/regtable[4][21] , \CPLD_Reg_1/regtable[1][21] , \CPLD_Reg_1/regtable[0][21] , \CPLD_Reg_1/N_277 , \DC_Con2[21] , \CPLD_Reg_1/regtable[15][21] , \CPLD_Reg_1/regtable[11][21] , \CPLD_Reg_1/regtable[3][21] , \CPLD_Reg_1/N_301 , \CPLD_Reg_1/regtable[13][21] , \DC_Con3[21] , \CPLD_Reg_1/regtable[12][21] , \CPLD_Reg_1/N_325 , \CPLD_Reg_1/regtable[5][22] , \CPLD_Reg_1/regtable[4][22] , \CPLD_Reg_1/regtable[1][22] , \CPLD_Reg_1/regtable[0][22] , \CPLD_Reg_1/N_278 , \CPLD_Reg_1/regtable[15][22] , \CPLD_Reg_1/regtable[11][22] , \CPLD_Reg_1/regtable[3][22] , \CPLD_Reg_1/N_302 , \CPLD_Reg_1/regtable[13][22] , \CPLD_Reg_1/regtable[12][22] , \CPLD_Reg_1/N_326 , \CPLD_Reg_1/regtable[5][23] , \CPLD_Reg_1/regtable[4][23] , \CPLD_Reg_1/regtable[0][23] , \CPLD_Reg_1/N_279 , \DC_Con2[23] , \CPLD_Reg_1/regtable[15][23] , \CPLD_Reg_1/regtable[11][23] , \CPLD_Reg_1/regtable[3][23] , \CPLD_Reg_1/N_303 , \CPLD_Reg_1/regtable[13][23] , \DC_Con3[23] , \CPLD_Reg_1/regtable[12][23] , \CPLD_Reg_1/N_327 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_75 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/rd_dout_te_1_u_i_a3[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[0][0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_5 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_4 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[1] , \xo2chub/genblk1.jtaghub_rom_0_0_0_f5a , \xo2chub/genblk1.jtaghub_rom_0_0_1_f5b , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 , \xo2chub/genblk1.jtaghub_rom_0_0_f5a , \xo2chub/genblk1.jtaghub_rom_0_1_f5b , \xo2chub/genblk1.jtaghub_rom_0_1_0_f5a , \xo2chub/genblk1.jtaghub_rom_0_f5a , o_err_c, \xo2chub/genblk1.jtaghub_rom_1_f5b , \xo2chub/genblk1.jtaghub_rom_1_0_0_f5a , \CPLD_Con_1/err_flag53lto4_1 , \CPLD_Con_1/dc_slot_flag_2_rep1 , \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_o2_1_0_0_0 , \xo2chub/genblk1.jtaghub_rom_1_0_f5a , \CPLD_Con_1/un90_RC_RLSel_c5_a0_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[187] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[188] , \CPLD_Con_1/un15_RC_RLSel_c4_i , \CPLD_Con_1/un11_RC_RLSellt4 , \CPLD_Con_1/RC_RLSel_1_sqmuxa_3 , \CPLD_Con_1/un15_RC_RLSel_axbxc3 , \CPLD_Con_1/N_23 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[169] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] , \CPLD_Con_1/N_207 , \CPLD_Con_1/io_RC9 , \CPLD_Con_1/N_364 , \CPLD_Con_1/N_195 , \BUS_Con_1/recv_reg[9] , \BUS_Con_1/un2_sclk_rise , \BUS_Con_1/cs_sync_RNI4H6C[1] , \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_0 , \BUS_Con_1/recv_reg[10] , \CPLD_Con_1/N_184 , \CPLD_Con_1/g0_10_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[141] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[142] , \CPLD_Con_1/g0_48_sx , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[161] , \CPLD_Con_1/err_flag97 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[162] , \BUS_Con_1/un1_addr_out_0_sqmuxa , \BUS_Con_1/recv_reg[19] , \BUS_Con_1/state_RNIS4Q6[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_tz , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_786 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] , \CPLD_Con_1/N_250 , \CPLD_Con_1/N_162 , \CPLD_Con_1/DMM_en_cnst_0_a2_0[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[204] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[205] , \CPLD_Con_1/PMU_OC_312_1 , \CPLD_Con_1/N_187 , \BUS_Con_1/recv_reg[20] , \BUS_Con_1/recv_reg[21] , \CPLD_Con_1/un40_RC_RLSel_c3_d , \CPLD_Con_1/RC_N_5_mux , \CPLD_Con_1/N_50 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] , \CPLD_Con_1/un45_RC_RLSel_m_1[16] , \xo2chub/er1_shift_reg[9] , \xo2chub/er1_shift_reg[8] , \CPLD_Con_1/N_84 , \CPLD_Con_1/N_89 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa , \CPLD_Con_1/N_92 , \CPLD_Con_1/un40_RC_RLSel_axbxc3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] , \CPLD_Con_1/un45_RC_RLSel_m[5] , \CPLD_Con_1/N_88 , \CPLD_Con_1/N_86 , \CPLD_Con_1/RC_RLSel_13_iv_0[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa , \CPLD_Con_1/N_87 , \CPLD_Con_1/RC_RLSel_13_iv_0[9] , \xo2chub/er1_shift_reg[12] , \xo2chub/er1_shift_reg[11] , \xo2chub/er1_shift_reg[10] , \CPLD_Con_1/N_182 , \CPLD_Con_1/N_275 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[202] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[203] , \CPLD_Con_1/N_75 , \CPLD_Con_1/N_72 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1 , \CPLD_Con_1/RC_RLSel_13_iv_0[15] , \CPLD_Con_1/N_78 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa , \CPLD_Con_1/RC_RLSel_13_iv_0[10] , \CPLD_Con_1/N_218 , \CPLD_Con_1/PMU_OC_312lto8_0_a2_0 , \CPLD_Con_1/PMU_OC_3_11_6_0_a2_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[88] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[87] , \CPLD_Con_1/DPS_m3_0_a2_2_1 , \CPLD_Con_1/DPS_m4_0 , \CPLD_Con_1/DPS_FS_1_9_i_a2_2_3[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[42] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[41] , \CPLD_Con_1/un4_DPS_FS_4_c3 , \CPLD_Con_1/g4_0_0_0_1 , \CPLD_Con_1/un1_i_DC_Con1_iv_0[0] , \CPLD_Con_1/i_DC_Con4_m[7] , \CPLD_Con_1/dc_slot_flag[2] , \BUS_Con_1/recv_reg[23] , \CPLD_Con_1/un3_DPS_FS_1_c9_a0_2 , \CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 , \CPLD_Con_1/DPS_FS_1_9_i_a2_2_0[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] , \CPLD_Con_1/err_flag22_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] , \CPLD_Con_1/un17lt8 , \CPLD_Con_1/err_flag_en_0_a2_3_1 , \CPLD_Con_1/g0_32 , \CPLD_Con_1/N_172 , \CPLD_Con_1/g0_41_1_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] , \CPLD_Con_1/DMM_en_1_sqmuxa_3_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[160] , \BUS_Con_1/err_flag8_1 , \BUS_Con_1/err_flag8_2 , \BUS_Con_1/data_ready17 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un15_jtdo_first_bit , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_m_2[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_tm_m_1_0[0] , \CPLD_Reg_1/regtable[10]_1_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1_N_5_mux , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/d_N_5_mux , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_70 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un4_jupdate_early_i_o2_RNIQKF31[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en_RNIGKQS , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_RNI5CHP , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_876 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_808 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_819 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_822 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] , \CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3_RNO , \CPLD_Con_1/freq_t_fast[0] , \CPLD_Con_1/freq_t_fast[1] , \BUS_Con_1/recv_reg[18] , \CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3 , \CPLD_Con_1/g0_2_0_N_2L1 , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[158] , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_RNI1TUB1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[159] , \CPLD_Con_1/err_flag75 , \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_N_2L1_0 , \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_1 , \BUS_Con_1/recv_reg[13] , \BUS_Con_1/recv_reg[12] , \CPLD_Con_1/N_410 , \BUS_Con_1/recv_reg[14] , \CPLD_Con_1/un4_DPS_FS_4_c8_i , \CPLD_Con_1/g0_27_1 , \CPLD_Con_1/RC_VSel41 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] , \CPLD_Con_1/N_366 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] , \CPLD_Con_1/g1_1 , \CPLD_Con_1/g1_0_1 , \CPLD_Con_1/PMU_m1_e_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[154] , \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[155] , \CPLD_Con_1/un1_PMU_OC_120 , \CPLD_Con_1/g0_5_1 , \CPLD_Con_1/PMU_OC_121 , \CPLD_Con_1/freq_slot_flag[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[145] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[146] , \CPLD_Con_1/g0_17_rn_1 , \CPLD_Con_1/err_flag31 , \CPLD_Con_1/g1 , \CPLD_Con_1/un16lto5_4_i_a2_0 , \CPLD_Con_1/un4_DPS_FS_3_c6_a0_1 , \CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV , \CPLD_Con_1/un4_DPS_FS_3_c5_i , \CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[59] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[58] , \CPLD_Con_1/N_74 , \CPLD_Con_1/N_134_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[201] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[200] , \CPLD_Con_1/freq_slot_flag[3] , \CPLD_Con_1/freq_slot_flag[2] , \CPLD_Con_1/freq_slot_flag[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[152] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[153] , \CPLD_Con_1/un4_DPS_FS_2_c6_a0_2 , \CPLD_Con_1/un4_DPS_FS_2_c6_a0_2_RNIUHVQ , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] , \CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 , \CPLD_Con_1/N_35_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] , \CPLD_Con_1.N_103_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] , \CPLD_Con_1/N_57 , \CPLD_Con_1/DMM_en_cnst_0_a2_i_0[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[24] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[23] , \CPLD_Con_1/DMM_en_cnst_0_a2_i_1[14] , \CPLD_Con_1/N_404 , \CPLD_Con_1/N_350_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[150] , \CPLD_Con_1.N_532 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[151] , \CPLD_Con_1/err_flag89_2 , \BUS_Con_1/wr_flag_0_sqmuxa , \CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0 , \CPLD_Con_1/N_246 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[208] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[209] , \CPLD_Con_1/N_150 , \CPLD_Con_1/N_255 , \CPLD_Con_1/un70_RC_RLSel_m_1[0] , \CPLD_Con_1/un65_RC_RLSel_c3 , \CPLD_Con_1/un65_RC_RLSel_axbxc4 , \CPLD_Con_1/N_70 , \xo2chub/er1_shift_reg[20] , \xo2chub/er1_shift_reg[19] , \CPLD_Con_1/un70_RC_RLSel_m[7] , \CPLD_Con_1/un70_RC_RLSel_m_0_a2_1[16] , \CPLD_Con_1/un95_RC_RLSel_m_0_a2_1[1] , \CPLD_Con_1/un70_RC_RLSel_m[1] , \CPLD_Con_1/un20_RC_RLSel_m[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] , \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[4] , \CPLD_Con_1/un70_RC_RLSel_m[4] , \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[3] , \CPLD_Con_1/un90_RC_RLSel_axbxc3 , \CPLD_Con_1/un70_RC_RLSel_m[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] , \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[0] , \CPLD_Con_1/un45_RC_RLSel_m[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] , \CPLD_Con_1/un4_DPS_FS_3_c3 , \CPLD_Con_1/PMU_OC_3_11_0_a2_0_0[7] , \CPLD_Con_1/N_447 , \CPLD_Con_1.PMU_OC_3_11[7] , \CPLD_Con_1.PMU_OC_3_11[19] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] , \CPLD_Con_1/un4_DPS_FS_3_c5_a0_0_0 , \CPLD_Con_1.PMU_OC_3_11[23] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] , \CPLD_Con_1/N_391 , \CPLD_Con_1.PMU_OC_3_11[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] , \CPLD_Con_1/un3_DPS_FS_1_axbxc7 , \CPLD_Con_1.PMU_OC_1_11[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] , \CPLD_Con_1/un3_DPS_FS_1_c3 , \CPLD_Con_1/N_34_3 , \CPLD_Con_1.PMU_OC_1_11[21] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] , \CPLD_Con_1/N_33_3 , \CPLD_Con_1.PMU_OC_1_11[20] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1 , \CPLD_Con_1/un4_DPS_FS_4_c5_i , \CPLD_Con_1/N_11 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa , \CPLD_Con_1.N_644 , \CPLD_Con_1/N_33_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[97] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[96] , \CPLD_Con_1.N_608 , N_438, \CPLD_Con_1.N_742 , \CPLD_Con_1/PMU_OC_4_11_409_a2_0_a2_0_0 , \CPLD_Con_1.N_706 , \CPLD_Con_1/N_394 , N_460, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[93] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[92] , \CPLD_Con_1.N_694 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[21] , \CPLD_Con_1.N_645 , \CPLD_Con_1/PMU_OC_4_4_313_0 , \CPLD_Con_1/OVER_1_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[209] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[208] , \CPLD_Con_1.PMU_OC_1_11[16] , \CPLD_Con_1/PMU_OC_1_1_sqmuxa_1_0 , \CPLD_Con_1/PMU_OC_4_4_297_0 , \CPLD_Con_1.PMU_OC_1_11[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] , \CPLD_Con_1/un4_DPS_FS_4_axbxc5 , \CPLD_Con_1.N_548 , \CPLD_Con_1/un4_DPS_FS_2_axbxc3 , \CPLD_Con_1/N_363 , \CPLD_Con_1/N_335_1 , \CPLD_Con_1/un4_DPS_FS_2_axbxc7 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[212] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[211] , \CPLD_Con_1.PMU_OC_2_11[16] , \CPLD_Con_1/N_403 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[53] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[52] , \CPLD_Con_1.PMU_OC_3_11[20] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[55] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[54] , \CPLD_Con_1.PMU_OC_3_11[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[84] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[83] , \CPLD_Con_1.N_518 , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_3_tz_RNI9M8I3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[37] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[36] , \CPLD_Con_1/un3_DPS_FS_1_c5 , \CPLD_Con_1.PMU_OC_1_11[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] , \CPLD_Con_1.PMU_OC_1_11[18] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] , \CPLD_Con_1/N_36_3 , \CPLD_Con_1.PMU_OC_1_11[19] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] , \CPLD_Con_1/N_259 , \CPLD_Con_1/N_462 , \CPLD_Con_1/N_371 , \CPLD_Con_1/PMU_OC_119 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[79] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[78] , \CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i , \CPLD_Con_1/un4_DPS_FS_4_axbxc8 , \CPLD_Con_1/N_572_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[9] , \CPLD_Con_1.N_596 , N_128, \CPLD_Con_1/DPS_m3_0_a2_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[210] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[20] , \CPLD_Con_1.PMU_OC_2_11[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[210] , \CPLD_Con_1/un4_DPS_FS_2_c4 , \CPLD_Con_1/un4_DPS_FS_2_axbxc4 , \CPLD_Con_1.PMU_OC_2_11[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] , \CPLD_Con_1.PMU_OC_2_11[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] , \CPLD_Con_1/N_345 , \CPLD_Con_1.PMU_OC_2_11[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] , \CPLD_Con_1/N_419 , \CPLD_Con_1.PMU_OC_2_11[23] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] , \CPLD_Con_1.N_100_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] , \CPLD_Con_1.N_104_3 , \CPLD_Con_1.PMU_OC_1_11[23] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] , \CPLD_Con_1/PMU_OC_3_11_0_a2_1_1[6] , \CPLD_Con_1/N_35_7 , \CPLD_Con_1.PMU_OC_3_11[6] , \CPLD_Con_1/dc_slot_flag_fast[3] , \CPLD_Con_1/dc_slot_flag_fast[2] , \CPLD_Con_1/dc_slot_flag_fast[1] , \CPLD_Con_1/dc_slot_flag_fast[0] , \CPLD_Con_1.PMU_OC_3_11[18] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] , \CPLD_Con_1.PMU_OC_3_11[22] , \CPLD_Con_1.PMU_OC_3_11[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] , \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa , \CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0_1 , \CPLD_Con_1/PMU_OC_3_11_6_a2_2_1 , \CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[89] , \CPLD_Con_1/err_flag_en_0_a2_6_mb_sn , \CPLD_Con_1/err_flag_en_0_a2_6_mb_rn_0 , \CPLD_Con_1/N_386 , \CPLD_Con_1/N_384 , \CPLD_Con_1/err_flag_en_0_a2_5_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] , \CPLD_Con_1/N_25 , \xo2chub/er1_shift_reg[7] , \xo2chub/er1_shift_reg[6] , \CPLD_Con_1/un20_RC_RLSel_m[6] , \xo2chub/er1_shift_reg[5] , \xo2chub/er1_shift_reg[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[95] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[94] , N_456, \CPLD_Con_1/N_381 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[205] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[204] , \CPLD_Con_1/N_453 , \CPLD_Con_1/PMU_OC_2_11_2[4] , \CPLD_Con_1.PMU_OC_2_11[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] , \CPLD_Con_1.PMU_OC_2_11[20] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] , \CPLD_Con_1/dc_slot_flag[0] , \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 , \CPLD_Con_1/N_36 , \CPLD_Con_1/un90_RC_RLSel_c4 , \CPLD_Con_1/RC_RLSel_13_iv_0[13] , \CPLD_Con_1/RC_RLSel_13_iv_0[8] , \CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[14] , \CPLD_Con_1/RC_RLSel_13_iv_0[14] , \CPLD_Con_1/RC_RLSel_13_iv_0[11] , \CPLD_Con_1/DMM_en_26_i_a4_1_0[15] , \CPLD_Con_1/DMM_en_26_i_a4_0_2[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[199] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[198] , \CPLD_Con_1/err_flag75lt3 , \CPLD_Con_1/un1_exec_flag_1_0_o2_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[196] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[197] , N_128_rep1, \CPLD_Con_1/N_276 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[51] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[50] , \CPLD_Con_1/g2_0_0 , \CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_c_d , \CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[180] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] , \CPLD_Con_1/un95_RC_RLSel_m_1[16] , \CPLD_Con_1/un95_RC_RLSel_m[16] , \CPLD_Con_1/un20_RC_RLSel_m_0_a2_1[16] , \CPLD_Con_1/un15_RC_RLSel_axbxc4 , \CPLD_Con_1/un20_RC_RLSel_m_0_a2_1[17] , \CPLD_Con_1/un20_RC_RLSel_m[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1 , \CPLD_Con_1/un4_DPS_FS_2_c8_a0_1 , \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_o2_2_N_2L1 , \CPLD_Con_1/N_233 , \CPLD_Con_1/err_flag53 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[77] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[76] , \CPLD_Con_1/N_225 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[91] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[90] , N_456_rep1, \CPLD_Con_1/un1_m1_0_a2_0 , N_168, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] , \CPLD_Con_1/N_204_tz , \CPLD_Con_1/un1_exec_flag_10_i_a2_0_1 , \CPLD_Con_1/N_272 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[190] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[191] , \CPLD_Con_1/err_flag45_i_a3_0_N_2L1 , \CPLD_Con_1/DPS_N_12_mux , \CPLD_Con_1/N_258 , \CPLD_Con_1/un1_exec_flag_4_i_a2_1 , \CPLD_Con_1/err_flag45_i_a3_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[200] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[201] , \CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 , \CPLD_Con_1/un4_DPS_FS_2_axbxc8 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] , \CPLD_Con_1/N_382 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[203] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[202] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[206] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[207] , \CPLD_Con_1/N_248 , \CPLD_Con_1/RC_Tx_0_0_iv_3_88_i_i_a3_1 , \CPLD_Con_1/N_270 , N_244, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] , \CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_a3_1 , \CPLD_Con_1/N_267 , N_243, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[140] , \CPLD_Con_1/N_126 , \CPLD_Con_1/RC_Tx_0_0_iv_4_74_i_i_a4_0 , \CPLD_Con_1/N_95 , N_38, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[139] , \CPLD_Con_1/DPS_FS_2_9_i_a2_4_2[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[46] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[45] , \CPLD_Con_1/N_133 , \CPLD_Con_1/N_132 , \CPLD_Con_1/N_100 , N_42, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] , \CPLD_Con_1/RC_Tx_0_0_iv_4_i_i_a4_0_0 , \CPLD_Con_1/N_102 , N_44, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] , \CPLD_Con_1/N_380 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[189] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] , \CPLD_Con_1/N_418 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] , \CPLD_Con_1/N_688_tz , \CPLD_Con_1/un1_i_DC_Con4_11_6_0_o2_i_a3_RNITGF53 , N_40, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] , \CPLD_Con_1/un4_DPS_FS_4_c8_a0_1 , \CPLD_Con_1/DPS_N_12_mux_1 , \CPLD_Con_1/un4_DPS_FS_3_axbxc8 , \CPLD_Con_1/err_flag_en_0_a2_5_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] , \CPLD_Con_1/un4_DPS_FS_3_c8_a0_3 , \CPLD_Con_1/un4_DPS_FS_3_c8_a0_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[57] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[56] , \CPLD_Con_1/DPS_FS_4_9_i_a2_4_2[8] , \CPLD_Con_1/N_400 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[60] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[5] , \CPLD_Con_1/N_169_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[44] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[43] , \CPLD_Con_1/dc_slot_flag_3_rep1 , \CPLD_Con_1/dc_slot_flag_1_rep1 , \CPLD_Con_1/dc_slot_flag_0_rep1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[176] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[177] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[181] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[182] , \BUS_Con_1/recv_reg[15] , \BUS_Con_1/recv_reg[16] , \CPLD_Con_1/N_165 , \CPLD_Con_1/un4_DPS_FS_3_c9 , \CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2_0_a2_1 , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[194] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[195] , \CPLD_Con_1/un1_exec_flag_3_i_a2_1 , \CPLD_Con_1/un1_exec_flag_3_i_0_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[198] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[199] , \CPLD_Con_1/N_217 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[192] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[193] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[207] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[206] , \CPLD_Con_1/N_256 , \BUS_Con_1/recv_reg[22] , \CPLD_Con_1/N_254 , \CPLD_Con_1/N_13_mux_i , \CPLD_Con_1/m4_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[39] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[38] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[31] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[30] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[28] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[27] , \CPLD_Con_1/err_flag45_i_a2_0_1 , \CPLD_Con_1/un17lto4_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[174] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[175] , \CPLD_Con_1/N_261 , \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_a4_1_1_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] , \CPLD_Con_1/RC_m1_e_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] , \CPLD_Con_1/un65_RC_RLSel_c4_i , \CPLD_Con_1/DPS_FS_4_9_i_a2_4_0[8] , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[35] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[34] , \CPLD_Con_1/err_flag_en_0_a2_1_N_2L1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[26] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[25] , \CPLD_Con_1/DMM_en_26_i_a4_0_0[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[19] , \CPLD_Con_1/DMM_en_26_0_a3_0_1[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[170] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[171] , \CPLD_Con_1/N_189_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[4] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[49] , \CPLD_Con_1/PMU_OC_313_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[86] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[85] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] , \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[33] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[32] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[80] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[7] , \CPLD_Con_1/g4 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] , \un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] , \CPLD_Con_1/g1_5 , \CPLD_Con_1/g1_4 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[165] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[166] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[167] , \CPLD_Con_1/g2_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[168] , \CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[147] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[148] , \CPLD_Con_1/err_flag31lt3_0_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[156] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[157] , \CPLD_Con_1/g0_11_1 , \CPLD_Con_1/g0_0_2 , \BUS_Con_1/recv_reg[11] , \CPLD_Con_1/g2_2 , \CPLD_Con_1/g0_45_1 , \CPLD_Con_1/g0_6_2_0 , \CPLD_Con_1/g1_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[163] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[164] , \CPLD_Con_1/g2 , \CPLD_Con_1/g1_1_0 , \CPLD_Con_1/g0_0_0_1_0 , \CPLD_Con_1/g4_0_0_0_0 , \CPLD_Con_1/g3 , \CPLD_Con_1/g0_0_0_0 , \un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA , \CPLD_Con_1/g2_1_0 , \CPLD_Con_1/g2_0_1 , \CPLD_Con_1/PMU_OC_312lto8_1_0_o2_0_sn , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[210] , \CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0 , \BUS_Con_1/recv_reg[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[143] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[144] , \CPLD_Reg_1/N_1137 , \CPLD_Reg_1/N_7 , \CPLD_Reg_1/regtable[0]_1_sqmuxa , \CPLD_Reg_1/regtable[5]_1_sqmuxa , \CPLD_Reg_1/N_1138 , \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 , \CPLD_Reg_1/regtable[13]_1_sqmuxa , \CPLD_Reg_1/un34_regtable_5[1] , \CPLD_Reg_1/un9_0_a3_0 , \CPLD_Reg_1/state_6_d , \CPLD_Reg_1/regtable[4]_1_sqmuxa , \CPLD_Reg_1/un34_regtable_2[1] , \CPLD_Reg_1/state_ns_0_a4_0_3[1] , \CPLD_Reg_1/un10_i_0_1 , N_694_rst, o_wready_c, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[120] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[119] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[118] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[117] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[116] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[1] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[113] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[112] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[115] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[114] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[171] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[170] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[175] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[174] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/N_5 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[162] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[161] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_105 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[168] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[167] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[137] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[136] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[135] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[134] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[164] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[163] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[133] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[132] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_32 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[124] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[123] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_clk , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[128] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[127] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_m , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_N_2L1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[122] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[121] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_m_1[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_m[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4362 , \CPLD_Reg_1/regtable[11]_1_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[3] , \CPLD_Reg_1/regtable[12]_1_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4371 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 , \CPLD_Reg_1/regtable[14]_1_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4_x , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jtdo_first_bit , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_first_bit_1_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_m_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un22_jtdo , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_871 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_877 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_a2_4_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_881 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_821 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_818 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_7_1[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_803 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[102] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[101] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_12[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_2[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_6_1[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_i_0_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[104] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[103] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[108] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[107] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_a2_2_0 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[100] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[0] , \xo2chub/jtdo1_1_1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[180] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[17] , \xo2chub/jtdo1 , \CPLD_Con_1.PMU_OC_2_11[19] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] , \CPLD_Con_1.PMU_OC_2_11[17] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] , \CPLD_Con_1.PMU_OC_2_11[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] , \CPLD_Con_1.PMU_OC_2_11[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] , \CPLD_Con_1.PMU_OC_2_11[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] , \CPLD_Con_1.PMU_OC_2_11[21] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/te_prog_din[0] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] , \xo2chub/er1_shift_reg[2] , \BUS_Con_1/recv_reg[8] , \CPLD_Con_1.io_RC_2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[82] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[81] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] , \CPLD_Reg_1/regtable[2]_1_sqmuxa , \CPLD_Reg_1/regtable[3]_1_sqmuxa , \CPLD_Reg_1/regtable[15]_1_sqmuxa , \CPLD_Reg_1/un10_i_0_1_RNI75F41 , \CPLD_Con_1.PMU_OC_2_11[18] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] , \CPLD_Con_1.PMU_OC_2_11[7] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[71] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[70] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[68] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[67] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[66] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[65] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[6] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[69] , \xo2chub/er1_shift_reg[3] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[64] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[63] , \CPLD_Con_1.N_98_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] , \CPLD_Con_1.N_102_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] , \un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B , \CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[111] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[110] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[10] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[109] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[140] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[13] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[16] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[169] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en , N_18_i, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[149] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[62] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[61] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[183] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[184] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[75] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[74] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[73] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[72] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[2] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[29] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[40] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[3] , \CPLD_Con_1.N_99_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] , \CPLD_Con_1.N_101_3 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[211] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[212] , N_694_en, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[173] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[172] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[139] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[138] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[126] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[125] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[12] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[129] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[131] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[130] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[99] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[98] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[178] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[179] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[185] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[186] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[172] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[173] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[177] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[176] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[179] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[178] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[166] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[165] , \xo2chub/jtdo2 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[106] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[105] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[159] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[158] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[160] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[15] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[48] , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[47] , miso_shift31, \o_PMU_OC_4_c[15] , \o_PMU_OC_4_c[14] , \o_PMU_OC_4_c[13] , \o_PMU_OC_4_c[12] , \o_PMU_OC_4_c[11] , \o_PMU_OC_4_c[10] , \o_PMU_OC_4_c[9] , \o_PMU_OC_4_c[8] , \o_PMU_OC_4_c[7] , \o_PMU_OC_4_c[6] , \o_PMU_OC_4_c[5] , \o_PMU_OC_4_c[4] , \o_PMU_OC_4_c[3] , \o_PMU_OC_4_c[2] , \o_PMU_OC_4_c[1] , \o_PMU_OC_4_c[0] , \o_PMU_OC_3_c[15] , \o_PMU_OC_3_c[14] , \o_PMU_OC_3_c[12] , \o_PMU_OC_3_c[11] , \o_PMU_OC_3_c[10] , \o_PMU_OC_3_c[8] , \o_PMU_OC_3_c[7] , \o_PMU_OC_3_c[6] , \o_PMU_OC_3_c[4] , \o_PMU_OC_3_c[3] , \o_PMU_OC_3_c[2] , \o_PMU_OC_3_c[0] , \o_PMU_OC_2_c[15] , \o_PMU_OC_2_c[14] , \o_PMU_OC_2_c[13] , \o_PMU_OC_2_c[12] , \o_PMU_OC_2_c[11] , \o_PMU_OC_2_c[10] , \o_PMU_OC_2_c[9] , \o_PMU_OC_2_c[8] , \o_PMU_OC_2_c[7] , \o_PMU_OC_2_c[6] , \o_PMU_OC_2_c[5] , \o_PMU_OC_2_c[4] , \o_PMU_OC_2_c[3] , \o_PMU_OC_2_c[2] , \o_PMU_OC_2_c[1] , \o_PMU_OC_2_c[0] , \o_PMU_OC_1_c[15] , \o_PMU_OC_1_c[14] , \o_PMU_OC_1_c[13] , \o_PMU_OC_1_c[12] , \o_PMU_OC_1_c[11] , \o_PMU_OC_1_c[10] , \o_PMU_OC_1_c[9] , \o_PMU_OC_1_c[8] , \o_PMU_OC_1_c[7] , \o_PMU_OC_1_c[6] , \o_PMU_OC_1_c[5] , \o_PMU_OC_1_c[4] , \o_PMU_OC_1_c[3] , \o_PMU_OC_1_c[2] , \o_PMU_OC_1_c[1] , \o_PMU_OC_1_c[0] , o_RC_T32_c, o_RC_T31_c, o_RC_T30_c, o_RC_T29_c, o_RC_T28_c, o_RC_T27_c, o_IO_RC1_c, i_cs_c, i_mosi_c, i_sclk_c, VCCI; RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_0 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_0 ( .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[157] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[156] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[14] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[15] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[156] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[157] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[146] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[145] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[12] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[13] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[145] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[14] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[146] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[14] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_2 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[144] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[143] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[10] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[11] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[143] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[12] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[144] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[12] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_3 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_3 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[155] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[154] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[8] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[9] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[154] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[10] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[155] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[10] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_4 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_4 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[153] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[152] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[6] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[7] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[152] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[8] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[153] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[8] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_5 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_5 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[151] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[150] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[5] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[150] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[6] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[151] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[6] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_6 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_6 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[14] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[149] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[3] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[149] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[4] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[4] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_7 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_7 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[148] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[147] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[1] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[147] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[2] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[148] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[2] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_8 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_8 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[142] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[141] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[141] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[142] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry[0] ) ); SLICE_9 SLICE_9( .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[6] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[7] ) , .Q0(\DC_Con2[15] ), .Q1(\DC_Con2[16] )); SLICE_10 SLICE_10( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] ) , .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[5] ) , .Q0(\DC_Con2[13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[6] ) , .Q1(\DC_Con2[14] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[6] ) ); SLICE_11 SLICE_11( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[3] ) , .Q0(\DC_Con2[11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[4] ) , .Q1(\DC_Con2[12] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[4] ) ); SLICE_12 SLICE_12( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[1] ) , .Q0(\DC_Con2[0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[2] ) , .Q1(\DC_Con2[10] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2] ) ); SLICE_13 SLICE_13( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] ) , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .Q0(\DC_Con1[8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[0] ) , .Q1(\DC_Con1[9] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[0] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_14 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_14 ( .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[5] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[5] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_15 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_15 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[4] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[3] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[3] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[4] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[4] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_16 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_16 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[2] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[1] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[1] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[2] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[2] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_17 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_17 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast_i ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry[0] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_18 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_18 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[0] ) ); SLICE_19 SLICE_19( .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] ) , .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[8] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[9] ) , .Q0(\DC_Con4[13] ), .Q1(\DC_Con4[14] )); SLICE_20 SLICE_20( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[6] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[7] ) , .Q0(\DC_Con4[11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[8] ) , .Q1(\DC_Con4[12] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[8] ) ); SLICE_21 SLICE_21( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[5] ) , .Q0(\DC_Con4[0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[6] ) , .Q1(\DC_Con4[10] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[6] ) ); SLICE_22 SLICE_22( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] ) , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[3] ) , .Q0(\DC_Con3[8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[4] ) , .Q1(\DC_Con3[9] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[4] ) ); SLICE_23 SLICE_23( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[1] ) , .Q0(\DC_Con3[6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[2] ) , .Q1(\DC_Con3[7] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[2] ) ); SLICE_24 SLICE_24( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .Q0(\DC_Con3[4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[0] ) , .Q1(\DC_Con3[5] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry[0] ) ); SLICE_25 SLICE_25( .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[8] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[9] ) , .Q0(\DC_Con4[2] ), .Q1(\DC_Con4[3] )); SLICE_26 SLICE_26( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] ) , .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[6] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[7] ) , .Q0(\DC_Con4[22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[8] ) , .Q1(\DC_Con4[23] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[8] ) ); SLICE_27 SLICE_27( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[5] ) , .Q0(\DC_Con4[20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[6] ) , .Q1(\DC_Con4[21] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[6] ) ); SLICE_28 SLICE_28( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[3] ) , .Q0(\DC_Con4[19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[4] ) , .Q1(\DC_Con4[1] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[4] ) ); SLICE_29 SLICE_29( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] ) , .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[1] ) , .Q0(\DC_Con4[17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[2] ) , .Q1(\DC_Con4[18] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[2] ) ); SLICE_30 SLICE_30( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .Q0(\DC_Con4[15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[0] ) , .Q1(\DC_Con4[16] ), .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry[0] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_31 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_31 ( .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[8] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[9] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_32 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_32 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[6] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[7] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[8] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[8] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_33 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_33 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[5] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[6] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[6] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_34 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_34 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[4] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_35 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_35 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_36 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_36 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_37 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_37 ( .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .CLK(jtaghub16_jtck), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[8] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[9] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_38 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_38 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[6] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[7] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[8] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[8] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_39 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_39 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[4] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[5] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[6] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[6] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_40 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_40 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[2] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[3] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[4] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[4] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_41 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_41 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .FCI(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[0] ) , .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[1] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[2] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] ) , .FCO(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry[2] ) ); xo2chub_SLICE_42 \xo2chub/SLICE_42 ( .C1(\xo2chub/bit_count[0] ), .B1(\xo2chub/bit_count15 ), .A1(\xo2chub/bit_count ), .B0(\xo2chub/bit_count ), .DI1(\xo2chub/bit_count_s[0] ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F1(\xo2chub/bit_count_s[0] ), .Q1(\xo2chub/bit_count[0] ), .FCO(\xo2chub/bit_count_cry[0] )); SLICE_43 SLICE_43( .B0(\xo2chub/id_enable ), .A0(\xo2chub/rom_dout ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[18] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[189] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_2_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[189] ) , .F1(\xo2chub/jtdo2_int ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] ) ); SLICE_44 SLICE_44( .B1(jtaghub16_ip_enable0), .A1(jtaghub16_er2_tdo0), .B0(\xo2chub/ip_enable[1] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[191] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[190] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_4_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[190] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[191] ) , .FCO(\xo2chub/jtdo2_int_prm_2_0 )); SLICE_45 SLICE_45( .B1(\xo2chub/ip_enable[2] ), .B0(\xo2chub/ip_enable[3] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[193] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[192] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_6_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[192] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[193] ) , .FCO(\xo2chub/jtdo2_int_prm_4_0 )); SLICE_46 SLICE_46( .B1(\xo2chub/ip_enable[4] ), .B0(\xo2chub/ip_enable[5] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[195] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[194] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_8_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[194] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[195] ) , .FCO(\xo2chub/jtdo2_int_prm_6_0 )); SLICE_47 SLICE_47( .B1(\xo2chub/ip_enable[6] ), .B0(\xo2chub/ip_enable[7] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[197] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[196] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_10_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[196] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[197] ) , .FCO(\xo2chub/jtdo2_int_prm_8_0 )); SLICE_48 SLICE_48( .B1(\xo2chub/ip_enable[8] ), .B0(\xo2chub/ip_enable[9] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[182] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[181] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_12_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[181] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[182] ) , .FCO(\xo2chub/jtdo2_int_prm_10_0 )); SLICE_49 SLICE_49( .B1(\xo2chub/ip_enable[10] ), .B0(\xo2chub/ip_enable[11] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[184] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[183] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_14_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[183] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[184] ) , .FCO(\xo2chub/jtdo2_int_prm_12_0 )); SLICE_50 SLICE_50( .B1(\xo2chub/ip_enable[12] ), .B0(\xo2chub/ip_enable[13] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[186] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[185] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .FCI(\xo2chub/jtdo2_int_prm_16_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[185] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[186] ) , .FCO(\xo2chub/jtdo2_int_prm_14_0 )); SLICE_51 SLICE_51( .B1(\xo2chub/ip_enable[14] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[188] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[187] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[187] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[188] ) , .FCO(\xo2chub/jtdo2_int_prm_16_0 )); xo2chub_SLICE_52 \xo2chub/SLICE_52 ( .B0(\xo2chub/rom_rd_addr[7] ), .A0(jtaghub16_jshift), .DI0(\xo2chub/rom_rd_addr_s[7] ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .FCI(\xo2chub/rom_rd_addr_cry[6] ), .F0(\xo2chub/rom_rd_addr_s[7] ), .Q0(\xo2chub/rom_rd_addr[7] )); xo2chub_SLICE_53 \xo2chub/SLICE_53 ( .B1(\xo2chub/rom_rd_addr[6] ), .A1(jtaghub16_jshift), .B0(\xo2chub/rom_rd_addr[5] ), .A0(jtaghub16_jshift), .DI1(\xo2chub/rom_rd_addr_s[6] ), .DI0(\xo2chub/rom_rd_addr_s[5] ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .FCI(\xo2chub/rom_rd_addr_cry[4] ), .F0(\xo2chub/rom_rd_addr_s[5] ), .Q0(\xo2chub/rom_rd_addr[5] ), .F1(\xo2chub/rom_rd_addr_s[6] ), .Q1(\xo2chub/rom_rd_addr[6] ), .FCO(\xo2chub/rom_rd_addr_cry[6] )); xo2chub_SLICE_54 \xo2chub/SLICE_54 ( .B1(\xo2chub/rom_rd_addr[4] ), .A1(jtaghub16_jshift), .B0(\xo2chub/rom_rd_addr[3] ), .A0(jtaghub16_jshift), .DI1(\xo2chub/rom_rd_addr_s[4] ), .DI0(\xo2chub/rom_rd_addr_s[3] ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .FCI(\xo2chub/rom_rd_addr_cry[2] ), .F0(\xo2chub/rom_rd_addr_s[3] ), .Q0(\xo2chub/rom_rd_addr[3] ), .F1(\xo2chub/rom_rd_addr_s[4] ), .Q1(\xo2chub/rom_rd_addr[4] ), .FCO(\xo2chub/rom_rd_addr_cry[4] )); xo2chub_SLICE_55 \xo2chub/SLICE_55 ( .B1(\xo2chub/rom_rd_addr[2] ), .A1(jtaghub16_jshift), .B0(\xo2chub/rom_rd_addr[1] ), .A0(jtaghub16_jshift), .DI1(\xo2chub/rom_rd_addr_s[2] ), .DI0(\xo2chub/rom_rd_addr_s[1] ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .FCI(\xo2chub/rom_rd_addr_cry[0] ), .F0(\xo2chub/rom_rd_addr_s[1] ), .Q0(\xo2chub/rom_rd_addr[1] ), .F1(\xo2chub/rom_rd_addr_s[2] ), .Q1(\xo2chub/rom_rd_addr[2] ), .FCO(\xo2chub/rom_rd_addr_cry[2] )); xo2chub_SLICE_56 \xo2chub/SLICE_56 ( .B1(\xo2chub/rom_rd_addr[0] ), .A1(jtaghub16_jshift), .B0(jtaghub16_jshift), .DI1(\xo2chub/rom_rd_addr_s[0] ), .M0(jtaghub16_jshift), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .Q0(\xo2chub/bit_count ), .F1(\xo2chub/rom_rd_addr_s[0] ), .Q1(\xo2chub/rom_rd_addr[0] ), .FCO(\xo2chub/rom_rd_addr_cry[0] )); xo2chub_SLICE_57 \xo2chub/SLICE_57 ( .B1(\xo2chub/bit_count[4] ), .A1(\xo2chub/bit_count ), .B0(\xo2chub/bit_count[3] ), .A0(\xo2chub/bit_count ), .DI1(\xo2chub/bit_count_s[4] ), .DI0(\xo2chub/bit_count_s[3] ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .FCI(\xo2chub/bit_count_cry[2] ), .F0(\xo2chub/bit_count_s[3] ), .Q0(\xo2chub/bit_count[3] ), .F1(\xo2chub/bit_count_s[4] ), .Q1(\xo2chub/bit_count[4] )); xo2chub_SLICE_58 \xo2chub/SLICE_58 ( .B1(\xo2chub/bit_count[2] ), .A1(\xo2chub/bit_count ), .B0(\xo2chub/bit_count[1] ), .A0(\xo2chub/bit_count ), .DI1(\xo2chub/bit_count_s[2] ), .DI0(\xo2chub/bit_count_s[1] ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .FCI(\xo2chub/bit_count_cry[0] ), .F0(\xo2chub/bit_count_s[1] ), .Q0(\xo2chub/bit_count[1] ), .F1(\xo2chub/bit_count_s[2] ), .Q1(\xo2chub/bit_count[2] ), .FCO(\xo2chub/bit_count_cry[2] )); SLICE_59 SLICE_59( .D1(\CPLD_Con_1/N_374 ), .C1(\CPLD_Con_1/g1_0 ), .B1(\CPLD_Con_1/g0_0_1 ), .A1(\CPLD_Con_1/PMU_OC_1_4_sqmuxa ), .B0(i_rst_n_c), .A0(\BUS_Con_1.cs_sync[0] ), .DI0(i_rst_n_c_i_set), .CLK(i_sys_clk_c), .F0(i_rst_n_c_i_set), .Q0(\BUS_Con_1.cs_sync_rep0[1] ), .F1(io_RC9_RNID445E)); BUS_Con_1_SLICE_60 \BUS_Con_1/SLICE_60 ( .D1(\BUS_Con_1.sclk_sync[0] ), .C1(\BUS_Con_1/sclk_sync[1] ), .B1(\BUS_Con_1/bit_cnt[0] ), .A1(\BUS_Con_1/bit_cnt[1] ), .C0(\BUS_Con_1.sclk_sync[0] ), .B0(\BUS_Con_1/sclk_sync[1] ), .A0(\BUS_Con_1/bit_cnt[0] ), .DI1(\BUS_Con_1/bit_cnt_6[1] ), .DI0(\BUS_Con_1/bit_cnt_6[0] ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/bit_cnt_6[0] ), .Q0(\BUS_Con_1/bit_cnt[0] ), .F1(\BUS_Con_1/bit_cnt_6[1] ), .Q1(\BUS_Con_1/bit_cnt[1] )); BUS_Con_1_SLICE_61 \BUS_Con_1/SLICE_61 ( .B1(\BUS_Con_1/un1_bit_cnt_7_c3 ), .A1(\BUS_Con_1/bit_cnt[3] ), .D0(\BUS_Con_1/sclk_rise ), .C0(\BUS_Con_1/bit_cnt[2] ), .B0(\BUS_Con_1/bit_cnt[1] ), .A0(\BUS_Con_1/bit_cnt[0] ), .DI1(\BUS_Con_1/bit_cnt_6[3] ), .DI0(\BUS_Con_1/bit_cnt_6[2] ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/bit_cnt_6[2] ), .Q0(\BUS_Con_1/bit_cnt[2] ), .F1(\BUS_Con_1/bit_cnt_6[3] ), .Q1(\BUS_Con_1/bit_cnt[3] )); BUS_Con_1_SLICE_62 \BUS_Con_1/SLICE_62 ( .D1(\BUS_Con_1/un1_bit_cnt_7_c3 ), .C1(\BUS_Con_1/bit_cnt[5] ), .B1(\BUS_Con_1/bit_cnt[4] ), .A1(\BUS_Con_1/bit_cnt[3] ), .C0(\BUS_Con_1/un1_bit_cnt_7_c3 ), .B0(\BUS_Con_1/bit_cnt[4] ), .A0(\BUS_Con_1/bit_cnt[3] ), .DI1(\BUS_Con_1/bit_cnt_6[5] ), .DI0(\BUS_Con_1/bit_cnt_6[4] ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/bit_cnt_6[4] ), .Q0(\BUS_Con_1/bit_cnt[4] ), .F1(\BUS_Con_1/bit_cnt_6[5] ), .Q1(\BUS_Con_1/bit_cnt[5] )); BUS_Con_1_SLICE_64 \BUS_Con_1/SLICE_64 ( .D1(\BUS_Con_1/state[1] ), .C1(\BUS_Con_1/state[0] ), .B1(\BUS_Con_1/data_ready_0_sqmuxa_1 ), .A1(\BUS_Con_1/cs_sync[1] ), .D0(\BUS_Con_1.sclk_sync[0] ), .C0(\BUS_Con_1/sclk_sync[1] ), .B0(\BUS_Con_1/cs_sync[1] ), .A0(\BUS_Con_1/un1_err_flag8 ), .DI0(\BUS_Con_1/data_ready_0_sqmuxa_1 ), .CE(\BUS_Con_1/data_ready_en_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/data_ready_0_sqmuxa_1 ), .Q0(\BUS_Con_1/data_ready ), .F1(\BUS_Con_1/data_ready_en_0 )); BUS_Con_1_SLICE_65 \BUS_Con_1/SLICE_65 ( .D1(\BUS_Con_1/miso_shift17lt3 ), .C1(\BUS_Con_1/miso_shift9_2 ), .B1(\BUS_Con_1/miso_shift9_1 ), .A1(\BUS_Con_1/cs_sync[1] ), .B0(\BUS_Con_1/miso_loaded ), .A0(\BUS_Con_1/miso_loaded_0_sqmuxa ), .DI0(\BUS_Con_1/fb_0 ), .M1(\BUS_Con_1.cs_sync[0] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/fb_0 ), .Q0(\BUS_Con_1/miso_loaded ), .F1(\BUS_Con_1/miso_loaded_0_sqmuxa ), .Q1(\BUS_Con_1/cs_sync[1] )); BUS_Con_1_SLICE_66 \BUS_Con_1/SLICE_66 ( .C1(\r_data[1] ), .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[8] ), .B0(\r_data[0] ), .A0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .DI1(\BUS_Con_1/miso_shift_8[9] ), .DI0(\BUS_Con_1/miso_shift_8[8] ), .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[8] ), .Q0(\BUS_Con_1/miso_shift[8] ), .F1(\BUS_Con_1/miso_shift_8[9] ), .Q1(\BUS_Con_1/miso_shift[9] )); BUS_Con_1_SLICE_67 \BUS_Con_1/SLICE_67 ( .C1(\r_data[3] ), .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[10] ), .C0(\r_data[2] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[9] ), .DI1(\BUS_Con_1/miso_shift_8[11] ), .DI0(\BUS_Con_1/miso_shift_8[10] ), .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[10] ), .Q0(\BUS_Con_1/miso_shift[10] ), .F1(\BUS_Con_1/miso_shift_8[11] ), .Q1(\BUS_Con_1/miso_shift[11] )); BUS_Con_1_SLICE_68 \BUS_Con_1/SLICE_68 ( .C1(\r_data[5] ), .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[12] ), .C0(\r_data[4] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[11] ), .DI1(\BUS_Con_1/miso_shift_8[13] ), .DI0(\BUS_Con_1/miso_shift_8[12] ), .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[12] ), .Q0(\BUS_Con_1/miso_shift[12] ), .F1(\BUS_Con_1/miso_shift_8[13] ), .Q1(\BUS_Con_1/miso_shift[13] )); BUS_Con_1_SLICE_69 \BUS_Con_1/SLICE_69 ( .C1(\r_data[7] ), .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[14] ), .C0(\r_data[6] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[13] ), .DI1(\BUS_Con_1/miso_shift_8[15] ), .DI0(\BUS_Con_1/miso_shift_8[14] ), .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[14] ), .Q0(\BUS_Con_1/miso_shift[14] ), .F1(\BUS_Con_1/miso_shift_8[15] ), .Q1(\BUS_Con_1/miso_shift[15] )); BUS_Con_1_SLICE_70 \BUS_Con_1/SLICE_70 ( .C1(\r_data[9] ), .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[16] ), .C0(\r_data[8] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[15] ), .DI1(\BUS_Con_1/miso_shift_8[17] ), .DI0(\BUS_Con_1/miso_shift_8[16] ), .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[16] ), .Q0(\BUS_Con_1/miso_shift[16] ), .F1(\BUS_Con_1/miso_shift_8[17] ), .Q1(\BUS_Con_1/miso_shift[17] )); BUS_Con_1_SLICE_71 \BUS_Con_1/SLICE_71 ( .C1(\r_data[11] ), .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[18] ), .C0(\r_data[10] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[17] ), .DI1(\BUS_Con_1/miso_shift_8[19] ), .DI0(\BUS_Con_1/miso_shift_8[18] ), .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[18] ), .Q0(\BUS_Con_1/miso_shift[18] ), .F1(\BUS_Con_1/miso_shift_8[19] ), .Q1(\BUS_Con_1/miso_shift[19] )); BUS_Con_1_SLICE_72 \BUS_Con_1/SLICE_72 ( .C1(\r_data[13] ), .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[20] ), .C0(\r_data[12] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[19] ), .DI1(\BUS_Con_1/miso_shift_8[21] ), .DI0(\BUS_Con_1/miso_shift_8[20] ), .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[20] ), .Q0(\BUS_Con_1/miso_shift[20] ), .F1(\BUS_Con_1/miso_shift_8[21] ), .Q1(\BUS_Con_1/miso_shift[21] )); BUS_Con_1_SLICE_73 \BUS_Con_1/SLICE_73 ( .C1(\r_data[15] ), .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[22] ), .C0(\r_data[14] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[21] ), .DI1(\BUS_Con_1/miso_shift_8[23] ), .DI0(\BUS_Con_1/miso_shift_8[22] ), .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[22] ), .Q0(\BUS_Con_1/miso_shift[22] ), .F1(\BUS_Con_1/miso_shift_8[23] ), .Q1(\BUS_Con_1/miso_shift[23] )); BUS_Con_1_SLICE_74 \BUS_Con_1/SLICE_74 ( .C1(\r_data[17] ), .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[24] ), .C0(\r_data[16] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[23] ), .DI1(\BUS_Con_1/miso_shift_8[25] ), .DI0(\BUS_Con_1/miso_shift_8[24] ), .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[24] ), .Q0(\BUS_Con_1/miso_shift[24] ), .F1(\BUS_Con_1/miso_shift_8[25] ), .Q1(\BUS_Con_1/miso_shift[25] )); BUS_Con_1_SLICE_75 \BUS_Con_1/SLICE_75 ( .C1(\r_data[19] ), .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[26] ), .C0(\r_data[18] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[25] ), .DI1(\BUS_Con_1/miso_shift_8[27] ), .DI0(\BUS_Con_1/miso_shift_8[26] ), .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[26] ), .Q0(\BUS_Con_1/miso_shift[26] ), .F1(\BUS_Con_1/miso_shift_8[27] ), .Q1(\BUS_Con_1/miso_shift[27] )); BUS_Con_1_SLICE_76 \BUS_Con_1/SLICE_76 ( .C1(\r_data[21] ), .B1(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A1(\BUS_Con_1/miso_shift[28] ), .C0(\r_data[20] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[27] ), .DI1(\BUS_Con_1/miso_shift_8[29] ), .DI0(\BUS_Con_1/miso_shift_8[28] ), .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[28] ), .Q0(\BUS_Con_1/miso_shift[28] ), .F1(\BUS_Con_1/miso_shift_8[29] ), .Q1(\BUS_Con_1/miso_shift[29] )); BUS_Con_1_SLICE_77 \BUS_Con_1/SLICE_77 ( .D1(\BUS_Con_1/miso_shift17lt3 ), .C1(\BUS_Con_1/bit_cnt[5] ), .B1(\BUS_Con_1/bit_cnt[4] ), .A1(\BUS_Con_1/bit_cnt[3] ), .C0(\r_data[22] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[29] ), .DI0(\BUS_Con_1/miso_shift_8[30] ), .CE(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift_8[30] ), .Q0(\BUS_Con_1/miso_shift[30] ), .F1(\BUS_Con_1/miso_shift17lto5_i_o2 )); BUS_Con_1_SLICE_96 \BUS_Con_1/SLICE_96 ( .D1(i_rst_n_c), .C1(\BUS_Con_1/N_497 ), .B1(\BUS_Con_1/state[1] ), .A1(\BUS_Con_1/state[0] ), .D0(reg_busy), .C0(i_rst_n_c), .B0(\BUS_Con_1/N_504 ), .A0(\BUS_Con_1/N_495 ), .DI1(\BUS_Con_1/state_nss[1] ), .DI0(\BUS_Con_1/state_nss[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/state_nss[0] ), .Q0(\BUS_Con_1/state[0] ), .F1(\BUS_Con_1/state_nss[1] ), .Q1(\BUS_Con_1/state[1] )); CPLD_Con_1_SLICE_106 \CPLD_Con_1/SLICE_106 ( .D1(\DC_Con4[0] ), .C1(\DC_Con3[0] ), .B1(\DC_Con2[0] ), .A1(\DC_Con1[0] ), .D0(\DC_Con4[0] ), .C0(\DC_Con3[0] ), .B0(\DC_Con2[0] ), .A0(\DC_Con1[0] ), .DI1(\CPLD_Con_1/SUM1_0 ), .DI0(\CPLD_Con_1/SUM0_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/SUM0_0 ), .Q0(\CPLD_Con_1/dc_t[0] ), .F1(\CPLD_Con_1/SUM1_0 ), .Q1(\CPLD_Con_1/dc_t[1] )); CPLD_Con_1_SLICE_107 \CPLD_Con_1/SLICE_107 ( .C1(\CPLD_Con_1/un1_en_t_c2 ), .B1(\CPLD_Con_1/CO1_0 ), .A1(\CPLD_Con_1/CO1 ), .D0(\CPLD_Con_1/SUM1_0 ), .C0(\CPLD_Con_1/SUM0_0 ), .B0(\CPLD_Con_1/SUM1 ), .A0(\CPLD_Con_1/SUM0 ), .DI1(\CPLD_Con_1/un1_en_t[2] ), .DI0(\CPLD_Con_1/un1_en_t[1] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_en_t[1] ), .Q0(\CPLD_Con_1/en_t[1] ), .F1(\CPLD_Con_1/un1_en_t[2] ), .Q1(\CPLD_Con_1/en_t[2] )); CPLD_Con_1_SLICE_108 \CPLD_Con_1/SLICE_108 ( .D1(\DC_Con4[0] ), .C1(\DC_Con3[0] ), .B1(\DC_Con2[0] ), .A1(\DC_Con1[0] ), .B0(\CPLD_Con_1/CO1_0 ), .A0(\CPLD_Con_1/CO1 ), .DI0(\CPLD_Con_1/un1_en_t[3] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_en_t[3] ), .Q0(\CPLD_Con_1/en_t[3] ), .F1(\CPLD_Con_1/CO1_0 )); CPLD_Con_1_SLICE_109 \CPLD_Con_1/SLICE_109 ( .B1(i_rst_n_c), .A1(\CPLD_Con_1/RC_VSel40 ), .B0(i_rst_n_c), .A0(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .DI0(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .CE(\CPLD_Con_1/N_247 ), .LSR(o_con_done_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_Tx_1_sqmuxa ), .Q0(\CPLD_Con_1/exec_flag ), .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_a2_3_0 )); CPLD_Con_1_SLICE_110 \CPLD_Con_1/SLICE_110 ( .C1(i_rst_n_c), .B1(\CPLD_Con_1/un1_i_DC_Con1_2 ), .A1(\CPLD_Con_1/PMU_OC_1_0_sqmuxa ), .B0(i_rst_n_c), .A0(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .DI0(\CPLD_Con_1/RC_Tx_1_sqmuxa_fast ), .CE(\CPLD_Con_1/N_247 ), .LSR(o_con_done_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_Tx_1_sqmuxa_fast ), .Q0(\CPLD_Con_1/exec_flag_fast ), .F1(\CPLD_Con_1/N_331 )); CPLD_Con_1_SLICE_111 \CPLD_Con_1/SLICE_111 ( .D1(i_rst_n_c), .C1(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc6 ), .A1(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), .B0(i_rst_n_c), .A0(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .DI0(\CPLD_Con_1/RC_Tx_1_sqmuxa_rep1 ), .CE(\CPLD_Con_1/N_247 ), .LSR(o_con_done_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_Tx_1_sqmuxa_rep1 ), .Q0(\CPLD_Con_1/exec_flag_rep1 ), .F1(\CPLD_Con_1/N_122 )); CPLD_Con_1_SLICE_114 \CPLD_Con_1/SLICE_114 ( .D1(\freq4_relay[0] ), .C1(\freq3_relay[0] ), .B1(\freq2_relay[0] ), .A1(\freq1_relay[0] ), .D0(\freq4_relay[0] ), .C0(\freq3_relay[0] ), .B0(\freq2_relay[0] ), .A0(\freq1_relay[0] ), .DI1(\CPLD_Con_1/SUM1 ), .DI0(\CPLD_Con_1/SUM0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/SUM0 ), .Q0(\CPLD_Con_1/freq_t[0] ), .F1(\CPLD_Con_1/SUM1 ), .Q1(\CPLD_Con_1/freq_t[1] )); CPLD_Reg_1_SLICE_116 \CPLD_Reg_1/SLICE_116 ( .D1(\reg_addr[6] ), .C1(\reg_addr[5] ), .B1(\reg_addr[4] ), .A1(\CPLD_Reg_1/N_1133 ), .D0(con_exec), .C0(cmd_valid), .B0(\CPLD_Reg_1/state[0] ), .A0(\CPLD_Reg_1/err_flag8 ), .DI0(\CPLD_Reg_1/N_814 ), .CE(\CPLD_Reg_1/un9_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_814 ), .Q0(\CPLD_Reg_1/reg_err_flag ), .F1(\CPLD_Reg_1/err_flag8 )); CPLD_Reg_1_SLICE_212 \CPLD_Reg_1/SLICE_212 ( .D0(\w_data[23] ), .C0(o_con_done_c), .B0(\CPLD_Reg_1/state[1] ), .A0(\CPLD_Reg_1/regtable[1][23] ), .DI0(\CPLD_Reg_1/N_1059_i ), .CE(\CPLD_Reg_1/un10_i_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_1059_i ), .Q0(\CPLD_Reg_1/regtable[1][23] )); CPLD_Reg_1_SLICE_258 \CPLD_Reg_1/SLICE_258 ( .D1(\CPLD_Reg_1/state[0] ), .C1(\CPLD_Reg_1/N_26 ), .B1(\CPLD_Reg_1/N_23 ), .A1(\CPLD_Reg_1/N_22 ), .D0(cmd_valid), .C0(\CPLD_Reg_1/state[0] ), .B0(\CPLD_Reg_1/N_23 ), .A0(\CPLD_Reg_1/N_22 ), .DI1(\CPLD_Reg_1/state_ns[1] ), .DI0(\CPLD_Reg_1/state_ns[0] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/state_ns[0] ), .Q0(\CPLD_Reg_1/state[0] ), .F1(\CPLD_Reg_1/state_ns[1] ), .Q1(\CPLD_Reg_1/state[1] )); CPLD_Con_1_SLICE_307 \CPLD_Con_1/SLICE_307 ( .C1(\CPLD_Con_1/N_332 ), .B1(\CPLD_Con_1/N_249 ), .A1(\CPLD_Con_1/DMM_en_26_0_a3_0_3[1] ), .D0(\CPLD_Con_1/N_249 ), .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), .B0(\CPLD_Con_1/PMU_OC_1_cnst[0] ), .A0(\CPLD_Con_1/N_1_11 ), .DI1(\CPLD_Con_1/DMM_en_26[1] ), .DI0(\CPLD_Con_1/DMM_en_26[0] ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26[0] ), .Q0(\DMM_EN[0] ), .F1(\CPLD_Con_1/DMM_en_26[1] ), .Q1(\DMM_EN[1] )); CPLD_Con_1_SLICE_308 \CPLD_Con_1/SLICE_308 ( .C1(\CPLD_Con_1/N_331 ), .B1(\CPLD_Con_1/N_249 ), .A1(\CPLD_Con_1/DMM_en_26_0_a3_0_0[3] ), .D0(\CPLD_Con_1/N_249 ), .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), .B0(\CPLD_Con_1/N_1_11 ), .A0(\CPLD_Con_1/DMM_en_cnst[2] ), .DI1(\CPLD_Con_1/DMM_en_26[3] ), .DI0(\CPLD_Con_1/DMM_en_26[2] ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26[2] ), .Q0(\DMM_EN[2] ), .F1(\CPLD_Con_1/DMM_en_26[3] ), .Q1(\DMM_EN[3] )); CPLD_Con_1_SLICE_309 \CPLD_Con_1/SLICE_309 ( .D1(\CPLD_Con_1/N_249 ), .C1(\CPLD_Con_1/un1_i_DC_Con1[1] ), .B1(\CPLD_Con_1/N_5_11 ), .A1(\CPLD_Con_1/DMM_en_cnst[6] ), .D0(\CPLD_Con_1/N_249 ), .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), .B0(\CPLD_Con_1/N_5_11 ), .A0(\CPLD_Con_1/DMM_en_cnst[4] ), .DI1(\CPLD_Con_1/DMM_en_26[6] ), .DI0(\CPLD_Con_1/DMM_en_26[4] ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26[4] ), .Q0(\DMM_EN[4] ), .F1(\CPLD_Con_1/DMM_en_26[6] ), .Q1(\DMM_EN[6] )); CPLD_Con_1_SLICE_310 \CPLD_Con_1/SLICE_310 ( .D1(\DC_Con2[9] ), .C1(\CPLD_Con_1/un1_i_DC_Con2_1_0 ), .B1(\CPLD_Con_1/PMU_OC_212 ), .A1(\CPLD_Con_1/PMU_OC_2_cnst_1[16] ), .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/dc_slot_flag[1] ), .DI0(\CPLD_Con_1/DMM_en_26[5] ), .M0(\CPLD_Con_1/N_249 ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Con_1/DMM_en_26[5] ), .Q0(\DMM_EN[5] )); CPLD_Con_1_SLICE_311 \CPLD_Con_1/SLICE_311 ( .C1(\CPLD_Con_1/PMU_OC_2_cnst_1[16] ), .B1(\CPLD_Con_1/un1_i_DC_Con2_1lt8 ), .A1(\DC_Con2[9] ), .C0(\CPLD_Con_1/dc_slot_flag[1] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/un1_i_DC_Con1[1] ), .DI0(\CPLD_Con_1/DMM_en_26[7] ), .M0(\CPLD_Con_1/N_249 ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Con_1/DMM_en_26[7] ), .Q0(\DMM_EN[7] )); CPLD_Con_1_SLICE_312 \CPLD_Con_1/SLICE_312 ( .D1(\CPLD_Con_1/N_416 ), .C1(\CPLD_Con_1/N_249 ), .B1(\CPLD_Con_1/PMU_OC_313 ), .A1(\CPLD_Con_1/DMM_en_26_0_a2_0[9] ), .C0(\CPLD_Con_1/N_351 ), .B0(\CPLD_Con_1/N_249 ), .A0(\CPLD_Con_1/DMM_en_26_0_a2_0[8] ), .DI1(\CPLD_Con_1/DMM_en_26[9] ), .DI0(\CPLD_Con_1/DMM_en_26[8] ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26[8] ), .Q0(\DMM_EN[8] ), .F1(\CPLD_Con_1/DMM_en_26[9] ), .Q1(\DMM_EN[9] )); CPLD_Con_1_SLICE_313 \CPLD_Con_1/SLICE_313 ( .C1(\CPLD_Con_1/N_354 ), .B1(\CPLD_Con_1/N_249 ), .A1(\CPLD_Con_1/DMM_en_26_0_a2_0[11] ), .C0(\CPLD_Con_1/N_349 ), .B0(\CPLD_Con_1/N_249 ), .A0(\CPLD_Con_1/DMM_en_26_0_a2_0[10] ), .DI1(\CPLD_Con_1/DMM_en_26[11] ), .DI0(\CPLD_Con_1/DMM_en_26[10] ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26[10] ), .Q0(\DMM_EN[10] ), .F1(\CPLD_Con_1/DMM_en_26[11] ), .Q1(\DMM_EN[11] )); CPLD_Con_1_SLICE_314 \CPLD_Con_1/SLICE_314 ( .C1(\CPLD_Con_1/N_249 ), .B1(\CPLD_Con_1/N_51 ), .A1(\CPLD_Con_1/DMM_en_26_0_a3_1_0[14] ), .C0(\CPLD_Con_1/N_249 ), .B0(\CPLD_Con_1/N_134 ), .A0(\CPLD_Con_1/DMM_en_26_0_a3_2[12] ), .DI1(\CPLD_Con_1/DMM_en_26[14] ), .DI0(\CPLD_Con_1/DMM_en_26[12] ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26[12] ), .Q0(\DMM_EN[12] ), .F1(\CPLD_Con_1/DMM_en_26[14] ), .Q1(\DMM_EN[14] )); CPLD_Con_1_SLICE_315 \CPLD_Con_1/SLICE_315 ( .D1(\CPLD_Con_1/dc_slot_flag[3] ), .C1(\CPLD_Con_1/un1_i_DC_Con1[0] ), .B1(\CPLD_Con_1/un1_i_DC_Con1[1] ), .A1(i_rst_n_c), .D0(\CPLD_Con_1/DMM_en_26_0_a4_0[13] ), .C0(\CPLD_Con_1/DMM_en_26_0_a4_1_1_0[13] ), .B0(\CPLD_Con_1/PMU_OC_4_1_sqmuxa ), .A0(\CPLD_Con_1/N_59 ), .DI0(\CPLD_Con_1/DMM_en_26[13] ), .M0(\CPLD_Con_1/N_274 ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Con_1/DMM_en_26[13] ), .Q0(\DMM_EN[13] )); CPLD_Con_1_SLICE_316 \CPLD_Con_1/SLICE_316 ( .D1(\CPLD_Con_1/un1_i_DC_Con1[1] ), .C1(\CPLD_Con_1/un1_i_DC_Con1[0] ), .B1(\CPLD_Con_1/DMM_en_26_i_1[15] ), .A1(i_rst_n_c), .D0(\CPLD_Con_1/PMU_OC_4_1_sqmuxa ), .C0(\CPLD_Con_1/N_273 ), .B0(\CPLD_Con_1/DMM_en_26_i_1[15] ), .A0(i_rst_n_c), .DI0(\CPLD_Con_1/N_46_i ), .M0(\CPLD_Con_1/N_274 ), .CE(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Con_1/N_46_i ), .Q0(\DMM_EN[15] )); SLICE_317 SLICE_317( .D1(DPSFS_RC1), .C1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .B1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_a2_3_0 ), .A1(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 ), .D0(DPSFS_RC1), .C0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1 ), .B0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_0 ), .A0(\CPLD_Con_1/DPSFS_RC1e_1 ), .DI0(\CPLD_Con_1/DPSFS_RC1e_0 ), .M1(\BUS_Con_1.mosi_sync[0] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DPSFS_RC1e_0 ), .Q0(DPSFS_RC1), .F1(\CPLD_Con_1/DPSFS_RC1e_1 ), .Q1(\BUS_Con_1/mosi_sync[1] )); CPLD_Con_1_SLICE_318 \CPLD_Con_1/SLICE_318 ( .D1(\CPLD_Con_1/N_153 ), .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), .A0(\CPLD_Con_1/N_153 ), .DI1(\CPLD_Con_1/N_146_i ), .DI0(\CPLD_Con_1/N_145_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_145_i ), .Q0(\DPS_FS_1[0] ), .F1(\CPLD_Con_1/N_146_i ), .Q1(\DPS_FS_1[1] )); CPLD_Con_1_SLICE_319 \CPLD_Con_1/SLICE_319 ( .D1(\CPLD_Con_1/N_154 ), .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), .A0(\CPLD_Con_1/N_154 ), .DI1(\CPLD_Con_1/N_138_i ), .DI0(\CPLD_Con_1/N_137_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_137_i ), .Q0(\DPS_FS_1[2] ), .F1(\CPLD_Con_1/N_138_i ), .Q1(\DPS_FS_1[3] )); CPLD_Con_1_SLICE_320 \CPLD_Con_1/SLICE_320 ( .D1(\CPLD_Con_1/N_153 ), .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), .A0(\CPLD_Con_1/N_153 ), .DI1(\CPLD_Con_1/N_140_i ), .DI0(\CPLD_Con_1/N_139_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_139_i ), .Q0(\DPS_FS_1[4] ), .F1(\CPLD_Con_1/N_140_i ), .Q1(\DPS_FS_1[5] )); CPLD_Con_1_SLICE_321 \CPLD_Con_1/SLICE_321 ( .D1(\CPLD_Con_1/N_154 ), .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), .A0(\CPLD_Con_1/N_154 ), .DI1(\CPLD_Con_1/N_142_i ), .DI0(\CPLD_Con_1/N_141_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_141_i ), .Q0(\DPS_FS_1[6] ), .F1(\CPLD_Con_1/N_142_i ), .Q1(\DPS_FS_1[7] )); CPLD_Con_1_SLICE_322 \CPLD_Con_1/SLICE_322 ( .D1(\CPLD_Con_1/N_153 ), .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), .A0(\CPLD_Con_1/N_153 ), .DI1(\CPLD_Con_1/N_144_i ), .DI0(\CPLD_Con_1/N_143_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_143_i ), .Q0(\DPS_FS_1[8] ), .F1(\CPLD_Con_1/N_144_i ), .Q1(\DPS_FS_1[9] )); CPLD_Con_1_SLICE_323 \CPLD_Con_1/SLICE_323 ( .D1(\CPLD_Con_1/N_154 ), .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), .A0(\CPLD_Con_1/N_154 ), .DI1(\CPLD_Con_1/N_124_i ), .DI0(\CPLD_Con_1/N_120_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_120_i ), .Q0(\DPS_FS_1[10] ), .F1(\CPLD_Con_1/N_124_i ), .Q1(\DPS_FS_1[11] )); CPLD_Con_1_SLICE_324 \CPLD_Con_1/SLICE_324 ( .D1(\CPLD_Con_1/N_153 ), .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), .A0(\CPLD_Con_1/N_153 ), .DI1(\CPLD_Con_1/N_129_i ), .DI0(\CPLD_Con_1/N_125_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_125_i ), .Q0(\DPS_FS_1[12] ), .F1(\CPLD_Con_1/N_129_i ), .Q1(\DPS_FS_1[13] )); CPLD_Con_1_SLICE_325 \CPLD_Con_1/SLICE_325 ( .D1(\CPLD_Con_1/N_154 ), .C1(\DC_Con1[1] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .A1(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .D0(\DC_Con1[4] ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .B0(\DC_Con1[1] ), .A0(\CPLD_Con_1/N_154 ), .DI1(\CPLD_Con_1/N_136_i ), .DI0(\CPLD_Con_1/N_130_i ), .CE(\CPLD_Con_1/N_28 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_130_i ), .Q0(\DPS_FS_1[14] ), .F1(\CPLD_Con_1/N_136_i ), .Q1(\DPS_FS_1[15] )); CPLD_Con_1_SLICE_326 \CPLD_Con_1/SLICE_326 ( .D1(\CPLD_Con_1/N_406 ), .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\CPLD_Con_1/N_406 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_291_i ), .DI0(\CPLD_Con_1/N_290_i ), .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_290_i ), .Q0(\DPS_FS_2[0] ), .F1(\CPLD_Con_1/N_291_i ), .Q1(\DPS_FS_2[1] )); CPLD_Con_1_SLICE_327 \CPLD_Con_1/SLICE_327 ( .D1(\CPLD_Con_1/N_406 ), .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\CPLD_Con_1/N_406 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_293_i ), .DI0(\CPLD_Con_1/N_292_i ), .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_292_i ), .Q0(\DPS_FS_2[2] ), .F1(\CPLD_Con_1/N_293_i ), .Q1(\DPS_FS_2[3] )); CPLD_Con_1_SLICE_328 \CPLD_Con_1/SLICE_328 ( .D1(\CPLD_Con_1/N_406 ), .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\CPLD_Con_1/N_406 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_279_i ), .DI0(\CPLD_Con_1/N_294_i ), .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_294_i ), .Q0(\DPS_FS_2[4] ), .F1(\CPLD_Con_1/N_279_i ), .Q1(\DPS_FS_2[5] )); CPLD_Con_1_SLICE_329 \CPLD_Con_1/SLICE_329 ( .D1(\CPLD_Con_1/N_406 ), .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\CPLD_Con_1/N_406 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_281_i ), .DI0(\CPLD_Con_1/N_280_i ), .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_280_i ), .Q0(\DPS_FS_2[6] ), .F1(\CPLD_Con_1/N_281_i ), .Q1(\DPS_FS_2[7] )); CPLD_Con_1_SLICE_330 \CPLD_Con_1/SLICE_330 ( .D1(\CPLD_Con_1/N_407 ), .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\CPLD_Con_1/N_407 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_283_i ), .DI0(\CPLD_Con_1/N_282_i ), .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_282_i ), .Q0(\DPS_FS_2[8] ), .F1(\CPLD_Con_1/N_283_i ), .Q1(\DPS_FS_2[9] )); CPLD_Con_1_SLICE_331 \CPLD_Con_1/SLICE_331 ( .D1(\CPLD_Con_1/N_407 ), .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\CPLD_Con_1/N_407 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_285_i ), .DI0(\CPLD_Con_1/N_284_i ), .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_284_i ), .Q0(\DPS_FS_2[10] ), .F1(\CPLD_Con_1/N_285_i ), .Q1(\DPS_FS_2[11] )); CPLD_Con_1_SLICE_332 \CPLD_Con_1/SLICE_332 ( .D1(\CPLD_Con_1/N_407 ), .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\CPLD_Con_1/N_407 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_287_i ), .DI0(\CPLD_Con_1/N_286_i ), .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_286_i ), .Q0(\DPS_FS_2[12] ), .F1(\CPLD_Con_1/N_287_i ), .Q1(\DPS_FS_2[13] )); CPLD_Con_1_SLICE_333 \CPLD_Con_1/SLICE_333 ( .D1(\CPLD_Con_1/N_407 ), .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\CPLD_Con_1/N_407 ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), .DI1(\CPLD_Con_1/N_289_i ), .DI0(\CPLD_Con_1/N_288_i ), .CE(\CPLD_Con_1/N_26 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_288_i ), .Q0(\DPS_FS_2[14] ), .F1(\CPLD_Con_1/N_289_i ), .Q1(\DPS_FS_2[15] )); CPLD_Con_1_SLICE_334 \CPLD_Con_1/SLICE_334 ( .D1(\CPLD_Con_1/N_392 ), .C1(\CPLD_Con_1/N_220 ), .B1(\CPLD_Con_1/N_169 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), .C0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .B0(\CPLD_Con_1/DPS_FS_3_9_i_a2_4[0] ), .A0(\CPLD_Con_1/DPS_FS_3_9_i_a2_1[0] ), .DI1(\CPLD_Con_1/N_329_i ), .DI0(\CPLD_Con_1/N_183_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_183_i ), .Q0(\DPS_FS_3[0] ), .F1(\CPLD_Con_1/N_329_i ), .Q1(\DPS_FS_3[1] )); CPLD_Con_1_SLICE_335 \CPLD_Con_1/SLICE_335 ( .D1(\CPLD_Con_1/N_392 ), .C1(\CPLD_Con_1/N_240 ), .B1(\CPLD_Con_1/N_169 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .A0(\CPLD_Con_1/N_67_0 ), .DI1(\CPLD_Con_1/N_312_i ), .DI0(\CPLD_Con_1/N_330_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_330_i ), .Q0(\DPS_FS_3[2] ), .F1(\CPLD_Con_1/N_312_i ), .Q1(\DPS_FS_3[3] )); CPLD_Con_1_SLICE_336 \CPLD_Con_1/SLICE_336 ( .D1(\CPLD_Con_1/N_392 ), .C1(\CPLD_Con_1/N_219 ), .B1(\CPLD_Con_1/N_169 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .A0(\CPLD_Con_1/N_69_0 ), .DI1(\CPLD_Con_1/N_315_i ), .DI0(\CPLD_Con_1/N_314_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_314_i ), .Q0(\DPS_FS_3[4] ), .F1(\CPLD_Con_1/N_315_i ), .Q1(\DPS_FS_3[5] )); CPLD_Con_1_SLICE_337 \CPLD_Con_1/SLICE_337 ( .D1(\CPLD_Con_1/N_392 ), .C1(\CPLD_Con_1/N_241 ), .B1(\CPLD_Con_1/N_169 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .A0(\CPLD_Con_1/N_71_0 ), .DI1(\CPLD_Con_1/N_317_i ), .DI0(\CPLD_Con_1/N_316_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_316_i ), .Q0(\DPS_FS_3[6] ), .F1(\CPLD_Con_1/N_317_i ), .Q1(\DPS_FS_3[7] )); CPLD_Con_1_SLICE_338 \CPLD_Con_1/SLICE_338 ( .D1(\CPLD_Con_1/N_392 ), .C1(\CPLD_Con_1/N_220 ), .B1(\CPLD_Con_1/N_169 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .A0(\CPLD_Con_1/DPS_FS_3_9_i_a2_0[8] ), .DI1(\CPLD_Con_1/N_178_i ), .DI0(\CPLD_Con_1/N_176_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_176_i ), .Q0(\DPS_FS_3[8] ), .F1(\CPLD_Con_1/N_178_i ), .Q1(\DPS_FS_3[9] )); CPLD_Con_1_SLICE_339 \CPLD_Con_1/SLICE_339 ( .D1(\CPLD_Con_1/N_392 ), .C1(\CPLD_Con_1/N_240 ), .B1(\CPLD_Con_1/N_169 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .A0(\CPLD_Con_1/N_67_0 ), .DI1(\CPLD_Con_1/N_180_i ), .DI0(\CPLD_Con_1/N_318_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_318_i ), .Q0(\DPS_FS_3[10] ), .F1(\CPLD_Con_1/N_180_i ), .Q1(\DPS_FS_3[11] )); CPLD_Con_1_SLICE_340 \CPLD_Con_1/SLICE_340 ( .D1(\CPLD_Con_1/N_392 ), .C1(\CPLD_Con_1/N_219 ), .B1(\CPLD_Con_1/N_169 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .A0(\CPLD_Con_1/N_69_0 ), .DI1(\CPLD_Con_1/N_173_i ), .DI0(\CPLD_Con_1/N_319_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_319_i ), .Q0(\DPS_FS_3[12] ), .F1(\CPLD_Con_1/N_173_i ), .Q1(\DPS_FS_3[13] )); CPLD_Con_1_SLICE_341 \CPLD_Con_1/SLICE_341 ( .D1(\CPLD_Con_1/N_392 ), .C1(\CPLD_Con_1/N_241 ), .B1(\CPLD_Con_1/N_169 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\CPLD_Con_1/N_392 ), .C0(\CPLD_Con_1/N_169 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .A0(\CPLD_Con_1/N_71_0 ), .DI1(\CPLD_Con_1/N_174_i ), .DI0(\CPLD_Con_1/N_305_i ), .CE(\CPLD_Con_1/N_24 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_305_i ), .Q0(\DPS_FS_3[14] ), .F1(\CPLD_Con_1/N_174_i ), .Q1(\DPS_FS_3[15] )); CPLD_Con_1_SLICE_342 \CPLD_Con_1/SLICE_342 ( .D1(\CPLD_Con_1/N_408 ), .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), .A0(\CPLD_Con_1/N_408 ), .DI1(\CPLD_Con_1/N_307_i ), .DI0(\CPLD_Con_1/N_306_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_306_i ), .Q0(\DPS_FS_4[0] ), .F1(\CPLD_Con_1/N_307_i ), .Q1(\DPS_FS_4[1] )); CPLD_Con_1_SLICE_343 \CPLD_Con_1/SLICE_343 ( .D1(\CPLD_Con_1/N_409 ), .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), .A0(\CPLD_Con_1/N_409 ), .DI1(\CPLD_Con_1/N_309_i ), .DI0(\CPLD_Con_1/N_308_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_308_i ), .Q0(\DPS_FS_4[2] ), .F1(\CPLD_Con_1/N_309_i ), .Q1(\DPS_FS_4[3] )); CPLD_Con_1_SLICE_344 \CPLD_Con_1/SLICE_344 ( .D1(\CPLD_Con_1/N_408 ), .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), .A0(\CPLD_Con_1/N_408 ), .DI1(\CPLD_Con_1/N_311_i ), .DI0(\CPLD_Con_1/N_310_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_310_i ), .Q0(\DPS_FS_4[4] ), .F1(\CPLD_Con_1/N_311_i ), .Q1(\DPS_FS_4[5] )); CPLD_Con_1_SLICE_345 \CPLD_Con_1/SLICE_345 ( .D1(\CPLD_Con_1/N_409 ), .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), .A0(\CPLD_Con_1/N_409 ), .DI1(\CPLD_Con_1/N_296_i ), .DI0(\CPLD_Con_1/N_295_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_295_i ), .Q0(\DPS_FS_4[6] ), .F1(\CPLD_Con_1/N_296_i ), .Q1(\DPS_FS_4[7] )); CPLD_Con_1_SLICE_346 \CPLD_Con_1/SLICE_346 ( .D1(\CPLD_Con_1/N_408 ), .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), .A0(\CPLD_Con_1/N_408 ), .DI1(\CPLD_Con_1/N_298_i ), .DI0(\CPLD_Con_1/N_297_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_297_i ), .Q0(\DPS_FS_4[8] ), .F1(\CPLD_Con_1/N_298_i ), .Q1(\DPS_FS_4[9] )); CPLD_Con_1_SLICE_347 \CPLD_Con_1/SLICE_347 ( .D1(\CPLD_Con_1/N_409 ), .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), .A0(\CPLD_Con_1/N_409 ), .DI1(\CPLD_Con_1/N_300_i ), .DI0(\CPLD_Con_1/N_299_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_299_i ), .Q0(\DPS_FS_4[10] ), .F1(\CPLD_Con_1/N_300_i ), .Q1(\DPS_FS_4[11] )); CPLD_Con_1_SLICE_348 \CPLD_Con_1/SLICE_348 ( .D1(\CPLD_Con_1/N_408 ), .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), .A0(\CPLD_Con_1/N_408 ), .DI1(\CPLD_Con_1/N_302_i ), .DI0(\CPLD_Con_1/N_301_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_301_i ), .Q0(\DPS_FS_4[12] ), .F1(\CPLD_Con_1/N_302_i ), .Q1(\DPS_FS_4[13] )); CPLD_Con_1_SLICE_349 \CPLD_Con_1/SLICE_349 ( .D1(\CPLD_Con_1/N_409 ), .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .D0(\DC_Con4[4] ), .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .B0(\DC_Con4[1] ), .A0(\CPLD_Con_1/N_409 ), .DI1(\CPLD_Con_1/N_304_i ), .DI0(\CPLD_Con_1/N_303_i ), .CE(\CPLD_Con_1/un1_exec_flag_10_i_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_303_i ), .Q0(\DPS_FS_4[14] ), .F1(\CPLD_Con_1/N_304_i ), .Q1(\DPS_FS_4[15] )); CPLD_Con_1_SLICE_350 \CPLD_Con_1/SLICE_350 ( .D1(\FSMC[1] ), .C1(\CPLD_Con_1/RC_VSel39 ), .B1(\CPLD_Con_1/DPS_FSMMCe_1_0[5] ), .A1(i_rst_n_c), .D0(\FSMC[0] ), .C0(\CPLD_Con_1/RC_VSel38 ), .B0(\CPLD_Con_1/DPS_FSMMCe_1_0[5] ), .A0(i_rst_n_c), .DI1(\CPLD_Con_1/DPS_FSMCd_0[1] ), .DI0(\CPLD_Con_1/DPS_FSMCd_0[0] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DPS_FSMCd_0[0] ), .Q0(\FSMC[0] ), .F1(\CPLD_Con_1/DPS_FSMCd_0[1] ), .Q1(\FSMC[1] )); CPLD_Con_1_SLICE_351 \CPLD_Con_1/SLICE_351 ( .D1(\FSMC[3] ), .C1(\CPLD_Con_1/DPS_FSMC_RNO_0[3] ), .B1(\CPLD_Con_1/DPS_FSMMCe_1_0[5] ), .A1(i_rst_n_c), .D0(\FSMC[2] ), .C0(\CPLD_Con_1/RC_VSel40 ), .B0(\CPLD_Con_1/DPS_FSMMCe_1_0[5] ), .A0(i_rst_n_c), .DI1(\CPLD_Con_1/DPS_FSMCd_0[3] ), .DI0(\CPLD_Con_1/DPS_FSMCd_0[2] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DPS_FSMCd_0[2] ), .Q0(\FSMC[2] ), .F1(\CPLD_Con_1/DPS_FSMCd_0[3] ), .Q1(\FSMC[3] )); CPLD_Con_1_SLICE_352 \CPLD_Con_1/SLICE_352 ( .D1(\FSMMC[5] ), .C1(\CPLD_Con_1/dc_slot_flag[1] ), .B1(\CPLD_Con_1/DPS_FSMMCe_N_2L1 ), .A1(\CPLD_Con_1/DPS_FSMMCe_1_0[5] ), .D0(\FSMMC[4] ), .C0(\CPLD_Con_1/DPS_FSMMCe_1[4] ), .B0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1 ), .A0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_0 ), .DI1(\CPLD_Con_1/DPS_FSMMCe_0[5] ), .DI0(\CPLD_Con_1/DPS_FSMMCe_0[4] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DPS_FSMMCe_0[4] ), .Q0(\FSMMC[4] ), .F1(\CPLD_Con_1/DPS_FSMMCe_0[5] ), .Q1(\FSMMC[5] )); CPLD_Con_1_SLICE_353 \CPLD_Con_1/SLICE_353 ( .C1(\CPLD_Con_1/N_65 ), .B1(\CPLD_Con_1/N_41 ), .A1(\CPLD_Con_1/RC_RLSel_13_0_iv_1[1] ), .D0(\CPLD_Con_1/N_80 ), .C0(\CPLD_Con_1/N_73 ), .B0(\CPLD_Con_1/un20_RC_RLSel_m[0] ), .A0(\CPLD_Con_1/RC_RLSel_13_0_iv_i_1[0] ), .DI1(\CPLD_Con_1/RC_RLSel_13_0_iv_i[1] ), .DI0(\CPLD_Con_1/RC_RLSel_13_0_iv_i[0] ), .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_0_iv_i[0] ), .Q0(\RC_RLSel[0] ), .F1(\CPLD_Con_1/RC_RLSel_13_0_iv_i[1] ), .Q1(\RC_RLSel[1] )); CPLD_Con_1_SLICE_354 \CPLD_Con_1/SLICE_354 ( .D1(\CPLD_Con_1/N_65 ), .C1(\CPLD_Con_1/N_45 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[3] ), .A1(\CPLD_Con_1/RC_RLSel_13_0_iv_0[3] ), .D0(\CPLD_Con_1/un95_RC_RLSel_m[2] ), .C0(\CPLD_Con_1/un70_RC_RLSel_m[2] ), .B0(\CPLD_Con_1/un45_RC_RLSel_m[2] ), .A0(\CPLD_Con_1/un20_RC_RLSel_m[2] ), .DI1(\CPLD_Con_1/RC_RLSel_13_0_iv_i[3] ), .DI0(\CPLD_Con_1/RC_RLSel_13_0_iv_i[2] ), .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_0_iv_i[2] ), .Q0(\RC_RLSel[2] ), .F1(\CPLD_Con_1/RC_RLSel_13_0_iv_i[3] ), .Q1(\RC_RLSel[3] )); CPLD_Con_1_SLICE_355 \CPLD_Con_1/SLICE_355 ( .D1(\CPLD_Con_1/un70_RC_RLSel_m[5] ), .C1(\CPLD_Con_1/un20_RC_RLSel_m[5] ), .B1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[5] ), .D0(\CPLD_Con_1/N_48 ), .C0(\CPLD_Con_1/N_43 ), .B0(\CPLD_Con_1/un20_RC_RLSel_m[4] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_1[4] ), .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[5] ), .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[4] ), .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[4] ), .Q0(\RC_RLSel[4] ), .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[5] ), .Q1(\RC_RLSel[5] )); CPLD_Con_1_SLICE_356 \CPLD_Con_1/SLICE_356 ( .D1(\CPLD_Con_1/N_65 ), .C1(\CPLD_Con_1/N_64 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[7] ), .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[7] ), .D0(\CPLD_Con_1/N_81 ), .C0(\CPLD_Con_1/N_80 ), .B0(\CPLD_Con_1/un95_RC_RLSel_m[6] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_i_1[6] ), .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[7] ), .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[6] ), .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[6] ), .Q0(\RC_RLSel[6] ), .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[7] ), .Q1(\RC_RLSel[7] )); CPLD_Con_1_SLICE_357 \CPLD_Con_1/SLICE_357 ( .D1(\CPLD_Con_1/N_47 ), .C1(\CPLD_Con_1/N_41 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[9] ), .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[9] ), .D0(\CPLD_Con_1/N_66 ), .C0(\CPLD_Con_1/N_41 ), .B0(\CPLD_Con_1/un20_RC_RLSel_m[8] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_1[8] ), .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[9] ), .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[8] ), .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[8] ), .Q0(\RC_RLSel[8] ), .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[9] ), .Q1(\RC_RLSel[9] )); CPLD_Con_1_SLICE_358 \CPLD_Con_1/SLICE_358 ( .D1(\CPLD_Con_1/N_47 ), .C1(\CPLD_Con_1/N_45 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[11] ), .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[11] ), .D0(\CPLD_Con_1/N_66 ), .C0(\CPLD_Con_1/N_45 ), .B0(\CPLD_Con_1/un20_RC_RLSel_m[10] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_1[10] ), .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[11] ), .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[10] ), .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[10] ), .Q0(\RC_RLSel[10] ), .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[11] ), .Q1(\RC_RLSel[11] )); CPLD_Con_1_SLICE_359 \CPLD_Con_1/SLICE_359 ( .D1(\CPLD_Con_1/N_47 ), .C1(\CPLD_Con_1/N_43 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[13] ), .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[13] ), .D0(\CPLD_Con_1/N_66 ), .C0(\CPLD_Con_1/N_43 ), .B0(\CPLD_Con_1/un20_RC_RLSel_m[12] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_1[12] ), .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[13] ), .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[12] ), .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[12] ), .Q0(\RC_RLSel[12] ), .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[13] ), .Q1(\RC_RLSel[13] )); CPLD_Con_1_SLICE_360 \CPLD_Con_1/SLICE_360 ( .D1(\CPLD_Con_1/N_64 ), .C1(\CPLD_Con_1/N_47 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[15] ), .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[15] ), .D0(\CPLD_Con_1/N_66 ), .C0(\CPLD_Con_1/N_64 ), .B0(\CPLD_Con_1/un20_RC_RLSel_m[14] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_1[14] ), .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[15] ), .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[14] ), .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[14] ), .Q0(\RC_RLSel[14] ), .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[15] ), .Q1(\RC_RLSel[15] )); CPLD_Con_1_SLICE_361 \CPLD_Con_1/SLICE_361 ( .D1(\CPLD_Con_1/un70_RC_RLSel_m[17] ), .C1(\CPLD_Con_1/un45_RC_RLSel_m[17] ), .B1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .A1(\CPLD_Con_1/RC_RLSel_13_iv_1[17] ), .D0(\CPLD_Con_1/un70_RC_RLSel_m[16] ), .C0(\CPLD_Con_1/un45_RC_RLSel_m[16] ), .B0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_1[16] ), .DI1(\CPLD_Con_1/RC_RLSel_13_iv_i[17] ), .DI0(\CPLD_Con_1/RC_RLSel_13_iv_i[16] ), .CE(\CPLD_Con_1/un1_exec_flag_1_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_i[16] ), .Q0(\RC_RLSel[16] ), .F1(\CPLD_Con_1/RC_RLSel_13_iv_i[17] ), .Q1(\RC_RLSel[17] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_370 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_370 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6 ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_374 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_374 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_65 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast ) , .B0(jtaghub16_jshift), .A0(jtaghub16_jce2), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d1 ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d1 ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4360 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_377 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_377 ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk_3[0] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[0] ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk_3[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_379 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_379 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) , .B0(jtaghub16_ip_enable0), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_57 ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_57 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_387 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_387 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) , .A1(jtaghub16_ip_enable0), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67_i ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_390 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_390 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3_1[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3[0] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[0] ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3_1[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_392 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_392 ( .D1(jtaghub16_jce2), .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_2_m_0 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_2_m_0 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_393 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_393 ( .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker ) , .C0(jtaghub16_jtdi), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_65 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4323_i ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4323_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_399 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_399 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] ) , .A1(jtaghub16_jtdi), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] ) , .C0(jtaghub16_jtdi), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_65 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_48_i ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_48_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_400 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_400 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_909 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_893 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_401 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_401 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_941 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_925 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_402 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_402 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_973 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_957 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_403 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_403 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1005 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_989 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_404 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_404 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1037 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1021 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_405 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_405 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1069 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1053 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_406 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_406 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1101 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1085 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_407 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_407 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1133 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1117 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_408 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_408 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1165 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1149 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_409 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_409 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1197 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1181 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_410 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_410 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1229 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1213 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_411 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_411 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1261 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1245 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_412 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_412 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1293 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1277 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_413 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_413 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1325 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1309 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_414 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_414 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1357 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1341 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_415 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_415 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1389 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1373 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_416 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_416 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1421 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1405 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_417 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_417 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1453 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1437 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_418 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_418 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1485 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1469 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_419 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_419 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1517 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1501 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_420 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_420 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1549 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1533 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_421 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_421 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1581 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1565 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_422 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_422 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1613 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1597 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_423 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_423 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1645 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1629 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[47] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[47] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_424 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_424 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1677 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1661 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[49] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[48] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[48] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[49] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_425 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_425 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1709 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1693 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[51] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[50] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[50] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[51] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_426 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_426 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1741 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1725 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[53] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[52] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[52] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[53] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_427 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_427 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1773 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1757 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[55] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[54] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[54] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[55] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_428 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_428 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1805 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1789 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[57] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[56] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[56] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[57] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_429 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_429 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1837 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1821 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[59] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[58] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[58] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[59] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_430 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_430 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1869 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1853 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[61] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[60] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[60] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[61] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_431 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_431 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1901 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1885 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[63] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[62] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[62] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[63] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_432 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_432 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1933 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1917 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[65] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[64] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[64] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[65] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_433 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_433 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1965 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1949 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[67] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[66] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[66] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[67] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_434 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_434 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1997 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1981 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[69] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[68] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[68] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[69] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[69] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_435 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_435 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2029 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2013 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[71] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[70] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[70] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[71] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_436 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_436 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2061 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2045 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[73] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[72] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[72] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[73] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_437 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_437 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2093 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2077 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[75] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[74] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[74] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[75] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_438 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_438 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2125 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2109 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[77] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[76] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[76] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[77] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_439 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_439 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2157 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2141 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[79] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[78] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[78] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[79] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_440 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_440 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2189 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2173 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[81] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[80] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[80] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[81] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_441 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_441 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2221 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2205 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[83] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[82] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[82] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[83] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_442 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_442 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2253 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2237 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[85] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[84] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[84] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[85] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_443 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_443 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2285 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2269 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[87] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[86] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[86] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[87] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_444 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_444 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2317 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2301 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[89] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[88] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[88] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[89] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_445 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_445 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2349 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2333 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[91] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[90] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[90] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[91] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_446 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_446 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2381 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2365 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[93] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[92] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[92] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[93] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_447 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_447 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2413 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2397 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[95] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[94] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[94] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[95] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_448 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_448 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2445 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2429 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[97] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[96] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[96] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[97] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_449 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_449 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2477 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2461 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[99] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[98] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[98] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[99] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_450 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_450 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2509 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2493 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[101] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[100] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[100] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[101] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_451 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_451 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2541 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2525 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[103] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[102] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[102] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[103] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_452 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_452 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2573 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2557 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[105] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[104] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[104] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[105] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_453 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_453 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2605 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2589 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[107] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[106] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[106] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[107] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_454 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_454 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2637 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2621 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[109] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[108] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[108] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[109] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_455 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_455 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2669 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2653 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[111] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[110] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[110] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[111] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_456 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_456 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2701 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2685 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[113] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[112] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[112] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[113] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_457 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_457 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2733 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2717 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[115] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[114] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[114] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[115] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_458 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_458 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2765 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2749 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[117] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[116] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[116] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[117] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_459 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_459 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2797 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2781 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[119] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[118] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[118] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[119] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_460 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_460 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2829 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2813 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[121] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[120] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[120] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[121] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_461 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_461 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2861 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2845 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[123] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[122] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[122] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[123] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_462 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_462 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2893 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2877 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[125] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[124] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[124] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[125] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_463 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_463 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2925 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2909 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[127] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[126] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[126] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[127] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_464 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_464 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2957 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2941 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[129] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[128] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[128] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[129] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_465 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_465 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2989 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2973 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[131] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[130] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[130] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[131] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_466 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_466 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3021 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3005 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[133] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[132] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[132] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[133] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_467 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_467 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3053 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3037 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[135] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[134] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[134] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[135] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_468 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_468 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3085 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3069 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[137] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[136] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[136] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[137] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_469 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_469 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[140] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3117 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[139] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3101 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[139] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[139] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[139] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_470 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_470 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[142] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3149 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[141] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3133 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[141] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[140] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[140] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[140] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[141] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[141] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_471 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_471 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[144] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3181 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[143] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3165 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[143] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[142] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[142] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[142] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[143] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[143] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_472 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_472 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[146] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3213 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[145] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3197 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[145] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[144] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[144] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[144] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[145] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[145] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_473 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_473 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[148] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3245 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[147] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3229 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[147] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[146] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[146] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[146] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[147] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[147] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_474 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_474 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[150] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3277 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[149] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3261 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[149] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[148] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[148] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[148] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[149] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[149] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_475 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_475 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[152] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3309 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[151] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3293 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[151] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[150] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[150] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[150] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[151] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[151] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_476 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_476 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[154] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3341 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[153] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3325 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[153] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[152] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[152] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[152] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[153] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[153] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_477 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_477 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[156] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3373 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[155] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3357 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[155] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[154] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[154] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[154] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[155] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[155] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_478 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_478 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[158] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3405 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[157] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3389 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[157] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[156] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[156] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[156] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[157] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[157] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_479 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_479 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[160] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3437 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[159] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3421 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[159] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[158] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[158] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[158] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[159] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[159] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_480 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_480 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[162] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3469 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[161] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3453 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[161] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[160] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[160] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[160] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[161] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[161] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_481 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_481 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[164] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3501 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[163] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3485 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[163] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[162] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[162] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[162] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[163] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[163] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_482 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_482 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[166] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3533 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[165] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3517 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[165] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[164] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[164] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[164] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[165] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[165] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_483 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_483 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[168] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3565 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[167] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3549 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[167] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[166] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[166] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[166] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[167] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[167] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_484 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_484 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[170] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3597 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[169] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3581 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[169] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[168] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[168] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[168] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[169] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[169] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_485 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_485 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[172] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3629 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[171] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3613 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[171] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[170] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[170] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[170] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[171] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[171] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_486 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_486 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[174] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3661 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[173] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3645 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[173] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[172] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[172] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[172] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[173] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[173] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_487 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_487 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[176] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3693 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[175] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3677 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[175] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[174] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[174] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[174] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[175] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[175] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_488 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_488 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[178] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3725 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[177] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3709 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[177] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[176] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[176] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[176] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[177] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[177] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_489 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_489 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[180] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3757 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[179] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3741 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[179] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[178] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[178] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[178] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[179] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[179] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_490 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_490 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[182] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3789 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[181] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3773 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[181] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[180] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[180] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[180] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[181] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[181] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_491 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_491 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[184] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3821 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[183] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3805 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[183] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[182] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[182] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[182] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[183] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[183] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_492 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_492 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[186] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3853 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[185] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3837 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[185] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[184] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[184] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[184] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[185] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[185] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_493 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_493 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[188] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3885 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[187] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3869 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[187] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[186] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[186] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[186] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[187] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[187] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_494 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_494 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[190] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3917 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[189] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3901 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[189] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[188] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[188] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[188] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[189] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[189] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_495 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_495 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[192] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3949 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[191] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3933 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[191] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[190] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[190] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[190] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[191] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[191] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_496 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_496 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[194] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3981 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[193] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3965 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[193] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[192] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[192] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[192] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[193] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[193] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_497 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_497 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[196] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4013 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[195] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3997 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[195] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[194] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[194] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[194] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[195] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[195] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_498 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_498 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[198] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4045 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[197] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4029 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[197] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[196] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[196] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[196] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[197] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[197] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_499 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_499 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[200] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4077 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[199] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4061 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[199] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[198] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[198] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[198] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[199] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[199] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_500 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_500 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[202] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4109 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[201] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4093 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[201] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[200] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[200] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[200] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[201] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[201] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_501 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_501 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[204] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4141 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[203] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4125 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[203] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[202] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[202] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[202] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[203] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[203] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_502 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_502 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[206] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4173 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[205] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4157 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[205] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[204] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[204] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[204] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[205] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[205] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_503 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_503 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[208] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4205 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[207] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4189 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[207] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[206] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[206] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[206] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[207] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[207] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_504 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_504 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_213_3774_i_m2_i_0 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[210] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[209] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_74 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4322_i ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_73 ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_73 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[208] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4322_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[209] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_505 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_505 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_211_3810_i_m2_i_0 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[212] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_212_3792_i_m2_i_0 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[211] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4320_i ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4321_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4321_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[210] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4320_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[211] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_506 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_506 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[212] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[211] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[212] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4319_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4319_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[212] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_211_3810_i_m2_i_0 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_507 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_507 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_0 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_0 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d3 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_508 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_508 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_1[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[1] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_509 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_509 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_123_i ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_123_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_510 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_510 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[5] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[5] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_511 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_511 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[7] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[7] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_512 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_512 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_122_i ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_122_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_513 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_513 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_120_i ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_121_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_121_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_120_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_514 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_514 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[13] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4378_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4378_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[13] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_515 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_515 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[15] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_118_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_118_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[15] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_517 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_517 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[1] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_518 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_518 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[3] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_519 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_519 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[5] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[4] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_520 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_520 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[7] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[6] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[7] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[7] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_521 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_521 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc19_i_0 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[1] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_522 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_522 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] ) , .C0(jtaghub16_jshift), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[3] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[3] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_523 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_523 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ) , .C0(jtaghub16_jshift), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[5] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[5] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_524 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_524 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] ) , .C0(jtaghub16_jshift), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[7] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[7] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_525 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_525 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] ) , .C0(jtaghub16_jshift), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[9] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[8] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[9] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_526 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_526 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] ) , .C0(jtaghub16_jshift), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[11] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[10] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[10] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[11] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_527 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_527 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] ) , .C0(jtaghub16_jshift), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[13] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[12] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[12] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[13] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_528 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_528 ( .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] ) , .C0(jtaghub16_jshift), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[15] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[14] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[14] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[15] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_529 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_529 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .C0(jtaghub16_jshift), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_125 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5 ) , .M1(jtaghub16_jshift), .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_125 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_530 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_530 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .B0(jtaghub16_jshift), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_105 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3 ) , .M1(jtaghub16_jshift), .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_105 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_531 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_531 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3 ) , .M1(jtaghub16_jce2), .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_532 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_532 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_3 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_792 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_804 ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_353_i ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_i[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_i[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_353_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_533 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_533 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_2_1_1 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_846 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_4 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_a2_0_0 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_388 ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_380_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_380_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_388 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_534 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_534 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_1_0 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_844_1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_843 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_1_1_0 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_878 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_830 ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_427 ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_407 ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_407 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_427 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[5] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_535 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_535 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_2 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_0 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_1_0 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_878 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_826 ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_481_i ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_448 ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_448 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_481_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[7] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_536 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_536 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_282_1_1 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_253_1_0 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_844_1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_840 ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_510 ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_489 ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_489 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[8] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_510 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[9] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_537 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_537 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_801 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_551 ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_539 ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_539 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[10] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_551 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[11] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_538 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_538 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_880 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_27_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_27_i ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[13] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_835 )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_540 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_540 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_7_i_0_a2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_655_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_655_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_7_i_0_a2 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_541 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_541 ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_39 ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_39 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_542 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_542 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_a2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_649_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_649_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_a2 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_543 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_543 ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_9 ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0 ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_9 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_544 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_544 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_0_0_a2_0_0 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_0_0_a2_0_0 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_545 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_545 ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_648_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_648_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_551 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_551 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_7 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_6 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_0 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_654_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_654_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_562 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_562 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[1] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[1] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_563 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_563 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[3] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[3] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[3] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_564 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_564 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[5] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[4] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[5] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[5] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_565 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_565 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[7] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[6] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[7] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[7] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_566 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_566 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[9] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s[8] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[9] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[8] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm[9] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_567 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_567 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_568 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_568 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[1] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[1] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_569 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_569 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[3] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[3] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[3] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_570 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_570 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[5] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[4] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[5] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[5] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_571 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_571 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[7] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[6] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[7] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[7] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_572 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_572 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[9] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s[8] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[9] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[8] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm[9] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_573 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_573 ( .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/VCC\000/BUF1 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[1] ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/VCC\000/BUF1 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_576 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_576 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_67 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen_jtck ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen_jtck )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_578 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_578 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_579 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_579 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_580 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_580 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[5] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[5] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[5] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_581 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_581 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[7] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[6] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[7] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[7] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_582 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_582 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[9] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s[8] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[9] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[8] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[9] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_583 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_583 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[1] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[0] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[1] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_584 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_584 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[3] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[2] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[3] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[3] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_585 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_585 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[5] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[4] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[5] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[5] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_586 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_586 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[7] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[6] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[7] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[7] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_587 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_587 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[9] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s[8] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[9] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[8] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_665_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_lm[9] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_695 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_695 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_653_i ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_653_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_696 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_696 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_652_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_652_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_703 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_703 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_651_i ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_651_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_812 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_812 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_8[3] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_8[3] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_813 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/SLICE_813 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7_0 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7 ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7_0 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_817 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/SLICE_817 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_27 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_26 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[0] ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[1] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_818 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_818 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa_3 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[2] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[2] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa_3 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_822 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_822 ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_39 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_90_i ) , .M1(\DC_Con4[5] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_90_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_824 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_824 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[1] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[1] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[1] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[1] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_825 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_825 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[3] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[3] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[2] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[3] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[3] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_826 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_826 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[5] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[5] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[4] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[5] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[5] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_827 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_827 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[7] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[7] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[6] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[6] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[7] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[6] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[7] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_828 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_828 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[9] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[9] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[8] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[9] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[8] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[8] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[9] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_829 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_829 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[11] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[11] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[10] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[10] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[11] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[10] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[10] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[11] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_830 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_830 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[13] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[13] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[12] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[12] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[13] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[12] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[12] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[13] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_831 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_831 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[15] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[15] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[14] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s[14] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[15] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[14] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[14] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm[15] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_840 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_840 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_88_i ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_89_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_89_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_88_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_841 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_841 ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_4[2] ) , .M1(\DC_Con4[7] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_4[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_842 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_842 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_10 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_9 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_8 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_96_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_96_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_844 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_844 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3_0_0 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_cnt_init_1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_98 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_845 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_845 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_out[0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/clear ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_39 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4 ) , .M1(\DC_Con4[6] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_out[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_39 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_SLICE_852 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_5_1 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] ) , .FXB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_18 ) , .FXA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_15 ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_18 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_out[0] ) , .OFX1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_853 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_853 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_out[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa_3 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[2] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ) , .M1(\DC_Con1[17] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_26 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_854 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/SLICE_854 ( .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_end_i ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_end_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_855 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_855 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[1] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4370 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4368 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4412_mux ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4326_i ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0] ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4326_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_856 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_856 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_1[6] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4330 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4325_i ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4325_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[6] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_857 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_528 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_858 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_529 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_859 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_530 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_860 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_860 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[8] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[8] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[7] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[7] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7] ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[7] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[8] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_861 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_861 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[10] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[10] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[9] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[9] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9] ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[9] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[10] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_862 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_862 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[12] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[12] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[11] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4344 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , .DI1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12] ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11] ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[11] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[12] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_863 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_554 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_864 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_539 ) , .DI0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] )); BUS_Con_1_SLICE_866 \BUS_Con_1/SLICE_866 ( .D1(reg_busy), .C1(\BUS_Con_1/state[1] ), .B1(\BUS_Con_1/state[0] ), .A1(\BUS_Con_1/data_ready ), .D0(reg_busy), .C0(\BUS_Con_1/state[1] ), .B0(\BUS_Con_1/state[0] ), .A0(\BUS_Con_1/data_ready ), .DI0(\BUS_Con_1/N_16_i ), .CE(\BUS_Con_1/N_493_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_16_i ), .Q0(cmd_valid), .F1(\BUS_Con_1/N_495 )); CPLD_Reg_1_SLICE_867 \CPLD_Reg_1/SLICE_867 ( .B1(o_con_done_c), .A1(\CPLD_Reg_1/state[1] ), .D0(o_con_done_c), .C0(\CPLD_Reg_1/state[1] ), .B0(con_exec), .A0(\w_data[0] ), .DI0(\CPLD_Reg_1/regtable[1]_RNO[0] ), .CE(\CPLD_Reg_1/un10_i_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[1]_RNO[0] ), .Q0(con_exec), .F1(\CPLD_Reg_1/N_23 )); CPLD_Reg_1_SLICE_868 \CPLD_Reg_1/SLICE_868 ( .D1(wr_flag), .C1(reg_addr_1_rep1), .B1(reg_addr_0_rep1), .A1(\CPLD_Reg_1/un34_regtable_1[1] ), .C0(wr_flag), .B0(\CPLD_Reg_1/reg_err_flag ), .A0(\CPLD_Reg_1/state[1] ), .DI0(\CPLD_Reg_1/N_1067 ), .CE(\CPLD_Reg_1/N_45_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_1067 ), .Q0(con_rvalid), .F1(\CPLD_Reg_1/N_1133 )); CPLD_Con_1_SLICE_869 \CPLD_Con_1/SLICE_869 ( .C1(\CPLD_Con_1/N_383 ), .B1(\CPLD_Con_1/N_362 ), .A1(\CPLD_Con_1/exec_flag ), .D0(\CPLD_Con_1/N_385 ), .C0(\CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0_1 ), .B0(\CPLD_Con_1/exec_flag ), .A0(\CPLD_Con_1/err_flag_en_0_o2_2 ), .DI0(\CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0 ), .CE(\CPLD_Con_1/err_flag_en_0_a2_6_mb_mb ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0 ), .Q0(cpld_err_flag), .F1(\CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0_1 )); CPLD_Con_1_SLICE_878 \CPLD_Con_1/SLICE_878 ( .D1(\o_PMU_OC_3_c[5] ), .C1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 ), .B1(\CPLD_Con_1/N_454 ), .A1(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .D0(\o_PMU_OC_3_c[1] ), .C0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 ), .B0(\CPLD_Con_1/N_426 ), .A0(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .DI1(\CPLD_Con_1/PMU_OC_3d_0[5] ), .DI0(\CPLD_Con_1/PMU_OC_3d_0[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3d_0[1] ), .Q0(\o_PMU_OC_3_c[1] ), .F1(\CPLD_Con_1/PMU_OC_3d_0[5] ), .Q1(\o_PMU_OC_3_c[5] )); CPLD_Con_1_SLICE_879 \CPLD_Con_1/SLICE_879 ( .D1(\o_PMU_OC_3_c[13] ), .C1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 ), .B1(\CPLD_Con_1/N_457 ), .A1(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .D0(\o_PMU_OC_3_c[9] ), .C0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 ), .B0(\CPLD_Con_1/N_437 ), .A0(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .DI1(\CPLD_Con_1/PMU_OC_3d_0[21] ), .DI0(\CPLD_Con_1/PMU_OC_3d_0[17] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3d_0[17] ), .Q0(\o_PMU_OC_3_c[9] ), .F1(\CPLD_Con_1/PMU_OC_3d_0[21] ), .Q1(\o_PMU_OC_3_c[13] )); CPLD_Con_1_SLICE_880 \CPLD_Con_1/SLICE_880 ( .D1(\DC_Con3[22] ), .C1(\DC_Con2[22] ), .B1(\CPLD_Con_1/RC_VSel40 ), .A1(\CPLD_Con_1/RC_VSel39 ), .D0(\CPLD_Con_1/N_189 ), .C0(\DC_Con1[22] ), .B0(\CPLD_Con_1/RC_VSel38 ), .A0(\CPLD_Con_1/m16_0_1 ), .DI0(\CPLD_Con_1/N_17_i ), .CE(\CPLD_Con_1/N_205_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_17_i ), .Q0(o_RC_ISel_c), .F1(\CPLD_Con_1/m16_0_1 )); CPLD_Con_1_SLICE_881 \CPLD_Con_1/SLICE_881 ( .D1(\DC_Con3[22] ), .C1(\DC_Con2[22] ), .B1(\CPLD_Con_1/RC_VSel40 ), .A1(\CPLD_Con_1/RC_VSel39 ), .D0(\CPLD_Con_1/N_193 ), .C0(\DC_Con1[22] ), .B0(\CPLD_Con_1/RC_VSel38 ), .A0(\CPLD_Con_1/m9_0_1 ), .DI0(\CPLD_Con_1/N_10_i ), .CE(\CPLD_Con_1/N_205_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_10_i ), .Q0(o_RC_VSel_c), .F1(\CPLD_Con_1/m9_0_1 )); CPLD_Reg_1_SLICE_883 \CPLD_Reg_1/SLICE_883 ( .C1(\DC_Con1[0] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][0] ), .C0(reg_addr_3_rep2), .B0(\freq1_relay[0] ), .A0(\CPLD_Reg_1/regtable[10][0] ), .DI1(\CPLD_Reg_1/rdata_reg_2[0] ), .M1(\reg_addr[1] ), .M0(\reg_addr_fast[2] ), .FXB(\CPLD_Reg_1/N_352 ), .FXA(\CPLD_Reg_1/N_328 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_232 ), .Q1(\r_data[0] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[0] )); CPLD_Reg_1_SLICE_884 \CPLD_Reg_1/SLICE_884 ( .C1(\DC_Con1[1] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][1] ), .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][1] ), .A0(\CPLD_Reg_1/regtable[2][1] ), .DI1(\CPLD_Reg_1/rdata_reg_2[1] ), .M1(\reg_addr[1] ), .M0(\reg_addr_fast[2] ), .FXB(\CPLD_Reg_1/N_353 ), .FXA(\CPLD_Reg_1/N_329 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_233 ), .Q1(\r_data[1] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[1] )); CPLD_Reg_1_SLICE_885 \CPLD_Reg_1/SLICE_885 ( .C1(\DC_Con1[2] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][2] ), .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][2] ), .A0(\CPLD_Reg_1/regtable[2][2] ), .DI1(\CPLD_Reg_1/rdata_reg_2[2] ), .M1(\reg_addr[1] ), .M0(\reg_addr_fast[2] ), .FXB(\CPLD_Reg_1/N_354 ), .FXA(\CPLD_Reg_1/N_330 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_234 ), .Q1(\r_data[2] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[2] )); CPLD_Reg_1_SLICE_886 \CPLD_Reg_1/SLICE_886 ( .C1(\DC_Con1[3] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][3] ), .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][3] ), .A0(\CPLD_Reg_1/regtable[2][3] ), .DI1(\CPLD_Reg_1/rdata_reg_2[3] ), .M1(\reg_addr[1] ), .M0(\reg_addr_fast[2] ), .FXB(\CPLD_Reg_1/N_355 ), .FXA(\CPLD_Reg_1/N_331 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_235 ), .Q1(\r_data[3] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[3] )); CPLD_Reg_1_SLICE_887 \CPLD_Reg_1/SLICE_887 ( .C1(\DC_Con1[4] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][4] ), .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][4] ), .A0(\CPLD_Reg_1/regtable[2][4] ), .DI1(\CPLD_Reg_1/rdata_reg_2[4] ), .M1(\reg_addr[1] ), .M0(\reg_addr_fast[2] ), .FXB(\CPLD_Reg_1/N_356 ), .FXA(\CPLD_Reg_1/N_332 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_236 ), .Q1(\r_data[4] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[4] )); CPLD_Reg_1_SLICE_888 \CPLD_Reg_1/SLICE_888 ( .C1(\DC_Con1[5] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][5] ), .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][5] ), .A0(\CPLD_Reg_1/regtable[2][5] ), .DI1(\CPLD_Reg_1/rdata_reg_2[5] ), .M1(\reg_addr[1] ), .M0(\reg_addr_fast[2] ), .FXB(\CPLD_Reg_1/N_357 ), .FXA(\CPLD_Reg_1/N_333 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_237 ), .Q1(\r_data[5] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[5] )); CPLD_Reg_1_SLICE_889 \CPLD_Reg_1/SLICE_889 ( .C1(\DC_Con1[6] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][6] ), .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][6] ), .A0(\CPLD_Reg_1/regtable[2][6] ), .DI1(\CPLD_Reg_1/rdata_reg_2[6] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_358 ), .FXA(\CPLD_Reg_1/N_334 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_238 ), .Q1(\r_data[6] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[6] )); CPLD_Reg_1_SLICE_890 \CPLD_Reg_1/SLICE_890 ( .C1(\DC_Con1[7] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][7] ), .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][7] ), .A0(\CPLD_Reg_1/regtable[2][7] ), .DI1(\CPLD_Reg_1/rdata_reg_2[7] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_359 ), .FXA(\CPLD_Reg_1/N_335 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_239 ), .Q1(\r_data[7] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[7] )); CPLD_Reg_1_SLICE_891 \CPLD_Reg_1/SLICE_891 ( .C1(\DC_Con1[8] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][8] ), .C0(reg_addr_3_rep2), .B0(\CPLD_Reg_1/regtable[10][8] ), .A0(\CPLD_Reg_1/regtable[2][8] ), .DI1(\CPLD_Reg_1/rdata_reg_2[8] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_360 ), .FXA(\CPLD_Reg_1/N_336 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_240 ), .Q1(\r_data[8] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[8] )); CPLD_Reg_1_SLICE_892 \CPLD_Reg_1/SLICE_892 ( .C1(\DC_Con1[9] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][9] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][9] ), .A0(\CPLD_Reg_1/regtable[2][9] ), .DI1(\CPLD_Reg_1/rdata_reg_2[9] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_361 ), .FXA(\CPLD_Reg_1/N_337 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_241 ), .Q1(\r_data[9] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[9] )); CPLD_Reg_1_SLICE_893 \CPLD_Reg_1/SLICE_893 ( .C1(\DC_Con1[10] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][10] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][10] ), .A0(\CPLD_Reg_1/regtable[2][10] ), .DI1(\CPLD_Reg_1/rdata_reg_2[10] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_362 ), .FXA(\CPLD_Reg_1/N_338 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_242 ), .Q1(\r_data[10] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[10] )); CPLD_Reg_1_SLICE_894 \CPLD_Reg_1/SLICE_894 ( .C1(\DC_Con1[11] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][11] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][11] ), .A0(\CPLD_Reg_1/regtable[2][11] ), .DI1(\CPLD_Reg_1/rdata_reg_2[11] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_363 ), .FXA(\CPLD_Reg_1/N_339 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_243 ), .Q1(\r_data[11] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[11] )); CPLD_Reg_1_SLICE_895 \CPLD_Reg_1/SLICE_895 ( .C1(\DC_Con1[12] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][12] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][12] ), .A0(\CPLD_Reg_1/regtable[2][12] ), .DI1(\CPLD_Reg_1/rdata_reg_2[12] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_364 ), .FXA(\CPLD_Reg_1/N_340 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_244 ), .Q1(\r_data[12] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[12] )); CPLD_Reg_1_SLICE_896 \CPLD_Reg_1/SLICE_896 ( .C1(\DC_Con1[13] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][13] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][13] ), .A0(\CPLD_Reg_1/regtable[2][13] ), .DI1(\CPLD_Reg_1/rdata_reg_2[13] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_365 ), .FXA(\CPLD_Reg_1/N_341 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_245 ), .Q1(\r_data[13] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[13] )); CPLD_Reg_1_SLICE_897 \CPLD_Reg_1/SLICE_897 ( .C1(\DC_Con1[14] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][14] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][14] ), .A0(\CPLD_Reg_1/regtable[2][14] ), .DI1(\CPLD_Reg_1/rdata_reg_2[14] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_366 ), .FXA(\CPLD_Reg_1/N_342 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_246 ), .Q1(\r_data[14] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[14] )); CPLD_Reg_1_SLICE_898 \CPLD_Reg_1/SLICE_898 ( .C1(\DC_Con1[15] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][15] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][15] ), .A0(\CPLD_Reg_1/regtable[2][15] ), .DI1(\CPLD_Reg_1/rdata_reg_2[15] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_367 ), .FXA(\CPLD_Reg_1/N_343 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_247 ), .Q1(\r_data[15] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[15] )); CPLD_Reg_1_SLICE_899 \CPLD_Reg_1/SLICE_899 ( .C1(\DC_Con1[16] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][16] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][16] ), .A0(\CPLD_Reg_1/regtable[2][16] ), .DI1(\CPLD_Reg_1/rdata_reg_2[16] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_368 ), .FXA(\CPLD_Reg_1/N_344 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_248 ), .Q1(\r_data[16] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[16] )); CPLD_Reg_1_SLICE_900 \CPLD_Reg_1/SLICE_900 ( .C1(\DC_Con1[17] ), .B1(reg_addr_3_rep1), .A1(\CPLD_Reg_1/regtable[14][17] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][17] ), .A0(\CPLD_Reg_1/regtable[2][17] ), .DI1(\CPLD_Reg_1/rdata_reg_2[17] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_369 ), .FXA(\CPLD_Reg_1/N_345 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_249 ), .Q1(\r_data[17] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[17] )); CPLD_Reg_1_SLICE_901 \CPLD_Reg_1/SLICE_901 ( .C1(\DC_Con1[18] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[14][18] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][18] ), .A0(\CPLD_Reg_1/regtable[2][18] ), .DI1(\CPLD_Reg_1/rdata_reg_2[18] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_370 ), .FXA(\CPLD_Reg_1/N_346 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_250 ), .Q1(\r_data[18] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[18] )); CPLD_Reg_1_SLICE_902 \CPLD_Reg_1/SLICE_902 ( .C1(\DC_Con1[19] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[14][19] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][19] ), .A0(\CPLD_Reg_1/regtable[2][19] ), .DI1(\CPLD_Reg_1/rdata_reg_2[19] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_371 ), .FXA(\CPLD_Reg_1/N_347 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_251 ), .Q1(\r_data[19] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[19] )); CPLD_Reg_1_SLICE_903 \CPLD_Reg_1/SLICE_903 ( .C1(\DC_Con1[20] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[14][20] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][20] ), .A0(\CPLD_Reg_1/regtable[2][20] ), .DI1(\CPLD_Reg_1/rdata_reg_2[20] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_372 ), .FXA(\CPLD_Reg_1/N_348 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_252 ), .Q1(\r_data[20] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[20] )); CPLD_Reg_1_SLICE_904 \CPLD_Reg_1/SLICE_904 ( .C1(\DC_Con1[21] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[14][21] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][21] ), .A0(\CPLD_Reg_1/regtable[2][21] ), .DI1(\CPLD_Reg_1/rdata_reg_2[21] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_373 ), .FXA(\CPLD_Reg_1/N_349 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_253 ), .Q1(\r_data[21] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[21] )); CPLD_Reg_1_SLICE_905 \CPLD_Reg_1/SLICE_905 ( .C1(\DC_Con1[22] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[14][22] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][22] ), .A0(\CPLD_Reg_1/regtable[2][22] ), .DI1(\CPLD_Reg_1/rdata_reg_2[22] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_374 ), .FXA(\CPLD_Reg_1/N_350 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_254 ), .Q1(\r_data[22] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[22] )); CPLD_Reg_1_SLICE_906 \CPLD_Reg_1/SLICE_906 ( .C1(\DC_Con1[23] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[14][23] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[10][23] ), .A0(\CPLD_Reg_1/regtable[2][23] ), .DI1(\CPLD_Reg_1/rdata_reg_2[23] ), .M1(\reg_addr[1] ), .M0(reg_addr_2_rep1), .FXB(\CPLD_Reg_1/N_375 ), .FXA(\CPLD_Reg_1/N_351 ), .CE(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .CLK(i_sys_clk_c), .OFX0(\CPLD_Reg_1/N_255 ), .Q1(\r_data[23] ), .OFX1(\CPLD_Reg_1/rdata_reg_2[23] )); BUS_Con_1_SLICE_907 \BUS_Con_1/SLICE_907 ( .D1(\BUS_Con_1/N_504 ), .C1(\BUS_Con_1/recv_reg[25] ), .B1(\BUS_Con_1/recv_reg[1] ), .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), .C0(\BUS_Con_1/recv_reg[24] ), .B0(\BUS_Con_1/recv_reg[0] ), .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_479_i ), .DI0(\BUS_Con_1/N_480_i ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_480_i ), .Q0(\reg_addr[0] ), .F1(\BUS_Con_1/N_479_i ), .Q1(\reg_addr[1] )); BUS_Con_1_SLICE_908 \BUS_Con_1/SLICE_908 ( .D1(\BUS_Con_1/N_504 ), .C1(\BUS_Con_1/recv_reg[27] ), .B1(\BUS_Con_1/recv_reg[3] ), .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), .C0(\BUS_Con_1/recv_reg[26] ), .B0(\BUS_Con_1/recv_reg[2] ), .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_477_i ), .DI0(\BUS_Con_1/N_478_i ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_478_i ), .Q0(\reg_addr[2] ), .F1(\BUS_Con_1/N_477_i ), .Q1(\reg_addr[3] )); BUS_Con_1_SLICE_909 \BUS_Con_1/SLICE_909 ( .D1(\BUS_Con_1/N_504 ), .C1(\BUS_Con_1/recv_reg[29] ), .B1(\BUS_Con_1/recv_reg[5] ), .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), .C0(\BUS_Con_1/recv_reg[28] ), .B0(\BUS_Con_1/recv_reg[4] ), .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_475_i ), .DI0(\BUS_Con_1/N_476_i ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_476_i ), .Q0(\reg_addr[4] ), .F1(\BUS_Con_1/N_475_i ), .Q1(\reg_addr[5] )); BUS_Con_1_SLICE_910 \BUS_Con_1/SLICE_910 ( .D0(\BUS_Con_1/N_504 ), .C0(\BUS_Con_1/recv_reg[30] ), .B0(\BUS_Con_1/recv_reg[6] ), .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI0(\BUS_Con_1/N_474_i ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_474_i ), .Q0(\reg_addr[6] )); BUS_Con_1_SLICE_911 \BUS_Con_1/SLICE_911 ( .D1(\BUS_Con_1/N_504 ), .C1(\BUS_Con_1/recv_reg[24] ), .B1(\BUS_Con_1/recv_reg[0] ), .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), .C0(\BUS_Con_1/recv_reg[24] ), .B0(\BUS_Con_1/recv_reg[0] ), .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_480_i_rep2 ), .DI0(\BUS_Con_1/N_480_i_rep1 ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_480_i_rep1 ), .Q0(reg_addr_0_rep1), .F1(\BUS_Con_1/N_480_i_rep2 ), .Q1(reg_addr_0_rep2)); BUS_Con_1_SLICE_912 \BUS_Con_1/SLICE_912 ( .D0(\BUS_Con_1/N_504 ), .C0(\BUS_Con_1/recv_reg[25] ), .B0(\BUS_Con_1/recv_reg[1] ), .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI0(\BUS_Con_1/N_479_i_rep1 ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_479_i_rep1 ), .Q0(reg_addr_1_rep1)); BUS_Con_1_SLICE_913 \BUS_Con_1/SLICE_913 ( .D1(\BUS_Con_1/N_504 ), .C1(\BUS_Con_1/recv_reg[26] ), .B1(\BUS_Con_1/recv_reg[2] ), .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), .C0(\BUS_Con_1/recv_reg[26] ), .B0(\BUS_Con_1/recv_reg[2] ), .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_478_i_rep2 ), .DI0(\BUS_Con_1/N_478_i_rep1 ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_478_i_rep1 ), .Q0(reg_addr_2_rep1), .F1(\BUS_Con_1/N_478_i_rep2 ), .Q1(reg_addr_2_rep2)); BUS_Con_1_SLICE_914 \BUS_Con_1/SLICE_914 ( .D1(\BUS_Con_1/N_504 ), .C1(\BUS_Con_1/recv_reg[27] ), .B1(\BUS_Con_1/recv_reg[3] ), .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), .C0(\BUS_Con_1/recv_reg[27] ), .B0(\BUS_Con_1/recv_reg[3] ), .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_477_i_rep2 ), .DI0(\BUS_Con_1/N_477_i_rep1 ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_477_i_rep1 ), .Q0(reg_addr_3_rep1), .F1(\BUS_Con_1/N_477_i_rep2 ), .Q1(reg_addr_3_rep2)); BUS_Con_1_SLICE_915 \BUS_Con_1/SLICE_915 ( .D1(\BUS_Con_1/N_504 ), .C1(\BUS_Con_1/recv_reg[25] ), .B1(\BUS_Con_1/recv_reg[1] ), .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), .C0(\BUS_Con_1/recv_reg[24] ), .B0(\BUS_Con_1/recv_reg[0] ), .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_479_i_fast ), .DI0(\BUS_Con_1/N_480_i_fast ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_480_i_fast ), .Q0(\reg_addr_fast[0] ), .F1(\BUS_Con_1/N_479_i_fast ), .Q1(\reg_addr_fast[1] )); BUS_Con_1_SLICE_916 \BUS_Con_1/SLICE_916 ( .D1(\BUS_Con_1/N_504 ), .C1(\BUS_Con_1/recv_reg[27] ), .B1(\BUS_Con_1/recv_reg[3] ), .A1(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .D0(\BUS_Con_1/N_504 ), .C0(\BUS_Con_1/recv_reg[26] ), .B0(\BUS_Con_1/recv_reg[2] ), .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI1(\BUS_Con_1/N_477_i_fast ), .DI0(\BUS_Con_1/N_478_i_fast ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_478_i_fast ), .Q0(\reg_addr_fast[2] ), .F1(\BUS_Con_1/N_477_i_fast ), .Q1(\reg_addr_fast[3] )); CPLD_Reg_1_SLICE_917 \CPLD_Reg_1/SLICE_917 ( .B1(con_exec), .A1(cmd_valid), .D0(o_con_done_c), .C0(\CPLD_Reg_1/state[1] ), .B0(\CPLD_Reg_1/state[0] ), .A0(\CPLD_Reg_1/busy_flag_1_i_a3_0_0 ), .DI0(\CPLD_Reg_1/N_44_i ), .CE(\CPLD_Reg_1/state_6_d_i ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_44_i ), .Q0(reg_busy), .F1(\CPLD_Reg_1/busy_flag_1_i_a3_0_0 )); BUS_Con_1_SLICE_930 \BUS_Con_1/SLICE_930 ( .C1(\BUS_Con_1/state[0] ), .B1(\BUS_Con_1/state[1] ), .A1(\BUS_Con_1/wr_flag ), .D0(\BUS_Con_1/recv_reg[31] ), .C0(\BUS_Con_1/recv_reg[7] ), .B0(\BUS_Con_1/data_out_0_sqmuxa ), .A0(\BUS_Con_1/addr_out_1_sqmuxa_1 ), .DI0(\BUS_Con_1/wr_out_8 ), .CE(\BUS_Con_1/un1_state_2_0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/wr_out_8 ), .Q0(wr_flag), .F1(\BUS_Con_1/addr_out_1_sqmuxa_1 )); xo2chub_SLICE_947 \xo2chub/SLICE_947 ( .C0(\xo2chub/er1_shift_reg[1] ), .B0(\xo2chub/bit_count[1] ), .A0(\xo2chub/bit_count[0] ), .M1(\xo2chub/er1_shift_reg[14] ), .M0(\xo2chub/er1_shift_reg[13] ), .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\xo2chub/jtdo1_1_0 ), .Q0(\xo2chub/ip_enable[9] ), .Q1(\xo2chub/ip_enable[10] )); xo2chub_SLICE_948 \xo2chub/SLICE_948 ( .B1(jtaghub16_jupdate), .A1(jtaghub16_jrstn), .B0(\xo2chub/jce1_d1 ), .A0(\xo2chub/bit_count ), .M1(\xo2chub/er1_shift_reg[16] ), .M0(\xo2chub/er1_shift_reg[15] ), .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\xo2chub/er1_shift_reg8 ), .Q0(\xo2chub/ip_enable[11] ), .F1(\xo2chub/id_enable_0_sqmuxa ), .Q1(\xo2chub/ip_enable[12] )); SLICE_949 SLICE_949( .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 ) , .M1(\xo2chub/er1_shift_reg[18] ), .M0(\xo2chub/er1_shift_reg[17] ), .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2[0] ) , .Q0(\xo2chub/ip_enable[13] ), .F1(GND), .Q1(\xo2chub/ip_enable[14] )); SLICE_950 SLICE_950( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity ), .M0(\xo2chub/jce1 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_m2_0 ) , .Q0(\xo2chub/jce1_d1 ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_6 ) ); CPLD_Con_1_un1_i_DC_Con3_2lto8_d_SLICE_951 \CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951 ( .D1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf1_1 ), .C1(\DC_Con3[6] ), .B1(\DC_Con3[7] ), .A1(\DC_Con3[9] ), .D0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf0_1 ), .C0(\DC_Con3[6] ), .B0(\DC_Con3[7] ), .A0(\DC_Con3[9] ), .M0(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), .OFX0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d )); CPLD_Reg_1_rdata_reg_2_11_20__SLICE_952 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952 ( .C1(\DC_Con4[20] ), .B1(\CPLD_Reg_1/regtable[13][20] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[20] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][20] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep2), .FXB(\CPLD_Reg_1/N_324 ), .FXA(\CPLD_Reg_1/N_276 ), .OFX0(\CPLD_Reg_1/N_324 ), .OFX1(\CPLD_Reg_1/N_348 )); CPLD_Reg_1_rdata_reg_2_10_20__SLICE_953 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953 ( .C1(\DC_Con2[20] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][20] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][20] ), .A0(\CPLD_Reg_1/regtable[3][20] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_300 ), .FXA(\CPLD_Reg_1/N_252 ), .OFX0(\CPLD_Reg_1/N_300 ), .OFX1(\CPLD_Reg_1/N_372 )); CPLD_Reg_1_rdata_reg_2_9_20__SLICE_954 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954 ( .C1(\CPLD_Reg_1/regtable[5][20] ), .B1(\CPLD_Reg_1/regtable[4][20] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][20] ), .A0(\CPLD_Reg_1/regtable[0][20] ), .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_276 )); CPLD_Reg_1_rdata_reg_2_9_0__SLICE_955 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955 ( .C1(reg_addr_0_rep2), .B1(\freq4_relay[0] ), .A1(\freq3_relay[0] ), .C0(con_exec), .B0(\reg_addr[0] ), .A0(\CPLD_Reg_1/regtable[0][0] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_256 )); CPLD_Reg_1_rdata_reg_2_10_0__SLICE_956 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956 ( .C1(\DC_Con2[0] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][0] ), .C0(\reg_addr[3] ), .B0(\freq2_relay[0] ), .A0(\CPLD_Reg_1/regtable[11][0] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_280 ), .FXA(\CPLD_Reg_1/N_232 ), .OFX0(\CPLD_Reg_1/N_280 ), .OFX1(\CPLD_Reg_1/N_352 )); CPLD_Reg_1_rdata_reg_2_11_0__SLICE_957 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957 ( .C1(\DC_Con4[0] ), .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][0] ), .C0(\DC_Con3[0] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][0] ), .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_304 ), .FXA(\CPLD_Reg_1/N_256 ), .OFX0(\CPLD_Reg_1/N_304 ), .OFX1(\CPLD_Reg_1/N_328 )); CPLD_Reg_1_rdata_reg_2_9_1__SLICE_958 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958 ( .C1(reg_addr_0_rep2), .B1(\CPLD_Reg_1/regtable[5][1] ), .A1(\CPLD_Reg_1/regtable[4][1] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][1] ), .A0(\CPLD_Reg_1/regtable[0][1] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_257 )); CPLD_Reg_1_rdata_reg_2_10_1__SLICE_959 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959 ( .C1(\DC_Con2[1] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][1] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][1] ), .A0(\CPLD_Reg_1/regtable[3][1] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_281 ), .FXA(\CPLD_Reg_1/N_233 ), .OFX0(\CPLD_Reg_1/N_281 ), .OFX1(\CPLD_Reg_1/N_353 )); CPLD_Reg_1_rdata_reg_2_11_1__SLICE_960 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960 ( .C1(\DC_Con4[1] ), .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][1] ), .C0(\DC_Con3[1] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][1] ), .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_305 ), .FXA(\CPLD_Reg_1/N_257 ), .OFX0(\CPLD_Reg_1/N_305 ), .OFX1(\CPLD_Reg_1/N_329 )); CPLD_Reg_1_rdata_reg_2_9_2__SLICE_961 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961 ( .C1(reg_addr_0_rep2), .B1(\CPLD_Reg_1/regtable[5][2] ), .A1(\CPLD_Reg_1/regtable[4][2] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][2] ), .A0(\CPLD_Reg_1/regtable[0][2] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_258 )); CPLD_Reg_1_rdata_reg_2_10_2__SLICE_962 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962 ( .C1(\DC_Con2[2] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][2] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][2] ), .A0(\CPLD_Reg_1/regtable[3][2] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_282 ), .FXA(\CPLD_Reg_1/N_234 ), .OFX0(\CPLD_Reg_1/N_282 ), .OFX1(\CPLD_Reg_1/N_354 )); CPLD_Reg_1_rdata_reg_2_11_2__SLICE_963 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963 ( .C1(\DC_Con4[2] ), .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][2] ), .C0(\DC_Con3[2] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][2] ), .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_306 ), .FXA(\CPLD_Reg_1/N_258 ), .OFX0(\CPLD_Reg_1/N_306 ), .OFX1(\CPLD_Reg_1/N_330 )); CPLD_Reg_1_rdata_reg_2_9_3__SLICE_964 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964 ( .C1(reg_addr_0_rep2), .B1(\CPLD_Reg_1/regtable[5][3] ), .A1(\CPLD_Reg_1/regtable[4][3] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][3] ), .A0(\CPLD_Reg_1/regtable[0][3] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_259 )); CPLD_Reg_1_rdata_reg_2_10_3__SLICE_965 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965 ( .C1(\DC_Con2[3] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][3] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][3] ), .A0(\CPLD_Reg_1/regtable[3][3] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_283 ), .FXA(\CPLD_Reg_1/N_235 ), .OFX0(\CPLD_Reg_1/N_283 ), .OFX1(\CPLD_Reg_1/N_355 )); CPLD_Reg_1_rdata_reg_2_11_3__SLICE_966 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966 ( .C1(\DC_Con4[3] ), .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][3] ), .C0(\DC_Con3[3] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][3] ), .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_307 ), .FXA(\CPLD_Reg_1/N_259 ), .OFX0(\CPLD_Reg_1/N_307 ), .OFX1(\CPLD_Reg_1/N_331 )); CPLD_Reg_1_rdata_reg_2_9_4__SLICE_967 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967 ( .C1(reg_addr_0_rep2), .B1(\CPLD_Reg_1/regtable[5][4] ), .A1(\CPLD_Reg_1/regtable[4][4] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][4] ), .A0(\CPLD_Reg_1/regtable[0][4] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_260 )); CPLD_Reg_1_rdata_reg_2_10_4__SLICE_968 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968 ( .C1(\DC_Con2[4] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][4] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][4] ), .A0(\CPLD_Reg_1/regtable[3][4] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_284 ), .FXA(\CPLD_Reg_1/N_236 ), .OFX0(\CPLD_Reg_1/N_284 ), .OFX1(\CPLD_Reg_1/N_356 )); CPLD_Reg_1_rdata_reg_2_11_4__SLICE_969 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969 ( .C1(\DC_Con4[4] ), .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][4] ), .C0(\DC_Con3[4] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][4] ), .M1(\reg_addr_fast[3] ), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_308 ), .FXA(\CPLD_Reg_1/N_260 ), .OFX0(\CPLD_Reg_1/N_308 ), .OFX1(\CPLD_Reg_1/N_332 )); CPLD_Reg_1_rdata_reg_2_9_5__SLICE_970 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970 ( .C1(reg_addr_0_rep2), .B1(\CPLD_Reg_1/regtable[5][5] ), .A1(\CPLD_Reg_1/regtable[4][5] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][5] ), .A0(\CPLD_Reg_1/regtable[0][5] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_261 )); CPLD_Reg_1_rdata_reg_2_10_5__SLICE_971 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971 ( .C1(\DC_Con2[5] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][5] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][5] ), .A0(\CPLD_Reg_1/regtable[3][5] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_285 ), .FXA(\CPLD_Reg_1/N_237 ), .OFX0(\CPLD_Reg_1/N_285 ), .OFX1(\CPLD_Reg_1/N_357 )); CPLD_Reg_1_rdata_reg_2_11_5__SLICE_972 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972 ( .C1(\DC_Con4[5] ), .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][5] ), .C0(\DC_Con3[5] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][5] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_309 ), .FXA(\CPLD_Reg_1/N_261 ), .OFX0(\CPLD_Reg_1/N_309 ), .OFX1(\CPLD_Reg_1/N_333 )); CPLD_Reg_1_rdata_reg_2_9_6__SLICE_973 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973 ( .C1(reg_addr_0_rep2), .B1(\CPLD_Reg_1/regtable[5][6] ), .A1(\CPLD_Reg_1/regtable[4][6] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][6] ), .A0(\CPLD_Reg_1/regtable[0][6] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_262 )); CPLD_Reg_1_rdata_reg_2_10_6__SLICE_974 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974 ( .C1(\DC_Con2[6] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][6] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][6] ), .A0(\CPLD_Reg_1/regtable[3][6] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_286 ), .FXA(\CPLD_Reg_1/N_238 ), .OFX0(\CPLD_Reg_1/N_286 ), .OFX1(\CPLD_Reg_1/N_358 )); CPLD_Reg_1_rdata_reg_2_11_6__SLICE_975 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975 ( .C1(\DC_Con4[6] ), .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][6] ), .C0(\DC_Con3[6] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][6] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_310 ), .FXA(\CPLD_Reg_1/N_262 ), .OFX0(\CPLD_Reg_1/N_310 ), .OFX1(\CPLD_Reg_1/N_334 )); CPLD_Reg_1_rdata_reg_2_9_7__SLICE_976 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976 ( .C1(reg_addr_0_rep2), .B1(\CPLD_Reg_1/regtable[5][7] ), .A1(\CPLD_Reg_1/regtable[4][7] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][7] ), .A0(\CPLD_Reg_1/regtable[0][7] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_263 )); CPLD_Reg_1_rdata_reg_2_10_7__SLICE_977 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977 ( .C1(\DC_Con2[7] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][7] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][7] ), .A0(\CPLD_Reg_1/regtable[3][7] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_287 ), .FXA(\CPLD_Reg_1/N_239 ), .OFX0(\CPLD_Reg_1/N_287 ), .OFX1(\CPLD_Reg_1/N_359 )); CPLD_Reg_1_rdata_reg_2_11_7__SLICE_978 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978 ( .C1(\DC_Con4[7] ), .B1(reg_addr_2_rep2), .A1(\CPLD_Reg_1/regtable[13][7] ), .C0(\DC_Con3[7] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][7] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_311 ), .FXA(\CPLD_Reg_1/N_263 ), .OFX0(\CPLD_Reg_1/N_311 ), .OFX1(\CPLD_Reg_1/N_335 )); CPLD_Reg_1_rdata_reg_2_9_8__SLICE_979 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979 ( .C1(\CPLD_Reg_1/regtable[5][8] ), .B1(\CPLD_Reg_1/regtable[4][8] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][8] ), .A0(\CPLD_Reg_1/regtable[0][8] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_264 )); CPLD_Reg_1_rdata_reg_2_10_8__SLICE_980 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980 ( .C1(\DC_Con2[8] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][8] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][8] ), .A0(\CPLD_Reg_1/regtable[3][8] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_288 ), .FXA(\CPLD_Reg_1/N_240 ), .OFX0(\CPLD_Reg_1/N_288 ), .OFX1(\CPLD_Reg_1/N_360 )); CPLD_Reg_1_rdata_reg_2_11_8__SLICE_981 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981 ( .C1(\DC_Con4[8] ), .B1(\CPLD_Reg_1/regtable[13][8] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[8] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][8] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_312 ), .FXA(\CPLD_Reg_1/N_264 ), .OFX0(\CPLD_Reg_1/N_312 ), .OFX1(\CPLD_Reg_1/N_336 )); CPLD_Reg_1_rdata_reg_2_9_9__SLICE_982 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982 ( .C1(\CPLD_Reg_1/regtable[5][9] ), .B1(\CPLD_Reg_1/regtable[4][9] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][9] ), .A0(\CPLD_Reg_1/regtable[0][9] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_265 )); CPLD_Reg_1_rdata_reg_2_10_9__SLICE_983 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983 ( .C1(\DC_Con2[9] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][9] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][9] ), .A0(\CPLD_Reg_1/regtable[3][9] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_289 ), .FXA(\CPLD_Reg_1/N_241 ), .OFX0(\CPLD_Reg_1/N_289 ), .OFX1(\CPLD_Reg_1/N_361 )); CPLD_Reg_1_rdata_reg_2_11_9__SLICE_984 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984 ( .C1(\DC_Con4[9] ), .B1(\CPLD_Reg_1/regtable[13][9] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[9] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][9] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_313 ), .FXA(\CPLD_Reg_1/N_265 ), .OFX0(\CPLD_Reg_1/N_313 ), .OFX1(\CPLD_Reg_1/N_337 )); CPLD_Reg_1_rdata_reg_2_9_10__SLICE_985 \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985 ( .C1(\CPLD_Reg_1/regtable[5][10] ), .B1(\CPLD_Reg_1/regtable[4][10] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][10] ), .A0(\CPLD_Reg_1/regtable[0][10] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_266 )); CPLD_Reg_1_rdata_reg_2_10_10__SLICE_986 \CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986 ( .C1(\DC_Con2[10] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][10] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][10] ), .A0(\CPLD_Reg_1/regtable[3][10] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_290 ), .FXA(\CPLD_Reg_1/N_242 ), .OFX0(\CPLD_Reg_1/N_290 ), .OFX1(\CPLD_Reg_1/N_362 )); CPLD_Reg_1_rdata_reg_2_11_10__SLICE_987 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987 ( .C1(\DC_Con4[10] ), .B1(\CPLD_Reg_1/regtable[13][10] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[10] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][10] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_314 ), .FXA(\CPLD_Reg_1/N_266 ), .OFX0(\CPLD_Reg_1/N_314 ), .OFX1(\CPLD_Reg_1/N_338 )); CPLD_Reg_1_rdata_reg_2_9_11__SLICE_988 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988 ( .C1(\CPLD_Reg_1/regtable[5][11] ), .B1(\CPLD_Reg_1/regtable[4][11] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][11] ), .A0(\CPLD_Reg_1/regtable[0][11] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_267 )); CPLD_Reg_1_rdata_reg_2_10_11__SLICE_989 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989 ( .C1(\DC_Con2[11] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][11] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][11] ), .A0(\CPLD_Reg_1/regtable[3][11] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_291 ), .FXA(\CPLD_Reg_1/N_243 ), .OFX0(\CPLD_Reg_1/N_291 ), .OFX1(\CPLD_Reg_1/N_363 )); CPLD_Reg_1_rdata_reg_2_11_11__SLICE_990 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990 ( .C1(\DC_Con4[11] ), .B1(\CPLD_Reg_1/regtable[13][11] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[11] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][11] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_315 ), .FXA(\CPLD_Reg_1/N_267 ), .OFX0(\CPLD_Reg_1/N_315 ), .OFX1(\CPLD_Reg_1/N_339 )); CPLD_Reg_1_rdata_reg_2_9_12__SLICE_991 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991 ( .C1(\freq4_relay[12] ), .B1(\CPLD_Reg_1/regtable[4][12] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][12] ), .A0(\CPLD_Reg_1/regtable[0][12] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_268 )); CPLD_Reg_1_rdata_reg_2_10_12__SLICE_992 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992 ( .C1(\DC_Con2[12] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][12] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][12] ), .A0(\CPLD_Reg_1/regtable[3][12] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_292 ), .FXA(\CPLD_Reg_1/N_244 ), .OFX0(\CPLD_Reg_1/N_292 ), .OFX1(\CPLD_Reg_1/N_364 )); CPLD_Reg_1_rdata_reg_2_11_12__SLICE_993 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993 ( .C1(\DC_Con4[12] ), .B1(\CPLD_Reg_1/regtable[13][12] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[12] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][12] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_316 ), .FXA(\CPLD_Reg_1/N_268 ), .OFX0(\CPLD_Reg_1/N_316 ), .OFX1(\CPLD_Reg_1/N_340 )); CPLD_Reg_1_rdata_reg_2_9_13__SLICE_994 \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994 ( .C1(\freq4_relay[13] ), .B1(\CPLD_Reg_1/regtable[4][13] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][13] ), .A0(\CPLD_Reg_1/regtable[0][13] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_269 )); CPLD_Reg_1_rdata_reg_2_10_13__SLICE_995 \CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995 ( .C1(\DC_Con2[13] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][13] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][13] ), .A0(\CPLD_Reg_1/regtable[3][13] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_293 ), .FXA(\CPLD_Reg_1/N_245 ), .OFX0(\CPLD_Reg_1/N_293 ), .OFX1(\CPLD_Reg_1/N_365 )); CPLD_Reg_1_rdata_reg_2_11_13__SLICE_996 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996 ( .C1(\DC_Con4[13] ), .B1(\CPLD_Reg_1/regtable[13][13] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[13] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][13] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_317 ), .FXA(\CPLD_Reg_1/N_269 ), .OFX0(\CPLD_Reg_1/N_317 ), .OFX1(\CPLD_Reg_1/N_341 )); CPLD_Reg_1_rdata_reg_2_9_14__SLICE_997 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997 ( .C1(\freq4_relay[14] ), .B1(\CPLD_Reg_1/regtable[4][14] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][14] ), .A0(\CPLD_Reg_1/regtable[0][14] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_270 )); CPLD_Reg_1_rdata_reg_2_10_14__SLICE_998 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998 ( .C1(\DC_Con2[14] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][14] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][14] ), .A0(\CPLD_Reg_1/regtable[3][14] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_294 ), .FXA(\CPLD_Reg_1/N_246 ), .OFX0(\CPLD_Reg_1/N_294 ), .OFX1(\CPLD_Reg_1/N_366 )); CPLD_Reg_1_rdata_reg_2_11_14__SLICE_999 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999 ( .C1(\DC_Con4[14] ), .B1(\CPLD_Reg_1/regtable[13][14] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[14] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][14] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_318 ), .FXA(\CPLD_Reg_1/N_270 ), .OFX0(\CPLD_Reg_1/N_318 ), .OFX1(\CPLD_Reg_1/N_342 )); CPLD_Reg_1_rdata_reg_2_9_15__SLICE_1000 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000 ( .C1(\freq4_relay[15] ), .B1(\CPLD_Reg_1/regtable[4][15] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][15] ), .A0(\CPLD_Reg_1/regtable[0][15] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_271 )); CPLD_Reg_1_rdata_reg_2_10_15__SLICE_1001 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001 ( .C1(\DC_Con2[15] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][15] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][15] ), .A0(\CPLD_Reg_1/regtable[3][15] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_295 ), .FXA(\CPLD_Reg_1/N_247 ), .OFX0(\CPLD_Reg_1/N_295 ), .OFX1(\CPLD_Reg_1/N_367 )); CPLD_Reg_1_rdata_reg_2_11_15__SLICE_1002 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002 ( .C1(\DC_Con4[15] ), .B1(\CPLD_Reg_1/regtable[13][15] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[15] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][15] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_319 ), .FXA(\CPLD_Reg_1/N_271 ), .OFX0(\CPLD_Reg_1/N_319 ), .OFX1(\CPLD_Reg_1/N_343 )); CPLD_Reg_1_rdata_reg_2_9_16__SLICE_1003 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003 ( .C1(\freq4_relay[16] ), .B1(\CPLD_Reg_1/regtable[4][16] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][16] ), .A0(\CPLD_Reg_1/regtable[0][16] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_272 )); CPLD_Reg_1_rdata_reg_2_10_16__SLICE_1004 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004 ( .C1(\DC_Con2[16] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][16] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][16] ), .A0(\CPLD_Reg_1/regtable[3][16] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_296 ), .FXA(\CPLD_Reg_1/N_248 ), .OFX0(\CPLD_Reg_1/N_296 ), .OFX1(\CPLD_Reg_1/N_368 )); CPLD_Reg_1_rdata_reg_2_11_16__SLICE_1005 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005 ( .C1(\DC_Con4[16] ), .B1(\CPLD_Reg_1/regtable[13][16] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[16] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][16] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_320 ), .FXA(\CPLD_Reg_1/N_272 ), .OFX0(\CPLD_Reg_1/N_320 ), .OFX1(\CPLD_Reg_1/N_344 )); CPLD_Reg_1_rdata_reg_2_9_17__SLICE_1006 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006 ( .C1(\freq4_relay[17] ), .B1(\CPLD_Reg_1/regtable[4][17] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][17] ), .A0(\CPLD_Reg_1/regtable[0][17] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_273 )); CPLD_Reg_1_rdata_reg_2_10_17__SLICE_1007 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007 ( .C1(\DC_Con2[17] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][17] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][17] ), .A0(\CPLD_Reg_1/regtable[3][17] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_297 ), .FXA(\CPLD_Reg_1/N_249 ), .OFX0(\CPLD_Reg_1/N_297 ), .OFX1(\CPLD_Reg_1/N_369 )); CPLD_Reg_1_rdata_reg_2_11_17__SLICE_1008 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008 ( .C1(\DC_Con4[17] ), .B1(\CPLD_Reg_1/regtable[13][17] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[17] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][17] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_321 ), .FXA(\CPLD_Reg_1/N_273 ), .OFX0(\CPLD_Reg_1/N_321 ), .OFX1(\CPLD_Reg_1/N_345 )); CPLD_Reg_1_rdata_reg_2_9_18__SLICE_1009 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009 ( .C1(\CPLD_Reg_1/regtable[5][18] ), .B1(\CPLD_Reg_1/regtable[4][18] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][18] ), .A0(\CPLD_Reg_1/regtable[0][18] ), .M0(reg_addr_2_rep1), .OFX0(\CPLD_Reg_1/N_274 )); CPLD_Reg_1_rdata_reg_2_10_18__SLICE_1010 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010 ( .C1(\DC_Con2[18] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][18] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][18] ), .A0(\CPLD_Reg_1/regtable[3][18] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_298 ), .FXA(\CPLD_Reg_1/N_250 ), .OFX0(\CPLD_Reg_1/N_298 ), .OFX1(\CPLD_Reg_1/N_370 )); CPLD_Reg_1_rdata_reg_2_11_18__SLICE_1011 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011 ( .C1(\DC_Con4[18] ), .B1(\CPLD_Reg_1/regtable[13][18] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[18] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][18] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep1), .FXB(\CPLD_Reg_1/N_322 ), .FXA(\CPLD_Reg_1/N_274 ), .OFX0(\CPLD_Reg_1/N_322 ), .OFX1(\CPLD_Reg_1/N_346 )); CPLD_Reg_1_rdata_reg_2_9_19__SLICE_1012 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012 ( .C1(\CPLD_Reg_1/regtable[5][19] ), .B1(\CPLD_Reg_1/regtable[4][19] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][19] ), .A0(\CPLD_Reg_1/regtable[0][19] ), .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_275 )); CPLD_Reg_1_rdata_reg_2_10_19__SLICE_1013 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013 ( .C1(\DC_Con2[19] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][19] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][19] ), .A0(\CPLD_Reg_1/regtable[3][19] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_299 ), .FXA(\CPLD_Reg_1/N_251 ), .OFX0(\CPLD_Reg_1/N_299 ), .OFX1(\CPLD_Reg_1/N_371 )); CPLD_Reg_1_rdata_reg_2_11_19__SLICE_1014 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014 ( .C1(\DC_Con4[19] ), .B1(\CPLD_Reg_1/regtable[13][19] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[19] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][19] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep2), .FXB(\CPLD_Reg_1/N_323 ), .FXA(\CPLD_Reg_1/N_275 ), .OFX0(\CPLD_Reg_1/N_323 ), .OFX1(\CPLD_Reg_1/N_347 )); CPLD_Reg_1_rdata_reg_2_9_21__SLICE_1015 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015 ( .C1(\CPLD_Reg_1/regtable[5][21] ), .B1(\CPLD_Reg_1/regtable[4][21] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][21] ), .A0(\CPLD_Reg_1/regtable[0][21] ), .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_277 )); CPLD_Reg_1_rdata_reg_2_10_21__SLICE_1016 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016 ( .C1(\DC_Con2[21] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][21] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][21] ), .A0(\CPLD_Reg_1/regtable[3][21] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_301 ), .FXA(\CPLD_Reg_1/N_253 ), .OFX0(\CPLD_Reg_1/N_301 ), .OFX1(\CPLD_Reg_1/N_373 )); CPLD_Reg_1_rdata_reg_2_11_21__SLICE_1017 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017 ( .C1(\DC_Con4[21] ), .B1(\CPLD_Reg_1/regtable[13][21] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[21] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][21] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep2), .FXB(\CPLD_Reg_1/N_325 ), .FXA(\CPLD_Reg_1/N_277 ), .OFX0(\CPLD_Reg_1/N_325 ), .OFX1(\CPLD_Reg_1/N_349 )); CPLD_Reg_1_rdata_reg_2_9_22__SLICE_1018 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018 ( .C1(\CPLD_Reg_1/regtable[5][22] ), .B1(\CPLD_Reg_1/regtable[4][22] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][22] ), .A0(\CPLD_Reg_1/regtable[0][22] ), .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_278 )); CPLD_Reg_1_rdata_reg_2_10_22__SLICE_1019 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019 ( .C1(\DC_Con2[22] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][22] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][22] ), .A0(\CPLD_Reg_1/regtable[3][22] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_302 ), .FXA(\CPLD_Reg_1/N_254 ), .OFX0(\CPLD_Reg_1/N_302 ), .OFX1(\CPLD_Reg_1/N_374 )); CPLD_Reg_1_rdata_reg_2_11_22__SLICE_1020 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020 ( .C1(\DC_Con4[22] ), .B1(\CPLD_Reg_1/regtable[13][22] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[22] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][22] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep2), .FXB(\CPLD_Reg_1/N_326 ), .FXA(\CPLD_Reg_1/N_278 ), .OFX0(\CPLD_Reg_1/N_326 ), .OFX1(\CPLD_Reg_1/N_350 )); CPLD_Reg_1_rdata_reg_2_9_23__SLICE_1021 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021 ( .C1(\CPLD_Reg_1/regtable[5][23] ), .B1(\CPLD_Reg_1/regtable[4][23] ), .A1(\reg_addr[0] ), .C0(\reg_addr[0] ), .B0(\CPLD_Reg_1/regtable[1][23] ), .A0(\CPLD_Reg_1/regtable[0][23] ), .M0(reg_addr_2_rep2), .OFX0(\CPLD_Reg_1/N_279 )); CPLD_Reg_1_rdata_reg_2_10_23__SLICE_1022 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022 ( .C1(\DC_Con2[23] ), .B1(reg_addr_3_rep2), .A1(\CPLD_Reg_1/regtable[15][23] ), .C0(\reg_addr[3] ), .B0(\CPLD_Reg_1/regtable[11][23] ), .A0(\CPLD_Reg_1/regtable[3][23] ), .M1(reg_addr_0_rep2), .M0(reg_addr_2_rep2), .FXB(\CPLD_Reg_1/N_303 ), .FXA(\CPLD_Reg_1/N_255 ), .OFX0(\CPLD_Reg_1/N_303 ), .OFX1(\CPLD_Reg_1/N_375 )); CPLD_Reg_1_rdata_reg_2_11_23__SLICE_1023 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023 ( .C1(\DC_Con4[23] ), .B1(\CPLD_Reg_1/regtable[13][23] ), .A1(\reg_addr[2] ), .C0(\DC_Con3[23] ), .B0(\reg_addr[2] ), .A0(\CPLD_Reg_1/regtable[12][23] ), .M1(reg_addr_3_rep1), .M0(reg_addr_0_rep2), .FXB(\CPLD_Reg_1/N_327 ), .FXA(\CPLD_Reg_1/N_279 ), .OFX0(\CPLD_Reg_1/N_327 ), .OFX1(\CPLD_Reg_1/N_351 )); BUS_Con_1_miso_shift_1_sqmuxa_i_0_SLICE_1024 \BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024 ( .C1(\BUS_Con_1/miso_loaded ), .B1(\BUS_Con_1.sclk_sync[0] ), .A1(\BUS_Con_1/sclk_sync[1] ), .D0(\BUS_Con_1/bit_cnt[3] ), .C0(\BUS_Con_1/bit_cnt[4] ), .B0(\BUS_Con_1/bit_cnt[5] ), .A0(con_rvalid), .M0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .OFX0(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_c_3_SLICE_1025 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] ) , .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/N_15 ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_addr_RNICFU83_0__SLICE_1026 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_75 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/rd_dout_te_1_u_i_a3[0] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/rd_dout_te_1_u_i_a3[0] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[0][0] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_shift_reg_11_0__SLICE_1027 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_5 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_4 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[1] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[1] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .OFX0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0] ) ); xo2chub_SLICE_1028 \xo2chub/SLICE_1028 ( .D1(\xo2chub/rom_rd_addr[3] ), .C1(\xo2chub/rom_rd_addr[2] ), .B1(\xo2chub/rom_rd_addr[1] ), .A1(\xo2chub/rom_rd_addr[0] ), .D0(\xo2chub/rom_rd_addr[3] ), .C0(\xo2chub/rom_rd_addr[2] ), .B0(\xo2chub/rom_rd_addr[1] ), .A0(\xo2chub/rom_rd_addr[0] ), .M0(\xo2chub/rom_rd_addr[4] ), .OFX0(\xo2chub/genblk1.jtaghub_rom_0_0_0_f5a )); SLICE_1029 SLICE_1029( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] ) , .M1(\xo2chub/rom_rd_addr[5] ), .FXB(\xo2chub/genblk1.jtaghub_rom_0_0_1_f5b ), .FXA(\xo2chub/genblk1.jtaghub_rom_0_0_0_f5a ), .OFX0(\xo2chub/genblk1.jtaghub_rom_0_0_1_f5b ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 ) , .OFX1(\xo2chub/genblk1.jtaghub_rom_0_0_f5a )); SLICE_1030 SLICE_1030( .B1(con_rvalid), .A1(\BUS_Con_1/bit_cnt[3] ), .M1(\xo2chub/rom_rd_addr[6] ), .FXB(\xo2chub/genblk1.jtaghub_rom_0_1_f5b ), .FXA(\xo2chub/genblk1.jtaghub_rom_0_0_f5a ), .OFX0(\xo2chub/genblk1.jtaghub_rom_0_1_0_f5a ), .F1(\BUS_Con_1/miso_shift9_1 ), .OFX1(\xo2chub/genblk1.jtaghub_rom_0_f5a )); CPLD_Reg_1_SLICE_1031 \CPLD_Reg_1/SLICE_1031 ( .B1(\CPLD_Reg_1/reg_err_flag ), .A1(cpld_err_flag), .FXA(\xo2chub/genblk1.jtaghub_rom_0_1_0_f5a ), .F1(o_err_c), .OFX1(\xo2chub/genblk1.jtaghub_rom_0_1_f5b )); SLICE_1032 SLICE_1032( .B1(\DC_Con2[20] ), .A1(\DC_Con2[19] ), .M1(\xo2chub/rom_rd_addr[7] ), .FXB(\xo2chub/genblk1.jtaghub_rom_1_f5b ), .FXA(\xo2chub/genblk1.jtaghub_rom_0_f5a ), .OFX0(\xo2chub/genblk1.jtaghub_rom_1_0_0_f5a ), .F1(\CPLD_Con_1/err_flag53lto4_1 ), .OFX1(\xo2chub/rom_dout )); CPLD_Con_1_SLICE_1033 \CPLD_Con_1/SLICE_1033 ( .B1(\CPLD_Con_1/dc_t[1] ), .A1(\CPLD_Con_1/dc_t[0] ), .M0(\DC_Con3[0] ), .FXA(\xo2chub/genblk1.jtaghub_rom_1_0_0_f5a ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .Q0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), .F1(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_o2_1_0_0_0 ), .OFX1(\xo2chub/genblk1.jtaghub_rom_1_0_f5a )); CPLD_Con_1_SLICE_1034 \CPLD_Con_1/SLICE_1034 ( .C1(\DC_Con4[21] ), .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .FXA(\xo2chub/genblk1.jtaghub_rom_1_0_f5a ), .F1(\CPLD_Con_1/un90_RC_RLSel_c5_a0_2 ), .OFX1(\xo2chub/genblk1.jtaghub_rom_1_f5b )); SLICE_1035 SLICE_1035( .D1(\CPLD_Con_1/SUM1_0 ), .C1(\CPLD_Con_1/SUM0_0 ), .B1(\CPLD_Con_1/SUM1 ), .A1(\CPLD_Con_1/SUM0 ), .M1(\DPS_FS_4[1] ), .M0(\DPS_FS_4[0] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[187] ) , .F1(\CPLD_Con_1/un1_en_t_c2 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[188] ) ); SLICE_1036 SLICE_1036( .D1(\DC_Con1[21] ), .C1(\CPLD_Con_1/un15_RC_RLSel_c4_i ), .B1(\CPLD_Con_1/un11_RC_RLSellt4 ), .A1(\CPLD_Con_1/RC_VSel38 ), .D0(\CPLD_Con_1/un15_RC_RLSel_c4_i ), .C0(\DC_Con1[21] ), .B0(\CPLD_Con_1/RC_RLSel_1_sqmuxa_3 ), .A0(\CPLD_Con_1/un15_RC_RLSel_axbxc3 ), .M1(\RC_RLSel[11] ), .M0(\DPS_FS_2[14] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_23 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[169] ) , .F1(\CPLD_Con_1/RC_RLSel_1_sqmuxa_3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] ) ); SLICE_1037 SLICE_1037( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_207 ), .B1(\CPLD_Con_1/io_RC9 ), .A1(\CPLD_Con_1/RC_VSel39 ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_364 ), .B0(\CPLD_Con_1/N_195 ), .A0(\CPLD_Con_1/io_RC9 ), .M1(\BUS_Con_1/recv_reg[9] ), .M0(\BUS_Con_1/mosi_sync[1] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_0 ), .Q0(\BUS_Con_1/recv_reg[0] ), .F1(\CPLD_Con_1/N_364 ), .Q1(\BUS_Con_1/recv_reg[10] )); SLICE_1038 SLICE_1038( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_184 ), .B1(\CPLD_Con_1/io_RC9 ), .A1(\CPLD_Con_1/g0_10_1 ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/io_RC9 ), .B0(\CPLD_Con_1/exec_flag_rep1 ), .A0(\CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_o2_1_0_0_0 ), .M1(\DPS_FS_1[3] ), .M0(\DPS_FS_1[2] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_184 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[141] ) , .F1(\CPLD_Con_1/g0_0_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[142] ) ); SLICE_1039 SLICE_1039( .D1(\DC_Con4[20] ), .C1(\DC_Con4[19] ), .B1(\DC_Con4[17] ), .A1(\CPLD_Con_1/g0_48_sx ), .D0(\DC_Con4[21] ), .C0(\DC_Con4[20] ), .B0(\DC_Con4[19] ), .A0(\DC_Con4[18] ), .M1(\DPS_FS_2[7] ), .M0(\DPS_FS_2[6] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_48_sx ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[161] ) , .F1(\CPLD_Con_1/err_flag97 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[162] ) ); BUS_Con_1_SLICE_1040 \BUS_Con_1/SLICE_1040 ( .D1(\BUS_Con_1/state[0] ), .C1(\BUS_Con_1/state[1] ), .B1(\BUS_Con_1/data_out_0_sqmuxa ), .A1(reg_busy), .D0(\BUS_Con_1/state[0] ), .C0(\BUS_Con_1/state[1] ), .B0(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .A0(i_rst_n_c), .M1(\BUS_Con_1/recv_reg[1] ), .M0(\BUS_Con_1/recv_reg[19] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/state_RNIS4Q6[0] ), .Q0(\w_data[19] ), .F1(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .Q1(\w_data[1] )); SLICE_1041 SLICE_1041( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0_1 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .B1(jtaghub16_ip_enable0), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_tz ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0 ) , .B0(jtaghub16_ip_enable0), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_55 ) , .Q0(\DC_Con2[22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0 ) , .Q1(\DC_Con2[23] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1042 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1042 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_786 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_0 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_786 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] ) ); SLICE_1043 SLICE_1043( .D1(\CPLD_Con_1/N_250 ), .C1(\CPLD_Con_1/N_162 ), .B1(\CPLD_Con_1/un1_i_DC_Con1_2 ), .A1(\CPLD_Con_1/DMM_en_cnst_0_a2_0[2] ), .D0(\DC_Con1[8] ), .C0(\DC_Con1[7] ), .B0(\DC_Con1[9] ), .A0(\CPLD_Con_1/N_162 ), .M1(\FSMC[2] ), .M0(\FSMC[1] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con1_2 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[204] ) , .F1(\CPLD_Con_1/DMM_en_cnst[2] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[205] ) ); SLICE_1044 SLICE_1044( .D1(\DC_Con3[9] ), .C1(\DC_Con3[7] ), .B1(\DC_Con3[6] ), .A1(\CPLD_Con_1/PMU_OC_312_1 ), .D0(\DC_Con3[8] ), .C0(\DC_Con3[9] ), .B0(\CPLD_Con_1/N_187 ), .A0(\CPLD_Con_1/N_416 ), .M1(\BUS_Con_1/recv_reg[20] ), .M0(\BUS_Con_1/recv_reg[19] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_354 ), .Q0(\BUS_Con_1/recv_reg[20] ), .F1(\CPLD_Con_1/N_187 ), .Q1(\BUS_Con_1/recv_reg[21] )); SLICE_1045 SLICE_1045( .D1(\DC_Con2[21] ), .C1(\DC_Con2[20] ), .B1(\CPLD_Con_1/un40_RC_RLSel_c3_d ), .A1(\CPLD_Con_1/RC_N_5_mux ), .C0(\DC_Con2[20] ), .B0(\DC_Con2[17] ), .A0(\CPLD_Con_1/N_50 ), .M1(\DC_Con2[15] ), .M0(\DC_Con2[14] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_48 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] ) , .F1(\CPLD_Con_1/N_50 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] ) ); SLICE_1046 SLICE_1046( .C1(\DC_Con2[19] ), .B1(\DC_Con2[18] ), .A1(\DC_Con2[17] ), .D0(\DC_Con2[20] ), .C0(\CPLD_Con_1/un45_RC_RLSel_m_1[16] ), .B0(\DC_Con2[17] ), .A0(\CPLD_Con_1/N_41 ), .M1(\xo2chub/er1_shift_reg[9] ), .M0(\xo2chub/er1_shift_reg[8] ), .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un45_RC_RLSel_m[16] ), .Q0(\xo2chub/ip_enable[4] ), .F1(\CPLD_Con_1/N_41 ), .Q1(\xo2chub/ip_enable[5] )); SLICE_1047 SLICE_1047( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .D0(\DC_Con4[17] ), .C0(\DC_Con4[20] ), .B0(\CPLD_Con_1/N_84 ), .A0(\CPLD_Con_1/N_89 ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un95_RC_RLSel_m[2] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] ) , .F1(\CPLD_Con_1/N_89 )); SLICE_1048 SLICE_1048( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .D0(\DC_Con4[17] ), .C0(\DC_Con4[20] ), .B0(\CPLD_Con_1/N_84 ), .A0(\CPLD_Con_1/N_92 ), .M0(\BUS_Con_1.sclk_sync[0] ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un95_RC_RLSel_m[6] ), .Q0(\BUS_Con_1/sclk_sync[1] ), .F1(\CPLD_Con_1/N_92 )); SLICE_1049 SLICE_1049( .C1(\DC_Con2[19] ), .B1(\DC_Con2[18] ), .A1(\DC_Con2[17] ), .D0(\DC_Con2[20] ), .C0(\DC_Con2[17] ), .B0(\CPLD_Con_1/N_45 ), .A0(\CPLD_Con_1/N_50 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un45_RC_RLSel_m[2] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] ) , .F1(\CPLD_Con_1/N_45 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity )); SLICE_1050 SLICE_1050( .D1(\DC_Con2[20] ), .C1(\DC_Con2[19] ), .B1(\DC_Con2[18] ), .A1(\DC_Con2[17] ), .C0(\CPLD_Con_1/N_50 ), .B0(\DC_Con2[17] ), .A0(\CPLD_Con_1/un40_RC_RLSel_axbxc3 ), .M1(\DC_Con2[12] ), .M0(\DC_Con2[11] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_47 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] ) , .F1(\CPLD_Con_1/un40_RC_RLSel_axbxc3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] ) ); SLICE_1051 SLICE_1051( .C1(\DC_Con2[19] ), .B1(\DC_Con2[18] ), .A1(\DC_Con2[17] ), .D0(\CPLD_Con_1/N_50 ), .C0(\CPLD_Con_1/N_43 ), .B0(\DC_Con2[17] ), .A0(\CPLD_Con_1/un40_RC_RLSel_axbxc3 ), .M1(\xo2chub/er1_shift_reg[18] ), .M0(\xo2chub/er1_shift_reg[17] ), .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un45_RC_RLSel_m[5] ), .Q0(\xo2chub/er1_shift_reg[16] ), .F1(\CPLD_Con_1/N_43 ), .Q1(\xo2chub/er1_shift_reg[17] )); SLICE_1052 SLICE_1052( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .D0(\CPLD_Con_1/N_88 ), .C0(\CPLD_Con_1/N_86 ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[12] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[12] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[15] ) , .F1(\CPLD_Con_1/N_88 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[1] ) ); SLICE_1053 SLICE_1053( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .D0(\CPLD_Con_1/N_87 ), .C0(\CPLD_Con_1/N_86 ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[9] ), .M1(\xo2chub/er1_shift_reg[12] ), .M0(\xo2chub/er1_shift_reg[11] ), .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[9] ), .Q0(\xo2chub/er1_shift_reg[10] ), .F1(\CPLD_Con_1/N_87 ), .Q1(\xo2chub/er1_shift_reg[11] )); SLICE_1054 SLICE_1054( .D1(\CPLD_Con_1/N_182 ), .C1(\CPLD_Con_1/exec_flag_rep1 ), .B1(\CPLD_Con_1/RC_VSel40 ), .A1(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 ), .D0(\CPLD_Con_1/N_275 ), .C0(\CPLD_Con_1/N_182 ), .B0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .A0(\CPLD_Con_1/exec_flag ), .M1(\FSMC[0] ), .M0(\DPS_FS_4[15] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_24 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[202] ) , .F1(\CPLD_Con_1/N_275 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[203] ) ); SLICE_1055 SLICE_1055( .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_75 ), .C0(\CPLD_Con_1/N_72 ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1 ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_0[12] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] ) , .F1(\CPLD_Con_1/N_75 )); SLICE_1056 SLICE_1056( .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_73 ), .C0(\CPLD_Con_1/N_72 ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_0[9] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[0] ) , .F1(\CPLD_Con_1/N_73 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[10] ) ); SLICE_1057 SLICE_1057( .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_81 ), .C0(\CPLD_Con_1/N_72 ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1 ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_0[15] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] ) , .F1(\CPLD_Con_1/N_81 )); SLICE_1058 SLICE_1058( .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\CPLD_Con_1/N_78 ), .C0(\CPLD_Con_1/N_72 ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_0[10] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] ) , .F1(\CPLD_Con_1/N_78 )); SLICE_1059 SLICE_1059( .D1(\CPLD_Con_1/N_416 ), .C1(\CPLD_Con_1/N_218 ), .B1(\CPLD_Con_1/PMU_OC_312lto8_0_a2_0 ), .A1(\CPLD_Con_1/PMU_OC_312_1 ), .D0(\CPLD_Con_1/N_218 ), .C0(\CPLD_Con_1/N_187 ), .B0(\CPLD_Con_1/PMU_OC_313 ), .A0(\CPLD_Con_1/PMU_OC_3_11_6_0_a2_0 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[88] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[87] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_349 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] ) , .F1(\CPLD_Con_1/PMU_OC_3_11_6_0_a2_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] ) ); SLICE_1060 SLICE_1060( .D1(\DC_Con1[5] ), .C1(\DC_Con1[4] ), .B1(\DC_Con1[2] ), .A1(\CPLD_Con_1/DPS_m3_0_a2_2_1 ), .D0(\DC_Con1[2] ), .C0(\DC_Con1[1] ), .B0(\CPLD_Con_1/DPS_m4_0 ), .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_3[12] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[42] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[41] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_154 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] ) , .F1(\CPLD_Con_1/DPS_m4_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] ) ); CPLD_Con_1_SLICE_1061 \CPLD_Con_1/SLICE_1061 ( .D1(\DC_Con4[5] ), .C1(\DC_Con4[4] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_c3 ), .A1(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .D0(\DC_Con4[4] ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), .A0(\DC_Con4[1] ), .F0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .F1(\CPLD_Con_1/g4_0_0_0_1 )); SLICE_1062 SLICE_1062( .D1(\DC_Con3[7] ), .C1(\CPLD_Con_1/un1_i_DC_Con1_iv_0[0] ), .B1(\CPLD_Con_1/i_DC_Con4_m[7] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/dc_slot_flag[2] ), .M1(\BUS_Con_1/recv_reg[24] ), .M0(\BUS_Con_1/recv_reg[23] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_a2_0[8] ), .Q0(\BUS_Con_1/recv_reg[24] ), .F1(\CPLD_Con_1/un1_i_DC_Con1[0] ), .Q1(\BUS_Con_1/recv_reg[25] )); SLICE_1063 SLICE_1063( .D1(\CPLD_Con_1/N_250 ), .C1(\DC_Con1[7] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_c9_a0_2 ), .A1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), .D0(\DC_Con1[7] ), .C0(\DC_Con1[3] ), .B0(\DC_Con1[1] ), .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_0[12] ), .M1(\DC_Con2[10] ), .M0(\DC_Con2[9] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_c9_a0_2 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] ) , .F1(\CPLD_Con_1/err_flag22_2 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] ) ); CPLD_Con_1_SLICE_1064 \CPLD_Con_1/SLICE_1064 ( .D1(\DC_Con1[23] ), .C1(\CPLD_Con_1/un17lt8 ), .B1(\CPLD_Con_1/err_flag_en_0_a2_3_1 ), .A1(\CPLD_Con_1/err_flag22_2 ), .D0(\CPLD_Con_1/N_182 ), .C0(\DC_Con1[23] ), .B0(\CPLD_Con_1/g0_32 ), .A0(\CPLD_Con_1/RC_VSel38 ), .M0(\CPLD_Con_1/exec_flag ), .CE(\CPLD_Con_1/N_172 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_a2_3_1 ), .Q0(o_con_done_c), .F1(\CPLD_Con_1/N_385 )); SLICE_1065 SLICE_1065( .D1(\DC_Con4[21] ), .C1(\DC_Con4[18] ), .B1(\DC_Con4[17] ), .A1(\CPLD_Con_1/g0_41_1_0 ), .D0(\DC_Con4[23] ), .C0(\DC_Con4[21] ), .B0(\DC_Con4[20] ), .A0(\DC_Con4[19] ), .M1(\DPS_FS_2[5] ), .M0(\RC_RLSel[10] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_41_1_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] ) , .F1(\CPLD_Con_1/DMM_en_1_sqmuxa_3_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[160] ) ); BUS_Con_1_SLICE_1066 \BUS_Con_1/SLICE_1066 ( .D1(\BUS_Con_1/miso_shift9_2 ), .C1(\BUS_Con_1/err_flag8_1 ), .B1(\BUS_Con_1/bit_cnt[3] ), .A1(\BUS_Con_1/bit_cnt[2] ), .D0(\BUS_Con_1/recv_reg[6] ), .C0(\BUS_Con_1/err_flag8_2 ), .B0(\BUS_Con_1/err_flag8_1 ), .A0(\BUS_Con_1/data_ready17 ), .M1(\BUS_Con_1/recv_reg[3] ), .M0(\BUS_Con_1/recv_reg[2] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/un1_err_flag8 ), .Q0(\w_data[2] ), .F1(\BUS_Con_1/data_ready17 ), .Q1(\w_data[3] )); SLICE_1067 SLICE_1067( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un15_jtdo_first_bit ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_m_2[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_tm_m_1_0[0] ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4 ) , .Q0(\CPLD_Reg_1/regtable[10][20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_m_2[0] ) , .Q1(\CPLD_Reg_1/regtable[10][21] )); SLICE_1068 SLICE_1068( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_m2_0 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1_N_5_mux ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/d_N_5_mux ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_m2_0 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_70 ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/d_N_5_mux ) , .Q0(\CPLD_Reg_1/regtable[10][6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1 ) , .Q1(\CPLD_Reg_1/regtable[10][7] )); SLICE_1069 SLICE_1069( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un4_jupdate_early_i_o2_RNIQKF31[0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en_RNIGKQS ) , .B1(jtaghub16_ip_enable0), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , .B0(jtaghub16_ip_enable0), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .Q0(\DC_Con3[0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnte ) , .Q1(\DC_Con3[10] )); SLICE_1070 SLICE_1070( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_RNI5CHP ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_51_i ), .Q0(\DC_Con3[20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_RNI5CHP ) , .Q1(\DC_Con3[21] )); SLICE_1071 SLICE_1071( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_876 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_808 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] ) , .Q0(\DC_Con4[6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_808 ), .Q1(\DC_Con4[7] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1072 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1072 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_819 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_1 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_819 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1073 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1073 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_a2_0_0 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_822 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_2 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_822 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] ) ); SLICE_1074 SLICE_1074( .D1(\DC_Con1[23] ), .C1(\CPLD_Con_1/g0_32 ), .B1(\CPLD_Con_1/RC_VSel38 ), .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3_RNO ), .C0(\CPLD_Con_1/freq_t_fast[0] ), .B0(\CPLD_Con_1/freq_t_fast[1] ), .A0(i_rst_n_c), .M1(\BUS_Con_1/recv_reg[0] ), .M0(\BUS_Con_1/recv_reg[18] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3_RNO ), .Q0(\BUS_Con_1/recv_reg[19] ), .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3 ), .Q1(\BUS_Con_1/recv_reg[1] )); SLICE_1075 SLICE_1075( .D1(\CPLD_Con_1/un3_DPS_FS_1_c9_a0_2 ), .C1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), .B1(\CPLD_Con_1/g0_2_0_N_2L1 ), .A1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1 ), .C0(\DC_Con1[8] ), .B0(\DC_Con1[9] ), .A0(\DC_Con1[7] ), .M1(\DPS_FS_2[4] ), .M0(\DPS_FS_2[3] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_2_0_N_2L1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[158] ) , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_RNI1TUB1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[159] ) ); SLICE_1076 SLICE_1076( .D1(\DC_Con3[23] ), .C1(\CPLD_Con_1/err_flag75 ), .B1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_N_2L1_0 ), .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_1 ), .D0(\CPLD_Con_1/freq_t_fast[0] ), .C0(\CPLD_Con_1/freq_t_fast[1] ), .B0(\CPLD_Con_1/RC_VSel40 ), .A0(i_rst_n_c), .M1(\BUS_Con_1/recv_reg[13] ), .M0(\BUS_Con_1/recv_reg[12] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_1 ), .Q0(\BUS_Con_1/recv_reg[13] ), .F1(\CPLD_Con_1/N_410 ), .Q1(\BUS_Con_1/recv_reg[14] )); SLICE_1077 SLICE_1077( .D1(\DC_Con4[9] ), .C1(\CPLD_Con_1/un4_DPS_FS_4_c8_i ), .B1(\CPLD_Con_1/g0_27_1 ), .A1(\CPLD_Con_1/DMM_en_1_sqmuxa_3_0 ), .D0(\CPLD_Con_1/freq_t_fast[0] ), .C0(\CPLD_Con_1/freq_t_fast[1] ), .B0(\CPLD_Con_1/RC_VSel41 ), .A0(i_rst_n_c), .M1(\DC_Con4[22] ), .M0(\DC_Con4[21] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_27_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] ) , .F1(\CPLD_Con_1/N_366 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] ) ); SLICE_1078 SLICE_1078( .C1(\CPLD_Con_1/N_184 ), .B1(\CPLD_Con_1/g1_1 ), .A1(\CPLD_Con_1/g1_0_1 ), .D0(\CPLD_Con_1/freq_t_fast[0] ), .C0(\CPLD_Con_1/freq_t_fast[1] ), .B0(\CPLD_Con_1/PMU_m1_e_0 ), .A0(i_rst_n_c), .M1(\DPS_FS_2[0] ), .M0(\DPS_FS_1[15] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1_0_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[154] ) , .F1(\CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[155] ) ); SLICE_1079 SLICE_1079( .C1(\CPLD_Con_1/un1_PMU_OC_120 ), .B1(\CPLD_Con_1/g0_5_1 ), .A1(\CPLD_Con_1/PMU_OC_121 ), .D0(\CPLD_Con_1/freq_t_fast[0] ), .C0(\CPLD_Con_1/freq_t_fast[1] ), .B0(\CPLD_Con_1/freq_slot_flag[0] ), .A0(i_rst_n_c), .M1(\DPS_FS_1[7] ), .M0(\DPS_FS_1[6] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_5_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[145] ) , .F1(\CPLD_Con_1/N_374 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[146] ) ); CPLD_Con_1_SLICE_1080 \CPLD_Con_1/SLICE_1080 ( .C1(\CPLD_Con_1/g0_17_rn_1 ), .B1(\CPLD_Con_1/err_flag31 ), .A1(\CPLD_Con_1/RC_VSel38 ), .D0(\CPLD_Con_1/freq_t_fast[0] ), .C0(\CPLD_Con_1/freq_t_fast[1] ), .B0(\CPLD_Con_1/g0_10_1 ), .A0(i_rst_n_c), .M1(\CPLD_Con_1/SUM1 ), .M0(\CPLD_Con_1/SUM0 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1 ), .Q0(\CPLD_Con_1/freq_t_fast[0] ), .F1(\CPLD_Con_1/g0_10_1 ), .Q1(\CPLD_Con_1/freq_t_fast[1] )); SLICE_1081 SLICE_1081( .D1(\DC_Con3[8] ), .C1(\DC_Con3[7] ), .B1(\CPLD_Con_1/un16lto5_4_i_a2_0 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1 ), .D0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV ), .C0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .B0(\DC_Con3[6] ), .A0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[59] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[58] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPS_FS_3_9_i_a2_4[0] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] ) , .F1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] ) ); SLICE_1082 SLICE_1082( .D1(\DC_Con4[4] ), .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), .D0(\DC_Con4[5] ), .C0(\DC_Con4[6] ), .B0(\CPLD_Con_1/N_74 ), .A0(\CPLD_Con_1/N_134_1 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[201] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[200] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_134 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[200] ) , .F1(\CPLD_Con_1/N_74 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[201] ) ); SLICE_1083 SLICE_1083( .D1(\CPLD_Con_1/freq_slot_flag[3] ), .C1(\CPLD_Con_1/freq_slot_flag[2] ), .B1(\CPLD_Con_1/freq_slot_flag[1] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), .C0(\CPLD_Con_1/freq_t_fast[0] ), .B0(\CPLD_Con_1/freq_t_fast[1] ), .A0(\CPLD_Con_1/PMU_OC_121 ), .M1(\DPS_FS_1[14] ), .M0(\DPS_FS_1[13] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_4_1_sqmuxa ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[152] ) , .F1(\CPLD_Con_1/PMU_OC_121 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[153] ) ); CPLD_Con_1_SLICE_1084 \CPLD_Con_1/SLICE_1084 ( .D1(\DC_Con3[6] ), .C1(\DC_Con3[5] ), .B1(\DC_Con3[3] ), .A1(\DC_Con3[2] ), .D0(\DC_Con3[1] ), .C0(\DC_Con3[4] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1 ), .A0(\DC_Con3[7] ), .F0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV ), .F1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1 )); SLICE_1085 SLICE_1085( .D1(\DC_Con2[6] ), .C1(\DC_Con2[5] ), .B1(\DC_Con2[4] ), .A1(\DC_Con2[2] ), .D0(\DC_Con2[1] ), .C0(\DC_Con2[3] ), .B0(\CPLD_Con_1/un4_DPS_FS_2_c6_a0_2 ), .A0(\DC_Con2[7] ), .M1(\DC_Con3[15] ), .M0(\DC_Con3[14] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_c6_a0_2_RNIUHVQ ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] ) , .F1(\CPLD_Con_1/un4_DPS_FS_2_c6_a0_2 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] ) ); SLICE_1086 SLICE_1086( .C1(\DC_Con1[6] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .A1(\CPLD_Con_1/N_35_3 ), .D0(\DC_Con1[1] ), .C0(\DC_Con1[3] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), .A0(\DC_Con1[7] ), .M1(\DC_Con2[8] ), .M0(\DC_Con2[7] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] ) , .F1(\CPLD_Con_1.N_103_3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] ) ); SLICE_1087 SLICE_1087( .D1(\CPLD_Con_1/N_57 ), .C1(\DC_Con4[8] ), .B1(\DC_Con4[7] ), .A1(\DC_Con4[4] ), .D0(\DC_Con4[9] ), .C0(i_rst_n_c), .B0(\CPLD_Con_1/DMM_en_cnst_0_a2_i_0[14] ), .A0(\CPLD_Con_1/PMU_OC_4_1_sqmuxa ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[24] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[23] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DMM_en_cnst_0_a2_i_1[14] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] ) , .F1(\CPLD_Con_1/DMM_en_cnst_0_a2_i_0[14] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] ) ); SLICE_1088 SLICE_1088( .D1(\CPLD_Con_1/N_437 ), .C1(\CPLD_Con_1/N_404 ), .B1(\CPLD_Con_1/N_350_1 ), .A1(\CPLD_Con_1/N_349 ), .D0(\CPLD_Con_1/freq_t_fast[0] ), .C0(\CPLD_Con_1/freq_t_fast[1] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV ), .A0(i_rst_n_c), .M1(\DPS_FS_1[12] ), .M0(\DPS_FS_1[11] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_350_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[150] ) , .F1(\CPLD_Con_1.N_532 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[151] ) ); SLICE_1089 SLICE_1089( .D1(\CPLD_Con_1/N_59 ), .C1(\CPLD_Con_1/io_RC9 ), .B1(\CPLD_Con_1/err_flag89_2 ), .A1(\CPLD_Con_1/PMU_OC_121 ), .D0(\DC_Con4[5] ), .C0(\DC_Con4[6] ), .B0(\CPLD_Con_1/N_74 ), .A0(\CPLD_Con_1/N_134_1 ), .M0(\BUS_Con_1/recv_reg[6] ), .CE(\BUS_Con_1/wr_flag_0_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_a4_0[13] ), .Q0(\BUS_Con_1/wr_flag ), .F1(\CPLD_Con_1/N_134_1 )); SLICE_1090 SLICE_1090( .B1(\DC_Con2[6] ), .A1(\DC_Con2[5] ), .D0(\DC_Con2[7] ), .C0(\CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0 ), .B0(\DC_Con2[8] ), .A0(\CPLD_Con_1/N_246 ), .M1(\FSMC[2] ), .M0(\FSMC[1] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con2_1_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[208] ) , .F1(\CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[209] ) ); SLICE_1091 SLICE_1091( .D1(\CPLD_Con_1/N_150 ), .C1(\DC_Con1[6] ), .B1(\DC_Con1[5] ), .A1(\DC_Con1[4] ), .D0(\DC_Con1[8] ), .C0(\DC_Con1[9] ), .B0(\DC_Con1[7] ), .A0(\CPLD_Con_1/N_162 ), .M1(\BUS_Con_1/recv_reg[6] ), .M0(\BUS_Con_1/recv_reg[5] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_255 ), .Q0(\BUS_Con_1/recv_reg[6] ), .F1(\CPLD_Con_1/N_162 ), .Q1(\BUS_Con_1/recv_reg[7] )); SLICE_1092 SLICE_1092( .D1(\DC_Con3[20] ), .C1(\CPLD_Con_1/un70_RC_RLSel_m_1[0] ), .B1(\CPLD_Con_1/un65_RC_RLSel_c3 ), .A1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), .D0(\DC_Con3[18] ), .C0(\DC_Con3[19] ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/N_70 ), .M1(\xo2chub/er1_shift_reg[20] ), .M0(\xo2chub/er1_shift_reg[19] ), .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un70_RC_RLSel_m[7] ), .Q0(\xo2chub/er1_shift_reg[18] ), .F1(\CPLD_Con_1/N_70 ), .Q1(\xo2chub/er1_shift_reg[19] )); SLICE_1093 SLICE_1093( .D1(\DC_Con3[20] ), .C1(\CPLD_Con_1/un70_RC_RLSel_m_1[0] ), .B1(\CPLD_Con_1/un65_RC_RLSel_c3 ), .A1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), .D0(\DC_Con3[18] ), .C0(\DC_Con3[19] ), .B0(\CPLD_Con_1/un70_RC_RLSel_m_0_a2_1[16] ), .A0(\DC_Con3[17] ), .M1(jtaghub16_jshift), .M0(jtaghub16_jshift), .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un70_RC_RLSel_m[17] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ) , .F1(\CPLD_Con_1/un70_RC_RLSel_m_0_a2_1[16] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ) ); SLICE_1094 SLICE_1094( .D1(\CPLD_Con_1/N_84 ), .C1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_1[1] ), .B1(\CPLD_Con_1/un70_RC_RLSel_m[1] ), .A1(\CPLD_Con_1/un20_RC_RLSel_m[1] ), .D0(\DC_Con3[18] ), .C0(\DC_Con3[19] ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/N_70 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un70_RC_RLSel_m[1] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] ) , .F1(\CPLD_Con_1/RC_RLSel_13_0_iv_1[1] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] ) ); SLICE_1095 SLICE_1095( .D1(\CPLD_Con_1/N_84 ), .C1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[4] ), .B1(\CPLD_Con_1/un70_RC_RLSel_m[4] ), .A1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .D0(\DC_Con3[18] ), .C0(\DC_Con3[19] ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/N_70 ), .M1(\xo2chub/er1_shift_reg[16] ), .M0(\xo2chub/er1_shift_reg[15] ), .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un70_RC_RLSel_m[4] ), .Q0(\xo2chub/er1_shift_reg[14] ), .F1(\CPLD_Con_1/RC_RLSel_13_iv_1[4] ), .Q1(\xo2chub/er1_shift_reg[15] )); SLICE_1096 SLICE_1096( .D1(\CPLD_Con_1/N_84 ), .C1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[3] ), .B1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), .A1(\CPLD_Con_1/un70_RC_RLSel_m[3] ), .D0(\DC_Con3[18] ), .C0(\DC_Con3[19] ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/N_70 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un70_RC_RLSel_m[3] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] ) , .F1(\CPLD_Con_1/RC_RLSel_13_0_iv_0[3] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] ) ); SLICE_1097 SLICE_1097( .C1(\CPLD_Con_1/N_84 ), .B1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[0] ), .A1(\CPLD_Con_1/un45_RC_RLSel_m[0] ), .D0(\DC_Con2[20] ), .C0(\DC_Con2[17] ), .B0(\CPLD_Con_1/N_41 ), .A0(\CPLD_Con_1/N_50 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un45_RC_RLSel_m[0] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] ) , .F1(\CPLD_Con_1/RC_RLSel_13_0_iv_i_1[0] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] ) ); SLICE_1098 SLICE_1098( .C1(\DC_Con3[5] ), .B1(\CPLD_Con_1/un4_DPS_FS_3_c3 ), .A1(\CPLD_Con_1/PMU_OC_3_11_0_a2_0_0[7] ), .D0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .C0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .B0(\DC_Con3[6] ), .A0(\CPLD_Con_1/N_447 ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_3_11[7] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ) , .F1(\CPLD_Con_1/N_447 )); SLICE_1099 SLICE_1099( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), .A1(\DC_Con3[1] ), .D0(\CPLD_Con_1/PMU_OC_3_11_0_a2_0_0[7] ), .C0(\CPLD_Con_1/un4_DPS_FS_3_c3 ), .B0(\DC_Con3[5] ), .A0(\CPLD_Con_1/N_437 ), .M1(\DC_Con3[20] ), .M0(\DC_Con3[19] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_3_11[19] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] ) , .F1(\CPLD_Con_1/un4_DPS_FS_3_c3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] ) ); SLICE_1100 SLICE_1100( .D1(\DC_Con3[5] ), .C1(\DC_Con3[2] ), .B1(\DC_Con3[1] ), .A1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0_0 ), .D0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .C0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .B0(\DC_Con3[6] ), .A0(\CPLD_Con_1/N_447 ), .M1(con_exec), .M0(\RC_RLSel[4] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_3_11[23] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] ) , .F1(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) ); SLICE_1101 SLICE_1101( .D1(\CPLD_Con_1/N_391 ), .C1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV ), .B1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .A1(\CPLD_Con_1/RC_VSel40 ), .D0(\CPLD_Con_1/PMU_OC_3_11_0_a2_0_0[7] ), .C0(\CPLD_Con_1/un4_DPS_FS_3_c3 ), .B0(\DC_Con3[5] ), .A0(\CPLD_Con_1/N_426 ), .M1(\DC_Con3[22] ), .M0(\DC_Con3[21] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_3_11[3] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] ) , .F1(\CPLD_Con_1/PMU_OC_3_11_0_a2_0_0[7] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] ) ); SLICE_1102 SLICE_1102( .D1(\DC_Con1[8] ), .C1(\DC_Con1[7] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), .A1(\CPLD_Con_1/DPS_m3_0_a2_2_1 ), .D0(\CPLD_Con_1/N_35_3 ), .C0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .B0(\DC_Con1[6] ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .M1(\DC_Con1[17] ), .M0(\DC_Con1[20] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[22] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] ) , .F1(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] ) ); SLICE_1103 SLICE_1103( .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), .A1(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .D0(\CPLD_Con_1/N_34_3 ), .C0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .B0(\DC_Con1[6] ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .M1(\DC_Con1[19] ), .M0(\DC_Con1[18] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[21] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] ) , .F1(\CPLD_Con_1/N_34_3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] ) ); SLICE_1104 SLICE_1104( .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), .A1(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .D0(\CPLD_Con_1/N_33_3 ), .C0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .B0(\DC_Con1[6] ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .M1(\DC_Con1[21] ), .M0(\DC_Con1[20] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[20] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] ) , .F1(\CPLD_Con_1/N_33_3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] ) ); SLICE_1105 SLICE_1105( .D1(\DC_Con4[5] ), .C1(\DC_Con4[2] ), .B1(\DC_Con4[1] ), .A1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1 ), .D0(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), .C0(\DC_Con4[6] ), .B0(\CPLD_Con_1/N_11 ), .A0(\CPLD_Con_1/N_122 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.N_644 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] ) , .F1(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] ) ); SLICE_1106 SLICE_1106( .C1(\DC_Con4[5] ), .B1(\DC_Con4[4] ), .A1(\CPLD_Con_1/un4_DPS_FS_4_c3 ), .D0(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), .C0(\DC_Con4[6] ), .B0(\CPLD_Con_1/N_33_1 ), .A0(\CPLD_Con_1/N_122 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[97] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[96] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.N_608 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] ) , .F1(\CPLD_Con_1/N_33_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] ) ); CPLD_Con_1_SLICE_1107 \CPLD_Con_1/SLICE_1107 ( .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), .D0(\CPLD_Con_1/un4_DPS_FS_4_c3 ), .C0(\DC_Con4[4] ), .B0(\DC_Con4[5] ), .A0(N_438), .F0(\CPLD_Con_1.N_742 ), .F1(\CPLD_Con_1/un4_DPS_FS_4_c3 )); CPLD_Con_1_SLICE_1108 \CPLD_Con_1/SLICE_1108 ( .D1(i_rst_n_c), .C1(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), .B1(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), .A1(\CPLD_Con_1/PMU_OC_4_11_409_a2_0_a2_0_0 ), .D0(\CPLD_Con_1/un4_DPS_FS_4_c3 ), .C0(\DC_Con4[4] ), .B0(\DC_Con4[5] ), .A0(N_438), .F0(\CPLD_Con_1.N_706 ), .F1(N_438)); SLICE_1109 SLICE_1109( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_394 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), .A1(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), .D0(\CPLD_Con_1/un4_DPS_FS_4_c3 ), .C0(\DC_Con4[4] ), .B0(\DC_Con4[5] ), .A0(N_460), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[93] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[92] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.N_694 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] ) , .F1(N_460), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] ) ); SLICE_1110 SLICE_1110( .D1(\CPLD_Con_1/N_74 ), .C1(\CPLD_Con_1/N_57 ), .B1(\DC_Con4[8] ), .A1(\CPLD_Con_1/DMM_en_cnst_0_a2_i_1[14] ), .C0(N_460), .B0(\CPLD_Con_1/N_51 ), .A0(\CPLD_Con_1/N_33_1 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[22] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[21] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.N_645 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] ) , .F1(\CPLD_Con_1/N_51 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] ) ); SLICE_1111 SLICE_1111( .C1(i_rst_n_c), .B1(\CPLD_Con_1/N_182 ), .A1(\CPLD_Con_1/RC_VSel38 ), .D0(\CPLD_Con_1/PMU_OC_4_4_313_0 ), .C0(\CPLD_Con_1/PMU_OC_1_4_sqmuxa ), .B0(\CPLD_Con_1/OVER_1_1 ), .A0(\CPLD_Con_1/DMM_en_cnst[2] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[209] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[208] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_1_11[16] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[208] ) , .F1(\CPLD_Con_1/PMU_OC_1_4_sqmuxa ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[209] ) ); SLICE_1112 SLICE_1112( .C1(\CPLD_Con_1/N_162 ), .B1(\CPLD_Con_1/PMU_OC_1_1_sqmuxa_1_0 ), .A1(\CPLD_Con_1/PMU_OC_1_0_sqmuxa ), .D0(\CPLD_Con_1/PMU_OC_4_4_297_0 ), .C0(\CPLD_Con_1/PMU_OC_1_cnst[0] ), .B0(\CPLD_Con_1/PMU_OC_1_4_sqmuxa ), .A0(\CPLD_Con_1/OVER_1_1 ), .M1(\DC_Con1[10] ), .M0(\DC_Con1[9] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[0] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] ) , .F1(\CPLD_Con_1/PMU_OC_1_cnst[0] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] ) ); CPLD_Con_1_SLICE_1113 \CPLD_Con_1/SLICE_1113 ( .B1(\DC_Con4[6] ), .A1(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), .D0(\CPLD_Con_1/N_134 ), .C0(\CPLD_Con_1/N_122 ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc5 ), .A0(\CPLD_Con_1/N_33_1 ), .F0(\CPLD_Con_1.N_548 ), .F1(\CPLD_Con_1/un4_DPS_FS_4_axbxc5 )); SLICE_1114 SLICE_1114( .B1(\DC_Con2[5] ), .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .D0(\CPLD_Con_1/N_363 ), .C0(\CPLD_Con_1/N_335_1 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .A0(\CPLD_Con_1/DMM_en_cnst[6] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[212] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[211] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_2_11[16] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[211] ) , .F1(\CPLD_Con_1/N_335_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[212] ) ); SLICE_1115 SLICE_1115( .C1(\DC_Con3[6] ), .B1(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .A1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .D0(\CPLD_Con_1/N_457 ), .C0(\CPLD_Con_1/N_403 ), .B0(\CPLD_Con_1/N_392 ), .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[53] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[52] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_3_11[20] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] ) , .F1(\CPLD_Con_1/N_457 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] ) ); SLICE_1116 SLICE_1116( .D1(\DC_Con3[4] ), .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), .A1(\DC_Con3[1] ), .D0(\CPLD_Con_1/N_454 ), .C0(\CPLD_Con_1/N_403 ), .B0(\CPLD_Con_1/N_392 ), .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[55] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[54] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_3_11[4] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] ) , .F1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] ) ); SLICE_1117 SLICE_1117( .D1(\CPLD_Con_1/N_416 ), .C1(\CPLD_Con_1/N_218 ), .B1(\CPLD_Con_1/PMU_OC_312lto8_0_a2_0 ), .A1(\CPLD_Con_1/PMU_OC_312_1 ), .D0(\CPLD_Con_1/N_426 ), .C0(\CPLD_Con_1/N_404 ), .B0(\CPLD_Con_1/N_351 ), .A0(\CPLD_Con_1/N_350_1 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[84] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[83] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.N_518 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] ) , .F1(\CPLD_Con_1/N_351 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] ) ); SLICE_1118 SLICE_1118( .D1(i_rst_n_c), .C1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_3_tz_RNI9M8I3 ), .B1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_RNI1TUB1 ), .A1(\CPLD_Con_1/RC_VSel38 ), .D0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_a2_3_0 ), .C0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1 ), .B0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_0 ), .A0(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[37] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[36] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPS_FSMMCe_1_0[5] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] ) , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] ) ); SLICE_1119 SLICE_1119( .C1(\DC_Con1[6] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_c5 ), .A1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .B0(\CPLD_Con_1/OVER_1_1 ), .A0(\CPLD_Con_1/N_34_3 ), .M1(\DC_Con2[4] ), .M0(\DC_Con2[3] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[17] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] ) , .F1(\CPLD_Con_1/OVER_1_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] ) ); SLICE_1120 SLICE_1120( .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), .A1(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .B0(\CPLD_Con_1/OVER_1_1 ), .A0(\CPLD_Con_1/N_35_3 ), .M1(\DC_Con1[21] ), .M0(\DC_Con2[2] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[18] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] ) , .F1(\CPLD_Con_1/N_35_3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] ) ); SLICE_1121 SLICE_1121( .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), .A1(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .C0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .B0(\CPLD_Con_1/OVER_1_1 ), .A0(\CPLD_Con_1/N_36_3 ), .M1(\DC_Con2[1] ), .M0(\DC_Con2[0] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[19] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] ) , .F1(\CPLD_Con_1/N_36_3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] ) ); SLICE_1122 SLICE_1122( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_259 ), .B1(\CPLD_Con_1/freq_t_fast[1] ), .A1(\CPLD_Con_1/freq_t_fast[0] ), .D0(\CPLD_Con_1/N_462 ), .C0(\CPLD_Con_1/N_371 ), .B0(\CPLD_Con_1/N_184 ), .A0(\CPLD_Con_1/PMU_OC_119 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[79] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[78] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] ) , .F1(\CPLD_Con_1/N_371 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] ) ); SLICE_1123 SLICE_1123( .D1(\CPLD_Con_1/N_182 ), .C1(\CPLD_Con_1/un4_DPS_FS_4_axbxc8 ), .B1(\CPLD_Con_1/RC_VSel41 ), .A1(\CPLD_Con_1/DMM_en_1_sqmuxa_3_0 ), .D0(\CPLD_Con_1/N_394 ), .C0(\CPLD_Con_1/N_11 ), .B0(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), .A0(\CPLD_Con_1/N_572_1 ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[9] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.N_596 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] ) , .F1(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 )); CPLD_Con_1_SLICE_1124 \CPLD_Con_1/SLICE_1124 ( .C1(\DC_Con4[7] ), .B1(\DC_Con4[6] ), .A1(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), .D0(\CPLD_Con_1/un4_DPS_FS_4_axbxc6 ), .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc5 ), .B0(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), .A0(\CPLD_Con_1/N_572_1 ), .F0(N_128), .F1(\CPLD_Con_1/un4_DPS_FS_4_axbxc6 )); SLICE_1125 SLICE_1125( .D1(\DC_Con2[8] ), .C1(\DC_Con2[7] ), .B1(\CPLD_Con_1/un4_DPS_FS_2_c6_a0_2 ), .A1(\CPLD_Con_1/DPS_m3_0_a2_1 ), .D0(\CPLD_Con_1/N_363 ), .C0(\CPLD_Con_1/N_335_1 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .A0(\CPLD_Con_1/DMM_en_cnst[4] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[210] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[20] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_2_11[0] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] ) , .F1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[210] ) ); SLICE_1126 SLICE_1126( .B1(\DC_Con2[5] ), .A1(\CPLD_Con_1/un4_DPS_FS_2_c4 ), .D0(\CPLD_Con_1/N_363 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con3[2] ), .M0(\DC_Con3[1] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[3] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] ) , .F1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] ) ); SLICE_1127 SLICE_1127( .D1(\DC_Con2[4] ), .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\CPLD_Con_1/N_363 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con3[6] ), .M0(\DC_Con3[5] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[2] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] ) , .F1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] ) ); SLICE_1128 SLICE_1128( .D1(\CPLD_Con_1/N_345 ), .C1(\DC_Con2[6] ), .B1(\DC_Con2[5] ), .A1(\CPLD_Con_1/un4_DPS_FS_2_c4 ), .D0(\CPLD_Con_1/N_363 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\RC_RLSel[1] ), .M0(\DC_Con2[22] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[1] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] ) , .F1(\CPLD_Con_1/N_363 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] ) ); SLICE_1129 SLICE_1129( .D1(\CPLD_Con_1/N_345 ), .C1(\DC_Con2[6] ), .B1(\DC_Con2[5] ), .A1(\CPLD_Con_1/un4_DPS_FS_2_c4 ), .D0(\CPLD_Con_1/N_419 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con2[19] ), .M0(\DC_Con2[18] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[23] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] ) , .F1(\CPLD_Con_1/N_419 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] ) ); SLICE_1130 SLICE_1130( .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), .A1(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .D0(\DC_Con1[6] ), .C0(\CPLD_Con_1/un3_DPS_FS_1_c5 ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .A0(\CPLD_Con_1/N_36_3 ), .M1(\DC_Con2[6] ), .M0(\DC_Con2[5] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.N_100_3 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] ) , .F1(\CPLD_Con_1/un3_DPS_FS_1_c5 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] ) ); SLICE_1131 SLICE_1131( .D1(\DC_Con1[6] ), .C1(\CPLD_Con_1/un3_DPS_FS_1_c5 ), .B1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .A1(\CPLD_Con_1/N_36_3 ), .B0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .A0(\CPLD_Con_1.N_104_3 ), .M1(\DC_Con1[23] ), .M0(\DC_Con1[22] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_11[23] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] ) , .F1(\CPLD_Con_1.N_104_3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] ) ); CPLD_Con_1_SLICE_1132 \CPLD_Con_1/SLICE_1132 ( .D1(i_rst_n_c), .C1(\CPLD_Con_1/io_RC9 ), .B1(\CPLD_Con_1/dc_t[1] ), .A1(\CPLD_Con_1/dc_t[0] ), .D0(\CPLD_Con_1/N_391 ), .C0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .B0(\CPLD_Con_1/PMU_OC_3_11_0_a2_1_1[6] ), .A0(\CPLD_Con_1/N_35_7 ), .F0(\CPLD_Con_1.PMU_OC_3_11[6] ), .F1(\CPLD_Con_1/N_391 )); SLICE_1133 SLICE_1133( .D1(\CPLD_Con_1/dc_slot_flag_fast[3] ), .C1(\CPLD_Con_1/dc_slot_flag_fast[2] ), .B1(\CPLD_Con_1/dc_slot_flag_fast[1] ), .A1(\CPLD_Con_1/dc_slot_flag_fast[0] ), .D0(\CPLD_Con_1/N_437 ), .C0(\CPLD_Con_1/N_403 ), .B0(\CPLD_Con_1/RC_VSel40 ), .A0(\CPLD_Con_1/N_35_7 ), .M1(\DC_Con4[0] ), .M0(\DC_Con3[23] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_3_11[18] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] ) , .F1(\CPLD_Con_1/RC_VSel40 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] ) ); CPLD_Con_1_SLICE_1134 \CPLD_Con_1/SLICE_1134 ( .D1(\DC_Con3[6] ), .C1(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .B1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV ), .A1(\CPLD_Con_1/RC_VSel40 ), .D0(\CPLD_Con_1/N_391 ), .C0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .B0(\CPLD_Con_1/PMU_OC_3_11_0_a2_1_1[6] ), .A0(\CPLD_Con_1/N_35_7 ), .F0(\CPLD_Con_1.PMU_OC_3_11[22] ), .F1(\CPLD_Con_1/PMU_OC_3_11_0_a2_1_1[6] )); SLICE_1135 SLICE_1135( .D1(\CPLD_Con_1/N_391 ), .C1(\DC_Con3[7] ), .B1(\CPLD_Con_1/un16lto5_4_i_a2_0 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1 ), .D0(\CPLD_Con_1/N_426 ), .C0(\CPLD_Con_1/N_403 ), .B0(\CPLD_Con_1/RC_VSel40 ), .A0(\CPLD_Con_1/N_35_7 ), .M1(\DC_Con4[2] ), .M0(\DC_Con4[1] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_3_11[2] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] ) , .F1(\CPLD_Con_1/N_403 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] ) ); SLICE_1136 SLICE_1136( .D1(\DC_Con4[20] ), .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .D0(\CPLD_Con_1/N_84 ), .C0(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[5] ), .B0(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), .A0(\CPLD_Con_1/un45_RC_RLSel_m[5] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[5] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) , .F1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 )); SLICE_1137 SLICE_1137( .D1(i_rst_n_c), .C1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0_1 ), .B1(\CPLD_Con_1/io_RC9 ), .A1(\CPLD_Con_1/PMU_OC_3_11_6_a2_2_1 ), .D0(\CPLD_Con_1/N_410 ), .C0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d ), .B0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0 ), .A0(\CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_0_1 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[8] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[89] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] ) , .F1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] ) ); SLICE_1138 SLICE_1138( .D1(\CPLD_Con_1/N_383 ), .C1(\CPLD_Con_1/err_flag_en_0_o2_2 ), .B1(\CPLD_Con_1/err_flag_en_0_a2_6_mb_sn ), .A1(\CPLD_Con_1/err_flag_en_0_a2_6_mb_rn_0 ), .D0(\CPLD_Con_1/N_386 ), .C0(\CPLD_Con_1/N_384 ), .B0(\CPLD_Con_1/err_flag_en_0_a2_5_1 ), .A0(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 ), .M1(\DMM_EN[9] ), .M0(\DMM_EN[8] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_o2_2 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] ) , .F1(\CPLD_Con_1/err_flag_en_0_a2_6_mb_mb ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] ) ); SLICE_1139 SLICE_1139( .B1(\CPLD_Con_1/un15_RC_RLSel_axbxc3 ), .A1(\CPLD_Con_1/RC_RLSel_1_sqmuxa_3 ), .D0(\DC_Con1[17] ), .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_25 ), .M1(\xo2chub/er1_shift_reg[7] ), .M0(\xo2chub/er1_shift_reg[6] ), .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m[15] ), .Q0(\xo2chub/ip_enable[2] ), .F1(\CPLD_Con_1/N_25 ), .Q1(\xo2chub/ip_enable[3] )); SLICE_1140 SLICE_1140( .D1(\CPLD_Con_1/N_64 ), .C1(\CPLD_Con_1/N_48 ), .B1(\CPLD_Con_1/un20_RC_RLSel_m[6] ), .A1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .D0(\DC_Con1[17] ), .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_23 ), .M1(\xo2chub/er1_shift_reg[6] ), .M0(\xo2chub/er1_shift_reg[5] ), .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m[6] ), .Q0(\xo2chub/er1_shift_reg[4] ), .F1(\CPLD_Con_1/RC_RLSel_13_iv_i_1[6] ), .Q1(\xo2chub/er1_shift_reg[5] )); SLICE_1141 SLICE_1141( .D1(\DC_Con4[8] ), .C1(\DC_Con4[7] ), .B1(\DC_Con4[6] ), .A1(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_394 ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), .A0(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[95] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[94] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(N_456), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] ) , .F1(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] ) ); SLICE_1142 SLICE_1142( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_381 ), .B1(\CPLD_Con_1/freq_slot_flag[1] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), .D0(\DC_Con2[9] ), .C0(\CPLD_Con_1/un1_i_DC_Con2_1lt8 ), .B0(\CPLD_Con_1/un1_i_DC_Con2_1_0 ), .A0(\CPLD_Con_1/PMU_OC_2_cnst_1[16] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[205] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[204] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DMM_en_cnst[6] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[204] ) , .F1(\CPLD_Con_1/PMU_OC_2_cnst_1[16] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[205] ) ); SLICE_1143 SLICE_1143( .D1(\CPLD_Con_1/N_391 ), .C1(\DC_Con2[5] ), .B1(\CPLD_Con_1/un4_DPS_FS_2_c4 ), .A1(\CPLD_Con_1/RC_VSel39 ), .D0(\CPLD_Con_1/N_453 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .A0(\CPLD_Con_1/PMU_OC_2_11_2[4] ), .M1(\DC_Con3[11] ), .M0(\DC_Con3[10] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[4] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] ) , .F1(\CPLD_Con_1/PMU_OC_2_11_2[4] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] ) ); SLICE_1144 SLICE_1144( .D1(\DC_Con2[6] ), .C1(\DC_Con2[5] ), .B1(\CPLD_Con_1/un4_DPS_FS_2_c4 ), .A1(\CPLD_Con_1/un4_DPS_FS_2_c6_a0_2_RNIUHVQ ), .D0(\CPLD_Con_1/N_453 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .A0(\CPLD_Con_1/PMU_OC_2_11_2[4] ), .M1(\DC_Con3[9] ), .M0(\RC_RLSel[2] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[20] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] ) , .F1(\CPLD_Con_1/N_453 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] ) ); SLICE_1145 SLICE_1145( .D1(\CPLD_Con_1/dc_slot_flag[3] ), .C1(\CPLD_Con_1/dc_slot_flag[2] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/N_84 ), .C0(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[7] ), .B0(\CPLD_Con_1/un70_RC_RLSel_m[7] ), .A0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[7] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] ) , .F1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] ) ); SLICE_1146 SLICE_1146( .D1(\CPLD_Con_1/N_36 ), .C1(\DC_Con4[21] ), .B1(\CPLD_Con_1/un90_RC_RLSel_c4 ), .A1(\CPLD_Con_1/un90_RC_RLSel_axbxc3 ), .D0(\CPLD_Con_1/N_88 ), .C0(\CPLD_Con_1/N_86 ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[13] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[13] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[2] ) , .F1(\CPLD_Con_1/N_86 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[3] ) ); SLICE_1147 SLICE_1147( .D1(\CPLD_Con_1/N_73 ), .C1(\CPLD_Con_1/N_72 ), .B1(\DC_Con3[17] ), .A1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .D0(\CPLD_Con_1/N_87 ), .C0(\CPLD_Con_1/N_86 ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[8] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[8] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) , .F1(\CPLD_Con_1/RC_RLSel_13_iv_0[8] )); SLICE_1148 SLICE_1148( .C1(\CPLD_Con_1/N_72 ), .B1(\CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[14] ), .A1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .D0(\CPLD_Con_1/N_92 ), .C0(\CPLD_Con_1/N_86 ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[14] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[5] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[4] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[14] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[4] ) , .F1(\CPLD_Con_1/RC_RLSel_13_iv_0[14] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[5] ) ); SLICE_1149 SLICE_1149( .D1(\CPLD_Con_1/N_78 ), .C1(\CPLD_Con_1/N_72 ), .B1(\DC_Con3[17] ), .A1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .D0(\CPLD_Con_1/N_89 ), .C0(\CPLD_Con_1/N_86 ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[11] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[14] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[11] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[13] ) , .F1(\CPLD_Con_1/RC_RLSel_13_iv_0[11] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[14] ) ); SLICE_1150 SLICE_1150( .B1(\DC_Con4[9] ), .A1(\DC_Con4[8] ), .D0(\CPLD_Con_1/N_274 ), .C0(\CPLD_Con_1/N_273 ), .B0(\CPLD_Con_1/DMM_en_26_i_a4_1_0[15] ), .A0(\CPLD_Con_1/DMM_en_26_i_a4_0_2[15] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[199] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[198] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DMM_en_26_i_1[15] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[198] ) , .F1(\CPLD_Con_1/DMM_en_26_i_a4_1_0[15] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[199] ) ); SLICE_1151 SLICE_1151( .D1(\DC_Con3[21] ), .C1(\DC_Con3[20] ), .B1(\DC_Con3[19] ), .A1(\CPLD_Con_1/err_flag75lt3 ), .D0(\CPLD_Con_1/N_195 ), .C0(\CPLD_Con_1/un1_exec_flag_1_0_o2_0 ), .B0(\CPLD_Con_1/err_flag75 ), .A0(\CPLD_Con_1/RC_VSel40 ), .M1(\DPS_FS_4[10] ), .M0(\DPS_FS_4[9] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_1_i ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[196] ) , .F1(\CPLD_Con_1/err_flag75 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[197] ) ); CPLD_Con_1_SLICE_1152 \CPLD_Con_1/SLICE_1152 ( .D1(\CPLD_Con_1/un4_DPS_FS_4_axbxc6 ), .C1(\CPLD_Con_1/un4_DPS_FS_4_axbxc5 ), .B1(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), .A1(\CPLD_Con_1/N_572_1 ), .B0(i_rst_n_c), .A0(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), .F0(\CPLD_Con_1/N_572_1 ), .F1(N_128_rep1)); SLICE_1153 SLICE_1153( .D1(\CPLD_Con_1/freq_t[1] ), .C1(\CPLD_Con_1/freq_t[0] ), .B1(\CPLD_Con_1/dc_t[1] ), .A1(\CPLD_Con_1/dc_t[0] ), .D0(\CPLD_Con_1/N_276 ), .C0(\CPLD_Con_1/N_182 ), .B0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .A0(\CPLD_Con_1/exec_flag ), .M1(\DC_Con1[18] ), .M0(\RC_RLSel[14] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_26 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] ) , .F1(\CPLD_Con_1/N_182 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] ) ); SLICE_1154 SLICE_1154( .C1(\CPLD_Con_1/N_403 ), .B1(\CPLD_Con_1/N_392 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_axbxc3 ), .D0(\DC_Con3[5] ), .C0(\DC_Con3[4] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c3 ), .A0(\CPLD_Con_1/RC_VSel40 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[51] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[50] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_392 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] ) , .F1(\CPLD_Con_1/g2_0_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] ) ); SLICE_1155 SLICE_1155( .D1(\DC_Con2[21] ), .C1(\DC_Con2[20] ), .B1(\CPLD_Con_1/un40_RC_RLSel_c3_d ), .A1(\CPLD_Con_1/RC_N_5_mux ), .D0(\CPLD_Con_1/N_41 ), .C0(\DC_Con2[17] ), .B0(\CPLD_Con_1/un45_RC_RLSel_m_1[16] ), .A0(\CPLD_Con_1/un40_RC_RLSel_axbxc3 ), .M1(\xo2chub/er1_shift_reg[11] ), .M0(\xo2chub/er1_shift_reg[10] ), .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un45_RC_RLSel_m[17] ), .Q0(\xo2chub/ip_enable[6] ), .F1(\CPLD_Con_1/un45_RC_RLSel_m_1[16] ), .Q1(\xo2chub/ip_enable[7] )); SLICE_1156 SLICE_1156( .C1(i_rst_n_c), .B1(\CPLD_Con_1/N_182 ), .A1(\CPLD_Con_1/exec_flag_rep1 ), .D0(\CPLD_Con_1/N_273 ), .C0(\CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_c_d ), .B0(\CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_0_0 ), .A0(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), .M1(\DPS_FS_3[9] ), .M0(\RC_RLSel[12] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_249 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] ) , .F1(\CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_0_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[180] ) ); SLICE_1157 SLICE_1157( .C1(\DC_Con1[3] ), .B1(\DC_Con1[2] ), .A1(\DC_Con1[1] ), .D0(\DC_Con1[5] ), .C0(\DC_Con1[4] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .M1(\DC_Con1[8] ), .M0(\DC_Con1[7] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_4_4_297_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] ) , .F1(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] ) ); SLICE_1158 SLICE_1158( .D1(\CPLD_Con_1/N_87 ), .C1(\CPLD_Con_1/un95_RC_RLSel_m_1[16] ), .B1(\DC_Con4[20] ), .A1(\DC_Con4[17] ), .D0(\CPLD_Con_1/un95_RC_RLSel_m[16] ), .C0(\CPLD_Con_1/un20_RC_RLSel_m_0_a2_1[16] ), .B0(\CPLD_Con_1/un15_RC_RLSel_axbxc4 ), .A0(\CPLD_Con_1/RC_RLSel_1_sqmuxa_3 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[16] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[8] ) , .F1(\CPLD_Con_1/un95_RC_RLSel_m[16] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[9] ) ); SLICE_1159 SLICE_1159( .D1(\CPLD_Con_1/un20_RC_RLSel_m_0_a2_1[17] ), .C1(\CPLD_Con_1/RC_RLSel_1_sqmuxa_3 ), .B1(\DC_Con1[21] ), .A1(\CPLD_Con_1/un15_RC_RLSel_c4_i ), .C0(\CPLD_Con_1/un95_RC_RLSel_m_1[16] ), .B0(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_1[1] ), .A0(\CPLD_Con_1/un20_RC_RLSel_m[17] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[17] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) , .F1(\CPLD_Con_1/un20_RC_RLSel_m[17] )); SLICE_1160 SLICE_1160( .D1(\DC_Con3[20] ), .C1(\CPLD_Con_1/un70_RC_RLSel_m_1[0] ), .B1(\CPLD_Con_1/un65_RC_RLSel_c3 ), .A1(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), .D0(\CPLD_Con_1/N_75 ), .C0(\CPLD_Con_1/N_72 ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1 ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_0[13] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ) , .F1(\CPLD_Con_1/N_72 )); SLICE_1161 SLICE_1161( .C1(\CPLD_Con_1/N_381 ), .B1(\CPLD_Con_1/freq_slot_flag[1] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), .C0(i_rst_n_c), .B0(\CPLD_Con_1/N_255 ), .A0(\CPLD_Con_1/PMU_OC_1_0_sqmuxa ), .M1(\BUS_Con_1/recv_reg[28] ), .M0(\BUS_Con_1/recv_reg[27] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_332 ), .Q0(\BUS_Con_1/recv_reg[28] ), .F1(\CPLD_Con_1/PMU_OC_1_0_sqmuxa ), .Q1(\BUS_Con_1/recv_reg[29] )); SLICE_1162 SLICE_1162( .D1(\DC_Con2[23] ), .C1(\DC_Con2[9] ), .B1(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_1 ), .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_o2_2_N_2L1 ), .D0(\CPLD_Con_1/N_233 ), .C0(\CPLD_Con_1/N_207 ), .B0(\CPLD_Con_1/err_flag53 ), .A0(\CPLD_Con_1/RC_VSel39 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[77] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[76] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_259 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] ) , .F1(\CPLD_Con_1/N_207 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] ) ); CPLD_Con_1_SLICE_1163 \CPLD_Con_1/SLICE_1163 ( .D1(\CPLD_Con_1/dc_slot_flag_fast[3] ), .C1(\CPLD_Con_1/dc_slot_flag_fast[2] ), .B1(\CPLD_Con_1/dc_slot_flag_fast[1] ), .A1(\CPLD_Con_1/dc_slot_flag_fast[0] ), .C0(\CPLD_Con_1/N_225 ), .B0(\CPLD_Con_1/N_182 ), .A0(\CPLD_Con_1/RC_VSel39 ), .M0(\DC_Con4[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_384 ), .Q0(\CPLD_Con_1/dc_slot_flag_fast[3] ), .F1(\CPLD_Con_1/RC_VSel39 )); SLICE_1164 SLICE_1164( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_394 ), .B1(\CPLD_Con_1/un4_DPS_FS_4_axbxc7 ), .A1(\CPLD_Con_1/RC_Tx_1_sqmuxa_1 ), .C0(\DC_Con4[7] ), .B0(\DC_Con4[6] ), .A0(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[91] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[90] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_394 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] ) , .F1(N_456_rep1), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] ) ); SLICE_1165 SLICE_1165( .C1(\CPLD_Con_1/N_182 ), .B1(\CPLD_Con_1/exec_flag_rep1 ), .A1(\CPLD_Con_1/RC_VSel41 ), .D0(\CPLD_Con_1/N_247 ), .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc8 ), .B0(\CPLD_Con_1/un1_m1_0_a2_0 ), .A0(\CPLD_Con_1/DMM_en_1_sqmuxa_3_0 ), .M1(\DC_Con4[13] ), .M0(\DC_Con4[12] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(N_168), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] ) , .F1(\CPLD_Con_1/un1_m1_0_a2_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] ) ); SLICE_1166 SLICE_1166( .D1(\CPLD_Con_1/N_204_tz ), .C1(\DC_Con4[23] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_c8_i ), .A1(\CPLD_Con_1/un1_exec_flag_10_i_a2_0_1 ), .D0(\CPLD_Con_1/N_272 ), .C0(\CPLD_Con_1/N_182 ), .B0(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .A0(\CPLD_Con_1/exec_flag ), .M1(\DPS_FS_4[4] ), .M0(\DPS_FS_4[3] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_10_i_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[190] ) , .F1(\CPLD_Con_1/N_272 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[191] ) ); SLICE_1167 SLICE_1167( .D1(\DC_Con2[6] ), .C1(\DC_Con2[5] ), .B1(\CPLD_Con_1/err_flag45_i_a3_0_N_2L1 ), .A1(\CPLD_Con_1/DPS_N_12_mux ), .D0(\CPLD_Con_1/N_258 ), .C0(\DC_Con2[23] ), .B0(\CPLD_Con_1/un1_exec_flag_4_i_a2_1 ), .A0(\CPLD_Con_1/err_flag45_i_a3_0_0 ), .M1(\DPS_FS_4[14] ), .M0(\DPS_FS_4[13] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_276 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[200] ) , .F1(\CPLD_Con_1/err_flag45_i_a3_0_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[201] ) ); SLICE_1168 SLICE_1168( .C1(\DC_Con2[9] ), .B1(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), .A1(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_1 ), .D0(\CPLD_Con_1/N_258 ), .C0(\DC_Con2[23] ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc8 ), .A0(\CPLD_Con_1/err_flag45_i_a3_0_0 ), .M1(\DMM_EN[7] ), .M0(\DMM_EN[6] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_225 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] ) , .F1(\CPLD_Con_1/un4_DPS_FS_2_axbxc8 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] ) ); SLICE_1169 SLICE_1169( .D1(\CPLD_Con_1/N_382 ), .C1(\CPLD_Con_1/N_246 ), .B1(\DC_Con2[9] ), .A1(\CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0 ), .B0(\CPLD_Con_1/PMU_OC_212 ), .A0(\CPLD_Con_1/PMU_OC_2_cnst_1[16] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[203] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[202] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DMM_en_cnst[4] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[202] ) , .F1(\CPLD_Con_1/PMU_OC_212 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[203] ) ); SLICE_1170 SLICE_1170( .D1(\DC_Con2[4] ), .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\CPLD_Con_1/N_246 ), .C0(\DC_Con2[8] ), .B0(\DC_Con2[7] ), .A0(\CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0 ), .M1(\FSMC[0] ), .M0(\FSMC[3] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con2_1lt8 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[206] ) , .F1(\CPLD_Con_1/N_246 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[207] ) ); SLICE_1171 SLICE_1171( .D1(\CPLD_Con_1/N_248 ), .C1(\CPLD_Con_1/N_59 ), .B1(\CPLD_Con_1/N_57 ), .A1(\CPLD_Con_1/RC_Tx_0_0_iv_3_88_i_i_a3_1 ), .D0(i_rst_n_c), .C0(\freq4_relay[13] ), .B0(\CPLD_Con_1/N_270 ), .A0(\CPLD_Con_1/exec_flag ), .M0(\DMM_EN[15] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(N_244), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] ) , .F1(\CPLD_Con_1/N_270 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] ) ); SLICE_1172 SLICE_1172( .D1(\CPLD_Con_1/N_248 ), .C1(\CPLD_Con_1/N_59 ), .B1(\CPLD_Con_1/N_57 ), .A1(\CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_a3_1 ), .D0(i_rst_n_c), .C0(\freq4_relay[17] ), .B0(\CPLD_Con_1/N_267 ), .A0(\CPLD_Con_1/exec_flag ), .M1(\DPS_FS_1[1] ), .M0(\RC_RLSel[8] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(N_243), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] ) , .F1(\CPLD_Con_1/N_267 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[140] ) ); SLICE_1173 SLICE_1173( .D1(\CPLD_Con_1/N_126 ), .C1(\CPLD_Con_1/N_57 ), .B1(\DC_Con4[4] ), .A1(\CPLD_Con_1/RC_Tx_0_0_iv_4_74_i_i_a4_0 ), .D0(i_rst_n_c), .C0(\freq4_relay[16] ), .B0(\CPLD_Con_1/N_95 ), .A0(\CPLD_Con_1/exec_flag ), .M1(\DPS_FS_1[0] ), .M0(DPSFS_RC1), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(N_38), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] ) , .F1(\CPLD_Con_1/N_95 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[139] ) ); SLICE_1174 SLICE_1174( .D1(\DC_Con2[4] ), .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\DC_Con2[5] ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .B0(\CPLD_Con_1/DPS_N_12_mux ), .A0(\CPLD_Con_1/DPS_FS_2_9_i_a2_4_2[5] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[46] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[45] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_407 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] ) , .F1(\CPLD_Con_1/DPS_N_12_mux ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] ) ); SLICE_1175 SLICE_1175( .D1(\CPLD_Con_1/N_133 ), .C1(\CPLD_Con_1/N_132 ), .B1(\CPLD_Con_1/N_57 ), .A1(\DC_Con4[4] ), .D0(i_rst_n_c), .C0(\freq4_relay[14] ), .B0(\CPLD_Con_1/N_100 ), .A0(\CPLD_Con_1/exec_flag ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(N_42), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] ) , .F1(\CPLD_Con_1/N_100 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] ) ); SLICE_1176 SLICE_1176( .D1(\CPLD_Con_1/N_57 ), .C1(\DC_Con4[8] ), .B1(\DC_Con4[4] ), .A1(\CPLD_Con_1/RC_Tx_0_0_iv_4_i_i_a4_0_0 ), .D0(i_rst_n_c), .C0(\freq4_relay[12] ), .B0(\CPLD_Con_1/N_102 ), .A0(\CPLD_Con_1/exec_flag ), .M1(\DMM_EN[14] ), .M0(\DMM_EN[13] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(N_44), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] ) , .F1(\CPLD_Con_1/N_102 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] ) ); SLICE_1177 SLICE_1177( .D1(con_exec), .C1(\CPLD_Con_1/en_t[3] ), .B1(\CPLD_Con_1/en_t[2] ), .A1(\CPLD_Con_1/en_t[1] ), .B0(\CPLD_Con_1/N_380 ), .A0(\CPLD_Con_1/exec_flag ), .M1(\RC_RLSel[13] ), .M0(\DPS_FS_4[2] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_172 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[189] ) , .F1(\CPLD_Con_1/N_380 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] ) ); SLICE_1178 SLICE_1178( .D1(\CPLD_Con_1/N_418 ), .C1(\CPLD_Con_1/en_t[3] ), .B1(\CPLD_Con_1/en_t[2] ), .A1(\CPLD_Con_1/en_t[1] ), .B0(i_rst_n_c), .A0(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .M1(\RC_RLSel[5] ), .M0(\DC_Con4[14] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_247 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] ) , .F1(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] ) ); SLICE_1179 SLICE_1179( .D1(\DC_Con4[20] ), .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .C0(\CPLD_Con_1/N_36 ), .B0(\DC_Con4[21] ), .A0(\CPLD_Con_1/un90_RC_RLSel_c4 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un95_RC_RLSel_m_1[16] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 ) , .F1(\CPLD_Con_1/un90_RC_RLSel_c4 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 ) ); SLICE_1180 SLICE_1180( .D1(\DC_Con4[20] ), .C1(\DC_Con4[19] ), .B1(\CPLD_Con_1/un90_RC_RLSel_c5_a0_2 ), .A1(\CPLD_Con_1/RC_VSel41 ), .C0(\CPLD_Con_1/N_36 ), .B0(\DC_Con4[21] ), .A0(\CPLD_Con_1/un90_RC_RLSel_c4 ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 ) , .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_84 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 ) , .F1(\CPLD_Con_1/N_36 )); SLICE_1181 SLICE_1181( .C1(\CPLD_Con_1/N_688_tz ), .B1(\CPLD_Con_1/N_126 ), .A1(\DC_Con4[7] ), .D0(i_rst_n_c), .C0(\freq4_relay[15] ), .B0(\CPLD_Con_1/un1_i_DC_Con4_11_6_0_o2_i_a3_RNITGF53 ), .A0(\CPLD_Con_1/exec_flag ), .M1(\RC_RLSel[7] ), .M0(\DMM_EN[10] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(N_40), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] ) , .F1(\CPLD_Con_1/un1_i_DC_Con4_11_6_0_o2_i_a3_RNITGF53 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] ) ); CPLD_Con_1_SLICE_1182 \CPLD_Con_1/SLICE_1182 ( .C1(\DC_Con4[9] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_c8_a0_1 ), .A1(\CPLD_Con_1/DPS_N_12_mux_1 ), .C0(\CPLD_Con_1/un4_DPS_FS_4_axbxc8 ), .B0(\CPLD_Con_1/un1_m1_0_a2_0 ), .A0(\CPLD_Con_1/DMM_en_1_sqmuxa_3_0 ), .F0(\CPLD_Con_1/N_274 ), .F1(\CPLD_Con_1/un4_DPS_FS_4_axbxc8 )); SLICE_1183 SLICE_1183( .B1(\CPLD_Con_1/N_182 ), .A1(\CPLD_Con_1/RC_VSel40 ), .D0(\DC_Con3[23] ), .C0(\CPLD_Con_1/un4_DPS_FS_3_axbxc8 ), .B0(\CPLD_Con_1/err_flag_en_0_a2_5_0 ), .A0(\CPLD_Con_1/err_flag75 ), .M1(\DMM_EN[3] ), .M0(\DMM_EN[2] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_a2_5_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] ) , .F1(\CPLD_Con_1/err_flag_en_0_a2_5_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] ) ); SLICE_1184 SLICE_1184( .D1(\DC_Con3[9] ), .C1(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), .B1(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_3 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_2 ), .D0(\DC_Con3[3] ), .C0(\DC_Con3[2] ), .B0(\DC_Con3[1] ), .A0(\CPLD_Con_1/un4_DPS_FS_3_axbxc8 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[57] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[56] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPS_FS_3_9_i_a2_1[0] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] ) , .F1(\CPLD_Con_1/un4_DPS_FS_3_axbxc8 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] ) ); SLICE_1185 SLICE_1185( .D1(\DC_Con4[5] ), .C1(\CPLD_Con_1/RC_VSel41 ), .B1(\CPLD_Con_1/DPS_N_12_mux_1 ), .A1(\CPLD_Con_1/DPS_FS_4_9_i_a2_4_2[8] ), .C0(\CPLD_Con_1/N_400 ), .B0(\DC_Con4[2] ), .A0(\DC_Con4[1] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[60] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[5] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_409 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] ) , .F1(\CPLD_Con_1/N_400 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] ) ); CPLD_Con_1_SLICE_1186 \CPLD_Con_1/SLICE_1186 ( .C1(\CPLD_Con_1/N_169_2 ), .B1(\CPLD_Con_1/un4_DPS_FS_3_axbxc8 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .C0(\DC_Con3[6] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .A0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNI3PNV ), .F0(\CPLD_Con_1/N_169_2 ), .F1(\CPLD_Con_1/N_169 )); SLICE_1187 SLICE_1187( .D1(\DC_Con1[7] ), .C1(\DC_Con1[6] ), .B1(\CPLD_Con_1/RC_VSel38 ), .A1(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_0[12] ), .D0(\DC_Con1[2] ), .C0(\DC_Con1[1] ), .B0(\CPLD_Con_1/DPS_m4_0 ), .A0(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_3[12] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[44] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[43] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_153 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] ) , .F1(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_3[12] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] ) ); SLICE_1188 SLICE_1188( .D1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .C1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .A1(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .D0(\CPLD_Con_1/N_182 ), .C0(\CPLD_Con_1/RC_VSel40 ), .B0(\CPLD_Con_1/RC_VSel39 ), .A0(\CPLD_Con_1/RC_VSel38 ), .M1(\DPS_FS_3[6] ), .M0(\DPS_FS_3[5] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_273 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[176] ) , .F1(\CPLD_Con_1/RC_VSel38 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[177] ) ); SLICE_1189 SLICE_1189( .B1(con_exec), .A1(\CPLD_Con_1/exec_flag_fast ), .D0(\CPLD_Con_1/N_418 ), .C0(\CPLD_Con_1/en_t[3] ), .B0(\CPLD_Con_1/en_t[2] ), .A0(\CPLD_Con_1/en_t[1] ), .M1(\DPS_FS_3[11] ), .M0(\DPS_FS_3[10] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_362 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[181] ) , .F1(\CPLD_Con_1/N_418 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[182] ) ); SLICE_1190 SLICE_1190( .D1(\DC_Con2[21] ), .C1(\DC_Con2[18] ), .B1(\DC_Con2[17] ), .A1(\CPLD_Con_1/err_flag53lto4_1 ), .D0(\CPLD_Con_1/err_flag53 ), .C0(\CPLD_Con_1/err_flag31 ), .B0(\CPLD_Con_1/RC_VSel39 ), .A0(\CPLD_Con_1/RC_VSel38 ), .M1(\BUS_Con_1/recv_reg[15] ), .M0(\BUS_Con_1/recv_reg[14] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_195 ), .Q0(\BUS_Con_1/recv_reg[15] ), .F1(\CPLD_Con_1/err_flag53 ), .Q1(\BUS_Con_1/recv_reg[16] )); CPLD_Con_1_SLICE_1191 \CPLD_Con_1/SLICE_1191 ( .D1(\CPLD_Con_1/N_165 ), .C1(\CPLD_Con_1/un4_DPS_FS_3_c9 ), .B1(\CPLD_Con_1/err_flag75 ), .A1(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2_0_a2_1 ), .D0(\DC_Con3[9] ), .C0(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_3 ), .A0(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_2 ), .F0(\CPLD_Con_1/un4_DPS_FS_3_c9 ), .F1(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 )); SLICE_1192 SLICE_1192( .D1(i_rst_n_c), .C1(\CPLD_Con_1/N_195 ), .B1(\CPLD_Con_1/un1_exec_flag_1_0_o2_0 ), .A1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1_0 ), .D0(\CPLD_Con_1/N_182 ), .C0(\CPLD_Con_1/exec_flag_rep1 ), .B0(\CPLD_Con_1/err_flag97 ), .A0(\CPLD_Con_1/RC_VSel41 ), .M1(\DPS_FS_4[8] ), .M0(\DPS_FS_4[7] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_1_0_o2_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[194] ) , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[195] ) ); SLICE_1193 SLICE_1193( .D1(\CPLD_Con_1/un1_exec_flag_3_i_a2_1 ), .C1(\CPLD_Con_1/un1_exec_flag_3_i_0_1 ), .B1(\CPLD_Con_1/err_flag22_2 ), .A1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1 ), .D0(\CPLD_Con_1/N_182 ), .C0(\CPLD_Con_1/exec_flag_rep1 ), .B0(\CPLD_Con_1/err_flag31 ), .A0(\CPLD_Con_1/RC_VSel38 ), .M1(\DPS_FS_4[12] ), .M0(\DPS_FS_4[11] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_3_i_a2_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[198] ) , .F1(\CPLD_Con_1/N_28 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[199] ) ); SLICE_1194 SLICE_1194( .D1(\CPLD_Con_1/dc_slot_flag[3] ), .C1(\CPLD_Con_1/dc_slot_flag[2] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/N_217 ), .C0(\CPLD_Con_1/N_182 ), .B0(\CPLD_Con_1/exec_flag_rep1 ), .A0(\CPLD_Con_1/err_flag97 ), .M1(\DPS_FS_4[6] ), .M0(\DPS_FS_4[5] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_exec_flag_10_i_a2_0_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[192] ) , .F1(\CPLD_Con_1/N_217 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[193] ) ); SLICE_1195 SLICE_1195( .B1(\DC_Con1[9] ), .A1(\DC_Con1[8] ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_250 ), .B0(\DC_Con1[7] ), .A0(\CPLD_Con_1/PMU_OC_1_0_sqmuxa ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[207] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[206] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DMM_en_cnst_0_a2_0[2] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[206] ) , .F1(\CPLD_Con_1/N_250 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[207] ) ); SLICE_1196 SLICE_1196( .C1(\CPLD_Con_1/N_256 ), .B1(\DC_Con4[8] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/dc_slot_flag[2] ), .M1(\BUS_Con_1/recv_reg[22] ), .M0(\BUS_Con_1/recv_reg[21] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_a2_0[10] ), .Q0(\BUS_Con_1/recv_reg[22] ), .F1(\CPLD_Con_1/un1_i_DC_Con1[1] ), .Q1(\BUS_Con_1/recv_reg[23] )); SLICE_1197 SLICE_1197( .C1(\CPLD_Con_1/N_254 ), .B1(\DC_Con1[8] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/N_256 ), .C0(\DC_Con4[8] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/dc_slot_flag[3] ), .M1(\BUS_Con_1/recv_reg[4] ), .M0(\BUS_Con_1/recv_reg[3] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_a3_2[12] ), .Q0(\BUS_Con_1/recv_reg[4] ), .F1(\CPLD_Con_1/N_256 ), .Q1(\BUS_Con_1/recv_reg[5] )); SLICE_1198 SLICE_1198( .D1(\FSMMC[4] ), .C1(\CPLD_Con_1/N_13_mux_i ), .B1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_a2_3_0 ), .A1(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2 ), .D0(\CPLD_Con_1/dc_slot_flag[2] ), .C0(\CPLD_Con_1/dc_slot_flag[1] ), .B0(\CPLD_Con_1/dc_slot_flag[0] ), .A0(\CPLD_Con_1/m4_0 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[39] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[38] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_13_mux_i ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] ) , .F1(\CPLD_Con_1/DPS_FSMMCe_1[4] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] ) ); SLICE_1199 SLICE_1199( .B1(\DC_Con3[4] ), .A1(\DC_Con3[1] ), .D0(\DC_Con3[6] ), .C0(\DC_Con3[5] ), .B0(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), .A0(\CPLD_Con_1/un16lto5_4_i_a2_0 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[31] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[30] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_165 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] ) , .F1(\CPLD_Con_1/un16lto5_4_i_a2_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] ) ); SLICE_1200 SLICE_1200( .B1(i_rst_n_c), .A1(\DC_Con4[9] ), .D0(\CPLD_Con_1/N_59 ), .C0(\DC_Con4[8] ), .B0(\DC_Con4[7] ), .A0(\CPLD_Con_1/exec_flag ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[28] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[27] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_132 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] ) , .F1(\CPLD_Con_1/N_59 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] ) ); CPLD_Con_1_SLICE_1201 \CPLD_Con_1/SLICE_1201 ( .D1(\CPLD_Con_1/N_258 ), .C1(\DC_Con2[23] ), .B1(\CPLD_Con_1/err_flag45_i_a3_0_0 ), .A1(\CPLD_Con_1/RC_VSel39 ), .D0(\DC_Con2[6] ), .C0(\DC_Con2[5] ), .B0(\DC_Con2[2] ), .A0(\CPLD_Con_1/err_flag45_i_a2_0_1 ), .M1(\DC_Con3[0] ), .M0(\DC_Con2[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_258 ), .Q0(\CPLD_Con_1/dc_slot_flag_fast[1] ), .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1_0 ), .Q1(\CPLD_Con_1/dc_slot_flag_fast[2] )); SLICE_1202 SLICE_1202( .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), .A1(\DC_Con1[3] ), .D0(\DC_Con1[6] ), .C0(\DC_Con1[2] ), .B0(\DC_Con1[1] ), .A0(\CPLD_Con_1/un17lto4_1 ), .M1(\DPS_FS_3[4] ), .M0(\DPS_FS_3[3] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un17lt8 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[174] ) , .F1(\CPLD_Con_1/un17lto4_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[175] ) ); SLICE_1203 SLICE_1203( .B1(\DC_Con4[6] ), .A1(\DC_Con4[5] ), .D0(\CPLD_Con_1/N_261 ), .C0(\CPLD_Con_1/N_57 ), .B0(\DC_Con4[4] ), .A0(\CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_a4_1_1_0 ), .M1(\DC_Con1[1] ), .M0(\DC_Con1[0] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_688_tz ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] ) , .F1(\CPLD_Con_1/N_57 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] ) ); SLICE_1204 SLICE_1204( .C1(\DC_Con2[21] ), .B1(\DC_Con2[20] ), .A1(\DC_Con2[17] ), .D0(\DC_Con2[19] ), .C0(\DC_Con2[18] ), .B0(\CPLD_Con_1/RC_m1_e_2 ), .A0(\CPLD_Con_1/RC_VSel39 ), .M1(\DC_Con4[16] ), .M0(\DC_Con4[15] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_N_5_mux ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] ) , .F1(\CPLD_Con_1/RC_m1_e_2 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] ) ); SLICE_1205 SLICE_1205( .D1(\DC_Con3[20] ), .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .C0(\DC_Con3[21] ), .B0(\CPLD_Con_1/un65_RC_RLSel_c4_i ), .A0(\CPLD_Con_1/RC_VSel40 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un70_RC_RLSel_m_1[0] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) , .F1(\CPLD_Con_1/un65_RC_RLSel_c4_i ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 ) ); SLICE_1206 SLICE_1206( .D1(\CPLD_Con_1/N_204_tz ), .C1(\DC_Con4[23] ), .B1(\DC_Con4[9] ), .A1(\CPLD_Con_1/un4_DPS_FS_4_c8_i ), .D0(\CPLD_Con_1/err_flag89_2 ), .C0(\CPLD_Con_1/DPS_FS_4_9_i_a2_4_0[8] ), .B0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1_0 ), .A0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[35] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[34] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_204_tz ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] ) , .F1(\CPLD_Con_1/err_flag_en_0_a2_1_N_2L1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] ) ); CPLD_Con_1_SLICE_1207 \CPLD_Con_1/SLICE_1207 ( .B1(\CPLD_Con_1/freq_t_fast[1] ), .A1(\CPLD_Con_1/freq_t_fast[0] ), .D0(\CPLD_Con_1/io_RC9 ), .C0(\CPLD_Con_1/exec_flag ), .B0(\CPLD_Con_1/dc_t[1] ), .A0(\CPLD_Con_1/dc_t[0] ), .M1(\DC_Con1[0] ), .M0(\DC_Con4[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_205_i ), .Q0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .F1(\CPLD_Con_1/io_RC9 ), .Q1(\CPLD_Con_1/dc_slot_flag_fast[0] )); SLICE_1208 SLICE_1208( .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), .D0(\CPLD_Con_1/N_133 ), .C0(\CPLD_Con_1/N_59 ), .B0(\DC_Con4[7] ), .A0(\CPLD_Con_1/exec_flag ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[26] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[25] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/RC_Tx_0_0_iv_4_i_i_a4_0_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] ) , .F1(\CPLD_Con_1/N_133 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] ) ); SLICE_1209 SLICE_1209( .B1(\DC_Con4[9] ), .A1(\DC_Con4[7] ), .D0(\CPLD_Con_1/N_261 ), .C0(\CPLD_Con_1/N_57 ), .B0(\DC_Con4[4] ), .A0(\CPLD_Con_1/DMM_en_26_i_a4_0_0[15] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[1] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[19] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DMM_en_26_i_a4_0_2[15] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] ) , .F1(\CPLD_Con_1/DMM_en_26_i_a4_0_0[15] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] ) ); SLICE_1210 SLICE_1210( .D1(\DC_Con4[8] ), .C1(\DC_Con1[8] ), .B1(\CPLD_Con_1/dc_slot_flag[3] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), .C0(\CPLD_Con_1/N_254 ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/DMM_en_26_0_a3_0_1[1] ), .M1(\BUS_Con_1/recv_reg[29] ), .M0(\BUS_Con_1/recv_reg[1] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_a3_0_3[1] ), .Q0(\BUS_Con_1/recv_reg[2] ), .F1(\CPLD_Con_1/DMM_en_26_0_a3_0_1[1] ), .Q1(\BUS_Con_1/recv_reg[30] )); SLICE_1211 SLICE_1211( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), .B1(\DC_Con1[19] ), .A1(\DC_Con1[20] ), .B0(\DC_Con1[21] ), .A0(\CPLD_Con_1/un15_RC_RLSel_c4_i ), .M1(\DPS_FS_3[0] ), .M0(\DPS_FS_2[15] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un15_RC_RLSel_axbxc4 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[170] ) , .F1(\CPLD_Con_1/un15_RC_RLSel_c4_i ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[171] ) ); SLICE_1212 SLICE_1212( .C1(\CPLD_Con_1/dc_slot_flag[3] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), .C0(\CPLD_Con_1/N_189_2 ), .B0(\DC_Con4[22] ), .A0(\CPLD_Con_1/dc_slot_flag[2] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_189 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] ) , .F1(\CPLD_Con_1/N_189_2 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] ) ); SLICE_1213 SLICE_1213( .C1(\DC_Con2[5] ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .A1(\CPLD_Con_1/DPS_FS_2_9_i_a2_4_2[5] ), .D0(\CPLD_Con_1/N_382 ), .C0(\DC_Con2[9] ), .B0(\DC_Con2[6] ), .A0(\CPLD_Con_1/RC_VSel39 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[4] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[49] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPS_FS_2_9_i_a2_4_2[5] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] ) , .F1(\CPLD_Con_1/N_406 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] ) ); SLICE_1214 SLICE_1214( .C1(\DC_Con3[6] ), .B1(\CPLD_Con_1/PMU_OC_313_1 ), .A1(\CPLD_Con_1/PMU_OC_312_1 ), .D0(\CPLD_Con_1/N_218 ), .C0(\DC_Con3[7] ), .B0(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), .A0(\CPLD_Con_1/un16lto5_4_i_a2_0 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[86] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[85] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/PMU_OC_313_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] ) , .F1(\CPLD_Con_1/PMU_OC_313 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] ) ); SLICE_1215 SLICE_1215( .C1(\CPLD_Con_1/N_182 ), .B1(\CPLD_Con_1/err_flag_en_0_a2_1_N_2L1 ), .A1(\CPLD_Con_1/RC_VSel41 ), .D0(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .C0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), .B0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .A0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .M1(\DC_Con4[20] ), .M0(\DC_Con4[19] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_VSel41 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] ) , .F1(\CPLD_Con_1/N_383 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] ) ); CPLD_Con_1_SLICE_1216 \CPLD_Con_1/SLICE_1216 ( .D1(\DC_Con3[9] ), .C1(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), .B1(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_3 ), .A1(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_2 ), .D0(\DC_Con3[8] ), .C0(\DC_Con3[6] ), .B0(\DC_Con3[5] ), .A0(\DC_Con3[4] ), .F0(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_3 ), .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_N_2L1_0 )); SLICE_1217 SLICE_1217( .D1(\DC_Con1[23] ), .C1(\DC_Con1[6] ), .B1(\DC_Con1[1] ), .A1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_1 ), .D0(\DC_Con1[5] ), .C0(\DC_Con1[4] ), .B0(\DC_Con1[3] ), .A0(\DC_Con1[2] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[33] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[32] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] ) , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] ) ); SLICE_1218 SLICE_1218( .D1(\CPLD_Con_1/freq_slot_flag[3] ), .C1(\CPLD_Con_1/freq_slot_flag[2] ), .B1(\CPLD_Con_1/freq_slot_flag[1] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/un1_PMU_OC_120 ), .B0(\CPLD_Con_1/io_RC9 ), .A0(\CPLD_Con_1/PMU_OC_121 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[80] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[7] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_462 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] ) , .F1(\CPLD_Con_1/un1_PMU_OC_120 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] ) ); SLICE_1219 SLICE_1219( .D1(\CPLD_Con_1/N_374 ), .C1(\CPLD_Con_1/g4 ), .B1(\CPLD_Con_1/g1_0 ), .A1(\CPLD_Con_1/g0_0_1 ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_182 ), .B0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .A0(\CPLD_Con_1/RC_VSel38 ), .M1(\DC_Con1[16] ), .M0(\DC_Con1[15] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g4 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] ) , .F1(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] ) ); SLICE_1220 SLICE_1220( .C1(\DC_Con1[9] ), .B1(\CPLD_Con_1/g1_5 ), .A1(\CPLD_Con_1/g1_4 ), .D0(\DC_Con1[8] ), .C0(\DC_Con1[7] ), .B0(\DC_Con1[3] ), .A0(\DC_Con1[2] ), .M1(\DPS_FS_2[11] ), .M0(\DPS_FS_2[10] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1_4 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[165] ) , .F1(\CPLD_Con_1/g0_32 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[166] ) ); SLICE_1221 SLICE_1221( .D1(\DC_Con1[23] ), .C1(\DC_Con1[9] ), .B1(\CPLD_Con_1/g1_5 ), .A1(\CPLD_Con_1/g1_4 ), .D0(\DC_Con1[6] ), .C0(\DC_Con1[5] ), .B0(\DC_Con1[4] ), .A0(\DC_Con1[1] ), .M1(\DPS_FS_2[13] ), .M0(\DPS_FS_2[12] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1_5 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[167] ) , .F1(\CPLD_Con_1/g2_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[168] ) ); SLICE_1222 SLICE_1222( .D1(i_rst_n_c), .C1(\CPLD_Con_1/io_RC9 ), .B1(\CPLD_Con_1/g2_0 ), .A1(\CPLD_Con_1/RC_VSel38 ), .D0(\CPLD_Con_1/N_374 ), .C0(\CPLD_Con_1/N_184 ), .B0(\CPLD_Con_1/g1_0 ), .A0(\CPLD_Con_1/g1 ), .M1(\DPS_FS_1[9] ), .M0(\DPS_FS_1[8] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[147] ) , .F1(\CPLD_Con_1/g1_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[148] ) ); SLICE_1223 SLICE_1223( .B1(\DC_Con1[18] ), .A1(\DC_Con1[17] ), .D0(\DC_Con1[21] ), .C0(\DC_Con1[20] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/err_flag31lt3_0_0_0 ), .M1(\DPS_FS_2[2] ), .M0(\DPS_FS_2[1] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag31 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[156] ) , .F1(\CPLD_Con_1/err_flag31lt3_0_0_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[157] ) ); SLICE_1224 SLICE_1224( .D1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d ), .C1(\CPLD_Con_1/g2_0_0 ), .B1(\CPLD_Con_1/g0_11_1 ), .A1(\CPLD_Con_1/g0_0_2 ), .D0(\CPLD_Con_1/N_410 ), .C0(\CPLD_Con_1/N_184 ), .B0(\CPLD_Con_1/g1_1 ), .A0(\CPLD_Con_1/g1_0_1 ), .M1(\BUS_Con_1/recv_reg[11] ), .M0(\BUS_Con_1/recv_reg[10] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g0_0_2 ), .Q0(\BUS_Con_1/recv_reg[11] ), .F1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 ), .Q1(\BUS_Con_1/recv_reg[12] )); CPLD_Con_1_SLICE_1225 \CPLD_Con_1/SLICE_1225 ( .C1(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .B1(\CPLD_Con_1/dc_slot_flag[3] ), .A1(\CPLD_Con_1/dc_slot_flag[1] ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/io_RC9 ), .B0(\CPLD_Con_1/g2_2 ), .A0(\CPLD_Con_1/dc_slot_flag[2] ), .M1(\DC_Con2[0] ), .M0(\DC_Con1[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1_1 ), .Q0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .F1(\CPLD_Con_1/g2_2 ), .Q1(\CPLD_Con_1/dc_slot_flag_1_rep1 )); SLICE_1226 SLICE_1226( .D1(\DC_Con4[7] ), .C1(\DC_Con4[1] ), .B1(\CPLD_Con_1/g0_45_1 ), .A1(\CPLD_Con_1/g0_6_2_0 ), .D0(\DC_Con4[23] ), .C0(\DC_Con4[9] ), .B0(\CPLD_Con_1/un4_DPS_FS_4_c8_i ), .A0(\CPLD_Con_1/err_flag97 ), .M1(\DPS_FS_2[9] ), .M0(\DPS_FS_2[8] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g1_2 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[163] ) , .F1(\CPLD_Con_1/un4_DPS_FS_4_c8_i ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[164] ) ); CPLD_Con_1_SLICE_1227 \CPLD_Con_1/SLICE_1227 ( .D1(\CPLD_Con_1/io_RC9 ), .C1(\CPLD_Con_1/g2 ), .B1(\CPLD_Con_1/g1_1_0 ), .A1(\CPLD_Con_1/g0_0_0_1_0 ), .D0(\CPLD_Con_1/N_184 ), .C0(\CPLD_Con_1/g4_0_0_0_0 ), .B0(\CPLD_Con_1/g3 ), .A0(\CPLD_Con_1/g0_0_0_0 ), .F0(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA ), .F1(\CPLD_Con_1/g0_0_0_0 )); CPLD_Con_1_SLICE_1228 \CPLD_Con_1/SLICE_1228 ( .D1(\DC_Con4[4] ), .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), .C0(\DC_Con4[5] ), .B0(\CPLD_Con_1/un4_DPS_FS_4_axbxc3 ), .A0(\CPLD_Con_1/g2_1_0 ), .F0(\CPLD_Con_1/g4_0_0_0_0 ), .F1(\CPLD_Con_1/g2_1_0 )); CPLD_Con_1_SLICE_1229 \CPLD_Con_1/SLICE_1229 ( .C1(i_rst_n_c), .B1(\CPLD_Con_1/g2_0_1 ), .A1(\CPLD_Con_1/freq_slot_flag[3] ), .C0(\CPLD_Con_1/freq_slot_flag[2] ), .B0(\CPLD_Con_1/freq_slot_flag[1] ), .A0(\CPLD_Con_1/freq_slot_flag[0] ), .M1(\freq4_relay[0] ), .M0(\freq3_relay[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g2_0_1 ), .Q0(\CPLD_Con_1/freq_slot_flag[2] ), .F1(\CPLD_Con_1/g0_0_0_1_0 ), .Q1(\CPLD_Con_1/freq_slot_flag[3] )); SLICE_1230 SLICE_1230( .D1(\DC_Con3[3] ), .C1(\DC_Con3[1] ), .B1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf0_1 ), .A1(\CPLD_Con_1/PMU_OC_312lto8_1_0_o2_0_sn ), .B0(\DC_Con3[5] ), .A0(\DC_Con3[4] ), .M1(\FSMC[3] ), .M0(\RC_RLSel[15] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf0_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] ) , .F1(\CPLD_Con_1/PMU_OC_312_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[210] ) ); SLICE_1231 SLICE_1231( .D1(\CPLD_Con_1/N_184 ), .C1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d ), .B1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0 ), .A1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3 ), .D0(\CPLD_Con_1/N_410 ), .C0(\CPLD_Con_1/N_366 ), .B0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0 ), .A0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_0 ), .M1(\BUS_Con_1/recv_reg[17] ), .M0(\BUS_Con_1/recv_reg[16] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i ), .Q0(\BUS_Con_1/recv_reg[17] ), .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0 ), .Q1(\BUS_Con_1/recv_reg[18] )); SLICE_1232 SLICE_1232( .D1(i_rst_n_c), .C1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0_1 ), .B1(\CPLD_Con_1/io_RC9 ), .A1(\CPLD_Con_1/PMU_OC_3_11_6_a2_2_1 ), .C0(\CPLD_Con_1/freq_slot_flag[2] ), .B0(\CPLD_Con_1/freq_slot_flag[1] ), .A0(\CPLD_Con_1/freq_slot_flag[0] ), .M1(\DPS_FS_1[5] ), .M0(\DPS_FS_1[4] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_3_11_6_a2_2_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[143] ) , .F1(\CPLD_Con_1/g0_11_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[144] ) ); CPLD_Reg_1_SLICE_1233 \CPLD_Reg_1/SLICE_1233 ( .B1(\reg_addr_fast[3] ), .A1(\reg_addr_fast[2] ), .D0(\reg_addr_fast[0] ), .C0(\reg_addr_fast[1] ), .B0(\CPLD_Reg_1/N_1137 ), .A0(\CPLD_Reg_1/N_7 ), .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][20] ), .F1(\CPLD_Reg_1/N_1137 ), .Q1(\CPLD_Reg_1/regtable[0][21] )); CPLD_Reg_1_SLICE_1234 \CPLD_Reg_1/SLICE_1234 ( .B1(\reg_addr_fast[3] ), .A1(\reg_addr_fast[2] ), .D0(\reg_addr_fast[0] ), .C0(\reg_addr_fast[1] ), .B0(\CPLD_Reg_1/N_1138 ), .A0(\CPLD_Reg_1/N_7 ), .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][4] ), .F1(\CPLD_Reg_1/N_1138 ), .Q1(\CPLD_Reg_1/regtable[0][5] )); CPLD_Reg_1_SLICE_1235 \CPLD_Reg_1/SLICE_1235 ( .B1(\reg_addr_fast[3] ), .A1(\reg_addr_fast[2] ), .D0(\reg_addr_fast[0] ), .C0(\reg_addr_fast[1] ), .B0(\CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 ), .A0(\CPLD_Reg_1/N_7 ), .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][15] ), .F1(\CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 ), .Q1(\CPLD_Reg_1/regtable[0][16] )); CPLD_Reg_1_SLICE_1236 \CPLD_Reg_1/SLICE_1236 ( .D1(con_exec), .C1(\CPLD_Reg_1/un34_regtable_5[1] ), .B1(\CPLD_Reg_1/un9_0_a3_0 ), .A1(\CPLD_Reg_1/state_6_d ), .D0(\reg_addr_fast[0] ), .C0(reg_addr_1_rep1), .B0(\CPLD_Reg_1/N_7 ), .A0(\CPLD_Reg_1/N_1137 ), .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][22] ), .F1(\CPLD_Reg_1/N_7 ), .Q1(\CPLD_Reg_1/regtable[0][23] )); CPLD_Reg_1_SLICE_1237 \CPLD_Reg_1/SLICE_1237 ( .B1(\reg_addr_fast[3] ), .A1(\reg_addr_fast[2] ), .D0(\reg_addr_fast[0] ), .C0(reg_addr_1_rep1), .B0(\CPLD_Reg_1/N_7 ), .A0(\CPLD_Reg_1/un34_regtable_1[1] ), .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][0] ), .F1(\CPLD_Reg_1/un34_regtable_1[1] ), .Q1(\CPLD_Reg_1/regtable[0][10] )); CPLD_Reg_1_SLICE_1238 \CPLD_Reg_1/SLICE_1238 ( .B1(con_exec), .A1(\CPLD_Reg_1/state[1] ), .D0(\CPLD_Reg_1/un34_regtable_5[1] ), .C0(\CPLD_Reg_1/un34_regtable_2[1] ), .B0(\CPLD_Reg_1/state_ns_0_a4_0_3[1] ), .A0(\CPLD_Reg_1/N_22 ), .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/N_26 ), .Q0(\CPLD_Reg_1/regtable[0][8] ), .F1(\CPLD_Reg_1/N_22 ), .Q1(\CPLD_Reg_1/regtable[0][9] )); CPLD_Reg_1_SLICE_1239 \CPLD_Reg_1/SLICE_1239 ( .B1(wr_flag), .A1(\CPLD_Reg_1/reg_err_flag ), .D0(con_exec), .C0(\CPLD_Reg_1/un9_0_a3_0 ), .B0(\CPLD_Reg_1/state[1] ), .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/un9_0 ), .Q0(\CPLD_Reg_1/regtable[10][13] ), .F1(\CPLD_Reg_1/un9_0_a3_0 ), .Q1(\CPLD_Reg_1/regtable[10][14] )); CPLD_Reg_1_SLICE_1240 \CPLD_Reg_1/SLICE_1240 ( .B1(\CPLD_Reg_1/state[1] ), .A1(\CPLD_Reg_1/state[0] ), .D0(wr_flag), .C0(\CPLD_Reg_1/reg_err_flag ), .B0(i_rst_n_c), .A0(\CPLD_Reg_1/state_6_d ), .F0(\CPLD_Reg_1/rdata_reg_1_sqmuxa ), .F1(\CPLD_Reg_1/state_6_d )); CPLD_Reg_1_SLICE_1241 \CPLD_Reg_1/SLICE_1241 ( .D1(con_exec), .C1(\CPLD_Reg_1/un34_regtable_5[1] ), .B1(\CPLD_Reg_1/un34_regtable_2[1] ), .A1(\CPLD_Reg_1/un9_0_a3_0 ), .C0(\reg_addr[6] ), .B0(\reg_addr[5] ), .A0(\reg_addr[4] ), .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/un34_regtable_5[1] ), .Q0(\CPLD_Reg_1/regtable[0][11] ), .F1(\CPLD_Reg_1/un10_i_0_1 ), .Q1(\CPLD_Reg_1/regtable[0][12] )); BUS_Con_1_SLICE_1242 \BUS_Con_1/SLICE_1242 ( .B1(i_rst_n_c), .A1(\BUS_Con_1/cs_sync[1] ), .D0(\r_data[23] ), .C0(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .B0(\BUS_Con_1/miso_shift17lto5_i_o2 ), .A0(\BUS_Con_1/miso_shift[30] ), .M1(\BUS_Con_1/recv_reg[18] ), .M0(\BUS_Con_1/recv_reg[17] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(N_694_rst), .Q0(\w_data[17] ), .F1(\BUS_Con_1/cs_sync_RNI4H6C_0[1] ), .Q1(\w_data[18] )); BUS_Con_1_SLICE_1243 \BUS_Con_1/SLICE_1243 ( .B1(\BUS_Con_1/sclk_sync[1] ), .A1(\BUS_Con_1.sclk_sync[0] ), .D0(\BUS_Con_1/sclk_rise ), .C0(\BUS_Con_1/bit_cnt[2] ), .B0(\BUS_Con_1/bit_cnt[1] ), .A0(\BUS_Con_1/bit_cnt[0] ), .M1(\BUS_Con_1/recv_reg[23] ), .M0(\BUS_Con_1/recv_reg[22] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/un1_bit_cnt_7_c3 ), .Q0(\w_data[22] ), .F1(\BUS_Con_1/sclk_rise ), .Q1(\w_data[23] )); BUS_Con_1_SLICE_1244 \BUS_Con_1/SLICE_1244 ( .B1(\BUS_Con_1/state[1] ), .A1(\BUS_Con_1/state[0] ), .D0(reg_busy), .C0(o_wready_c), .B0(\BUS_Con_1/N_504 ), .A0(\BUS_Con_1/data_ready ), .M1(\BUS_Con_1/recv_reg[5] ), .M0(\BUS_Con_1/recv_reg[4] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/un1_state_2_0 ), .Q0(\w_data[4] ), .F1(\BUS_Con_1/N_504 ), .Q1(\w_data[5] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1245 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1245 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[120] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[11] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1246 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1246 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[119] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[118] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_1 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1247 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1247 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[117] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[116] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1248 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1248 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][1] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[1] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[113] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[112] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[1] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1249 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1249 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][2] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[2] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[115] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[114] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[2] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1250 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1250 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[171] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[170] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[170] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[171] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1251 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1251 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[175] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[174] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[174] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/N_5 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[175] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1252 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1252 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_98 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[162] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[161] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[161] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_98 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[162] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1253 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1253 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen_jtck ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_105 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[168] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[167] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[167] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_105 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[168] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1254 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1254 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_75 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[137] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[136] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_75 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1255 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1255 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_cnt_init_1 ) , .B1(jtaghub16_jrstn), .A1(jtaghub16_ip_enable0), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_te[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_75 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[135] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[134] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_cnt_init_1 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1256 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1256 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tt_prog_en_0 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[164] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[163] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/N_77 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[163] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnte ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[164] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1257 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1257 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_out[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[133] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[132] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_27 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1258 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1258 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_32 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[124] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[123] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/N_32 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1259 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1259 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_clk ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[128] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[127] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_clk ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1260 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1260 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_m ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_N_2L1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_tu ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_te ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_te[0][0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/N_5 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[122] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[121] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_1 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] ) ); SLICE_1261 SLICE_1261( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_m_1[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_m[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_1 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_m_1[0] ) , .Q0(\CPLD_Reg_1/regtable[10][4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 ) , .Q1(\CPLD_Reg_1/regtable[10][5] )); SLICE_1262 SLICE_1262( .D1(jtaghub16_jce2), .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4362 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4360 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_1[6] ) , .Q0(\CPLD_Reg_1/regtable[11][2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .Q1(\CPLD_Reg_1/regtable[11][3] )); SLICE_1263 SLICE_1263( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[3] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_125 ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[2] ) , .Q0(\CPLD_Reg_1/regtable[12][19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[3] ) , .Q1(\CPLD_Reg_1/regtable[12][1] )); SLICE_1264 SLICE_1264( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_4 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[13] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[12] ) , .Q0(\CPLD_Reg_1/regtable[11][6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .Q1(\CPLD_Reg_1/regtable[11][7] )); SLICE_1265 SLICE_1265( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[11] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[10] ) , .Q0(\CPLD_Reg_1/regtable[11][4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) , .Q1(\CPLD_Reg_1/regtable[11][5] )); SLICE_1266 SLICE_1266( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4371 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[1] ) , .Q0(\CPLD_Reg_1/regtable[12][17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_126 ) , .Q1(\CPLD_Reg_1/regtable[12][18] )); SLICE_1267 SLICE_1267( .D1(jtaghub16_jce2), .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc19_i_0 ) , .B0(jtaghub16_ip_enable0), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_70 ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_i ) , .Q0(\DC_Con2[19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_70 ) , .Q1(\DC_Con2[1] )); SLICE_1268 SLICE_1268( .D1(jtaghub16_jce2), .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4371 ) , .Q0(\CPLD_Reg_1/regtable[12][2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .Q1(\CPLD_Reg_1/regtable[12][3] )); SLICE_1269 SLICE_1269( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_trig[2] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4368 ) , .Q0(\CPLD_Reg_1/regtable[12][20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .Q1(\CPLD_Reg_1/regtable[12][21] )); SLICE_1270 SLICE_1270( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[211] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[210] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_212_3792_i_m2_i_0 ) , .Q0(\CPLD_Reg_1/regtable[14][15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .Q1(\CPLD_Reg_1/regtable[14][16] )); SLICE_1271 SLICE_1271( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un15_jtdo_first_bit ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4_x ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_5 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_4 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jtdo_first_bit ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un15_jtdo_first_bit ) , .Q0(\DC_Con2[20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1_N_5_mux ) , .Q1(\DC_Con2[21] )); SLICE_1272 SLICE_1272( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_65 ) , .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4412_mux ) , .Q0(\CPLD_Reg_1/regtable[12][13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_65 ) , .Q1(\CPLD_Reg_1/regtable[12][14] )); SLICE_1273 SLICE_1273( .B1(jtaghub16_jshift), .A1(jtaghub16_jce2), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , .B0(jtaghub16_ip_enable0), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) , .Q0(\DC_Con1[2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) , .Q1(\DC_Con1[3] )); SLICE_1274 SLICE_1274( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast ) , .C1(jtaghub16_jshift), .B1(jtaghub16_jce2), .A1(jtaghub16_ip_enable0), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_first_bit_1_sqmuxa ) , .Q0(\CPLD_Reg_1/regtable[10][17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .Q1(\CPLD_Reg_1/regtable[10][18] )); SLICE_1275 SLICE_1275( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_3 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_2 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_m_1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_m ) , .Q0(\CPLD_Reg_1/regtable[10][2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_2 ) , .Q1(\CPLD_Reg_1/regtable[10][3] )); SLICE_1276 SLICE_1276( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_2 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jtdo_first_bit ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4328 ) , .Q0(\DC_Con2[6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_N_2L1 ) , .Q1(\DC_Con2[7] )); SLICE_1277 SLICE_1277( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/ren ), .Q0(\CPLD_Reg_1/regtable[11][11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_i ) , .Q1(\CPLD_Reg_1/regtable[11][12] )); SLICE_1278 SLICE_1278( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_3 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_2 ) , .B1(jtaghub16_ip_enable0), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_3 ) , .Q0(\DC_Con2[4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un22_jtdo ) , .Q1(\DC_Con2[5] )); SLICE_1279 SLICE_1279( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_m_2[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_tm_m_1_0[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[0] ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_tm_m_1_0[0] ) , .Q0(\CPLD_Reg_1/regtable[11][0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4_x ) , .Q1(\CPLD_Reg_1/regtable[11][10] )); SLICE_1280 SLICE_1280( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0_1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0] ) , .A0(jtaghub16_ip_enable0), .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0_1 ) , .Q0(\CPLD_Reg_1/regtable[10][22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0 ) , .Q1(\CPLD_Reg_1/regtable[10][23] )); SLICE_1281 SLICE_1281( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0 ) , .Q0(\DC_Con3[17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .Q1(\DC_Con3[18] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1282 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1282 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_871 ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_877 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_2_1_1 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1283 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1283 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_876 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_877 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_282_1_1 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_877 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1284 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1284 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_a2_4_1 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_881 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_2 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_0 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_4 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_2 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1285 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1285 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_1 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_821 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_818 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_3_i_0_0_3 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_821 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] )); SLICE_1286 SLICE_1286( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_871 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_7_1[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_803 ), .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] ) , .Q0(\DC_Con4[8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_7_1[0] ) , .Q1(\DC_Con4[9] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1287 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1287 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .B1(jtaghub16_jshift), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_746_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] ) ); SLICE_1288 SLICE_1288( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_650_i ) , .Q0(\DC_Con3[15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 ) , .Q1(\DC_Con3[16] )); SLICE_1289 SLICE_1289( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 ) , .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa ) , .Q0(\DC_Con3[22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 ) , .Q1(\DC_Con3[23] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1290 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1290 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[102] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[101] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1291 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1291 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_12[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_2[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[15] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_803 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_2[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1292 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1292 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_6_1[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_804 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_6_1[0] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] )); SLICE_1293 SLICE_1293( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_871 ), .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_0_sqmuxa_1 ) , .Q0(\DC_Con3[19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_871 ), .Q1(\DC_Con3[1] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1294 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1294 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trigger ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_i_0_0 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[104] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[103] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_i_0_0 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1295 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1295 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_876 ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_844_1 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_876 )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1296 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1296 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_880 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[108] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[107] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_880 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1297 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1297 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_881 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_786 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_0 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_881 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1298 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1298 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_a2_2_0 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_840 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_a2_2_0 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1299 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1299 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .B0(jtaghub16_jshift), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[100] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[0] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] ) ); SLICE_1300 SLICE_1300( .D1(\xo2chub/jtdo1_1_0 ), .C1(\xo2chub/bit_count[4] ), .B1(\xo2chub/bit_count[3] ), .A1(\xo2chub/bit_count[2] ), .D0(\xo2chub/jtdo1_1_1 ), .C0(jtaghub16_jshift), .B0(\xo2chub/jce1 ), .A0(\xo2chub/er1_shift_reg[1] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[180] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[17] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\xo2chub/jtdo1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] ) , .F1(\xo2chub/jtdo1_1_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[180] ) ); SLICE_1301 SLICE_1301( .D1(\DC_Con3[18] ), .C1(\DC_Con3[19] ), .B1(\DC_Con3[17] ), .A1(\CPLD_Con_1/N_70 ), .D0(\DC_Con3[18] ), .C0(\DC_Con3[19] ), .B0(\DC_Con3[17] ), .A0(\CPLD_Con_1/N_70 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un70_RC_RLSel_m[2] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] ) , .F1(\CPLD_Con_1/un70_RC_RLSel_m[5] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] ) ); SLICE_1302 SLICE_1302( .D1(\CPLD_Con_1/N_363 ), .C1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .D0(\CPLD_Con_1/N_363 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con2[21] ), .M0(\DC_Con2[20] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[19] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] ) , .F1(\CPLD_Con_1.PMU_OC_2_11[17] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] ) ); SLICE_1303 SLICE_1303( .D1(\CPLD_Con_1/N_419 ), .C1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .D0(\CPLD_Con_1/N_419 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con3[8] ), .M0(\DC_Con3[7] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[5] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] ) , .F1(\CPLD_Con_1.PMU_OC_2_11[22] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] ) ); SLICE_1304 SLICE_1304( .D1(\CPLD_Con_1/N_419 ), .C1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .D0(\CPLD_Con_1/N_419 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con3[4] ), .M0(\DC_Con3[3] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[6] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] ) , .F1(\CPLD_Con_1.PMU_OC_2_11[21] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] ) ); SLICE_1305 SLICE_1305( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_25 ), .D0(\DC_Con1[17] ), .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_25 ), .M1(\xo2chub/er1_shift_reg[8] ), .M0(\xo2chub/er1_shift_reg[7] ), .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m[11] ), .Q0(\xo2chub/er1_shift_reg[6] ), .F1(\CPLD_Con_1/un20_RC_RLSel_m[10] ), .Q1(\xo2chub/er1_shift_reg[7] )); SLICE_1306 SLICE_1306( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_25 ), .D0(\DC_Con1[17] ), .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_25 ), .M1(\xo2chub/er1_shift_reg[10] ), .M0(\xo2chub/er1_shift_reg[9] ), .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m[12] ), .Q0(\xo2chub/er1_shift_reg[8] ), .F1(\CPLD_Con_1/un20_RC_RLSel_m[9] ), .Q1(\xo2chub/er1_shift_reg[9] )); SLICE_1307 SLICE_1307( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_25 ), .D0(\DC_Con1[17] ), .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_25 ), .M0(\xo2chub/er1_shift_reg[20] ), .CE(\xo2chub/id_enable_0_sqmuxa ), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m[13] ), .Q0(\xo2chub/id_enable ), .F1(\CPLD_Con_1/un20_RC_RLSel_m[8] )); SLICE_1308 SLICE_1308( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_23 ), .D0(\DC_Con1[17] ), .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_23 ), .M0(jtaghub16_jtdi), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnte ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m[7] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/te_prog_din[0] ) , .F1(\CPLD_Con_1/un20_RC_RLSel_m[3] )); SLICE_1309 SLICE_1309( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_23 ), .D0(\DC_Con1[17] ), .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_23 ), .M0(\xo2chub/er1_shift_reg[12] ), .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m[4] ), .Q0(\xo2chub/ip_enable[8] ), .F1(\CPLD_Con_1/un20_RC_RLSel_m[2] )); SLICE_1310 SLICE_1310( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_23 ), .D0(\DC_Con1[17] ), .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_23 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jshift_d1 ), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m[5] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ) , .F1(\CPLD_Con_1/un20_RC_RLSel_m[1] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ) ); CPLD_Con_1_SLICE_1311 \CPLD_Con_1/SLICE_1311 ( .D1(\DC_Con4[20] ), .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .D0(\DC_Con4[20] ), .C0(\DC_Con4[19] ), .B0(\DC_Con4[18] ), .A0(\DC_Con4[17] ), .F0(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_1[1] ), .F1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[7] )); SLICE_1312 SLICE_1312( .D1(\DC_Con4[20] ), .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .D0(\DC_Con4[20] ), .C0(\DC_Con4[19] ), .B0(\DC_Con4[18] ), .A0(\DC_Con4[17] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_i ) , .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[0] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] ) , .F1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[4] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] ) ); SLICE_1313 SLICE_1313( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), .B1(\DC_Con1[19] ), .A1(\DC_Con1[20] ), .D0(\DC_Con1[17] ), .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\DC_Con1[20] ), .M1(jtaghub16_jtdi), .M0(\xo2chub/er1_shift_reg[2] ), .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m_0_a2_1[17] ), .Q0(\xo2chub/er1_shift_reg[1] ), .F1(\CPLD_Con_1/un11_RC_RLSellt4 ), .Q1(\xo2chub/er1_shift_reg[20] )); SLICE_1314 SLICE_1314( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), .B1(\DC_Con1[19] ), .A1(\DC_Con1[20] ), .D0(\DC_Con1[17] ), .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\DC_Con1[20] ), .M1(\xo2chub/er1_shift_reg[14] ), .M0(\xo2chub/er1_shift_reg[13] ), .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m_0_a2_1[16] ), .Q0(\xo2chub/er1_shift_reg[12] ), .F1(\CPLD_Con_1/un15_RC_RLSel_axbxc3 ), .Q1(\xo2chub/er1_shift_reg[13] )); SLICE_1315 SLICE_1315( .D1(\freq4_relay[0] ), .C1(\freq3_relay[0] ), .B1(\freq2_relay[0] ), .A1(\freq1_relay[0] ), .D0(\freq4_relay[0] ), .C0(\freq3_relay[0] ), .B0(\freq2_relay[0] ), .A0(\freq1_relay[0] ), .M1(\BUS_Con_1/recv_reg[9] ), .M0(\BUS_Con_1/recv_reg[8] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/CO1 ), .Q0(\w_data[8] ), .F1(\CPLD_Con_1.io_RC_2 ), .Q1(\w_data[9] )); SLICE_1316 SLICE_1316( .D1(\CPLD_Con_1/dc_slot_flag[3] ), .C1(\CPLD_Con_1/dc_slot_flag[2] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\CPLD_Con_1/dc_slot_flag[3] ), .C0(\CPLD_Con_1/dc_slot_flag[2] ), .B0(\CPLD_Con_1/dc_slot_flag[1] ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[82] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[81] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_233 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] ) , .F1(\CPLD_Con_1/DPS_FSMC_RNO_0[3] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] ) ); CPLD_Con_1_SLICE_1317 \CPLD_Con_1/SLICE_1317 ( .D1(\CPLD_Con_1/freq_slot_flag[3] ), .C1(\CPLD_Con_1/freq_slot_flag[2] ), .B1(\CPLD_Con_1/freq_slot_flag[1] ), .A1(\CPLD_Con_1/freq_slot_flag[0] ), .D0(\CPLD_Con_1/freq_slot_flag[3] ), .C0(\CPLD_Con_1/freq_slot_flag[2] ), .B0(\CPLD_Con_1/freq_slot_flag[1] ), .A0(\CPLD_Con_1/freq_slot_flag[0] ), .M1(\freq2_relay[0] ), .M0(\freq1_relay[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_m1_e_0 ), .Q0(\CPLD_Con_1/freq_slot_flag[0] ), .F1(\CPLD_Con_1/PMU_OC_119 ), .Q1(\CPLD_Con_1/freq_slot_flag[1] )); SLICE_1318 SLICE_1318( .D1(\DC_Con2[5] ), .C1(\DC_Con2[3] ), .B1(\DC_Con2[2] ), .A1(\DC_Con2[1] ), .D0(\DC_Con2[5] ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), .M1(\RC_RLSel[3] ), .M0(\DC_Con3[18] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_2 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] ) , .F1(\CPLD_Con_1/DMM_en_0_sqmuxa_5_0_o2_2_N_2L1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] ) ); SLICE_1319 SLICE_1319( .D1(\DC_Con4[8] ), .C1(\DC_Con4[7] ), .B1(\DC_Con4[1] ), .A1(\CPLD_Con_1/exec_flag ), .D0(\DC_Con4[8] ), .C0(\DC_Con4[7] ), .B0(\DC_Con4[1] ), .A0(\CPLD_Con_1/exec_flag ), .M1(\DMM_EN[12] ), .M0(\DMM_EN[11] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_a3_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] ) , .F1(\CPLD_Con_1/RC_Tx_0_0_iv_3_88_i_i_a3_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] ) ); CPLD_Reg_1_SLICE_1320 \CPLD_Reg_1/SLICE_1320 ( .D1(reg_addr_1_rep1), .C1(reg_addr_0_rep1), .B1(\CPLD_Reg_1/N_7 ), .A1(\CPLD_Reg_1/N_1137 ), .D0(reg_addr_1_rep1), .C0(reg_addr_0_rep1), .B0(\CPLD_Reg_1/N_7 ), .A0(\CPLD_Reg_1/N_1137 ), .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][2] ), .F1(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][3] )); CPLD_Reg_1_SLICE_1321 \CPLD_Reg_1/SLICE_1321 ( .D1(reg_addr_1_rep1), .C1(reg_addr_0_rep1), .B1(\CPLD_Reg_1/N_7 ), .A1(\CPLD_Reg_1/N_1138 ), .D0(reg_addr_1_rep1), .C0(reg_addr_0_rep1), .B0(\CPLD_Reg_1/N_7 ), .A0(\CPLD_Reg_1/N_1138 ), .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][6] ), .F1(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][7] )); CPLD_Reg_1_SLICE_1322 \CPLD_Reg_1/SLICE_1322 ( .D1(\reg_addr_fast[0] ), .C1(reg_addr_1_rep1), .B1(\CPLD_Reg_1/N_7 ), .A1(\CPLD_Reg_1/un34_regtable_1[1] ), .D0(\reg_addr_fast[0] ), .C0(reg_addr_1_rep1), .B0(\CPLD_Reg_1/N_7 ), .A0(\CPLD_Reg_1/un34_regtable_1[1] ), .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][19] ), .F1(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][1] )); CPLD_Reg_1_SLICE_1323 \CPLD_Reg_1/SLICE_1323 ( .D1(reg_addr_1_rep1), .C1(reg_addr_0_rep1), .B1(\CPLD_Reg_1/N_7 ), .A1(\CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 ), .D0(reg_addr_1_rep1), .C0(reg_addr_0_rep1), .B0(\CPLD_Reg_1/N_7 ), .A0(\CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 ), .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][17] ), .F1(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][18] )); CPLD_Reg_1_SLICE_1324 \CPLD_Reg_1/SLICE_1324 ( .D1(\CPLD_Reg_1/state[0] ), .C1(\CPLD_Reg_1/un10_i_0_1 ), .B1(\CPLD_Reg_1/un34_regtable_1[1] ), .A1(\CPLD_Reg_1/state[1] ), .D0(\CPLD_Reg_1/un34_regtable_1[1] ), .C0(\CPLD_Reg_1/un10_i_0_1 ), .B0(\CPLD_Reg_1/state[1] ), .A0(\CPLD_Reg_1/state[0] ), .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/un10_i_0 ), .Q0(\CPLD_Reg_1/regtable[10][0] ), .F1(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .Q1(\CPLD_Reg_1/regtable[10][10] )); SLICE_1325 SLICE_1325( .C1(\DC_Con3[19] ), .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .D0(\DC_Con3[18] ), .C0(\DC_Con3[19] ), .B0(\CPLD_Con_1/un70_RC_RLSel_m_0_a2_1[16] ), .A0(\DC_Con3[17] ), .M1(jtaghub16_jshift), .M0(jtaghub16_jshift), .CE(jtaghub16_ip_enable0), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un70_RC_RLSel_m[16] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast ) , .F1(\CPLD_Con_1/un65_RC_RLSel_c3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) ); SLICE_1326 SLICE_1326( .D1(\CPLD_Con_1/N_419 ), .C1(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B1(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .A1(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .D0(\CPLD_Con_1/N_363 ), .C0(\CPLD_Con_1/un4_DPS_FS_2_axbxc7 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_axbxc4 ), .A0(\CPLD_Con_1/un4_DPS_FS_2_axbxc3 ), .M1(\DC_Con3[0] ), .M0(\DC_Con2[23] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.PMU_OC_2_11[18] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] ) , .F1(\CPLD_Con_1.PMU_OC_2_11[7] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] ) ); SLICE_1327 SLICE_1327( .C1(\DC_Con3[5] ), .B1(\DC_Con3[4] ), .A1(\CPLD_Con_1/un4_DPS_FS_3_c3 ), .D0(\DC_Con3[5] ), .C0(\DC_Con3[4] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c3 ), .A0(\CPLD_Con_1/RC_VSel40 ), .M1(\DC_Con4[4] ), .M0(\DC_Con4[3] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_404 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] ) , .F1(\CPLD_Con_1/N_35_7 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] ) ); SLICE_1328 SLICE_1328( .D1(\DC_Con1[17] ), .C1(\DC_Con1[18] ), .B1(\DC_Con1[19] ), .A1(\CPLD_Con_1/N_23 ), .D0(\DC_Con1[17] ), .C0(\DC_Con1[18] ), .B0(\DC_Con1[19] ), .A0(\CPLD_Con_1/N_25 ), .M1(\xo2chub/er1_shift_reg[5] ), .M0(\xo2chub/er1_shift_reg[4] ), .CE(jtaghub16_jupdate), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un20_RC_RLSel_m[14] ), .Q0(jtaghub16_ip_enable0), .F1(\CPLD_Con_1/un20_RC_RLSel_m[0] ), .Q1(\xo2chub/ip_enable[1] )); CPLD_Con_1_SLICE_1329 \CPLD_Con_1/SLICE_1329 ( .C1(\DC_Con3[6] ), .B1(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .A1(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .C0(\DC_Con3[6] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .A0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .F0(\CPLD_Con_1/N_454 ), .F1(\CPLD_Con_1/N_426 )); SLICE_1330 SLICE_1330( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), .A1(\DC_Con3[1] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[71] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[70] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_241 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] ) , .F1(\CPLD_Con_1/N_71_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] ) ); SLICE_1331 SLICE_1331( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), .A1(\DC_Con3[1] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[68] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[67] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_240 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] ) , .F1(\CPLD_Con_1/N_69_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] ) ); SLICE_1332 SLICE_1332( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), .A1(\DC_Con3[1] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[66] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[65] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_220 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] ) , .F1(\CPLD_Con_1/DPS_FS_3_9_i_a2_0[8] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] ) ); SLICE_1333 SLICE_1333( .C1(\DC_Con3[3] ), .B1(\DC_Con3[2] ), .A1(\DC_Con3[1] ), .C0(\DC_Con3[3] ), .B0(\DC_Con3[2] ), .A0(\DC_Con3[1] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[6] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[69] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_219 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] ) , .F1(\CPLD_Con_1/N_67_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] ) ); SLICE_1334 SLICE_1334( .C1(\DC_Con4[19] ), .B1(\DC_Con4[18] ), .A1(\DC_Con4[17] ), .C0(\DC_Con4[19] ), .B0(\DC_Con4[18] ), .A0(\DC_Con4[17] ), .M1(\xo2chub/er1_shift_reg[4] ), .M0(\xo2chub/er1_shift_reg[3] ), .CE(\xo2chub/er1_shift_reg8 ), .LSR(jtaghub16_jrstn), .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[5] ), .Q0(\xo2chub/er1_shift_reg[2] ), .F1(\CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[3] ), .Q1(\xo2chub/er1_shift_reg[3] )); SLICE_1335 SLICE_1335( .C1(\CPLD_Con_1/un1_i_DC_Con1[1] ), .B1(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), .C0(\CPLD_Con_1/un1_i_DC_Con1[1] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/dc_slot_flag[2] ), .M1(\BUS_Con_1/recv_reg[26] ), .M0(\BUS_Con_1/recv_reg[25] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_a2_0[9] ), .Q0(\BUS_Con_1/recv_reg[26] ), .F1(\CPLD_Con_1/DMM_en_26_0_a2_0[11] ), .Q1(\BUS_Con_1/recv_reg[27] )); SLICE_1336 SLICE_1336( .C1(\DC_Con2[19] ), .B1(\DC_Con2[18] ), .A1(\DC_Con2[17] ), .C0(\DC_Con2[19] ), .B0(\DC_Con2[18] ), .A0(\DC_Con2[17] ), .M1(\DC_Con2[17] ), .M0(\DC_Con2[16] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_64 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] ) , .F1(\CPLD_Con_1/un40_RC_RLSel_c3_d ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] ) ); SLICE_1337 SLICE_1337( .C1(\DC_Con1[3] ), .B1(\DC_Con1[2] ), .A1(\DC_Con1[1] ), .D0(\DC_Con1[4] ), .C0(\DC_Con1[3] ), .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), .M1(\DC_Con1[14] ), .M0(\DC_Con1[13] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_axbxc3 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] ) , .F1(\CPLD_Con_1/N_150 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] ) ); SLICE_1338 SLICE_1338( .C1(\DC_Con2[4] ), .B1(\DC_Con2[3] ), .A1(\DC_Con2[1] ), .D0(\DC_Con2[4] ), .C0(\DC_Con2[3] ), .B0(\DC_Con2[2] ), .A0(\DC_Con2[1] ), .M1(\DC_Con3[13] ), .M0(\DC_Con3[12] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_c4 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] ) , .F1(\CPLD_Con_1/err_flag45_i_a2_0_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] ) ); SLICE_1339 SLICE_1339( .C1(\DC_Con4[4] ), .B1(\DC_Con4[3] ), .A1(\DC_Con4[2] ), .C0(\DC_Con4[4] ), .B0(\DC_Con4[3] ), .A0(\DC_Con4[2] ), .M1(\DC_Con4[9] ), .M0(\DC_Con4[8] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_248 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] ) , .F1(\CPLD_Con_1/g0_45_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] ) ); CPLD_Con_1_SLICE_1340 \CPLD_Con_1/SLICE_1340 ( .D1(\DC_Con4[4] ), .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), .A0(\DC_Con4[1] ), .F0(\CPLD_Con_1/un4_DPS_FS_4_axbxc2 ), .F1(\CPLD_Con_1/DPS_N_12_mux_1 )); SLICE_1341 SLICE_1341( .C1(\DC_Con4[3] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), .D0(\DC_Con4[7] ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), .A0(\DC_Con4[1] ), .M1(\DC_Con4[11] ), .M0(\DC_Con4[10] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_Tx_0_0_iv_4_74_i_i_a4_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] ) , .F1(\CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_a4_1_1_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] ) ); SLICE_1342 SLICE_1342( .D1(\DC_Con4[8] ), .C1(\DC_Con4[7] ), .B1(\DC_Con4[6] ), .A1(\DC_Con4[5] ), .D0(\DC_Con4[9] ), .C0(\DC_Con4[8] ), .B0(\DC_Con4[7] ), .A0(\DC_Con4[6] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[64] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[63] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPS_FS_4_9_i_a2_4_2[8] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] ) , .F1(\CPLD_Con_1/un4_DPS_FS_4_c8_a0_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] ) ); SLICE_1343 SLICE_1343( .C1(\DC_Con1[6] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .A1(\CPLD_Con_1/N_34_3 ), .C0(\DC_Con1[6] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .A0(\CPLD_Con_1/N_34_3 ), .M1(\DC_Con1[3] ), .M0(\DC_Con1[2] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.N_98_3 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] ) , .F1(\CPLD_Con_1.N_102_3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] ) ); CPLD_Con_1_SLICE_1344 \CPLD_Con_1/SLICE_1344 ( .C1(\CPLD_Con_1/N_366 ), .B1(\CPLD_Con_1/N_184 ), .A1(\CPLD_Con_1/g0_0_0_0 ), .D0(\CPLD_Con_1/N_366 ), .C0(\CPLD_Con_1/N_184 ), .B0(\CPLD_Con_1/g4_0_0_0_1 ), .A0(\CPLD_Con_1/g0_0_0_0 ), .F0(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B ), .F1(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i )); SLICE_1345 SLICE_1345( .D1(con_exec), .C1(\CPLD_Con_1/N_385 ), .B1(\CPLD_Con_1/exec_flag_fast ), .A1(\CPLD_Con_1/exec_flag ), .C0(con_exec), .B0(\CPLD_Con_1/exec_flag_fast ), .A0(\CPLD_Con_1/exec_flag ), .M1(\DMM_EN[5] ), .M0(\DMM_EN[4] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/err_flag_en_0_a2_6_mb_rn_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] ) , .F1(\CPLD_Con_1/err_flag_en_0_a2_6_mb_sn ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] ) ); CPLD_Reg_1_SLICE_1346 \CPLD_Reg_1/SLICE_1346 ( .D1(reg_addr_1_rep1), .C1(reg_addr_0_rep1), .B1(\CPLD_Reg_1/N_7 ), .A1(\CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 ), .D0(reg_addr_1_rep1), .C0(reg_addr_0_rep1), .B0(\CPLD_Reg_1/N_7 ), .A0(\CPLD_Reg_1/N_1138 ), .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[0]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .Q0(\CPLD_Reg_1/regtable[0][13] ), .F1(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .Q1(\CPLD_Reg_1/regtable[0][14] )); BUS_Con_1_SLICE_1347 \BUS_Con_1/SLICE_1347 ( .C1(\BUS_Con_1/sclk_sync[1] ), .B1(\BUS_Con_1.sclk_sync[0] ), .A1(\BUS_Con_1/cs_sync[1] ), .D0(\BUS_Con_1.sclk_sync[0] ), .C0(\BUS_Con_1/sclk_sync[1] ), .B0(\BUS_Con_1/cs_sync[1] ), .A0(\BUS_Con_1/data_ready17 ), .M1(\BUS_Con_1/recv_reg[7] ), .M0(\BUS_Con_1/recv_reg[6] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/wr_flag_0_sqmuxa ), .Q0(\w_data[6] ), .F1(\BUS_Con_1/un2_sclk_rise ), .Q1(\w_data[7] )); BUS_Con_1_SLICE_1348 \BUS_Con_1/SLICE_1348 ( .D1(reg_busy), .C1(\BUS_Con_1/state[1] ), .B1(\BUS_Con_1/state[0] ), .A1(\BUS_Con_1/data_ready ), .D0(\BUS_Con_1/wr_flag ), .C0(\BUS_Con_1/state[1] ), .B0(\BUS_Con_1/state[0] ), .A0(\BUS_Con_1/data_ready ), .M1(\BUS_Con_1/recv_reg[10] ), .M0(\BUS_Con_1/recv_reg[0] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/data_out_0_sqmuxa ), .Q0(\w_data[0] ), .F1(\BUS_Con_1/N_493_i ), .Q1(\w_data[10] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1349 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1349 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[111] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[110] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_2_i_0_0_a2_4_1 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1350 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1350 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[11] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[10] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[10] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[109] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_4 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1351 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1351 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[140] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[13] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/rd_dout_te_1_u_i_a3[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_5 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[140] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1352 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1352 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[16] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[169] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[169] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] ) ); SLICE_1353 SLICE_1353( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[11] ) , .Q0(\CPLD_Reg_1/regtable[11][19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[10] ) , .Q1(\CPLD_Reg_1/regtable[11][1] )); SLICE_1354 SLICE_1354( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[1] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[3] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[2] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2] ) , .Q0(\CPLD_Reg_1/regtable[12][15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1] ) , .Q1(\CPLD_Reg_1/regtable[12][16] )); SLICE_1355 SLICE_1355( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[10] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[9] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[9] ) , .Q0(\CPLD_Reg_1/regtable[11][22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[8] ) , .Q1(\CPLD_Reg_1/regtable[11][23] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1356 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1356 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_846 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_826 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1357 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1357 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_1_0 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_253_1_0 ) ); SLICE_1358 SLICE_1358( .D1(i_rst_n_c), .C1(\DC_Con4[9] ), .B1(\DC_Con4[8] ), .A1(\CPLD_Con_1/exec_flag ), .D0(\CPLD_Con_1/freq_t_fast[0] ), .C0(\CPLD_Con_1/freq_t_fast[1] ), .B0(\CPLD_Con_1/exec_flag ), .A0(i_rst_n_c), .M1(\RC_RLSel[9] ), .M0(\DPS_FS_1[10] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(N_18_i), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[149] ) , .F1(\CPLD_Con_1/N_126 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] ) ); SLICE_1359 SLICE_1359( .C1(\CPLD_Con_1/N_50 ), .B1(\DC_Con2[17] ), .A1(\CPLD_Con_1/un40_RC_RLSel_axbxc3 ), .C0(\DC_Con2[20] ), .B0(\DC_Con2[17] ), .A0(\CPLD_Con_1/N_50 ), .M1(\DC_Con2[13] ), .M0(\RC_RLSel[0] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_66 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] ) , .F1(\CPLD_Con_1/N_65 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] ) ); SLICE_1360 SLICE_1360( .D1(\CPLD_Con_1/N_89 ), .C1(\CPLD_Con_1/N_86 ), .B1(\DC_Con4[17] ), .A1(\CPLD_Con_1/RC_RLSel_13_iv_0[10] ), .D0(\CPLD_Con_1/N_92 ), .C0(\CPLD_Con_1/N_86 ), .B0(\DC_Con4[17] ), .A0(\CPLD_Con_1/RC_RLSel_13_iv_0[15] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[6] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/RC_RLSel_13_iv_1[15] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[6] ) , .F1(\CPLD_Con_1/RC_RLSel_13_iv_1[10] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[7] ) ); SLICE_1361 SLICE_1361( .D1(\DC_Con1[6] ), .C1(\DC_Con1[5] ), .B1(\DC_Con1[4] ), .A1(\DC_Con1[2] ), .D0(\DC_Con1[5] ), .C0(\DC_Con1[4] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c3 ), .A0(\CPLD_Con_1/un3_DPS_FS_1_axbxc7 ), .M1(\DC_Con1[19] ), .M0(\DC_Con1[6] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/PMU_OC_4_4_313_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] ) , .F1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] ) ); SLICE_1362 SLICE_1362( .D1(\DC_Con4[9] ), .C1(\DC_Con4[5] ), .B1(\DC_Con4[2] ), .A1(\DC_Con4[1] ), .C0(\CPLD_Con_1/N_400 ), .B0(\DC_Con4[2] ), .A0(\DC_Con4[1] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[62] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[61] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_408 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] ) , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] ) ); SLICE_1363 SLICE_1363( .D1(\CPLD_Con_1/N_182 ), .C1(\CPLD_Con_1/exec_flag_rep1 ), .B1(\CPLD_Con_1/err_flag53 ), .A1(\CPLD_Con_1/RC_VSel39 ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/N_182 ), .B0(\CPLD_Con_1/un4_DPS_FS_2_c6_a0_2_RNIUHVQ ), .A0(\CPLD_Con_1/RC_VSel39 ), .M1(\DC_Con4[18] ), .M0(\DC_Con4[17] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_345 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] ) , .F1(\CPLD_Con_1/un1_exec_flag_4_i_a2_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] ) ); SLICE_1364 SLICE_1364( .B1(\DC_Con3[18] ), .A1(\DC_Con3[17] ), .C0(\DC_Con3[19] ), .B0(\DC_Con3[18] ), .A0(\DC_Con3[17] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[11] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[14] ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[11] ) , .F1(\CPLD_Con_1/err_flag75lt3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[12] ) ); SLICE_1365 SLICE_1365( .C1(\DC_Con1[8] ), .B1(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/dc_slot_flag[0] ), .M1(\DPS_FS_3[13] ), .M0(\DPS_FS_3[12] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_1_11 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[183] ) , .F1(\CPLD_Con_1/DMM_en_26_0_a3_0_0[3] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[184] ) ); SLICE_1366 SLICE_1366( .B1(\DC_Con4[8] ), .A1(\DC_Con4[7] ), .D0(\CPLD_Con_1/N_57 ), .C0(\DC_Con4[8] ), .B0(\DC_Con4[7] ), .A0(\DC_Con4[4] ), .M1(\BUS_Con_1/recv_reg[8] ), .M0(\BUS_Con_1/recv_reg[7] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_a4_1_1_0[13] ), .Q0(\BUS_Con_1/recv_reg[8] ), .F1(\CPLD_Con_1/err_flag89_2 ), .Q1(\BUS_Con_1/recv_reg[9] )); SLICE_1367 SLICE_1367( .B1(\DC_Con1[3] ), .A1(\DC_Con1[1] ), .C0(\DC_Con1[3] ), .B0(\DC_Con1[2] ), .A0(\DC_Con1[1] ), .M1(\DC_Con1[12] ), .M0(\DC_Con1[11] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un3_DPS_FS_1_axbxc2 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] ) , .F1(\CPLD_Con_1/DPS_m3_0_a2_2_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] ) ); SLICE_1368 SLICE_1368( .B1(\DC_Con1[9] ), .A1(\DC_Con1[8] ), .D0(i_rst_n_c), .C0(\DC_Con1[9] ), .B0(\DC_Con1[8] ), .A0(\DC_Con1[7] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[75] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[74] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/PMU_OC_1_1_sqmuxa_1_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] ) , .F1(\CPLD_Con_1/DPS_FS_1_9_i_a2_2_0[12] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] ) ); CPLD_Con_1_SLICE_1369 \CPLD_Con_1/SLICE_1369 ( .D1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .C1(\CPLD_Con_1/dc_slot_flag_2_rep1 ), .B1(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), .D0(\DC_Con3[8] ), .C0(\DC_Con2[8] ), .B0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), .A0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .M1(\DC_Con4[0] ), .M0(\DC_Con3[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_254 ), .Q0(\CPLD_Con_1/dc_slot_flag[2] ), .F1(\CPLD_Con_1/g0_17_rn_1 ), .Q1(\CPLD_Con_1/dc_slot_flag[3] )); SLICE_1370 SLICE_1370( .D1(i_rst_n_c), .C1(\CPLD_Con_1/freq_t[1] ), .B1(\CPLD_Con_1/freq_t[0] ), .A1(\CPLD_Con_1/dc_slot_flag_3_rep1 ), .D0(\CPLD_Con_1/freq_t[1] ), .C0(\CPLD_Con_1/freq_t[0] ), .B0(\CPLD_Con_1/freq_slot_flag[3] ), .A0(\CPLD_Con_1/freq_slot_flag[2] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[73] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[72] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_381 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] ) , .F1(\CPLD_Con_1/g1_1_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] ) ); SLICE_1371 SLICE_1371( .C1(\DC_Con2[9] ), .B1(\DC_Con2[8] ), .A1(\DC_Con2[7] ), .D0(\DC_Con2[8] ), .C0(\DC_Con2[7] ), .B0(\DC_Con2[6] ), .A0(\DC_Con2[4] ), .M1(\DC_Con3[17] ), .M0(\DC_Con3[16] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un4_DPS_FS_2_c8_a0_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] ) , .F1(\CPLD_Con_1/err_flag45_i_a3_0_N_2L1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] ) ); SLICE_1372 SLICE_1372( .C1(\DC_Con3[9] ), .B1(\DC_Con3[8] ), .A1(\CPLD_Con_1/freq_slot_flag[3] ), .D0(\DC_Con3[23] ), .C0(\DC_Con3[9] ), .B0(\DC_Con3[8] ), .A0(\DC_Con3[7] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[2] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[29] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2_0_a2_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] ) , .F1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_0_0_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] ) ); SLICE_1373 SLICE_1373( .D1(i_rst_n_c), .C1(\CPLD_Con_1/dc_slot_flag[3] ), .B1(\CPLD_Con_1/dc_slot_flag[2] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), .B0(i_rst_n_c), .A0(\CPLD_Con_1/dc_slot_flag[3] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[40] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[3] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/m4_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] ) , .F1(\CPLD_Con_1/DPS_FSMMCe_N_2L1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] ) ); SLICE_1374 SLICE_1374( .C1(\DC_Con1[6] ), .B1(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .A1(\CPLD_Con_1/N_33_3 ), .C0(\DC_Con1[6] ), .B0(\CPLD_Con_1/un3_DPS_FS_1_c6_a0_3_RNIOSA01 ), .A0(\CPLD_Con_1/N_35_3 ), .M1(\DC_Con1[5] ), .M0(\DC_Con1[4] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1.N_99_3 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] ) , .F1(\CPLD_Con_1.N_101_3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] ) ); SLICE_1375 SLICE_1375( .D1(i_rst_n_c), .C1(\CPLD_Con_1/io_RC9 ), .B1(\CPLD_Con_1/freq_slot_flag[3] ), .A1(\CPLD_Con_1/PMU_OC_3_11_6_a2_2_1 ), .D0(i_rst_n_c), .C0(\CPLD_Con_1/io_RC9 ), .B0(\CPLD_Con_1/g1_2 ), .A0(\CPLD_Con_1/RC_VSel41 ), .M1(\DMM_EN[0] ), .M0(\DC_Con4[23] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g3 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] ) , .F1(\CPLD_Con_1/N_416 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] ) ); SLICE_1376 SLICE_1376( .C1(\DC_Con3[5] ), .B1(\DC_Con3[4] ), .A1(\DC_Con3[2] ), .C0(\DC_Con3[5] ), .B0(\DC_Con3[4] ), .A0(\DC_Con3[1] ), .M1(\FSMMC[5] ), .M0(\FSMMC[4] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf1_1 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[211] ) , .F1(\CPLD_Con_1/PMU_OC_312lto8_1_0_o2_0_sn ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[212] ) ); CPLD_Reg_1_SLICE_1377 \CPLD_Reg_1/SLICE_1377 ( .B1(\CPLD_Reg_1/state[1] ), .A1(\CPLD_Reg_1/state[0] ), .B0(\CPLD_Reg_1/state[0] ), .A0(\CPLD_Reg_1/state[1] ), .F0(\CPLD_Reg_1/state_6_d_i ), .F1(\CPLD_Reg_1/N_45_i )); BUS_Con_1_SLICE_1378 \BUS_Con_1/SLICE_1378 ( .B1(i_rst_n_c), .A1(\BUS_Con_1/cs_sync[1] ), .C0(\BUS_Con_1/cs_sync[1] ), .B0(i_rst_n_c), .A0(\BUS_Con_1/miso_shift_1_sqmuxa_i_0 ), .M1(\BUS_Con_1/recv_reg[16] ), .M0(\BUS_Con_1/recv_reg[15] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(N_694_en), .Q0(\w_data[15] ), .F1(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .Q1(\w_data[16] )); BUS_Con_1_SLICE_1379 \BUS_Con_1/SLICE_1379 ( .B1(\BUS_Con_1/bit_cnt[1] ), .A1(\BUS_Con_1/bit_cnt[0] ), .C0(\BUS_Con_1/bit_cnt[2] ), .B0(\BUS_Con_1/bit_cnt[1] ), .A0(\BUS_Con_1/bit_cnt[0] ), .M1(\BUS_Con_1/recv_reg[14] ), .M0(\BUS_Con_1/recv_reg[13] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/miso_shift17lt3 ), .Q0(\w_data[13] ), .F1(\BUS_Con_1/err_flag8_1 ), .Q1(\w_data[14] )); BUS_Con_1_SLICE_1380 \BUS_Con_1/SLICE_1380 ( .B1(\BUS_Con_1/bit_cnt[5] ), .A1(\BUS_Con_1/bit_cnt[4] ), .D0(\BUS_Con_1/bit_cnt[5] ), .C0(\BUS_Con_1/bit_cnt[4] ), .B0(\BUS_Con_1/bit_cnt[3] ), .A0(\BUS_Con_1/bit_cnt[2] ), .M1(\BUS_Con_1/recv_reg[12] ), .M0(\BUS_Con_1/recv_reg[11] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/err_flag8_2 ), .Q0(\w_data[11] ), .F1(\BUS_Con_1/miso_shift9_2 ), .Q1(\w_data[12] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1381 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1381 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tu[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[173] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[172] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[172] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[173] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1382 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1382 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[139] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[138] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[139] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1383 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1383 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_881 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/even_parity ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[126] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[125] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_818 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1384 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1384 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_871 ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/wen_tcnt ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[12] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[129] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_878 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1385 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1385 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[131] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[130] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tcnt[1] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_830 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] ) ); SLICE_1386 SLICE_1386( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[10] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[10] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[9] ) , .Q0(\CPLD_Reg_1/regtable[12][11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_539 ) , .Q1(\CPLD_Reg_1/regtable[12][12] )); SLICE_1387 SLICE_1387( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[7] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[9] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[8] ) , .Q0(\CPLD_Reg_1/regtable[12][0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4362 ) , .Q1(\CPLD_Reg_1/regtable[12][10] )); SLICE_1388 SLICE_1388( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[8] ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[7] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[13] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[12] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_54 ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[12] ) , .Q0(\CPLD_Reg_1/regtable[11][20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[7] ) , .Q1(\CPLD_Reg_1/regtable[11][21] )); SLICE_1389 SLICE_1389( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_554 ) , .Q0(\CPLD_Reg_1/regtable[11][17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_801 ), .Q1(\CPLD_Reg_1/regtable[11][18] )); SLICE_1390 SLICE_1390( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) , .C1(jtaghub16_jshift), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_tz ) , .Q0(\DC_Con2[2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0_1 ) , .Q1(\DC_Con2[3] )); SLICE_1391 SLICE_1391( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/parity_err ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 ) , .Q0(\DC_Con3[13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 ) , .Q1(\DC_Con3[14] )); SLICE_1392 SLICE_1392( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[14] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[13] ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[12] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 ) , .Q0(\DC_Con1[4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ) , .Q1(\DC_Con1[5] )); SLICE_1393 SLICE_1393( .B1(jtaghub16_jrstn), .A1(jtaghub16_ip_enable0), .B0(jtaghub16_jrstn), .A0(jtaghub16_ip_enable0), .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa ) , .Q0(\CPLD_Reg_1/regtable[10][15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ), .Q1(\CPLD_Reg_1/regtable[10][16] )); SLICE_1394 SLICE_1394( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wen ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 ) , .Q0(\DC_Con3[11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 ) , .Q1(\DC_Con3[12] )); SLICE_1395 SLICE_1395( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_71 ) , .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4370 ) , .Q0(\CPLD_Reg_1/regtable[12][22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4344 ) , .Q1(\CPLD_Reg_1/regtable[12][23] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1396 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1396 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_877 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_877 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_1_1_0 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_1_0 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ) ); SLICE_1397 SLICE_1397( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[8] ), .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[9]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] ) , .Q0(\DC_Con4[4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_12[0] ) , .Q1(\DC_Con4[5] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1398 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1398 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_876 ), .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 ) ); SLICE_1399 SLICE_1399( .C1(\DC_Con4[8] ), .B1(\DC_Con4[6] ), .A1(\DC_Con4[5] ), .C0(\DC_Con4[5] ), .B0(\DC_Con4[4] ), .A0(\CPLD_Con_1/un4_DPS_FS_4_c3 ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[99] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[98] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_11 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] ) , .F1(\CPLD_Con_1/g0_6_2_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] ) ); CPLD_Con_1_SLICE_1400 \CPLD_Con_1/SLICE_1400 ( .B1(\DC_Con3[7] ), .A1(\DC_Con3[6] ), .C0(\DC_Con3[6] ), .B0(\CPLD_Con_1/un4_DPS_FS_3_c5_i ), .A0(\CPLD_Con_1/un4_DPS_FS_3_c6_a0_1_RNIF4MU ), .F0(\CPLD_Con_1/N_437 ), .F1(\CPLD_Con_1/PMU_OC_312lto8_0_a2_0 )); CPLD_Con_1_SLICE_1401 \CPLD_Con_1/SLICE_1401 ( .B1(\DC_Con4[9] ), .A1(\DC_Con4[6] ), .C0(\DC_Con4[7] ), .B0(\DC_Con4[6] ), .A0(\CPLD_Con_1/un4_DPS_FS_4_c5_i ), .F0(\CPLD_Con_1/PMU_OC_4_11_409_a2_0_a2_0_0 ), .F1(\CPLD_Con_1/DPS_FS_4_9_i_a2_4_0[8] )); SLICE_1402 SLICE_1402( .C1(\CPLD_Con_1/N_182 ), .B1(\CPLD_Con_1/un1_RC_VSel41_1_0_a2 ), .A1(\CPLD_Con_1/exec_flag ), .D0(\CPLD_Con_1/exec_flag ), .C0(\CPLD_Con_1/RC_VSel40 ), .B0(\CPLD_Con_1/RC_VSel39 ), .A0(\CPLD_Con_1/RC_VSel38 ), .M1(\DPS_FS_3[8] ), .M0(\DPS_FS_3[7] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_c_d ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[178] ) , .F1(\CPLD_Con_1/un1_exec_flag_3_i_0_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[179] ) ); SLICE_1403 SLICE_1403( .D1(\DC_Con2[7] ), .C1(\DC_Con1[7] ), .B1(\CPLD_Con_1/dc_slot_flag[1] ), .A1(\CPLD_Con_1/dc_slot_flag[0] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/dc_slot_flag[1] ), .M1(\DPS_FS_3[15] ), .M0(\DPS_FS_3[14] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_5_11 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[185] ) , .F1(\CPLD_Con_1/un1_i_DC_Con1_iv_0[0] ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[186] ) ); SLICE_1404 SLICE_1404( .B1(\DC_Con4[7] ), .A1(\CPLD_Con_1/dc_slot_flag[3] ), .C0(\DC_Con4[8] ), .B0(\CPLD_Con_1/un1_i_DC_Con1[0] ), .A0(\CPLD_Con_1/dc_slot_flag[3] ), .M1(\BUS_Con_1/recv_reg[2] ), .M0(\BUS_Con_1/recv_reg[30] ), .CE(\BUS_Con_1/un2_sclk_rise ), .LSR(\BUS_Con_1/cs_sync_RNI4H6C[1] ), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/DMM_en_26_0_a3_1_0[14] ), .Q0(\BUS_Con_1/recv_reg[31] ), .F1(\CPLD_Con_1/i_DC_Con4_m[7] ), .Q1(\BUS_Con_1/recv_reg[3] )); SLICE_1405 SLICE_1405( .B1(\DC_Con4[4] ), .A1(\DC_Con4[3] ), .C0(\DC_Con4[3] ), .B0(\DC_Con4[2] ), .A0(\DC_Con4[1] ), .M1(\RC_RLSel[17] ), .M0(\RC_RLSel[16] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_261 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] ) , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] ) ); SLICE_1406 SLICE_1406( .B1(\DC_Con3[4] ), .A1(\DC_Con3[3] ), .B0(\DC_Con3[3] ), .A0(\DC_Con3[2] ), .M1(\DPS_FS_3[2] ), .M0(\DPS_FS_3[1] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/un16lto5_4_i_a2_0_0 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[172] ) , .F1(\CPLD_Con_1/un4_DPS_FS_3_c5_a0_0_0 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[173] ) ); SLICE_1407 SLICE_1407( .D1(\CPLD_Con_1/N_204_tz ), .C1(\DC_Con4[23] ), .B1(\CPLD_Con_1/un4_DPS_FS_4_c8_i ), .A1(\CPLD_Con_1/RC_VSel41 ), .D0(\CPLD_Con_1/N_195 ), .C0(\CPLD_Con_1/N_182 ), .B0(\CPLD_Con_1/err_flag97 ), .A0(\CPLD_Con_1/RC_VSel41 ), .M1(\DMM_EN[1] ), .M0(\RC_RLSel[6] ), .LSR(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/N_386 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] ) , .F1(\CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_3_tz_RNI9M8I3 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] ) ); BUS_Con_1_SLICE_1408 \BUS_Con_1/SLICE_1408 ( .B1(\BUS_Con_1/state[1] ), .A1(\BUS_Con_1/state[0] ), .C0(reg_busy), .B0(\BUS_Con_1/state[1] ), .A0(\BUS_Con_1/data_ready ), .M1(\BUS_Con_1/recv_reg[21] ), .M0(\BUS_Con_1/recv_reg[20] ), .CE(\BUS_Con_1/un1_addr_out_0_sqmuxa ), .LSR(\BUS_Con_1/state_RNIS4Q6[0] ), .CLK(i_sys_clk_c), .F0(\BUS_Con_1/N_497 ), .Q0(\w_data[20] ), .F1(o_wready_c), .Q1(\w_data[21] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1409 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1409 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[4] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[177] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[176] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][1] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[176] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_tu[0][2] ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[177] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1410 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1410 ( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[179] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[178] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[178] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_5_1 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[179] ) ); SLICE_1411 SLICE_1411( .C1(\xo2chub/jtdo2_int ), .B1(jtaghub16_jshift), .A1(jtaghub16_jce2), .B0(jtaghub16_jce2), .A0(jtaghub16_ip_enable0), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[166] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[165] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3_0_0 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[165] ) , .F1(\xo2chub/jtdo2 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[166] ) ); SLICE_1412 SLICE_1412( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[4] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[8] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_124 ) , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[7] ) , .Q0(\CPLD_Reg_1/regtable[11][8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_528 ) , .Q1(\CPLD_Reg_1/regtable[11][9] )); SLICE_1413 SLICE_1413( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_63 ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[210] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[209] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_7_213_3774_i_m2_i_0 ) , .Q0(\CPLD_Reg_1/regtable[14][11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un4_jupdate_early_i_o2_RNIQKF31[0] ) , .Q1(\CPLD_Reg_1/regtable[14][12] )); SLICE_1414 SLICE_1414( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[6] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[3] ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4330 ) , .Q0(\CPLD_Reg_1/regtable[11][15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_530 ) , .Q1(\CPLD_Reg_1/regtable[11][16] )); SLICE_1415 SLICE_1415( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[208] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[209] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[1] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2] ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_909 ) , .Q0(\CPLD_Reg_1/regtable[14][0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_74 ) , .Q1(\CPLD_Reg_1/regtable[14][10] )); SLICE_1416 SLICE_1416( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[207] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[208] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[2] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3] ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_925 ) , .Q0(\CPLD_Reg_1/regtable[15][11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4205 ) , .Q1(\CPLD_Reg_1/regtable[15][12] )); SLICE_1417 SLICE_1417( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[206] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[207] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[3] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] ) , .M1(\w_data[11] ), .M0(\w_data[10] ), .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_941 ) , .Q0(\CPLD_Reg_1/regtable[1][10] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4189 ) , .Q1(\CPLD_Reg_1/regtable[1][11] )); SLICE_1418 SLICE_1418( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[205] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[206] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[4] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_957 ) , .Q0(\freq1_relay[0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4173 ) , .Q1(\CPLD_Reg_1/regtable[2][10] )); SLICE_1419 SLICE_1419( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[204] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[205] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[5] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] ) , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_973 ) , .Q0(\CPLD_Reg_1/regtable[2][8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4157 ) , .Q1(\CPLD_Reg_1/regtable[2][9] )); SLICE_1420 SLICE_1420( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[203] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[204] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[6] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_989 ) , .Q0(\CPLD_Reg_1/regtable[3][6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4141 ) , .Q1(\CPLD_Reg_1/regtable[3][7] )); SLICE_1421 SLICE_1421( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[202] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[203] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[7] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1005 ) , .Q0(\CPLD_Reg_1/regtable[4][4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4125 ) , .Q1(\CPLD_Reg_1/regtable[4][5] )); SLICE_1422 SLICE_1422( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[201] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[202] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[8] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1021 ) , .Q0(\CPLD_Reg_1/regtable[5][2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4109 ) , .Q1(\CPLD_Reg_1/regtable[5][3] )); SLICE_1423 SLICE_1423( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[200] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[201] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[9] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] ) , .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1037 ) , .Q0(\DC_Con1[22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4093 ) , .Q1(\DC_Con1[23] )); SLICE_1424 SLICE_1424( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[199] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[200] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[10] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] ) , .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1053 ) , .Q0(\CPLD_Reg_1/regtable[13][13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4077 ) , .Q1(\CPLD_Reg_1/regtable[13][14] )); SLICE_1425 SLICE_1425( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[198] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[199] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[11] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1069 ) , .Q0(\CPLD_Reg_1/regtable[13][15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4061 ) , .Q1(\CPLD_Reg_1/regtable[13][16] )); SLICE_1426 SLICE_1426( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[197] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[198] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[12] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] ) , .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1085 ) , .Q0(\CPLD_Reg_1/regtable[13][17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4045 ) , .Q1(\CPLD_Reg_1/regtable[13][18] )); SLICE_1427 SLICE_1427( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[196] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[197] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[13] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1101 ) , .Q0(\CPLD_Reg_1/regtable[13][19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4029 ) , .Q1(\CPLD_Reg_1/regtable[13][1] )); SLICE_1428 SLICE_1428( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[195] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[196] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[14] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1117 ) , .Q0(\CPLD_Reg_1/regtable[13][20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_4013 ) , .Q1(\CPLD_Reg_1/regtable[13][21] )); SLICE_1429 SLICE_1429( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[194] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[195] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] ) , .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1133 ) , .Q0(\CPLD_Reg_1/regtable[13][22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3997 ) , .Q1(\CPLD_Reg_1/regtable[13][23] )); SLICE_1430 SLICE_1430( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[193] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[194] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[16] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1149 ) , .Q0(\CPLD_Reg_1/regtable[13][2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3981 ) , .Q1(\CPLD_Reg_1/regtable[13][3] )); SLICE_1431 SLICE_1431( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[192] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[193] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[17] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1165 ) , .Q0(\CPLD_Reg_1/regtable[13][4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3965 ) , .Q1(\CPLD_Reg_1/regtable[13][5] )); SLICE_1432 SLICE_1432( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[191] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[192] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[18] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1181 ) , .Q0(\CPLD_Reg_1/regtable[13][6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3949 ) , .Q1(\CPLD_Reg_1/regtable[13][7] )); SLICE_1433 SLICE_1433( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[190] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[191] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[19] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] ) , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1197 ) , .Q0(\CPLD_Reg_1/regtable[13][8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3933 ) , .Q1(\CPLD_Reg_1/regtable[13][9] )); SLICE_1434 SLICE_1434( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[189] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[190] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[20] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] ) , .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1213 ) , .Q0(\CPLD_Reg_1/regtable[14][13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3917 ) , .Q1(\CPLD_Reg_1/regtable[14][14] )); SLICE_1435 SLICE_1435( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[188] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[189] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[21] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] ) , .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1229 ) , .Q0(\CPLD_Reg_1/regtable[14][17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3901 ) , .Q1(\CPLD_Reg_1/regtable[14][18] )); SLICE_1436 SLICE_1436( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[187] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[188] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[22] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1245 ) , .Q0(\CPLD_Reg_1/regtable[14][19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3885 ) , .Q1(\CPLD_Reg_1/regtable[14][1] )); SLICE_1437 SLICE_1437( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[186] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[187] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[23] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1261 ) , .Q0(\CPLD_Reg_1/regtable[14][20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3869 ) , .Q1(\CPLD_Reg_1/regtable[14][21] )); SLICE_1438 SLICE_1438( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[185] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[186] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[0] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_893 ) , .Q0(\CPLD_Reg_1/regtable[12][4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3853 ) , .Q1(\CPLD_Reg_1/regtable[12][5] )); SLICE_1439 SLICE_1439( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[184] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[185] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[24] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] ) , .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1277 ) , .Q0(\CPLD_Reg_1/regtable[14][22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3837 ) , .Q1(\CPLD_Reg_1/regtable[14][23] )); SLICE_1440 SLICE_1440( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[183] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[184] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[25] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1293 ) , .Q0(\CPLD_Reg_1/regtable[14][2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3821 ) , .Q1(\CPLD_Reg_1/regtable[14][3] )); SLICE_1441 SLICE_1441( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[182] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[183] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[26] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1309 ) , .Q0(\CPLD_Reg_1/regtable[14][4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3805 ) , .Q1(\CPLD_Reg_1/regtable[14][5] )); SLICE_1442 SLICE_1442( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[181] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[182] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[27] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1325 ) , .Q0(\CPLD_Reg_1/regtable[14][6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3789 ) , .Q1(\CPLD_Reg_1/regtable[14][7] )); SLICE_1443 SLICE_1443( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[180] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[181] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[28] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] ) , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[14]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1341 ) , .Q0(\CPLD_Reg_1/regtable[14][8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3773 ) , .Q1(\CPLD_Reg_1/regtable[14][9] )); SLICE_1444 SLICE_1444( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[179] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[180] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[29] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1357 ) , .Q0(\CPLD_Reg_1/regtable[15][0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3757 ) , .Q1(\CPLD_Reg_1/regtable[15][10] )); SLICE_1445 SLICE_1445( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[178] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[179] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[30] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] ) , .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1373 ) , .Q0(\CPLD_Reg_1/regtable[15][13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3741 ) , .Q1(\CPLD_Reg_1/regtable[15][14] )); SLICE_1446 SLICE_1446( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[177] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[178] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[31] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1389 ) , .Q0(\CPLD_Reg_1/regtable[15][15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3725 ) , .Q1(\CPLD_Reg_1/regtable[15][16] )); SLICE_1447 SLICE_1447( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[176] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[177] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[32] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] ) , .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1405 ) , .Q0(\CPLD_Reg_1/regtable[15][17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3709 ) , .Q1(\CPLD_Reg_1/regtable[15][18] )); SLICE_1448 SLICE_1448( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[175] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[176] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[33] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1421 ) , .Q0(\CPLD_Reg_1/regtable[15][19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3693 ) , .Q1(\CPLD_Reg_1/regtable[15][1] )); SLICE_1449 SLICE_1449( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[174] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[175] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[34] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1437 ) , .Q0(\CPLD_Reg_1/regtable[15][20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3677 ) , .Q1(\CPLD_Reg_1/regtable[15][21] )); SLICE_1450 SLICE_1450( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[173] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[174] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[35] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] ) , .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1453 ) , .Q0(\CPLD_Reg_1/regtable[15][22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3661 ) , .Q1(\CPLD_Reg_1/regtable[15][23] )); SLICE_1451 SLICE_1451( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[172] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[173] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[36] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1469 ) , .Q0(\CPLD_Reg_1/regtable[15][2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3645 ) , .Q1(\CPLD_Reg_1/regtable[15][3] )); SLICE_1452 SLICE_1452( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[171] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[172] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[37] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1485 ) , .Q0(\CPLD_Reg_1/regtable[15][4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3629 ) , .Q1(\CPLD_Reg_1/regtable[15][5] )); SLICE_1453 SLICE_1453( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[170] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[171] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[38] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1501 ) , .Q0(\CPLD_Reg_1/regtable[15][6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3613 ) , .Q1(\CPLD_Reg_1/regtable[15][7] )); SLICE_1454 SLICE_1454( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[169] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[170] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[39] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] ) , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[15]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1517 ) , .Q0(\CPLD_Reg_1/regtable[15][8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3597 ) , .Q1(\CPLD_Reg_1/regtable[15][9] )); SLICE_1455 SLICE_1455( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[168] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[169] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[40] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] ) , .M1(\w_data[13] ), .M0(\w_data[12] ), .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1533 ) , .Q0(\CPLD_Reg_1/regtable[1][12] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3581 ) , .Q1(\CPLD_Reg_1/regtable[1][13] )); SLICE_1456 SLICE_1456( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[167] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[168] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[41] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] ) , .M1(\w_data[15] ), .M0(\w_data[14] ), .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1549 ) , .Q0(\CPLD_Reg_1/regtable[1][14] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3565 ) , .Q1(\CPLD_Reg_1/regtable[1][15] )); SLICE_1457 SLICE_1457( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[166] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[167] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[42] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] ) , .M1(\w_data[17] ), .M0(\w_data[16] ), .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1565 ) , .Q0(\CPLD_Reg_1/regtable[1][16] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3549 ) , .Q1(\CPLD_Reg_1/regtable[1][17] )); SLICE_1458 SLICE_1458( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[165] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[166] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[43] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] ) , .M1(\w_data[19] ), .M0(\w_data[18] ), .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1581 ) , .Q0(\CPLD_Reg_1/regtable[1][18] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3533 ) , .Q1(\CPLD_Reg_1/regtable[1][19] )); SLICE_1459 SLICE_1459( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[164] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[165] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[44] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] ) , .M1(\w_data[20] ), .M0(\w_data[1] ), .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1597 ) , .Q0(\CPLD_Reg_1/regtable[1][1] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3517 ) , .Q1(\CPLD_Reg_1/regtable[1][20] )); SLICE_1460 SLICE_1460( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[163] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[164] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[45] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] ) , .M1(\w_data[22] ), .M0(\w_data[21] ), .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1613 ) , .Q0(\CPLD_Reg_1/regtable[1][21] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3501 ) , .Q1(\CPLD_Reg_1/regtable[1][22] )); SLICE_1461 SLICE_1461( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[162] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[163] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[46] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1629 ) , .Q0(\CPLD_Reg_1/regtable[1][2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3485 ) , .Q1(\CPLD_Reg_1/regtable[1][3] )); SLICE_1462 SLICE_1462( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[161] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[162] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1645 ) , .Q0(\CPLD_Reg_1/regtable[1][4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3469 ) , .Q1(\CPLD_Reg_1/regtable[1][5] )); SLICE_1463 SLICE_1463( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[160] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[161] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1661 ) , .Q0(\CPLD_Reg_1/regtable[1][6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3453 ) , .Q1(\CPLD_Reg_1/regtable[1][7] )); SLICE_1464 SLICE_1464( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[159] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[160] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[49] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] ) , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/un10_i_0_1_RNI75F41 ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1677 ) , .Q0(\CPLD_Reg_1/regtable[1][8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3437 ) , .Q1(\CPLD_Reg_1/regtable[1][9] )); SLICE_1465 SLICE_1465( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[158] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[159] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[50] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1693 ) , .Q0(\CPLD_Reg_1/regtable[2][11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3421 ) , .Q1(\CPLD_Reg_1/regtable[2][12] )); SLICE_1466 SLICE_1466( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[157] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[158] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[51] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] ) , .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1709 ) , .Q0(\CPLD_Reg_1/regtable[2][13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3405 ) , .Q1(\CPLD_Reg_1/regtable[2][14] )); SLICE_1467 SLICE_1467( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[156] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[157] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[52] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1725 ) , .Q0(\CPLD_Reg_1/regtable[2][15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3389 ) , .Q1(\CPLD_Reg_1/regtable[2][16] )); SLICE_1468 SLICE_1468( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[155] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[156] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[53] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] ) , .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1741 ) , .Q0(\CPLD_Reg_1/regtable[2][17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3373 ) , .Q1(\CPLD_Reg_1/regtable[2][18] )); SLICE_1469 SLICE_1469( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[154] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[155] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[54] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1757 ) , .Q0(\CPLD_Reg_1/regtable[2][19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3357 ) , .Q1(\CPLD_Reg_1/regtable[2][1] )); SLICE_1470 SLICE_1470( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[153] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[154] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[55] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1773 ) , .Q0(\CPLD_Reg_1/regtable[2][20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3341 ) , .Q1(\CPLD_Reg_1/regtable[2][21] )); SLICE_1471 SLICE_1471( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[152] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[153] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[56] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] ) , .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1789 ) , .Q0(\CPLD_Reg_1/regtable[2][22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3325 ) , .Q1(\CPLD_Reg_1/regtable[2][23] )); SLICE_1472 SLICE_1472( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[151] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[152] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[57] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1805 ) , .Q0(\CPLD_Reg_1/regtable[2][2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3309 ) , .Q1(\CPLD_Reg_1/regtable[2][3] )); SLICE_1473 SLICE_1473( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[150] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[151] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[58] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1821 ) , .Q0(\CPLD_Reg_1/regtable[2][4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3293 ) , .Q1(\CPLD_Reg_1/regtable[2][5] )); SLICE_1474 SLICE_1474( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[149] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[150] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[59] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[2]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1837 ) , .Q0(\CPLD_Reg_1/regtable[2][6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3277 ) , .Q1(\CPLD_Reg_1/regtable[2][7] )); SLICE_1475 SLICE_1475( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[148] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[149] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[60] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1853 ) , .Q0(\freq2_relay[0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3261 ) , .Q1(\CPLD_Reg_1/regtable[3][10] )); SLICE_1476 SLICE_1476( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[147] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[148] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[61] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1869 ) , .Q0(\CPLD_Reg_1/regtable[3][11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3245 ) , .Q1(\CPLD_Reg_1/regtable[3][12] )); SLICE_1477 SLICE_1477( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[146] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[147] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[62] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] ) , .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1885 ) , .Q0(\CPLD_Reg_1/regtable[3][13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3229 ) , .Q1(\CPLD_Reg_1/regtable[3][14] )); SLICE_1478 SLICE_1478( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[145] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[146] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[63] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1901 ) , .Q0(\CPLD_Reg_1/regtable[3][15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3213 ) , .Q1(\CPLD_Reg_1/regtable[3][16] )); SLICE_1479 SLICE_1479( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[144] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[145] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[64] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] ) , .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1917 ) , .Q0(\CPLD_Reg_1/regtable[3][17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3197 ) , .Q1(\CPLD_Reg_1/regtable[3][18] )); SLICE_1480 SLICE_1480( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[143] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[144] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[65] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1933 ) , .Q0(\CPLD_Reg_1/regtable[3][19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3181 ) , .Q1(\CPLD_Reg_1/regtable[3][1] )); SLICE_1481 SLICE_1481( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[142] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[143] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[66] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1949 ) , .Q0(\CPLD_Reg_1/regtable[3][20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3165 ) , .Q1(\CPLD_Reg_1/regtable[3][21] )); SLICE_1482 SLICE_1482( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[141] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[142] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[67] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] ) , .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1965 ) , .Q0(\CPLD_Reg_1/regtable[3][22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3149 ) , .Q1(\CPLD_Reg_1/regtable[3][23] )); SLICE_1483 SLICE_1483( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[140] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[141] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[68] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[69] ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1981 ) , .Q0(\CPLD_Reg_1/regtable[3][2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3133 ) , .Q1(\CPLD_Reg_1/regtable[3][3] )); SLICE_1484 SLICE_1484( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[139] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[140] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[69] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_1997 ) , .Q0(\CPLD_Reg_1/regtable[3][4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3117 ) , .Q1(\CPLD_Reg_1/regtable[3][5] )); SLICE_1485 SLICE_1485( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[138] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[139] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[70] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] ) , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[3]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2013 ) , .Q0(\CPLD_Reg_1/regtable[3][8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3101 ) , .Q1(\CPLD_Reg_1/regtable[3][9] )); SLICE_1486 SLICE_1486( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[137] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[71] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2029 ) , .Q0(\freq3_relay[0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3085 ) , .Q1(\CPLD_Reg_1/regtable[4][10] )); SLICE_1487 SLICE_1487( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[136] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[72] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2045 ) , .Q0(\CPLD_Reg_1/regtable[4][11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3069 ) , .Q1(\CPLD_Reg_1/regtable[4][12] )); SLICE_1488 SLICE_1488( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[135] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[73] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] ) , .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2061 ) , .Q0(\CPLD_Reg_1/regtable[4][13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3053 ) , .Q1(\CPLD_Reg_1/regtable[4][14] )); SLICE_1489 SLICE_1489( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[134] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[74] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2077 ) , .Q0(\CPLD_Reg_1/regtable[4][15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3037 ) , .Q1(\CPLD_Reg_1/regtable[4][16] )); SLICE_1490 SLICE_1490( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[133] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[75] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] ) , .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2093 ) , .Q0(\CPLD_Reg_1/regtable[4][17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3021 ) , .Q1(\CPLD_Reg_1/regtable[4][18] )); SLICE_1491 SLICE_1491( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[132] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[76] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2109 ) , .Q0(\CPLD_Reg_1/regtable[4][19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_3005 ) , .Q1(\CPLD_Reg_1/regtable[4][1] )); SLICE_1492 SLICE_1492( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[131] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[77] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2125 ) , .Q0(\CPLD_Reg_1/regtable[4][20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2989 ) , .Q1(\CPLD_Reg_1/regtable[4][21] )); SLICE_1493 SLICE_1493( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[130] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[78] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] ) , .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2141 ) , .Q0(\CPLD_Reg_1/regtable[4][22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2973 ) , .Q1(\CPLD_Reg_1/regtable[4][23] )); SLICE_1494 SLICE_1494( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[129] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[79] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2157 ) , .Q0(\CPLD_Reg_1/regtable[4][2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2957 ) , .Q1(\CPLD_Reg_1/regtable[4][3] )); SLICE_1495 SLICE_1495( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[128] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[80] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2173 ) , .Q0(\CPLD_Reg_1/regtable[4][6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2941 ) , .Q1(\CPLD_Reg_1/regtable[4][7] )); SLICE_1496 SLICE_1496( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[127] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[81] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] ) , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[4]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2189 ) , .Q0(\CPLD_Reg_1/regtable[4][8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2925 ) , .Q1(\CPLD_Reg_1/regtable[4][9] )); SLICE_1497 SLICE_1497( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[126] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[82] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2205 ) , .Q0(\freq4_relay[0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2909 ) , .Q1(\CPLD_Reg_1/regtable[5][10] )); SLICE_1498 SLICE_1498( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[125] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[83] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2221 ) , .Q0(\CPLD_Reg_1/regtable[5][11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2893 ) , .Q1(\freq4_relay[12] )); SLICE_1499 SLICE_1499( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[124] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[84] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] ) , .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2237 ) , .Q0(\freq4_relay[13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2877 ) , .Q1(\freq4_relay[14] )); SLICE_1500 SLICE_1500( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[123] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[85] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2253 ) , .Q0(\freq4_relay[15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2861 ) , .Q1(\freq4_relay[16] )); SLICE_1501 SLICE_1501( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[122] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[86] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] ) , .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2269 ) , .Q0(\freq4_relay[17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2845 ) , .Q1(\CPLD_Reg_1/regtable[5][18] )); SLICE_1502 SLICE_1502( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[121] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[87] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2285 ) , .Q0(\CPLD_Reg_1/regtable[5][19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2829 ) , .Q1(\CPLD_Reg_1/regtable[5][1] )); SLICE_1503 SLICE_1503( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[120] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[88] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2301 ) , .Q0(\CPLD_Reg_1/regtable[5][20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2813 ) , .Q1(\CPLD_Reg_1/regtable[5][21] )); SLICE_1504 SLICE_1504( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[119] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[89] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] ) , .M1(\w_data[23] ), .M0(\w_data[22] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2317 ) , .Q0(\CPLD_Reg_1/regtable[5][22] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2797 ) , .Q1(\CPLD_Reg_1/regtable[5][23] )); SLICE_1505 SLICE_1505( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[118] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[90] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] ) , .M1(\w_data[5] ), .M0(\w_data[4] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2333 ) , .Q0(\CPLD_Reg_1/regtable[5][4] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2781 ) , .Q1(\CPLD_Reg_1/regtable[5][5] )); SLICE_1506 SLICE_1506( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[117] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[91] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2349 ) , .Q0(\CPLD_Reg_1/regtable[5][6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2765 ) , .Q1(\CPLD_Reg_1/regtable[5][7] )); SLICE_1507 SLICE_1507( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[116] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[92] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] ) , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[5]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2365 ) , .Q0(\CPLD_Reg_1/regtable[5][8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2749 ) , .Q1(\CPLD_Reg_1/regtable[5][9] )); SLICE_1508 SLICE_1508( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[115] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[93] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2381 ) , .Q0(\DC_Con1[0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2733 ) , .Q1(\DC_Con1[10] )); SLICE_1509 SLICE_1509( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[114] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[94] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2397 ) , .Q0(\DC_Con1[11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2717 ) , .Q1(\DC_Con1[12] )); SLICE_1510 SLICE_1510( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[113] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[95] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] ) , .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2413 ) , .Q0(\DC_Con1[13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2701 ) , .Q1(\DC_Con1[14] )); SLICE_1511 SLICE_1511( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[112] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[96] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] ) , .M1(\w_data[16] ), .M0(\w_data[15] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2429 ) , .Q0(\DC_Con1[15] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2685 ) , .Q1(\DC_Con1[16] )); SLICE_1512 SLICE_1512( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[111] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[97] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] ) , .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2445 ) , .Q0(\DC_Con1[17] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2669 ) , .Q1(\DC_Con1[18] )); SLICE_1513 SLICE_1513( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[110] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[98] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2461 ) , .Q0(\DC_Con1[19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2653 ) , .Q1(\DC_Con1[1] )); SLICE_1514 SLICE_1514( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[109] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[99] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] ) , .M1(\w_data[21] ), .M0(\w_data[20] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2477 ) , .Q0(\DC_Con1[20] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2637 ) , .Q1(\DC_Con1[21] )); SLICE_1515 SLICE_1515( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[108] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[100] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2493 ) , .Q0(\CPLD_Reg_1/regtable[12][6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2621 ) , .Q1(\CPLD_Reg_1/regtable[12][7] )); SLICE_1516 SLICE_1516( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[107] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[101] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] ) , .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[12]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2509 ) , .Q0(\CPLD_Reg_1/regtable[12][8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2605 ) , .Q1(\CPLD_Reg_1/regtable[12][9] )); SLICE_1517 SLICE_1517( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[102] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] ) , .M1(\w_data[10] ), .M0(\w_data[0] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2525 ) , .Q0(\CPLD_Reg_1/regtable[13][0] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2589 ) , .Q1(\CPLD_Reg_1/regtable[13][10] )); SLICE_1518 SLICE_1518( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[103] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] ) , .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[13]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2541 ) , .Q0(\CPLD_Reg_1/regtable[13][11] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2573 ) , .Q1(\CPLD_Reg_1/regtable[13][12] )); SLICE_1519 SLICE_1519( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ) , .B1(jtaghub16_ip_enable0), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d3 ) , .A0(jtaghub16_ip_enable0), .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa ) , .Q0(\CPLD_Reg_1/regtable[10][8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_m_1 ) , .Q1(\CPLD_Reg_1/regtable[10][9] )); SLICE_1520 SLICE_1520( .B1(jtaghub16_jshift), .A1(\xo2chub/bit_count ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ) , .A0(jtaghub16_jshift), .M1(\w_data[18] ), .M0(\w_data[17] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc19_i_0 ) , .Q0(\DC_Con2[17] ), .F1(\xo2chub/bit_count15 ), .Q1(\DC_Con2[18] )); SLICE_1521 SLICE_1521( .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr_15 ), .M1(\w_data[9] ), .M0(\w_data[8] ), .CE(\CPLD_Reg_1/regtable[7]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jtdo_first_bit ) , .Q0(\DC_Con2[8] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en_RNIGKQS ) , .Q1(\DC_Con2[9] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1522 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1522 ( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_1_a2_2_0 ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_843 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[5] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_1_iv_0_i_0_0_a2_0_0 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1523 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1523 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[9] ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[0] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[3] ), .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] ), .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[1] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_792 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/addr[2] )); SLICE_1524 SLICE_1524( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] ) , .M1(\w_data[3] ), .M0(\w_data[2] ), .CE(\CPLD_Reg_1/regtable[8]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_0 ) , .Q0(\DC_Con3[2] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_capture18_0_359_0_0_o2_7 ) , .Q1(\DC_Con3[3] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1525 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/SLICE_1525 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[106] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[105] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[105] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[106] ) ); SLICE_1526 SLICE_1526( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[104] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tr_bit_0 ), .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] ) , .M1(\w_data[7] ), .M0(\w_data[6] ), .CE(\CPLD_Reg_1/regtable[6]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 ) , .Q0(\DC_Con1[6] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_2557 ) , .Q1(\DC_Con1[7] )); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1527 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1527 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[159] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[158] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[158] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_10 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[159] ) ); RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1528 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/SLICE_1528 ( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] ) , .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] ) , .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[160] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[15] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_9 ) , .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[15] ) , .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_8 ) , .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[160] ) ); CPLD_Con_1_SLICE_1529 \CPLD_Con_1/SLICE_1529 ( .B1(\CPLD_Con_1/N_70 ), .A1(\DC_Con3[17] ), .B0(\DC_Con3[21] ), .A0(\CPLD_Con_1/un65_RC_RLSel_c4_i ), .F0(\CPLD_Con_1/un65_RC_RLSel_axbxc4 ), .F1(\CPLD_Con_1/N_80 )); SLICE_1530 SLICE_1530( .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un22_jtdo ) , .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/wr_din[0] ), .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_first_bit_1_sqmuxa ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/capture_dr ), .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4 ) , .M1(\w_data[1] ), .M0(\w_data[19] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(jtaghub16_er2_tdo0), .Q0(\CPLD_Reg_1/regtable[10][19] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_m[0] ) , .Q1(\CPLD_Reg_1/regtable[10][1] )); CPLD_Con_1_SLICE_1531 \CPLD_Con_1/SLICE_1531 ( .B1(\DC_Con3[9] ), .A1(\DC_Con3[8] ), .C0(\CPLD_Con_1/dc_slot_flag_2_rep1 ), .B0(\CPLD_Con_1/dc_slot_flag_1_rep1 ), .A0(\CPLD_Con_1/dc_slot_flag_0_rep1 ), .M1(\DC_Con2[0] ), .M0(\DC_Con1[0] ), .CE(\CPLD_Con_1/dc_slot_flag_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Con_1/g2 ), .Q0(\CPLD_Con_1/dc_slot_flag[0] ), .F1(\CPLD_Con_1/N_218 ), .Q1(\CPLD_Con_1/dc_slot_flag[1] )); CPLD_Reg_1_SLICE_1532 \CPLD_Reg_1/SLICE_1532 ( .D1(\w_data[0] ), .C1(\CPLD_Reg_1/un34_regtable_1[1] ), .B1(\CPLD_Reg_1/un9_0_a3_0 ), .A1(\CPLD_Reg_1/state[0] ), .B0(\reg_addr_fast[1] ), .A0(\reg_addr_fast[0] ), .M1(\w_data[12] ), .M0(\w_data[11] ), .CE(\CPLD_Reg_1/regtable[10]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\CPLD_Reg_1/un34_regtable_2[1] ), .Q0(\CPLD_Reg_1/regtable[10][11] ), .F1(\CPLD_Reg_1/state_ns_0_a4_0_3[1] ), .Q1(\CPLD_Reg_1/regtable[10][12] )); SLICE_1533 SLICE_1533( .B1(\DC_Con2[3] ), .A1(\DC_Con2[1] ), .B0(\DC_Con2[8] ), .A0(\DC_Con2[7] ), .M1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[48] ) , .M0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[47] ) , .CE(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ) , .CLK(jtaghub16_jtck), .F0(\CPLD_Con_1/N_382 ), .Q0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[47] ) , .F1(\CPLD_Con_1/DPS_m3_0_a2_1 ), .Q1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trace_dout[48] ) ); CPLD_Con_1_SLICE_1534 \CPLD_Con_1/SLICE_1534 ( .C1(\CPLD_Con_1/N_189_2 ), .B1(\DC_Con4[22] ), .A1(\CPLD_Con_1/dc_slot_flag[2] ), .B0(\DC_Con3[7] ), .A0(\DC_Con3[1] ), .F0(\CPLD_Con_1/un4_DPS_FS_3_c8_a0_2 ), .F1(\CPLD_Con_1/N_193 )); SLICE_1535 SLICE_1535( .C1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] ) , .B1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ) , .A1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ) , .C0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ) , .B0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] ) , .A0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/rd_dout_tm[5] ) , .M1(\w_data[14] ), .M0(\w_data[13] ), .CE(\CPLD_Reg_1/regtable[11]_1_sqmuxa ), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .F0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/N_529 ) , .Q0(\CPLD_Reg_1/regtable[11][13] ), .F1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_1[0] ) , .Q1(\CPLD_Reg_1/regtable[11][14] )); o_miso o_miso_I( .IOLDO(miso_shift31), .PADDT(\BUS_Con_1.cs_sync_rep0[1] ), .o_miso(o_miso)); o_miso_MGIOL o_miso_MGIOL( .IOLDO(miso_shift31), .OPOS(N_694_rst), .CE(N_694_en), .CLK(i_sys_clk_c)); o_wready o_wready_I( .PADDO(o_wready_c), .o_wready(o_wready)); i_sys_clk i_sys_clk_I( .PADDI(i_sys_clk_c), .i_sys_clk(i_sys_clk)); o_DPS_S_4_15_ \o_DPS_S_4[15]_I ( .PADDO(\DPS_FS_4[15] ), .oDPSS415(o_DPS_S_4[15])); o_DPS_S_4_14_ \o_DPS_S_4[14]_I ( .PADDO(\DPS_FS_4[14] ), .oDPSS414(o_DPS_S_4[14])); o_DPS_S_4_13_ \o_DPS_S_4[13]_I ( .PADDO(\DPS_FS_4[13] ), .oDPSS413(o_DPS_S_4[13])); o_DPS_S_4_12_ \o_DPS_S_4[12]_I ( .PADDO(\DPS_FS_4[12] ), .oDPSS412(o_DPS_S_4[12])); o_DPS_S_4_11_ \o_DPS_S_4[11]_I ( .PADDO(\DPS_FS_4[11] ), .oDPSS411(o_DPS_S_4[11])); o_DPS_S_4_10_ \o_DPS_S_4[10]_I ( .PADDO(\DPS_FS_4[10] ), .oDPSS410(o_DPS_S_4[10])); o_DPS_S_4_9_ \o_DPS_S_4[9]_I ( .PADDO(\DPS_FS_4[9] ), .oDPSS49(o_DPS_S_4[9])); o_DPS_S_4_8_ \o_DPS_S_4[8]_I ( .PADDO(\DPS_FS_4[8] ), .oDPSS48(o_DPS_S_4[8])); o_DPS_S_4_7_ \o_DPS_S_4[7]_I ( .PADDO(\DPS_FS_4[7] ), .oDPSS47(o_DPS_S_4[7])); o_DPS_S_4_6_ \o_DPS_S_4[6]_I ( .PADDO(\DPS_FS_4[6] ), .oDPSS46(o_DPS_S_4[6])); o_DPS_S_4_5_ \o_DPS_S_4[5]_I ( .PADDO(\DPS_FS_4[5] ), .oDPSS45(o_DPS_S_4[5])); o_DPS_S_4_4_ \o_DPS_S_4[4]_I ( .PADDO(\DPS_FS_4[4] ), .oDPSS44(o_DPS_S_4[4])); o_DPS_S_4_3_ \o_DPS_S_4[3]_I ( .PADDO(\DPS_FS_4[3] ), .oDPSS43(o_DPS_S_4[3])); o_DPS_S_4_2_ \o_DPS_S_4[2]_I ( .PADDO(\DPS_FS_4[2] ), .oDPSS42(o_DPS_S_4[2])); o_DPS_S_4_1_ \o_DPS_S_4[1]_I ( .PADDO(\DPS_FS_4[1] ), .oDPSS41(o_DPS_S_4[1])); o_DPS_S_4_0_ \o_DPS_S_4[0]_I ( .PADDO(\DPS_FS_4[0] ), .oDPSS40(o_DPS_S_4[0])); o_DPS_F_4_15_ \o_DPS_F_4[15]_I ( .PADDO(\DPS_FS_4[15] ), .oDPSF415(o_DPS_F_4[15])); o_DPS_F_4_14_ \o_DPS_F_4[14]_I ( .PADDO(\DPS_FS_4[14] ), .oDPSF414(o_DPS_F_4[14])); o_DPS_F_4_13_ \o_DPS_F_4[13]_I ( .PADDO(\DPS_FS_4[13] ), .oDPSF413(o_DPS_F_4[13])); o_DPS_F_4_12_ \o_DPS_F_4[12]_I ( .PADDO(\DPS_FS_4[12] ), .oDPSF412(o_DPS_F_4[12])); o_DPS_F_4_11_ \o_DPS_F_4[11]_I ( .PADDO(\DPS_FS_4[11] ), .oDPSF411(o_DPS_F_4[11])); o_DPS_F_4_10_ \o_DPS_F_4[10]_I ( .PADDO(\DPS_FS_4[10] ), .oDPSF410(o_DPS_F_4[10])); o_DPS_F_4_9_ \o_DPS_F_4[9]_I ( .PADDO(\DPS_FS_4[9] ), .oDPSF49(o_DPS_F_4[9])); o_DPS_F_4_8_ \o_DPS_F_4[8]_I ( .PADDO(\DPS_FS_4[8] ), .oDPSF48(o_DPS_F_4[8])); o_DPS_F_4_7_ \o_DPS_F_4[7]_I ( .PADDO(\DPS_FS_4[7] ), .oDPSF47(o_DPS_F_4[7])); o_DPS_F_4_6_ \o_DPS_F_4[6]_I ( .PADDO(\DPS_FS_4[6] ), .oDPSF46(o_DPS_F_4[6])); o_DPS_F_4_5_ \o_DPS_F_4[5]_I ( .PADDO(\DPS_FS_4[5] ), .oDPSF45(o_DPS_F_4[5])); o_DPS_F_4_4_ \o_DPS_F_4[4]_I ( .PADDO(\DPS_FS_4[4] ), .oDPSF44(o_DPS_F_4[4])); o_DPS_F_4_3_ \o_DPS_F_4[3]_I ( .PADDO(\DPS_FS_4[3] ), .oDPSF43(o_DPS_F_4[3])); o_DPS_F_4_2_ \o_DPS_F_4[2]_I ( .PADDO(\DPS_FS_4[2] ), .oDPSF42(o_DPS_F_4[2])); o_DPS_F_4_1_ \o_DPS_F_4[1]_I ( .PADDO(\DPS_FS_4[1] ), .oDPSF41(o_DPS_F_4[1])); o_DPS_F_4_0_ \o_DPS_F_4[0]_I ( .PADDO(\DPS_FS_4[0] ), .oDPSF40(o_DPS_F_4[0])); o_DPS_S_3_15_ \o_DPS_S_3[15]_I ( .PADDO(\DPS_FS_3[15] ), .oDPSS315(o_DPS_S_3[15])); o_DPS_S_3_14_ \o_DPS_S_3[14]_I ( .PADDO(\DPS_FS_3[14] ), .oDPSS314(o_DPS_S_3[14])); o_DPS_S_3_13_ \o_DPS_S_3[13]_I ( .PADDO(\DPS_FS_3[13] ), .oDPSS313(o_DPS_S_3[13])); o_DPS_S_3_12_ \o_DPS_S_3[12]_I ( .PADDO(\DPS_FS_3[12] ), .oDPSS312(o_DPS_S_3[12])); o_DPS_S_3_11_ \o_DPS_S_3[11]_I ( .PADDO(\DPS_FS_3[11] ), .oDPSS311(o_DPS_S_3[11])); o_DPS_S_3_10_ \o_DPS_S_3[10]_I ( .PADDO(\DPS_FS_3[10] ), .oDPSS310(o_DPS_S_3[10])); o_DPS_S_3_9_ \o_DPS_S_3[9]_I ( .PADDO(\DPS_FS_3[9] ), .oDPSS39(o_DPS_S_3[9])); o_DPS_S_3_8_ \o_DPS_S_3[8]_I ( .PADDO(\DPS_FS_3[8] ), .oDPSS38(o_DPS_S_3[8])); o_DPS_S_3_7_ \o_DPS_S_3[7]_I ( .PADDO(\DPS_FS_3[7] ), .oDPSS37(o_DPS_S_3[7])); o_DPS_S_3_6_ \o_DPS_S_3[6]_I ( .PADDO(\DPS_FS_3[6] ), .oDPSS36(o_DPS_S_3[6])); o_DPS_S_3_5_ \o_DPS_S_3[5]_I ( .PADDO(\DPS_FS_3[5] ), .oDPSS35(o_DPS_S_3[5])); o_DPS_S_3_4_ \o_DPS_S_3[4]_I ( .PADDO(\DPS_FS_3[4] ), .oDPSS34(o_DPS_S_3[4])); o_DPS_S_3_3_ \o_DPS_S_3[3]_I ( .PADDO(\DPS_FS_3[3] ), .oDPSS33(o_DPS_S_3[3])); o_DPS_S_3_2_ \o_DPS_S_3[2]_I ( .PADDO(\DPS_FS_3[2] ), .oDPSS32(o_DPS_S_3[2])); o_DPS_S_3_1_ \o_DPS_S_3[1]_I ( .PADDO(\DPS_FS_3[1] ), .oDPSS31(o_DPS_S_3[1])); o_DPS_S_3_0_ \o_DPS_S_3[0]_I ( .PADDO(\DPS_FS_3[0] ), .oDPSS30(o_DPS_S_3[0])); o_DPS_F_3_15_ \o_DPS_F_3[15]_I ( .PADDO(\DPS_FS_3[15] ), .oDPSF315(o_DPS_F_3[15])); o_DPS_F_3_14_ \o_DPS_F_3[14]_I ( .PADDO(\DPS_FS_3[14] ), .oDPSF314(o_DPS_F_3[14])); o_DPS_F_3_13_ \o_DPS_F_3[13]_I ( .PADDO(\DPS_FS_3[13] ), .oDPSF313(o_DPS_F_3[13])); o_DPS_F_3_12_ \o_DPS_F_3[12]_I ( .PADDO(\DPS_FS_3[12] ), .oDPSF312(o_DPS_F_3[12])); o_DPS_F_3_11_ \o_DPS_F_3[11]_I ( .PADDO(\DPS_FS_3[11] ), .oDPSF311(o_DPS_F_3[11])); o_DPS_F_3_10_ \o_DPS_F_3[10]_I ( .PADDO(\DPS_FS_3[10] ), .oDPSF310(o_DPS_F_3[10])); o_DPS_F_3_9_ \o_DPS_F_3[9]_I ( .PADDO(\DPS_FS_3[9] ), .oDPSF39(o_DPS_F_3[9])); o_DPS_F_3_8_ \o_DPS_F_3[8]_I ( .PADDO(\DPS_FS_3[8] ), .oDPSF38(o_DPS_F_3[8])); o_DPS_F_3_7_ \o_DPS_F_3[7]_I ( .PADDO(\DPS_FS_3[7] ), .oDPSF37(o_DPS_F_3[7])); o_DPS_F_3_6_ \o_DPS_F_3[6]_I ( .PADDO(\DPS_FS_3[6] ), .oDPSF36(o_DPS_F_3[6])); o_DPS_F_3_5_ \o_DPS_F_3[5]_I ( .PADDO(\DPS_FS_3[5] ), .oDPSF35(o_DPS_F_3[5])); o_DPS_F_3_4_ \o_DPS_F_3[4]_I ( .PADDO(\DPS_FS_3[4] ), .oDPSF34(o_DPS_F_3[4])); o_DPS_F_3_3_ \o_DPS_F_3[3]_I ( .PADDO(\DPS_FS_3[3] ), .oDPSF33(o_DPS_F_3[3])); o_DPS_F_3_2_ \o_DPS_F_3[2]_I ( .PADDO(\DPS_FS_3[2] ), .oDPSF32(o_DPS_F_3[2])); o_DPS_F_3_1_ \o_DPS_F_3[1]_I ( .PADDO(\DPS_FS_3[1] ), .oDPSF31(o_DPS_F_3[1])); o_DPS_F_3_0_ \o_DPS_F_3[0]_I ( .PADDO(\DPS_FS_3[0] ), .oDPSF30(o_DPS_F_3[0])); o_DPS_S_2_15_ \o_DPS_S_2[15]_I ( .PADDO(\DPS_FS_2[15] ), .oDPSS215(o_DPS_S_2[15])); o_DPS_S_2_14_ \o_DPS_S_2[14]_I ( .PADDO(\DPS_FS_2[14] ), .oDPSS214(o_DPS_S_2[14])); o_DPS_S_2_13_ \o_DPS_S_2[13]_I ( .PADDO(\DPS_FS_2[13] ), .oDPSS213(o_DPS_S_2[13])); o_DPS_S_2_12_ \o_DPS_S_2[12]_I ( .PADDO(\DPS_FS_2[12] ), .oDPSS212(o_DPS_S_2[12])); o_DPS_S_2_11_ \o_DPS_S_2[11]_I ( .PADDO(\DPS_FS_2[11] ), .oDPSS211(o_DPS_S_2[11])); o_DPS_S_2_10_ \o_DPS_S_2[10]_I ( .PADDO(\DPS_FS_2[10] ), .oDPSS210(o_DPS_S_2[10])); o_DPS_S_2_9_ \o_DPS_S_2[9]_I ( .PADDO(\DPS_FS_2[9] ), .oDPSS29(o_DPS_S_2[9])); o_DPS_S_2_8_ \o_DPS_S_2[8]_I ( .PADDO(\DPS_FS_2[8] ), .oDPSS28(o_DPS_S_2[8])); o_DPS_S_2_7_ \o_DPS_S_2[7]_I ( .PADDO(\DPS_FS_2[7] ), .oDPSS27(o_DPS_S_2[7])); o_DPS_S_2_6_ \o_DPS_S_2[6]_I ( .PADDO(\DPS_FS_2[6] ), .oDPSS26(o_DPS_S_2[6])); o_DPS_S_2_5_ \o_DPS_S_2[5]_I ( .PADDO(\DPS_FS_2[5] ), .oDPSS25(o_DPS_S_2[5])); o_DPS_S_2_4_ \o_DPS_S_2[4]_I ( .PADDO(\DPS_FS_2[4] ), .oDPSS24(o_DPS_S_2[4])); o_DPS_S_2_3_ \o_DPS_S_2[3]_I ( .PADDO(\DPS_FS_2[3] ), .oDPSS23(o_DPS_S_2[3])); o_DPS_S_2_2_ \o_DPS_S_2[2]_I ( .PADDO(\DPS_FS_2[2] ), .oDPSS22(o_DPS_S_2[2])); o_DPS_S_2_1_ \o_DPS_S_2[1]_I ( .PADDO(\DPS_FS_2[1] ), .oDPSS21(o_DPS_S_2[1])); o_DPS_S_2_0_ \o_DPS_S_2[0]_I ( .PADDO(\DPS_FS_2[0] ), .oDPSS20(o_DPS_S_2[0])); o_DPS_F_2_15_ \o_DPS_F_2[15]_I ( .PADDO(\DPS_FS_2[15] ), .oDPSF215(o_DPS_F_2[15])); o_DPS_F_2_14_ \o_DPS_F_2[14]_I ( .PADDO(\DPS_FS_2[14] ), .oDPSF214(o_DPS_F_2[14])); o_DPS_F_2_13_ \o_DPS_F_2[13]_I ( .PADDO(\DPS_FS_2[13] ), .oDPSF213(o_DPS_F_2[13])); o_DPS_F_2_12_ \o_DPS_F_2[12]_I ( .PADDO(\DPS_FS_2[12] ), .oDPSF212(o_DPS_F_2[12])); o_DPS_F_2_11_ \o_DPS_F_2[11]_I ( .PADDO(\DPS_FS_2[11] ), .oDPSF211(o_DPS_F_2[11])); o_DPS_F_2_10_ \o_DPS_F_2[10]_I ( .PADDO(\DPS_FS_2[10] ), .oDPSF210(o_DPS_F_2[10])); o_DPS_F_2_9_ \o_DPS_F_2[9]_I ( .PADDO(\DPS_FS_2[9] ), .oDPSF29(o_DPS_F_2[9])); o_DPS_F_2_8_ \o_DPS_F_2[8]_I ( .PADDO(\DPS_FS_2[8] ), .oDPSF28(o_DPS_F_2[8])); o_DPS_F_2_7_ \o_DPS_F_2[7]_I ( .PADDO(\DPS_FS_2[7] ), .oDPSF27(o_DPS_F_2[7])); o_DPS_F_2_6_ \o_DPS_F_2[6]_I ( .PADDO(\DPS_FS_2[6] ), .oDPSF26(o_DPS_F_2[6])); o_DPS_F_2_5_ \o_DPS_F_2[5]_I ( .PADDO(\DPS_FS_2[5] ), .oDPSF25(o_DPS_F_2[5])); o_DPS_F_2_4_ \o_DPS_F_2[4]_I ( .PADDO(\DPS_FS_2[4] ), .oDPSF24(o_DPS_F_2[4])); o_DPS_F_2_3_ \o_DPS_F_2[3]_I ( .PADDO(\DPS_FS_2[3] ), .oDPSF23(o_DPS_F_2[3])); o_DPS_F_2_2_ \o_DPS_F_2[2]_I ( .PADDO(\DPS_FS_2[2] ), .oDPSF22(o_DPS_F_2[2])); o_DPS_F_2_1_ \o_DPS_F_2[1]_I ( .PADDO(\DPS_FS_2[1] ), .oDPSF21(o_DPS_F_2[1])); o_DPS_F_2_0_ \o_DPS_F_2[0]_I ( .PADDO(\DPS_FS_2[0] ), .oDPSF20(o_DPS_F_2[0])); o_DPS_S_1_15_ \o_DPS_S_1[15]_I ( .PADDO(\DPS_FS_1[15] ), .oDPSS115(o_DPS_S_1[15])); o_DPS_S_1_14_ \o_DPS_S_1[14]_I ( .PADDO(\DPS_FS_1[14] ), .oDPSS114(o_DPS_S_1[14])); o_DPS_S_1_13_ \o_DPS_S_1[13]_I ( .PADDO(\DPS_FS_1[13] ), .oDPSS113(o_DPS_S_1[13])); o_DPS_S_1_12_ \o_DPS_S_1[12]_I ( .PADDO(\DPS_FS_1[12] ), .oDPSS112(o_DPS_S_1[12])); o_DPS_S_1_11_ \o_DPS_S_1[11]_I ( .PADDO(\DPS_FS_1[11] ), .oDPSS111(o_DPS_S_1[11])); o_DPS_S_1_10_ \o_DPS_S_1[10]_I ( .PADDO(\DPS_FS_1[10] ), .oDPSS110(o_DPS_S_1[10])); o_DPS_S_1_9_ \o_DPS_S_1[9]_I ( .PADDO(\DPS_FS_1[9] ), .oDPSS19(o_DPS_S_1[9])); o_DPS_S_1_8_ \o_DPS_S_1[8]_I ( .PADDO(\DPS_FS_1[8] ), .oDPSS18(o_DPS_S_1[8])); o_DPS_S_1_7_ \o_DPS_S_1[7]_I ( .PADDO(\DPS_FS_1[7] ), .oDPSS17(o_DPS_S_1[7])); o_DPS_S_1_6_ \o_DPS_S_1[6]_I ( .PADDO(\DPS_FS_1[6] ), .oDPSS16(o_DPS_S_1[6])); o_DPS_S_1_5_ \o_DPS_S_1[5]_I ( .PADDO(\DPS_FS_1[5] ), .oDPSS15(o_DPS_S_1[5])); o_DPS_S_1_4_ \o_DPS_S_1[4]_I ( .PADDO(\DPS_FS_1[4] ), .oDPSS14(o_DPS_S_1[4])); o_DPS_S_1_3_ \o_DPS_S_1[3]_I ( .PADDO(\DPS_FS_1[3] ), .oDPSS13(o_DPS_S_1[3])); o_DPS_S_1_2_ \o_DPS_S_1[2]_I ( .PADDO(\DPS_FS_1[2] ), .oDPSS12(o_DPS_S_1[2])); o_DPS_S_1_1_ \o_DPS_S_1[1]_I ( .PADDO(\DPS_FS_1[1] ), .oDPSS11(o_DPS_S_1[1])); o_DPS_S_1_0_ \o_DPS_S_1[0]_I ( .PADDO(\DPS_FS_1[0] ), .oDPSS10(o_DPS_S_1[0])); o_DPS_F_1_15_ \o_DPS_F_1[15]_I ( .PADDO(\DPS_FS_1[15] ), .oDPSF115(o_DPS_F_1[15])); o_DPS_F_1_14_ \o_DPS_F_1[14]_I ( .PADDO(\DPS_FS_1[14] ), .oDPSF114(o_DPS_F_1[14])); o_DPS_F_1_13_ \o_DPS_F_1[13]_I ( .PADDO(\DPS_FS_1[13] ), .oDPSF113(o_DPS_F_1[13])); o_DPS_F_1_12_ \o_DPS_F_1[12]_I ( .PADDO(\DPS_FS_1[12] ), .oDPSF112(o_DPS_F_1[12])); o_DPS_F_1_11_ \o_DPS_F_1[11]_I ( .PADDO(\DPS_FS_1[11] ), .oDPSF111(o_DPS_F_1[11])); o_DPS_F_1_10_ \o_DPS_F_1[10]_I ( .PADDO(\DPS_FS_1[10] ), .oDPSF110(o_DPS_F_1[10])); o_DPS_F_1_9_ \o_DPS_F_1[9]_I ( .PADDO(\DPS_FS_1[9] ), .oDPSF19(o_DPS_F_1[9])); o_DPS_F_1_8_ \o_DPS_F_1[8]_I ( .PADDO(\DPS_FS_1[8] ), .oDPSF18(o_DPS_F_1[8])); o_DPS_F_1_7_ \o_DPS_F_1[7]_I ( .PADDO(\DPS_FS_1[7] ), .oDPSF17(o_DPS_F_1[7])); o_DPS_F_1_6_ \o_DPS_F_1[6]_I ( .PADDO(\DPS_FS_1[6] ), .oDPSF16(o_DPS_F_1[6])); o_DPS_F_1_5_ \o_DPS_F_1[5]_I ( .PADDO(\DPS_FS_1[5] ), .oDPSF15(o_DPS_F_1[5])); o_DPS_F_1_4_ \o_DPS_F_1[4]_I ( .PADDO(\DPS_FS_1[4] ), .oDPSF14(o_DPS_F_1[4])); o_DPS_F_1_3_ \o_DPS_F_1[3]_I ( .PADDO(\DPS_FS_1[3] ), .oDPSF13(o_DPS_F_1[3])); o_DPS_F_1_2_ \o_DPS_F_1[2]_I ( .PADDO(\DPS_FS_1[2] ), .oDPSF12(o_DPS_F_1[2])); o_DPS_F_1_1_ \o_DPS_F_1[1]_I ( .PADDO(\DPS_FS_1[1] ), .oDPSF11(o_DPS_F_1[1])); o_DPS_F_1_0_ \o_DPS_F_1[0]_I ( .PADDO(\DPS_FS_1[0] ), .oDPSF10(o_DPS_F_1[0])); o_PMU_OC_4_15_ \o_PMU_OC_4[15]_I ( .IOLDO(\o_PMU_OC_4_c[15] ), .oPMUOC415(o_PMU_OC_4[15])); o_PMU_OC_4_15__MGIOL \o_PMU_OC_4[15]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[15] ), .OPOS(\CPLD_Con_1.N_742 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_4_14_ \o_PMU_OC_4[14]_I ( .IOLDO(\o_PMU_OC_4_c[14] ), .oPMUOC414(o_PMU_OC_4[14])); o_PMU_OC_4_14__MGIOL \o_PMU_OC_4[14]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[14] ), .OPOS(N_438), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA ), .CLK(i_sys_clk_c)); o_PMU_OC_4_13_ \o_PMU_OC_4[13]_I ( .IOLDO(\o_PMU_OC_4_c[13] ), .oPMUOC413(o_PMU_OC_4[13])); o_PMU_OC_4_13__MGIOL \o_PMU_OC_4[13]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[13] ), .OPOS(N_438), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B ), .CLK(i_sys_clk_c)); o_PMU_OC_4_12_ \o_PMU_OC_4[12]_I ( .IOLDO(\o_PMU_OC_4_c[12] ), .oPMUOC412(o_PMU_OC_4[12])); o_PMU_OC_4_12__MGIOL \o_PMU_OC_4[12]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[12] ), .OPOS(\CPLD_Con_1.N_706 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_4_11_ \o_PMU_OC_4[11]_I ( .IOLDO(\o_PMU_OC_4_c[11] ), .oPMUOC411(o_PMU_OC_4[11])); o_PMU_OC_4_11__MGIOL \o_PMU_OC_4[11]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[11] ), .OPOS(\CPLD_Con_1.N_694 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_4_10_ \o_PMU_OC_4[10]_I ( .IOLDO(\o_PMU_OC_4_c[10] ), .oPMUOC410(o_PMU_OC_4[10])); o_PMU_OC_4_10__MGIOL \o_PMU_OC_4[10]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[10] ), .OPOS(N_460), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA ), .CLK(i_sys_clk_c)); o_PMU_OC_4_9_ \o_PMU_OC_4[9]_I ( .IOLDO(\o_PMU_OC_4_c[9] ), .oPMUOC49(o_PMU_OC_4[9])); o_PMU_OC_4_9__MGIOL \o_PMU_OC_4[9]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[9] ), .OPOS(N_460), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B ), .CLK(i_sys_clk_c)); o_PMU_OC_4_8_ \o_PMU_OC_4[8]_I ( .IOLDO(\o_PMU_OC_4_c[8] ), .oPMUOC48(o_PMU_OC_4[8])); o_PMU_OC_4_8__MGIOL \o_PMU_OC_4[8]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[8] ), .OPOS(\CPLD_Con_1.N_645 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_4_7_ \o_PMU_OC_4[7]_I ( .IOLDO(\o_PMU_OC_4_c[7] ), .oPMUOC47(o_PMU_OC_4[7])); o_PMU_OC_4_7__MGIOL \o_PMU_OC_4[7]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[7] ), .OPOS(\CPLD_Con_1.N_644 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_4_6_ \o_PMU_OC_4[6]_I ( .IOLDO(\o_PMU_OC_4_c[6] ), .oPMUOC46(o_PMU_OC_4[6])); o_PMU_OC_4_6__MGIOL \o_PMU_OC_4[6]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[6] ), .OPOS(N_128), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA ), .CLK(i_sys_clk_c)); o_PMU_OC_4_5_ \o_PMU_OC_4[5]_I ( .IOLDO(\o_PMU_OC_4_c[5] ), .oPMUOC45(o_PMU_OC_4[5])); o_PMU_OC_4_5__MGIOL \o_PMU_OC_4[5]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[5] ), .OPOS(N_128_rep1), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B ), .CLK(i_sys_clk_c)); o_PMU_OC_4_4_ \o_PMU_OC_4[4]_I ( .IOLDO(\o_PMU_OC_4_c[4] ), .oPMUOC44(o_PMU_OC_4[4])); o_PMU_OC_4_4__MGIOL \o_PMU_OC_4[4]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[4] ), .OPOS(\CPLD_Con_1.N_608 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_4_3_ \o_PMU_OC_4[3]_I ( .IOLDO(\o_PMU_OC_4_c[3] ), .oPMUOC43(o_PMU_OC_4[3])); o_PMU_OC_4_3__MGIOL \o_PMU_OC_4[3]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[3] ), .OPOS(\CPLD_Con_1.N_596 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_4_2_ \o_PMU_OC_4[2]_I ( .IOLDO(\o_PMU_OC_4_c[2] ), .oPMUOC42(o_PMU_OC_4[2])); o_PMU_OC_4_2__MGIOL \o_PMU_OC_4[2]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[2] ), .OPOS(N_456), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA ), .CLK(i_sys_clk_c)); o_PMU_OC_4_1_ \o_PMU_OC_4[1]_I ( .IOLDO(\o_PMU_OC_4_c[1] ), .oPMUOC41(o_PMU_OC_4[1])); o_PMU_OC_4_1__MGIOL \o_PMU_OC_4[1]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[1] ), .OPOS(N_456_rep1), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .LSR(\un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B ), .CLK(i_sys_clk_c)); o_PMU_OC_4_0_ \o_PMU_OC_4[0]_I ( .IOLDO(\o_PMU_OC_4_c[0] ), .oPMUOC40(o_PMU_OC_4[0])); o_PMU_OC_4_0__MGIOL \o_PMU_OC_4[0]_MGIOL ( .IOLDO(\o_PMU_OC_4_c[0] ), .OPOS(\CPLD_Con_1.N_548 ), .CE(\CPLD_Con_1.PMU_OC_4_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_15_ \o_PMU_OC_3[15]_I ( .IOLDO(\o_PMU_OC_3_c[15] ), .oPMUOC315(o_PMU_OC_3[15])); o_PMU_OC_3_15__MGIOL \o_PMU_OC_3[15]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[15] ), .OPOS(\CPLD_Con_1.PMU_OC_3_11[23] ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_14_ \o_PMU_OC_3[14]_I ( .IOLDO(\o_PMU_OC_3_c[14] ), .oPMUOC314(o_PMU_OC_3[14])); o_PMU_OC_3_14__MGIOL \o_PMU_OC_3[14]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[14] ), .OPOS(\CPLD_Con_1.PMU_OC_3_11[22] ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_13_ \o_PMU_OC_3[13]_I ( .PADDO(\o_PMU_OC_3_c[13] ), .oPMUOC313(o_PMU_OC_3[13])); o_PMU_OC_3_12_ \o_PMU_OC_3[12]_I ( .IOLDO(\o_PMU_OC_3_c[12] ), .oPMUOC312(o_PMU_OC_3[12])); o_PMU_OC_3_12__MGIOL \o_PMU_OC_3[12]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[12] ), .OPOS(\CPLD_Con_1.PMU_OC_3_11[20] ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_11_ \o_PMU_OC_3[11]_I ( .IOLDO(\o_PMU_OC_3_c[11] ), .oPMUOC311(o_PMU_OC_3[11])); o_PMU_OC_3_11__MGIOL \o_PMU_OC_3[11]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[11] ), .OPOS(\CPLD_Con_1.PMU_OC_3_11[19] ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_10_ \o_PMU_OC_3[10]_I ( .IOLDO(\o_PMU_OC_3_c[10] ), .oPMUOC310(o_PMU_OC_3[10])); o_PMU_OC_3_10__MGIOL \o_PMU_OC_3[10]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[10] ), .OPOS(\CPLD_Con_1.PMU_OC_3_11[18] ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_9_ \o_PMU_OC_3[9]_I ( .PADDO(\o_PMU_OC_3_c[9] ), .oPMUOC39(o_PMU_OC_3[9])); o_PMU_OC_3_8_ \o_PMU_OC_3[8]_I ( .IOLDO(\o_PMU_OC_3_c[8] ), .oPMUOC38(o_PMU_OC_3[8])); o_PMU_OC_3_8__MGIOL \o_PMU_OC_3[8]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[8] ), .OPOS(\CPLD_Con_1.N_532 ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_7_ \o_PMU_OC_3[7]_I ( .IOLDO(\o_PMU_OC_3_c[7] ), .oPMUOC37(o_PMU_OC_3[7])); o_PMU_OC_3_7__MGIOL \o_PMU_OC_3[7]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[7] ), .OPOS(\CPLD_Con_1.PMU_OC_3_11[7] ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_6_ \o_PMU_OC_3[6]_I ( .IOLDO(\o_PMU_OC_3_c[6] ), .oPMUOC36(o_PMU_OC_3[6])); o_PMU_OC_3_6__MGIOL \o_PMU_OC_3[6]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[6] ), .OPOS(\CPLD_Con_1.PMU_OC_3_11[6] ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_5_ \o_PMU_OC_3[5]_I ( .PADDO(\o_PMU_OC_3_c[5] ), .oPMUOC35(o_PMU_OC_3[5])); o_PMU_OC_3_4_ \o_PMU_OC_3[4]_I ( .IOLDO(\o_PMU_OC_3_c[4] ), .oPMUOC34(o_PMU_OC_3[4])); o_PMU_OC_3_4__MGIOL \o_PMU_OC_3[4]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[4] ), .OPOS(\CPLD_Con_1.PMU_OC_3_11[4] ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_3_ \o_PMU_OC_3[3]_I ( .IOLDO(\o_PMU_OC_3_c[3] ), .oPMUOC33(o_PMU_OC_3[3])); o_PMU_OC_3_3__MGIOL \o_PMU_OC_3[3]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[3] ), .OPOS(\CPLD_Con_1.PMU_OC_3_11[3] ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_2_ \o_PMU_OC_3[2]_I ( .IOLDO(\o_PMU_OC_3_c[2] ), .oPMUOC32(o_PMU_OC_3[2])); o_PMU_OC_3_2__MGIOL \o_PMU_OC_3[2]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[2] ), .OPOS(\CPLD_Con_1.PMU_OC_3_11[2] ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_3_1_ \o_PMU_OC_3[1]_I ( .PADDO(\o_PMU_OC_3_c[1] ), .oPMUOC31(o_PMU_OC_3[1])); o_PMU_OC_3_0_ \o_PMU_OC_3[0]_I ( .IOLDO(\o_PMU_OC_3_c[0] ), .oPMUOC30(o_PMU_OC_3[0])); o_PMU_OC_3_0__MGIOL \o_PMU_OC_3[0]_MGIOL ( .IOLDO(\o_PMU_OC_3_c[0] ), .OPOS(\CPLD_Con_1.N_518 ), .CE(\CPLD_Con_1.PMU_OC_3_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_15_ \o_PMU_OC_2[15]_I ( .IOLDO(\o_PMU_OC_2_c[15] ), .oPMUOC215(o_PMU_OC_2[15])); o_PMU_OC_2_15__MGIOL \o_PMU_OC_2[15]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[15] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[23] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_14_ \o_PMU_OC_2[14]_I ( .IOLDO(\o_PMU_OC_2_c[14] ), .oPMUOC214(o_PMU_OC_2[14])); o_PMU_OC_2_14__MGIOL \o_PMU_OC_2[14]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[14] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[22] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_13_ \o_PMU_OC_2[13]_I ( .IOLDO(\o_PMU_OC_2_c[13] ), .oPMUOC213(o_PMU_OC_2[13])); o_PMU_OC_2_13__MGIOL \o_PMU_OC_2[13]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[13] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[21] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_12_ \o_PMU_OC_2[12]_I ( .IOLDO(\o_PMU_OC_2_c[12] ), .oPMUOC212(o_PMU_OC_2[12])); o_PMU_OC_2_12__MGIOL \o_PMU_OC_2[12]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[12] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[20] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_11_ \o_PMU_OC_2[11]_I ( .IOLDO(\o_PMU_OC_2_c[11] ), .oPMUOC211(o_PMU_OC_2[11])); o_PMU_OC_2_11__MGIOL \o_PMU_OC_2[11]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[11] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[19] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_10_ \o_PMU_OC_2[10]_I ( .IOLDO(\o_PMU_OC_2_c[10] ), .oPMUOC210(o_PMU_OC_2[10])); o_PMU_OC_2_10__MGIOL \o_PMU_OC_2[10]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[10] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[18] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_9_ \o_PMU_OC_2[9]_I ( .IOLDO(\o_PMU_OC_2_c[9] ), .oPMUOC29(o_PMU_OC_2[9])); o_PMU_OC_2_9__MGIOL \o_PMU_OC_2[9]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[9] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[17] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_8_ \o_PMU_OC_2[8]_I ( .IOLDO(\o_PMU_OC_2_c[8] ), .oPMUOC28(o_PMU_OC_2[8])); o_PMU_OC_2_8__MGIOL \o_PMU_OC_2[8]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[8] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[16] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_7_ \o_PMU_OC_2[7]_I ( .IOLDO(\o_PMU_OC_2_c[7] ), .oPMUOC27(o_PMU_OC_2[7])); o_PMU_OC_2_7__MGIOL \o_PMU_OC_2[7]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[7] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[7] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_6_ \o_PMU_OC_2[6]_I ( .IOLDO(\o_PMU_OC_2_c[6] ), .oPMUOC26(o_PMU_OC_2[6])); o_PMU_OC_2_6__MGIOL \o_PMU_OC_2[6]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[6] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[6] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_5_ \o_PMU_OC_2[5]_I ( .IOLDO(\o_PMU_OC_2_c[5] ), .oPMUOC25(o_PMU_OC_2[5])); o_PMU_OC_2_5__MGIOL \o_PMU_OC_2[5]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[5] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[5] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_4_ \o_PMU_OC_2[4]_I ( .IOLDO(\o_PMU_OC_2_c[4] ), .oPMUOC24(o_PMU_OC_2[4])); o_PMU_OC_2_4__MGIOL \o_PMU_OC_2[4]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[4] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[4] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_3_ \o_PMU_OC_2[3]_I ( .IOLDO(\o_PMU_OC_2_c[3] ), .oPMUOC23(o_PMU_OC_2[3])); o_PMU_OC_2_3__MGIOL \o_PMU_OC_2[3]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[3] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[3] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_2_ \o_PMU_OC_2[2]_I ( .IOLDO(\o_PMU_OC_2_c[2] ), .oPMUOC22(o_PMU_OC_2[2])); o_PMU_OC_2_2__MGIOL \o_PMU_OC_2[2]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[2] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[2] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_1_ \o_PMU_OC_2[1]_I ( .IOLDO(\o_PMU_OC_2_c[1] ), .oPMUOC21(o_PMU_OC_2[1])); o_PMU_OC_2_1__MGIOL \o_PMU_OC_2[1]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[1] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[1] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_2_0_ \o_PMU_OC_2[0]_I ( .IOLDO(\o_PMU_OC_2_c[0] ), .oPMUOC20(o_PMU_OC_2[0])); o_PMU_OC_2_0__MGIOL \o_PMU_OC_2[0]_MGIOL ( .IOLDO(\o_PMU_OC_2_c[0] ), .OPOS(\CPLD_Con_1.PMU_OC_2_11[0] ), .CE(\CPLD_Con_1.PMU_OC_2_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_1_15_ \o_PMU_OC_1[15]_I ( .IOLDO(\o_PMU_OC_1_c[15] ), .oPMUOC115(o_PMU_OC_1[15])); o_PMU_OC_1_15__MGIOL \o_PMU_OC_1[15]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[15] ), .OPOS(\CPLD_Con_1.PMU_OC_1_11[23] ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), .CLK(i_sys_clk_c)); o_PMU_OC_1_14_ \o_PMU_OC_1[14]_I ( .IOLDO(\o_PMU_OC_1_c[14] ), .oPMUOC114(o_PMU_OC_1[14])); o_PMU_OC_1_14__MGIOL \o_PMU_OC_1[14]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[14] ), .OPOS(\CPLD_Con_1.PMU_OC_1_11[22] ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), .CLK(i_sys_clk_c)); o_PMU_OC_1_13_ \o_PMU_OC_1[13]_I ( .IOLDO(\o_PMU_OC_1_c[13] ), .oPMUOC113(o_PMU_OC_1[13])); o_PMU_OC_1_13__MGIOL \o_PMU_OC_1[13]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[13] ), .OPOS(\CPLD_Con_1.PMU_OC_1_11[21] ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), .CLK(i_sys_clk_c)); o_PMU_OC_1_12_ \o_PMU_OC_1[12]_I ( .IOLDO(\o_PMU_OC_1_c[12] ), .oPMUOC112(o_PMU_OC_1[12])); o_PMU_OC_1_12__MGIOL \o_PMU_OC_1[12]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[12] ), .OPOS(\CPLD_Con_1.PMU_OC_1_11[20] ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), .CLK(i_sys_clk_c)); o_PMU_OC_1_11_ \o_PMU_OC_1[11]_I ( .IOLDO(\o_PMU_OC_1_c[11] ), .oPMUOC111(o_PMU_OC_1[11])); o_PMU_OC_1_11__MGIOL \o_PMU_OC_1[11]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[11] ), .OPOS(\CPLD_Con_1.PMU_OC_1_11[19] ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), .CLK(i_sys_clk_c)); o_PMU_OC_1_10_ \o_PMU_OC_1[10]_I ( .IOLDO(\o_PMU_OC_1_c[10] ), .oPMUOC110(o_PMU_OC_1[10])); o_PMU_OC_1_10__MGIOL \o_PMU_OC_1[10]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[10] ), .OPOS(\CPLD_Con_1.PMU_OC_1_11[18] ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), .CLK(i_sys_clk_c)); o_PMU_OC_1_9_ \o_PMU_OC_1[9]_I ( .IOLDO(\o_PMU_OC_1_c[9] ), .oPMUOC19(o_PMU_OC_1[9])); o_PMU_OC_1_9__MGIOL \o_PMU_OC_1[9]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[9] ), .OPOS(\CPLD_Con_1.PMU_OC_1_11[17] ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(io_RC9_RNID445E), .CLK(i_sys_clk_c)); o_PMU_OC_1_8_ \o_PMU_OC_1[8]_I ( .IOLDO(\o_PMU_OC_1_c[8] ), .oPMUOC18(o_PMU_OC_1[8])); o_PMU_OC_1_8__MGIOL \o_PMU_OC_1[8]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[8] ), .OPOS(\CPLD_Con_1.PMU_OC_1_11[16] ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_PMU_OC_1_7_ \o_PMU_OC_1[7]_I ( .IOLDO(\o_PMU_OC_1_c[7] ), .oPMUOC17(o_PMU_OC_1[7])); o_PMU_OC_1_7__MGIOL \o_PMU_OC_1[7]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[7] ), .OPOS(\CPLD_Con_1.N_104_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); o_PMU_OC_1_6_ \o_PMU_OC_1[6]_I ( .IOLDO(\o_PMU_OC_1_c[6] ), .oPMUOC16(o_PMU_OC_1[6])); o_PMU_OC_1_6__MGIOL \o_PMU_OC_1[6]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[6] ), .OPOS(\CPLD_Con_1.N_103_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); o_PMU_OC_1_5_ \o_PMU_OC_1[5]_I ( .IOLDO(\o_PMU_OC_1_c[5] ), .oPMUOC15(o_PMU_OC_1[5])); o_PMU_OC_1_5__MGIOL \o_PMU_OC_1[5]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[5] ), .OPOS(\CPLD_Con_1.N_102_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); o_PMU_OC_1_4_ \o_PMU_OC_1[4]_I ( .IOLDO(\o_PMU_OC_1_c[4] ), .oPMUOC14(o_PMU_OC_1[4])); o_PMU_OC_1_4__MGIOL \o_PMU_OC_1[4]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[4] ), .OPOS(\CPLD_Con_1.N_101_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); o_PMU_OC_1_3_ \o_PMU_OC_1[3]_I ( .IOLDO(\o_PMU_OC_1_c[3] ), .oPMUOC13(o_PMU_OC_1[3])); o_PMU_OC_1_3__MGIOL \o_PMU_OC_1[3]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[3] ), .OPOS(\CPLD_Con_1.N_100_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); o_PMU_OC_1_2_ \o_PMU_OC_1[2]_I ( .IOLDO(\o_PMU_OC_1_c[2] ), .oPMUOC12(o_PMU_OC_1[2])); o_PMU_OC_1_2__MGIOL \o_PMU_OC_1[2]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[2] ), .OPOS(\CPLD_Con_1.N_99_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); o_PMU_OC_1_1_ \o_PMU_OC_1[1]_I ( .IOLDO(\o_PMU_OC_1_c[1] ), .oPMUOC11(o_PMU_OC_1[1])); o_PMU_OC_1_1__MGIOL \o_PMU_OC_1[1]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[1] ), .OPOS(\CPLD_Con_1.N_98_3 ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .LSR(\un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ), .CLK(i_sys_clk_c)); o_PMU_OC_1_0_ \o_PMU_OC_1[0]_I ( .IOLDO(\o_PMU_OC_1_c[0] ), .oPMUOC10(o_PMU_OC_1[0])); o_PMU_OC_1_0__MGIOL \o_PMU_OC_1[0]_MGIOL ( .IOLDO(\o_PMU_OC_1_c[0] ), .OPOS(\CPLD_Con_1.PMU_OC_1_11[0] ), .CE(\CPLD_Con_1.PMU_OC_1_0_sqmuxa_2_i ), .CLK(i_sys_clk_c)); o_DPSS_RC1 o_DPSS_RC1_I( .PADDO(DPSFS_RC1), .o_DPSS_RC1(o_DPSS_RC1)); o_DPSF_RC1 o_DPSF_RC1_I( .PADDO(DPSFS_RC1), .o_DPSF_RC1(o_DPSF_RC1)); o_SMMC_5_ \o_SMMC[5]_I ( .PADDO(\FSMMC[5] ), .oSMMC5(o_SMMC[5])); o_SMMC_4_ \o_SMMC[4]_I ( .PADDO(\FSMMC[4] ), .oSMMC4(o_SMMC[4])); o_SMMC_3_ \o_SMMC[3]_I ( .PADDO(\FSMC[3] ), .oSMMC3(o_SMMC[3])); o_SMMC_2_ \o_SMMC[2]_I ( .PADDO(\FSMC[2] ), .oSMMC2(o_SMMC[2])); o_SMMC_1_ \o_SMMC[1]_I ( .PADDO(\FSMC[1] ), .oSMMC1(o_SMMC[1])); o_SMMC_0_ \o_SMMC[0]_I ( .PADDO(\FSMC[0] ), .oSMMC0(o_SMMC[0])); o_FMMC_5_ \o_FMMC[5]_I ( .PADDO(\FSMMC[5] ), .oFMMC5(o_FMMC[5])); o_FMMC_4_ \o_FMMC[4]_I ( .PADDO(\FSMMC[4] ), .oFMMC4(o_FMMC[4])); o_FMMC_3_ \o_FMMC[3]_I ( .PADDO(\FSMC[3] ), .oFMMC3(o_FMMC[3])); o_FMMC_2_ \o_FMMC[2]_I ( .PADDO(\FSMC[2] ), .oFMMC2(o_FMMC[2])); o_FMMC_1_ \o_FMMC[1]_I ( .PADDO(\FSMC[1] ), .oFMMC1(o_FMMC[1])); o_FMMC_0_ \o_FMMC[0]_I ( .PADDO(\FSMC[0] ), .oFMMC0(o_FMMC[0])); o_SMC_3_ \o_SMC[3]_I ( .PADDO(\FSMC[3] ), .oSMC3(o_SMC[3])); o_SMC_2_ \o_SMC[2]_I ( .PADDO(\FSMC[2] ), .oSMC2(o_SMC[2])); o_SMC_1_ \o_SMC[1]_I ( .PADDO(\FSMC[1] ), .oSMC1(o_SMC[1])); o_SMC_0_ \o_SMC[0]_I ( .PADDO(\FSMC[0] ), .oSMC0(o_SMC[0])); o_FMC_3_ \o_FMC[3]_I ( .PADDO(\FSMC[3] ), .oFMC3(o_FMC[3])); o_FMC_2_ \o_FMC[2]_I ( .PADDO(\FSMC[2] ), .oFMC2(o_FMC[2])); o_FMC_1_ \o_FMC[1]_I ( .PADDO(\FSMC[1] ), .oFMC1(o_FMC[1])); o_FMC_0_ \o_FMC[0]_I ( .PADDO(\FSMC[0] ), .oFMC0(o_FMC[0])); o_RC_LOS_1_ \o_RC_LOS[1]_I ( .PADDO(o_RC_ISel_c), .oRCLOS1(o_RC_LOS[1])); o_RC_LOS_0_ \o_RC_LOS[0]_I ( .PADDO(o_RC_VSel_c), .oRCLOS0(o_RC_LOS[0])); o_RC_LOF_1_ \o_RC_LOF[1]_I ( .PADDO(o_RC_ISel_c), .oRCLOF1(o_RC_LOF[1])); o_RC_LOF_0_ \o_RC_LOF[0]_I ( .PADDO(o_RC_VSel_c), .oRCLOF0(o_RC_LOF[0])); o_RC_ISel o_RC_ISel_I( .PADDO(o_RC_ISel_c), .o_RC_ISel(o_RC_ISel)); o_RC_VSel o_RC_VSel_I( .PADDO(o_RC_VSel_c), .o_RC_VSel(o_RC_VSel)); o_RC_RLSel_17_ \o_RC_RLSel[17]_I ( .PADDO(\RC_RLSel[17] ), .oRCRLSel17(o_RC_RLSel[17])); o_RC_RLSel_16_ \o_RC_RLSel[16]_I ( .PADDO(\RC_RLSel[16] ), .oRCRLSel16(o_RC_RLSel[16])); o_RC_RLSel_15_ \o_RC_RLSel[15]_I ( .PADDO(\RC_RLSel[15] ), .oRCRLSel15(o_RC_RLSel[15])); o_RC_RLSel_14_ \o_RC_RLSel[14]_I ( .PADDO(\RC_RLSel[14] ), .oRCRLSel14(o_RC_RLSel[14])); o_RC_RLSel_13_ \o_RC_RLSel[13]_I ( .PADDO(\RC_RLSel[13] ), .oRCRLSel13(o_RC_RLSel[13])); o_RC_RLSel_12_ \o_RC_RLSel[12]_I ( .PADDO(\RC_RLSel[12] ), .oRCRLSel12(o_RC_RLSel[12])); o_RC_RLSel_11_ \o_RC_RLSel[11]_I ( .PADDO(\RC_RLSel[11] ), .oRCRLSel11(o_RC_RLSel[11])); o_RC_RLSel_10_ \o_RC_RLSel[10]_I ( .PADDO(\RC_RLSel[10] ), .oRCRLSel10(o_RC_RLSel[10])); o_RC_RLSel_9_ \o_RC_RLSel[9]_I ( .PADDO(\RC_RLSel[9] ), .oRCRLSel9(o_RC_RLSel[9])); o_RC_RLSel_8_ \o_RC_RLSel[8]_I ( .PADDO(\RC_RLSel[8] ), .oRCRLSel8(o_RC_RLSel[8])); o_RC_RLSel_7_ \o_RC_RLSel[7]_I ( .PADDO(\RC_RLSel[7] ), .oRCRLSel7(o_RC_RLSel[7])); o_RC_RLSel_6_ \o_RC_RLSel[6]_I ( .PADDO(\RC_RLSel[6] ), .oRCRLSel6(o_RC_RLSel[6])); o_RC_RLSel_5_ \o_RC_RLSel[5]_I ( .PADDO(\RC_RLSel[5] ), .oRCRLSel5(o_RC_RLSel[5])); o_RC_RLSel_4_ \o_RC_RLSel[4]_I ( .PADDO(\RC_RLSel[4] ), .oRCRLSel4(o_RC_RLSel[4])); o_RC_RLSel_3_ \o_RC_RLSel[3]_I ( .PADDO(\RC_RLSel[3] ), .oRCRLSel3(o_RC_RLSel[3])); o_RC_RLSel_2_ \o_RC_RLSel[2]_I ( .PADDO(\RC_RLSel[2] ), .oRCRLSel2(o_RC_RLSel[2])); o_RC_RLSel_1_ \o_RC_RLSel[1]_I ( .PADDO(\RC_RLSel[1] ), .oRCRLSel1(o_RC_RLSel[1])); o_RC_RLSel_0_ \o_RC_RLSel[0]_I ( .PADDO(\RC_RLSel[0] ), .oRCRLSel0(o_RC_RLSel[0])); o_RC_T32 o_RC_T32_I( .IOLDO(o_RC_T32_c), .o_RC_T32(o_RC_T32)); o_RC_T32_MGIOL o_RC_T32_MGIOL( .IOLDO(o_RC_T32_c), .OPOS(N_243), .CE(N_168), .CLK(i_sys_clk_c)); o_RC_T31 o_RC_T31_I( .IOLDO(o_RC_T31_c), .o_RC_T31(o_RC_T31)); o_RC_T31_MGIOL o_RC_T31_MGIOL( .IOLDO(o_RC_T31_c), .OPOS(N_38), .CE(N_168), .CLK(i_sys_clk_c)); o_RC_T30 o_RC_T30_I( .IOLDO(o_RC_T30_c), .o_RC_T30(o_RC_T30)); o_RC_T30_MGIOL o_RC_T30_MGIOL( .IOLDO(o_RC_T30_c), .OPOS(N_40), .CE(N_168), .CLK(i_sys_clk_c)); o_RC_T29 o_RC_T29_I( .IOLDO(o_RC_T29_c), .o_RC_T29(o_RC_T29)); o_RC_T29_MGIOL o_RC_T29_MGIOL( .IOLDO(o_RC_T29_c), .OPOS(N_42), .CE(N_168), .CLK(i_sys_clk_c)); o_RC_T28 o_RC_T28_I( .IOLDO(o_RC_T28_c), .o_RC_T28(o_RC_T28)); o_RC_T28_MGIOL o_RC_T28_MGIOL( .IOLDO(o_RC_T28_c), .OPOS(N_244), .CE(N_168), .CLK(i_sys_clk_c)); o_RC_T27 o_RC_T27_I( .IOLDO(o_RC_T27_c), .o_RC_T27(o_RC_T27)); o_RC_T27_MGIOL o_RC_T27_MGIOL( .IOLDO(o_RC_T27_c), .OPOS(N_44), .CE(N_168), .CLK(i_sys_clk_c)); o_IO_RC1 o_IO_RC1_I( .IOLDO(o_IO_RC1_c), .o_IO_RC1(o_IO_RC1)); o_IO_RC1_MGIOL o_IO_RC1_MGIOL( .IOLDO(o_IO_RC1_c), .OPOS(\CPLD_Con_1.io_RC_2 ), .CE(N_18_i), .CLK(i_sys_clk_c)); o_DMM_EN_18_ \o_DMM_EN[18]_I ( .PADDO(GND), .oDMMEN18(o_DMM_EN[18])); o_DMM_EN_17_ \o_DMM_EN[17]_I ( .PADDO(GND), .oDMMEN17(o_DMM_EN[17])); o_DMM_EN_16_ \o_DMM_EN[16]_I ( .PADDO(GND), .oDMMEN16(o_DMM_EN[16])); o_DMM_EN_15_ \o_DMM_EN[15]_I ( .PADDO(\DMM_EN[15] ), .oDMMEN15(o_DMM_EN[15])); o_DMM_EN_14_ \o_DMM_EN[14]_I ( .PADDO(\DMM_EN[14] ), .oDMMEN14(o_DMM_EN[14])); o_DMM_EN_13_ \o_DMM_EN[13]_I ( .PADDO(\DMM_EN[13] ), .oDMMEN13(o_DMM_EN[13])); o_DMM_EN_12_ \o_DMM_EN[12]_I ( .PADDO(\DMM_EN[12] ), .oDMMEN12(o_DMM_EN[12])); o_DMM_EN_11_ \o_DMM_EN[11]_I ( .PADDO(\DMM_EN[11] ), .oDMMEN11(o_DMM_EN[11])); o_DMM_EN_10_ \o_DMM_EN[10]_I ( .PADDO(\DMM_EN[10] ), .oDMMEN10(o_DMM_EN[10])); o_DMM_EN_9_ \o_DMM_EN[9]_I ( .PADDO(\DMM_EN[9] ), .oDMMEN9(o_DMM_EN[9])); o_DMM_EN_8_ \o_DMM_EN[8]_I ( .PADDO(\DMM_EN[8] ), .oDMMEN8(o_DMM_EN[8])); o_DMM_EN_7_ \o_DMM_EN[7]_I ( .PADDO(\DMM_EN[7] ), .oDMMEN7(o_DMM_EN[7])); o_DMM_EN_6_ \o_DMM_EN[6]_I ( .PADDO(\DMM_EN[6] ), .oDMMEN6(o_DMM_EN[6])); o_DMM_EN_5_ \o_DMM_EN[5]_I ( .PADDO(\DMM_EN[5] ), .oDMMEN5(o_DMM_EN[5])); o_DMM_EN_4_ \o_DMM_EN[4]_I ( .PADDO(\DMM_EN[4] ), .oDMMEN4(o_DMM_EN[4])); o_DMM_EN_3_ \o_DMM_EN[3]_I ( .PADDO(\DMM_EN[3] ), .oDMMEN3(o_DMM_EN[3])); o_DMM_EN_2_ \o_DMM_EN[2]_I ( .PADDO(\DMM_EN[2] ), .oDMMEN2(o_DMM_EN[2])); o_DMM_EN_1_ \o_DMM_EN[1]_I ( .PADDO(\DMM_EN[1] ), .oDMMEN1(o_DMM_EN[1])); o_DMM_EN_0_ \o_DMM_EN[0]_I ( .PADDO(\DMM_EN[0] ), .oDMMEN0(o_DMM_EN[0])); o_con_done o_con_done_I( .PADDO(o_con_done_c), .o_con_done(o_con_done)); o_err o_err_I( .PADDO(o_err_c), .o_err(o_err)); i_cs i_cs_I( .PADDI(i_cs_c), .i_cs(i_cs)); i_cs_MGIOL i_cs_MGIOL( .DI(i_cs_c), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .IN(\BUS_Con_1.cs_sync[0] )); i_mosi i_mosi_I( .PADDI(i_mosi_c), .i_mosi(i_mosi)); i_mosi_MGIOL i_mosi_MGIOL( .DI(i_mosi_c), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .IN(\BUS_Con_1.mosi_sync[0] )); i_sclk i_sclk_I( .PADDI(i_sclk_c), .i_sclk(i_sclk)); i_sclk_MGIOL i_sclk_MGIOL( .DI(i_sclk_c), .LSR(i_rst_n_c), .CLK(i_sys_clk_c), .IN(\BUS_Con_1.sclk_sync[0] )); i_rst_n i_rst_n_I( .PADDI(i_rst_n_c), .i_rst_n(i_rst_n)); RelayConTop_reveal_coretop_instance_GSR_INST GSR_INST( .GSRNET(jtaghub16_jrstn)); lsblk0onTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_genblk1_te_tt_ebr_ram_pmi_ram_dpXbnonesadr112112p12e1aace_0_0_0 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_ebr_ram/pmi_ram_dpXbnonesadr112112p12e1aace_0_0_0 ( .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/te_prog_din[0] ) , .ADA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active ) , .CLKA(i_sys_clk_c), .CLKB(i_sys_clk_c), .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_out[0] ) , .ADB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_out[0] ) ); lsblk1ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_23_0 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_23_0 ( .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[212] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[211] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[210] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[209] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[208] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[207] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[207] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[208] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[209] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[210] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[211] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[212] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk2ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_0_23 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_0_23 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[0] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[1] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[2] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[3] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[4] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[5] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[6] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[7] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[8] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk3ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_1_22 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_1_22 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[9] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[10] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[11] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[12] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[13] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[14] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[15] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[16] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[17] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk4ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_2_21 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_2_21 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[18] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[19] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[20] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[21] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[22] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[23] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[24] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[25] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[26] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk5ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_3_20 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_3_20 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[27] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[28] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[29] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[30] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[31] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[32] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[33] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[34] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[35] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk6ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_4_19 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_4_19 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[36] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[37] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[38] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[39] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[40] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[41] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[42] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[43] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[44] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk7ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_5_18 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_5_18 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[45] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[46] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[47] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[48] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[49] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[50] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[51] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[52] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[53] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk8ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_6_17 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_6_17 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[54] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[55] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[56] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[57] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[58] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[59] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[60] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[61] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[62] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk9ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_7_16 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_7_16 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[63] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[64] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[65] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[66] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[67] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[68] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[69] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[70] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[71] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk10ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_8_15 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_8_15 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[72] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[73] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[74] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[75] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[76] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[77] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[78] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[79] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[80] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk11ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_9_14 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_9_14 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[81] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[82] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[83] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[84] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[85] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[86] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[87] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[88] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[89] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk12onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_10_13 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_10_13 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[90] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[91] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[92] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[93] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[94] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[95] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[96] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[97] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[98] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk13onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_11_12 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_11_12 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[99] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[100] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[101] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[102] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[103] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[104] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[105] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[106] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[107] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk14onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_12_11 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_12_11 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[108] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[109] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[110] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[111] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[112] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[113] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[114] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[115] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[116] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk15onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_13_10 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_13_10 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[117] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[118] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[119] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[120] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[121] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[122] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[123] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[124] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[125] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk16ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_14_9 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_14_9 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[126] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[127] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[128] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[129] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[130] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[131] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[132] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[133] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[134] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk17ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_15_8 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_15_8 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[143] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[142] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[141] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[140] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[139] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[135] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[136] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[137] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[138] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[139] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[140] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[141] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[142] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[143] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk18ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_16_7 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_16_7 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[152] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[151] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[150] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[149] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[148] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[147] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[146] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[145] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[144] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[144] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[145] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[146] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[147] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[148] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[149] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[150] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[151] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[152] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk19ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_17_6 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_17_6 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[161] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[160] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[159] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[158] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[157] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[156] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[155] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[154] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[153] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[153] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[154] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[155] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[156] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[157] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[158] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[159] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[160] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[161] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk20ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_18_5 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_18_5 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[170] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[169] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[168] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[167] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[166] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[165] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[164] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[163] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[162] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[162] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[163] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[164] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[165] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[166] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[167] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[168] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[169] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[170] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk21ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_19_4 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_19_4 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[179] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[178] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[177] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[176] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[175] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[174] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[173] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[172] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[171] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[171] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[172] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[173] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[174] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[175] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[176] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[177] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[178] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[179] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk22ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_20_3 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_20_3 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[188] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[187] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[186] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[185] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[184] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[183] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[182] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[181] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[180] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[180] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[181] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[182] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[183] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[184] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[185] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[186] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[187] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[188] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk23ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_21_2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_21_2 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[197] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[196] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[195] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[194] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[193] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[192] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[191] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[190] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[189] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[189] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[190] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[191] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[192] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[193] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[194] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[195] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[196] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[197] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); lsblk24ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_22_1 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_22_1 ( .DIA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[206] ) , .DIA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[205] ) , .DIA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[204] ) , .DIA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[203] ) , .DIA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[202] ) , .DIA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[201] ) , .DIA2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[200] ) , .DIA1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[199] ) , .DIA0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[198] ) , .ADA12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ) , .ADA11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ) , .ADA10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ) , .ADA9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ) , .ADA8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ) , .ADA7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ) , .ADA6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ) , .ADA5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ) , .ADA4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ) , .ADA3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ) , .WEA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/N_656_1_i ) , .RSTA(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .CLKA(i_sys_clk_c), .CLKB(jtaghub16_jtck), .RSTB(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ) , .DOB0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[198] ) , .DOB1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[199] ) , .DOB2(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[200] ) , .DOB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[201] ) , .DOB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[202] ) , .DOB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[203] ) , .DOB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[204] ) , .DOB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[205] ) , .DOB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_int[206] ) , .ADB3(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ) , .ADB4(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ) , .ADB5(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ) , .ADB6(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ) , .ADB7(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ) , .ADB8(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ) , .ADB9(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ) , .ADB10(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ) , .ADB11(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ) , .ADB12(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ) ); xo2chub_genblk7_jtagf_u \xo2chub/genblk7.jtagf_u ( .JTDO1(\xo2chub/jtdo1 ), .JTDO2(\xo2chub/jtdo2 ), .JCE2(jtaghub16_jce2), .JCE1(\xo2chub/jce1 ), .JRSTN(jtaghub16_jrstn), .JUPDATE(jtaghub16_jupdate), .JSHIFT(jtaghub16_jshift), .JTCK(jtaghub16_jtck), .JTDI(jtaghub16_jtdi)); VHI VHI_INST( .Z(VCCI)); PUR PUR_INST( .PUR(VCCI)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_0 ( input A0, M1, M0, CE, CLK, FCI, output F0, Q0, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[157] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[156] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_s_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); specify (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; endmodule module vcc ( output PWR1 ); VHI INST1( .Z(PWR1)); endmodule module gnd ( output PWR0 ); VLO INST1( .Z(PWR0)); endmodule module inverter ( input I, output Z ); INV INST1( .A(I), .Z(Z)); endmodule module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h5001; defparam inst1.INIT1 = 16'h300A; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[146] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[145] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h0001; defparam inst1.INIT1 = 16'h0001; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_2 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[144] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[143] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_3 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[155] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[154] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_4 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[153] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[152] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_5 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[151] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[150] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_6 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[149] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_7 ( input A1, A0, M1, M0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[148] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[147] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_8 ( input A1, M1, M0, CE, CLK, output Q0, F1, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[142] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[141] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20002 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h300A; defparam inst1.INIT1 = 16'h5001; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "YES"; endmodule module SLICE_9 ( input A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[7][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[7][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); specify (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_10 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[7][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[7][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_11 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[7][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[7][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_12 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[7][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[7][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_13 ( input A1, M1, M0, CE, LSR, CLK, output Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[6][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[6][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20002 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_14 ( input B0, A0, DI0, CE, CLK, FCI, output F0, Q0 ); wire VCCI, CLK_NOTIN, GNDI, DI0_dly, CLK_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); ccu20003 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_s_0[5] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); specify (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module ccu20003 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h5002; defparam inst1.INIT1 = 16'h300A; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_15 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20004 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0[3] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (B1 => F1) = (0:0:0,0:0:0); (B1 => FCO) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (B0 => F1) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module ccu20004 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h0007; defparam inst1.INIT1 = 16'h0007; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_16 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20005 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0[1] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (B1 => F1) = (0:0:0,0:0:0); (B1 => FCO) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (B0 => F1) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module ccu20005 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h0002; defparam inst1.INIT1 = 16'h0007; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_17 ( input B1, A1, B0, DI1, CE, CLK, output F1, Q1, FCO ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); ccu20006 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0[0] ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); specify (B1 => F1) = (0:0:0,0:0:0); (B1 => FCO) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (B0 => F1) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module ccu20006 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h300A; defparam inst1.INIT1 = 16'h0007; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_18 ( input A1, M1, M0, CE, LSR, CLK, output Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20007 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module ccu20007 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h000A; defparam inst1.INIT1 = 16'h300A; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module SLICE_19 ( input A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[9][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[9][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_s_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); specify (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_20 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[9][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[9][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_21 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[9][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[9][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_22 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[8][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[8][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_23 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[8][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[8][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_24 ( input A1, M1, M0, CE, LSR, CLK, output Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[8][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[8][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20002 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_25 ( input A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[9][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[9][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_s_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); specify (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_26 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[9][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[9][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_27 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[9][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[9][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_28 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[9][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[9][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_29 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[9][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[9][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20001 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_30 ( input A1, M1, M0, CE, LSR, CLK, output Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \CPLD_Reg_1/regtable[9][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[9][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20002 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_31 ( input A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20003 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_s_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); specify (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_32 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module ccu20008 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h300A; defparam inst1.INIT1 = 16'h300A; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_33 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_34 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_35 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_36 ( input A1, M1, M0, CE, LSR, CLK, output Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20007 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_37 ( input A0, M1, M0, CLK, FCI, output F0, Q0, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d2 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd_d1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20003 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_s_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); specify (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_38 ( input A1, A0, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_bit ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_39 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_40 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_41 ( input A1, A0, M1, M0, CE, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); ccu20008 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); specify (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module xo2chub_SLICE_42 ( input C1, B1, A1, B0, DI1, LSR, CLK, output F1, Q1, FCO ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, LSR_dly; vmuxregsre \xo2chub/bit_count[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); ccu20009 \xo2chub/bit_count_cry_0[0] ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(C1), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); gnd DRIVEGND( .PWR0(GNDI)); specify (C1 => F1) = (0:0:0,0:0:0); (C1 => FCO) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (B1 => FCO) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (B0 => F1) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module ccu20009 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h300A; defparam inst1.INIT1 = 16'hF0E4; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module SLICE_43 ( input B0, A0, M1, M0, CE, CLK, FCI, output Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[189] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20010 \xo2chub/jtdo2_int_prm_1_0_0 ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(F1), .CO1()); specify (B0 => F1) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module ccu20010 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h5003; defparam inst1.INIT1 = 16'h300A; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module SLICE_44 ( input B1, A1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[191] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[190] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20011 \xo2chub/jtdo2_int_prm_3_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module ccu20011 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h5003; defparam inst1.INIT1 = 16'h5003; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module SLICE_45 ( input B1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[193] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[192] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20011 \xo2chub/jtdo2_int_prm_5_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_46 ( input B1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[195] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[194] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20011 \xo2chub/jtdo2_int_prm_7_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_47 ( input B1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[197] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[196] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20011 \xo2chub/jtdo2_int_prm_9_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_48 ( input B1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[182] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[181] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20011 \xo2chub/jtdo2_int_prm_11_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_49 ( input B1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[184] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[183] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20011 \xo2chub/jtdo2_int_prm_13_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_50 ( input B1, B0, M1, M0, CE, CLK, FCI, output Q0, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[186] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[185] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20011 \xo2chub/jtdo2_int_prm_15_0_0 ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_51 ( input B1, M1, M0, CE, CLK, output Q0, Q1, FCO ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[188] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[187] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); ccu20012 \xo2chub/jtdo2_int_prm_16_0_0 ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(), .CO1(FCO)); specify (B1 => FCO) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module ccu20012 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h300A; defparam inst1.INIT1 = 16'h5003; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module xo2chub_SLICE_52 ( input B0, A0, DI0, LSR, CLK, FCI, output F0, Q0 ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI0_dly, CLK_dly, LSR_dly; vmuxregsre \xo2chub/rom_rd_addr[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); ccu20013 \xo2chub/rom_rd_addr_s_0[7] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(GNDI), .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); gnd DRIVEGND( .PWR0(GNDI)); specify (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module ccu20013 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h5008; defparam inst1.INIT1 = 16'h300A; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module xo2chub_SLICE_53 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; vmuxregsre \xo2chub/rom_rd_addr[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/rom_rd_addr[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); ccu20014 \xo2chub/rom_rd_addr_cry_0[5] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); gnd DRIVEGND( .PWR0(GNDI)); specify (B1 => F1) = (0:0:0,0:0:0); (B1 => FCO) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (B0 => F1) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module ccu20014 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'hF008; defparam inst1.INIT1 = 16'hF008; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module xo2chub_SLICE_54 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; vmuxregsre \xo2chub/rom_rd_addr[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/rom_rd_addr[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); ccu20014 \xo2chub/rom_rd_addr_cry_0[3] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); gnd DRIVEGND( .PWR0(GNDI)); specify (B1 => F1) = (0:0:0,0:0:0); (B1 => FCO) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (B0 => F1) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module xo2chub_SLICE_55 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; vmuxregsre \xo2chub/rom_rd_addr[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/rom_rd_addr[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); ccu20014 \xo2chub/rom_rd_addr_cry_0[1] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); gnd DRIVEGND( .PWR0(GNDI)); specify (B1 => F1) = (0:0:0,0:0:0); (B1 => FCO) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (B0 => F1) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module xo2chub_SLICE_56 ( input B1, A1, B0, DI1, M0, LSR, CLK, output Q0, F1, Q1, FCO ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, M0_dly, LSR_dly; vmuxregsre \xo2chub/rom_rd_addr[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/jshift_d1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); gnd DRIVEGND( .PWR0(GNDI)); ccu20015 \xo2chub/rom_rd_addr_cry_0[0] ( .A0(GNDI), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); specify (B1 => F1) = (0:0:0,0:0:0); (B1 => FCO) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (B0 => F1) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module ccu20015 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'h300A; defparam inst1.INIT1 = 16'hF008; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module xo2chub_SLICE_57 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; vmuxregsre \xo2chub/bit_count[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/bit_count[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); ccu20016 \xo2chub/bit_count_cry_0[3] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1()); gnd DRIVEGND( .PWR0(GNDI)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (B0 => F1) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module ccu20016 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); defparam inst1.INIT0 = 16'hF008; defparam inst1.INIT1 = 16'h5008; defparam inst1.INJECT1_0 = "NO"; defparam inst1.INJECT1_1 = "NO"; endmodule module xo2chub_SLICE_58 ( input B1, A1, B0, A0, DI1, DI0, LSR, CLK, FCI, output F0, Q0, F1, Q1, FCO ); wire VCCI, CLK_NOTIN, LSR_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; vmuxregsre \xo2chub/bit_count[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/bit_count[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); ccu20014 \xo2chub/bit_count_cry_0[1] ( .A0(A0), .B0(B0), .C0(GNDI), .D0(GNDI), .A1(A1), .B1(B1), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); gnd DRIVEGND( .PWR0(GNDI)); specify (B1 => F1) = (0:0:0,0:0:0); (B1 => FCO) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (A1 => FCO) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (B0 => F1) = (0:0:0,0:0:0); (B0 => FCO) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (A0 => F1) = (0:0:0,0:0:0); (A0 => FCO) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); (FCI => F0) = (0:0:0,0:0:0); (FCI => F1) = (0:0:0,0:0:0); (FCI => FCO) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module SLICE_59 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly; lut4 \CPLD_Con_1/io_RC9_RNID445E ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40017 \BUS_Con_1/cs_sync_rep0_set[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \BUS_Con_1_cs_sync_rep0io[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut4 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40017 ( input A, B, C, D, output Z ); ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_60 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; lut40018 \BUS_Con_1/bit_cnt_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40019 \BUS_Con_1/bit_cnt_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/bit_cnt[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/bit_cnt[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40018 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA6AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40019 ( input A, B, C, D, output Z ); ROM16X1A #(16'h9A9A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module vmuxregsre0020 ( input D0, D1, SD, SP, CK, LSR, output Q ); FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; endmodule module BUS_Con_1_SLICE_61 ( input B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; lut40021 \BUS_Con_1/un1_bit_cnt_7_axbxc3 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40022 \BUS_Con_1/un1_bit_cnt_7_axbxc2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/bit_cnt[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/bit_cnt[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40021 ( input A, B, C, D, output Z ); ROM16X1A #(16'h6666) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40022 ( input A, B, C, D, output Z ); ROM16X1A #(16'h78F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_62 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; lut40022 \BUS_Con_1/un1_bit_cnt_7_axbxc5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40023 \BUS_Con_1/un1_bit_cnt_7_axbxc4 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/bit_cnt[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/bit_cnt[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40023 ( input A, B, C, D, output Z ); ROM16X1A #(16'h6C6C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_64 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40024 \BUS_Con_1/data_ready_en_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40025 \BUS_Con_1/data_ready_0_sqmuxa_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_ready ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40024 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40025 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_65 ( input D1, C1, B1, A1, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; lut40026 \BUS_Con_1/miso_loaded_0_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40027 \BUS_Con_1/miso_loaded.fb ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0028 \BUS_Con_1/cs_sync[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \BUS_Con_1/miso_loaded ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40026 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40027 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module vmuxregsre0028 ( input D0, D1, SD, SP, CK, LSR, output Q ); FL1P3JY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; endmodule module BUS_Con_1_SLICE_66 ( input C1, B1, A1, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40029 \BUS_Con_1/miso_shift_8[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40030 \BUS_Con_1/miso_shift_8[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/miso_shift[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/miso_shift[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40029 ( input A, B, C, D, output Z ); ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40030 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_67 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40029 \BUS_Con_1/miso_shift_8[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \BUS_Con_1/miso_shift_8[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/miso_shift[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/miso_shift[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_68 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40029 \BUS_Con_1/miso_shift_8[13] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \BUS_Con_1/miso_shift_8[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/miso_shift[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/miso_shift[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_69 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40029 \BUS_Con_1/miso_shift_8[15] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \BUS_Con_1/miso_shift_8[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/miso_shift[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/miso_shift[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_70 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40029 \BUS_Con_1/miso_shift_8[17] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \BUS_Con_1/miso_shift_8[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/miso_shift[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/miso_shift[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_71 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40029 \BUS_Con_1/miso_shift_8[19] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \BUS_Con_1/miso_shift_8[18] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/miso_shift[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/miso_shift[18] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_72 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40029 \BUS_Con_1/miso_shift_8[21] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \BUS_Con_1/miso_shift_8[20] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/miso_shift[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/miso_shift[20] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_73 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40029 \BUS_Con_1/miso_shift_8[23] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \BUS_Con_1/miso_shift_8[22] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/miso_shift[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/miso_shift[22] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_74 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40029 \BUS_Con_1/miso_shift_8[25] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \BUS_Con_1/miso_shift_8[24] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/miso_shift[25] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/miso_shift[24] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_75 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40029 \BUS_Con_1/miso_shift_8[27] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \BUS_Con_1/miso_shift_8[26] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/miso_shift[27] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/miso_shift[26] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_76 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40029 \BUS_Con_1/miso_shift_8[29] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \BUS_Con_1/miso_shift_8[28] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/miso_shift[29] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/miso_shift[28] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_77 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40031 \BUS_Con_1/miso_shift17lto5_i_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40029 \BUS_Con_1/miso_shift_8[30] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/miso_shift[30] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40031 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; lut40032 \BUS_Con_1/state_srsts[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40033 \BUS_Con_1/state_srsts[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \BUS_Con_1/state[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \BUS_Con_1/state[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40032 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40033 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_106 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; lut40034 \CPLD_Con_1/SUM1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40035 \CPLD_Con_1/SUM0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/dc_t[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \CPLD_Con_1/dc_t[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40034 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7EE8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40035 ( input A, B, C, D, output Z ); ROM16X1A #(16'h6996) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_107 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; lut40036 \CPLD_Con_1/un1_en_t_axbxc2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40037 \CPLD_Con_1/un1_en_t_axbxc1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/en_t[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \CPLD_Con_1/en_t[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40036 ( input A, B, C, D, output Z ); ROM16X1A #(16'h9696) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40037 ( input A, B, C, D, output Z ); ROM16X1A #(16'h936C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_108 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, LSR_dly; lut40038 \CPLD_Con_1/CO1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40039 \CPLD_Con_1/un1_en_t_c3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \CPLD_Con_1/en_t[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40038 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40039 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_109 ( input B1, A1, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40039 \CPLD_Con_1/dc_slot_flag_fast_RNI08G61[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40039 \CPLD_Con_1/RC_Tx_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/exec_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_110 ( input C1, B1, A1, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40040 \CPLD_Con_1/DMM_en_26_0_a3_1[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40039 \CPLD_Con_1/RC_Tx_1_sqmuxa_0_a2_fast ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/exec_flag_fast ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40040 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_111 ( input D1, C1, B1, A1, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40025 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc6_RNIKL8D ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40039 \CPLD_Con_1/RC_Tx_1_sqmuxa_0_a2_rep1 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \CPLD_Con_1/exec_flag_rep1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; lut40034 \CPLD_Con_1/SUM1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40035 \CPLD_Con_1/SUM0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/freq_t[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \CPLD_Con_1/freq_t[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_116 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40041 \CPLD_Reg_1/err_flag8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40042 \CPLD_Reg_1/err_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/err_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40041 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40042 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_SLICE_212 ( input D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40043 \CPLD_Reg_1/regtable[1]_RNO[23] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0044 \CPLD_Reg_1/regtable[1][23] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40043 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFBC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module vmuxregsre0044 ( input D0, D1, SD, SP, CK, LSR, output Q ); FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; endmodule module CPLD_Reg_1_SLICE_258 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; lut40045 \CPLD_Reg_1/state_ns_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40046 \CPLD_Reg_1/state_ns_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/state[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/state[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40045 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40046 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_307 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40047 \CPLD_Con_1/DMM_en_26_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40048 \CPLD_Con_1/DMM_en_26[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Con_1/DMM_en[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \CPLD_Con_1/DMM_en[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40047 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF2F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40048 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCC0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_308 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40047 \CPLD_Con_1/DMM_en_26_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40049 \CPLD_Con_1/DMM_en_26[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Con_1/DMM_en[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \CPLD_Con_1/DMM_en[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40049 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_309 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40049 \CPLD_Con_1/DMM_en_26[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40050 \CPLD_Con_1/DMM_en_26[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Con_1/DMM_en[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Con_1/DMM_en[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40050 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAA0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_310 ( input D1, C1, B1, A1, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); wire \CPLD_Con_1/SLICE_310/CPLD_Con_1/SLICE_310_K1_H1 , GNDI, \CPLD_Con_1/SLICE_310/CPLD_Con_1/DMM_en_26[5]/GATE_H0 , VCCI, DI0_dly, CLK_dly, CE_dly; lut40051 \CPLD_Con_1/SLICE_310_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(\CPLD_Con_1/SLICE_310/CPLD_Con_1/SLICE_310_K1_H1 )); lut40052 \CPLD_Con_1/DMM_en_26[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Con_1/SLICE_310/CPLD_Con_1/DMM_en_26[5]/GATE_H0 )); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Con_1/DMM_en[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Con_1/SLICE_310_K0K1MUX ( .D0(\CPLD_Con_1/SLICE_310/CPLD_Con_1/DMM_en_26[5]/GATE_H0 ), .D1(\CPLD_Con_1/SLICE_310/CPLD_Con_1/SLICE_310_K1_H1 ), .SD(M0), .Z(OFX0)); specify (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40051 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40052 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module selmux2 ( input D0, D1, SD, output Z ); MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); endmodule module CPLD_Con_1_SLICE_311 ( input C1, B1, A1, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); wire GNDI, \CPLD_Con_1/SLICE_311/CPLD_Con_1/SLICE_311_K1_H1 , \CPLD_Con_1/SLICE_311/CPLD_Con_1/DMM_en_26[7]/GATE_H0 , VCCI, DI0_dly, CLK_dly, CE_dly; lut40053 \CPLD_Con_1/SLICE_311_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Con_1/SLICE_311/CPLD_Con_1/SLICE_311_K1_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40054 \CPLD_Con_1/DMM_en_26[7]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Con_1/SLICE_311/CPLD_Con_1/DMM_en_26[7]/GATE_H0 )); vmuxregsre \CPLD_Con_1/DMM_en[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Con_1/SLICE_311_K0K1MUX ( .D0(\CPLD_Con_1/SLICE_311/CPLD_Con_1/DMM_en_26[7]/GATE_H0 ), .D1(\CPLD_Con_1/SLICE_311/CPLD_Con_1/SLICE_311_K1_H1 ), .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40053 ( input A, B, C, D, output Z ); ROM16X1A #(16'hB0B0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40054 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_312 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40055 \CPLD_Con_1/DMM_en_26_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40047 \CPLD_Con_1/DMM_en_26_0[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Con_1/DMM_en[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \CPLD_Con_1/DMM_en[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40055 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_313 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40047 \CPLD_Con_1/DMM_en_26_0[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40047 \CPLD_Con_1/DMM_en_26_0[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Con_1/DMM_en[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \CPLD_Con_1/DMM_en[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_314 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40056 \CPLD_Con_1/DMM_en_26_0[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40056 \CPLD_Con_1/DMM_en_26_0[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Con_1/DMM_en[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \CPLD_Con_1/DMM_en[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40056 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3B3B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_315 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); wire \CPLD_Con_1/SLICE_315/CPLD_Con_1/SLICE_315_K1_H1 , \CPLD_Con_1/SLICE_315/CPLD_Con_1/DMM_en_26_0[13]/GATE_H0 , VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; lut40057 \CPLD_Con_1/SLICE_315_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(\CPLD_Con_1/SLICE_315/CPLD_Con_1/SLICE_315_K1_H1 )); lut40058 \CPLD_Con_1/DMM_en_26_0[13]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\CPLD_Con_1/SLICE_315/CPLD_Con_1/DMM_en_26_0[13]/GATE_H0 )); vmuxregsre \CPLD_Con_1/DMM_en[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); selmux2 \CPLD_Con_1/SLICE_315_K0K1MUX ( .D0(\CPLD_Con_1/SLICE_315/CPLD_Con_1/DMM_en_26_0[13]/GATE_H0 ), .D1(\CPLD_Con_1/SLICE_315/CPLD_Con_1/SLICE_315_K1_H1 ), .SD(M0), .Z(OFX0)); specify (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40057 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40058 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_316 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); wire \CPLD_Con_1/SLICE_316/CPLD_Con_1/SLICE_316_K1_H1 , \CPLD_Con_1/SLICE_316/CPLD_Con_1/DMM_en_RNO[15]/GATE_H0 , VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; lut40057 \CPLD_Con_1/SLICE_316_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(\CPLD_Con_1/SLICE_316/CPLD_Con_1/SLICE_316_K1_H1 )); lut40059 \CPLD_Con_1/DMM_en_RNO[15]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\CPLD_Con_1/SLICE_316/CPLD_Con_1/DMM_en_RNO[15]/GATE_H0 )); vmuxregsre \CPLD_Con_1/DMM_en[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); selmux2 \CPLD_Con_1/SLICE_316_K0K1MUX ( .D0(\CPLD_Con_1/SLICE_316/CPLD_Con_1/DMM_en_RNO[15]/GATE_H0 ), .D1(\CPLD_Con_1/SLICE_316/CPLD_Con_1/SLICE_316_K1_H1 ), .SD(M0), .Z(OFX0)); specify (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40059 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_317 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; lut40060 \CPLD_Con_1/DPSFS_RC1e_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40061 \CPLD_Con_1/DPSFS_RC1e ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/mosi_sync[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPSFS_RC1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40060 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0B4F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40061 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFD01) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_318 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40062 \CPLD_Con_1/DPS_FS_1_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40063 \CPLD_Con_1/DPS_FS_1_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40062 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40063 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_319 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40062 \CPLD_Con_1/DPS_FS_1_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40063 \CPLD_Con_1/DPS_FS_1_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_320 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40064 \CPLD_Con_1/DPS_FS_1_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40065 \CPLD_Con_1/DPS_FS_1_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40064 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFDFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40065 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_321 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40064 \CPLD_Con_1/DPS_FS_1_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40065 \CPLD_Con_1/DPS_FS_1_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_322 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40066 \CPLD_Con_1/DPS_FS_1_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40067 \CPLD_Con_1/DPS_FS_1_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40066 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40067 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF7FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_323 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40066 \CPLD_Con_1/DPS_FS_1_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40067 \CPLD_Con_1/DPS_FS_1_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_324 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40067 \CPLD_Con_1/DPS_FS_1_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40068 \CPLD_Con_1/DPS_FS_1_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40068 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_325 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40067 \CPLD_Con_1/DPS_FS_1_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40068 \CPLD_Con_1/DPS_FS_1_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_1[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_326 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40066 \CPLD_Con_1/DPS_FS_2_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40064 \CPLD_Con_1/DPS_FS_2_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_327 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40069 \CPLD_Con_1/DPS_FS_2_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40067 \CPLD_Con_1/DPS_FS_2_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40069 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_328 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40070 \CPLD_Con_1/DPS_FS_2_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40071 \CPLD_Con_1/DPS_FS_2_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40070 ( input A, B, C, D, output Z ); ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40071 ( input A, B, C, D, output Z ); ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_329 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40062 \CPLD_Con_1/DPS_FS_2_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40068 \CPLD_Con_1/DPS_FS_2_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_330 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40066 \CPLD_Con_1/DPS_FS_2_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40064 \CPLD_Con_1/DPS_FS_2_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_331 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40069 \CPLD_Con_1/DPS_FS_2_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40067 \CPLD_Con_1/DPS_FS_2_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_332 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40070 \CPLD_Con_1/DPS_FS_2_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40071 \CPLD_Con_1/DPS_FS_2_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_333 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40062 \CPLD_Con_1/DPS_FS_2_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40068 \CPLD_Con_1/DPS_FS_2_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_2[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_334 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40070 \CPLD_Con_1/DPS_FS_3_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40067 \CPLD_Con_1/DPS_FS_3_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_335 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40070 \CPLD_Con_1/DPS_FS_3_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40071 \CPLD_Con_1/DPS_FS_3_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_336 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40070 \CPLD_Con_1/DPS_FS_3_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40071 \CPLD_Con_1/DPS_FS_3_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_337 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40070 \CPLD_Con_1/DPS_FS_3_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40071 \CPLD_Con_1/DPS_FS_3_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_338 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40068 \CPLD_Con_1/DPS_FS_3_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40068 \CPLD_Con_1/DPS_FS_3_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_339 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40068 \CPLD_Con_1/DPS_FS_3_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40068 \CPLD_Con_1/DPS_FS_3_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_340 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40068 \CPLD_Con_1/DPS_FS_3_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40068 \CPLD_Con_1/DPS_FS_3_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_341 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40068 \CPLD_Con_1/DPS_FS_3_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40068 \CPLD_Con_1/DPS_FS_3_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_3[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_342 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40062 \CPLD_Con_1/DPS_FS_4_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40063 \CPLD_Con_1/DPS_FS_4_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_343 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40062 \CPLD_Con_1/DPS_FS_4_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40063 \CPLD_Con_1/DPS_FS_4_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_344 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40064 \CPLD_Con_1/DPS_FS_4_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40065 \CPLD_Con_1/DPS_FS_4_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_345 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40064 \CPLD_Con_1/DPS_FS_4_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40065 \CPLD_Con_1/DPS_FS_4_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_346 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40066 \CPLD_Con_1/DPS_FS_4_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40067 \CPLD_Con_1/DPS_FS_4_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_347 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40066 \CPLD_Con_1/DPS_FS_4_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40067 \CPLD_Con_1/DPS_FS_4_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_348 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40067 \CPLD_Con_1/DPS_FS_4_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40068 \CPLD_Con_1/DPS_FS_4_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_349 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40067 \CPLD_Con_1/DPS_FS_4_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40068 \CPLD_Con_1/DPS_FS_4_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/DPS_FS_4[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_350 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; lut40072 \CPLD_Con_1/DPS_FSMCd[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40072 \CPLD_Con_1/DPS_FSMCd[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Con_1/DPS_FSMC[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Con_1/DPS_FSMC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40072 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7F5D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_351 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; lut40073 \CPLD_Con_1/DPS_FSMC_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40072 \CPLD_Con_1/DPS_FSMCd[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Con_1/DPS_FSMC[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Con_1/DPS_FSMC[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40073 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7F5D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_352 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; lut40074 \CPLD_Con_1/DPS_FSMMCe[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40075 \CPLD_Con_1/DPS_FSMMCe[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Con_1/DPS_FSMMC[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Con_1/DPS_FSMMC[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40074 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF7A2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40075 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEF01) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_353 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40076 \CPLD_Con_1/RC_RLSel_13_0_iv_i[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40077 \CPLD_Con_1/RC_RLSel_13_0_iv_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40076 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40077 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_354 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40078 \CPLD_Con_1/RC_RLSel_13_0_iv_i[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \CPLD_Con_1/RC_RLSel_13_0_iv_i[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40078 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40079 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_355 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40079 \CPLD_Con_1/RC_RLSel_13_iv_i[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_356 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40077 \CPLD_Con_1/RC_RLSel_13_iv_i[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_357 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_358 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_359 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[13] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_360 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_361 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40079 \CPLD_Con_1/RC_RLSel_13_iv_i[17] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \CPLD_Con_1/RC_RLSel_13_iv_i[16] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0028 \CPLD_Con_1/RC_RLSel[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_370 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40080 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNITT1M ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40081 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear_6_0_o2_1_o2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/clear ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40080 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8A88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40081 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4FF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_374 ( input D1, C1, B1, A1, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; lut40082 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40083 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast_RNI2QU11 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d2 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40082 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1D00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40083 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_377 ( input D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, Q1 ); wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; lut40041 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk_3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_379 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; lut40084 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_1_sqmuxa_i_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40085 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/cmd_block_extend ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40084 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEEEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40085 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_387 ( input D1, C1, B1, A1, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; lut40086 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40040 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d2 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40086 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_390 ( input B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; lut40027 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3_1[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40041 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk_3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_392 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; lut40087 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_RNO ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40088 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15_d1 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40087 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40088 ( input A, B, C, D, output Z ); ROM16X1A #(16'h75EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_393 ( input A1, D0, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; lut40089 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/bit_cnt_cry_0_RNO[0] ( .A(A1), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40090 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d3 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_checker ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40089 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5555) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40090 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8C40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_399 ( input B1, A1, D0, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; lut40021 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_2_0[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40091 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_RNO[35] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d2 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[35] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40091 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_400 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_401 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_402 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_403 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_404 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_405 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_406 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_407 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_408 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_409 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_410 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_411 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_412 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_413 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_414 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[29] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_415 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[30] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_416 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_417 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[34] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_418 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_419 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_420 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_421 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[43] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_422 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[45] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[44] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_423 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[47] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[46] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[47] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_424 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[49] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[48] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[49] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[48] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_425 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[51] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[50] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[51] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[50] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_426 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[53] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[52] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[53] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[52] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_427 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[55] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[54] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[55] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[54] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_428 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[57] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[56] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[57] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[56] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_429 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[59] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[58] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[59] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[58] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_430 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[61] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[60] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[61] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[60] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_431 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[63] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[62] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[63] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[62] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_432 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[65] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[64] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[65] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[64] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_433 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[67] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[66] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[67] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[66] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_434 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[69] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[68] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[69] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[68] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_435 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[71] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[70] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[71] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[70] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_436 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[73] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[72] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[73] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[72] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_437 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[75] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[74] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[75] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[74] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_438 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[77] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[76] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[77] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[76] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_439 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[79] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[78] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[79] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[78] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_440 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[81] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[80] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[81] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[80] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_441 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[83] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[82] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[83] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[82] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_442 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[85] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[84] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[85] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[84] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_443 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[87] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[86] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[87] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[86] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_444 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[89] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[88] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[89] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[88] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_445 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[91] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[90] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[91] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[90] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_446 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[93] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[92] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[93] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[92] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_447 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[95] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[94] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[95] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[94] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_448 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[97] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[96] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[97] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[96] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_449 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[99] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[98] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[99] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[98] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_450 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[101] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[100] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[101] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[100] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_451 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[103] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[102] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[103] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[102] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_452 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[105] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[104] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[105] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[104] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_453 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[107] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[106] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[107] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[106] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_454 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[109] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[108] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[109] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[108] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_455 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[111] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[110] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[111] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[110] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_456 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[113] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[112] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[113] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[112] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_457 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[115] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[114] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[115] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[114] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_458 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[117] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[116] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[117] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[116] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_459 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[119] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[118] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[119] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[118] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_460 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[121] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[120] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[121] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[120] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_461 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[123] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[122] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[123] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[122] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_462 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[125] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[124] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[125] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[124] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_463 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[127] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[126] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[127] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[126] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_464 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[129] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[128] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[129] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[128] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_465 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[131] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[130] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[131] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[130] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_466 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[133] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[132] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[133] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[132] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_467 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[135] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[134] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[135] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[134] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_468 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[137] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[136] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[137] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[136] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_469 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[139] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[138] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[139] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[138] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_470 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[141] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[140] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[141] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[140] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_471 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[143] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[142] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[143] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[142] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_472 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[145] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[144] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[145] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[144] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_473 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[147] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[146] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[147] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[146] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_474 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[149] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[148] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[149] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[148] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_475 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[151] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[150] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[151] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[150] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_476 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[153] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[152] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[153] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[152] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_477 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[155] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[154] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[155] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[154] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_478 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[157] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[156] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[157] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[156] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_479 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[159] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[158] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[159] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[158] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_480 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[161] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[160] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[161] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[160] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_481 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[163] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[162] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[163] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[162] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_482 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[165] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[164] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[165] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[164] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_483 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[167] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[166] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[167] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[166] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_484 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[169] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[168] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[169] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[168] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_485 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[171] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[170] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[171] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[170] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_486 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[173] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[172] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[173] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[172] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_487 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[175] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[174] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[175] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[174] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_488 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[177] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[176] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[177] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[176] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_489 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[179] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[178] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[179] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[178] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_490 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[181] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[180] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[181] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[180] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_491 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[183] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[182] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[183] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[182] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_492 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[185] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[184] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[185] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[184] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_493 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[187] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[186] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[187] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[186] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_494 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[189] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[188] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[189] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[188] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_495 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[191] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[190] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[191] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[190] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_496 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[193] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[192] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[193] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[192] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_497 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[195] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[194] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[195] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[194] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_498 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[197] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[196] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[197] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[196] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_499 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[199] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[198] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[199] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[198] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_500 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[201] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[200] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[201] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[200] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_501 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[203] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[202] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[203] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[202] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_502 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[205] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[204] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[205] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[204] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_503 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[207] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[206] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[207] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[206] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_504 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40092 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[209] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40029 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[208] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[209] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[208] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40092 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0F0D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_505 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40092 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[211] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40092 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[210] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[211] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[210] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_506 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; lut40093 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[211] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40094 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[212] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout[212] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40093 ( input A, B, C, D, output Z ); ROM16X1A #(16'h085D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40094 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_507 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; lut40095 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40096 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d3 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40095 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40096 ( input A, B, C, D, output Z ); ROM16X1A #(16'hD888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_508 ( input B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40098 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40097 ( input A, B, C, D, output Z ); ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40098 ( input A, B, C, D, output Z ); ROM16X1A #(16'h57FD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_509 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_510 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[5] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_511 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_512 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_RNO[9] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[8] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_513 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_RNO[11] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_RNO[10] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_514 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[13] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_RNO[12] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_515 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_7[15] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40097 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_RNO[14] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_517 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40099 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF2D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_518 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40040 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40100 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40100 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2F0D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_519 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40040 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40101 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40101 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_520 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40101 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40101 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_521 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40103 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_7[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40102 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40103 ( input A, B, C, D, output Z ); ROM16X1A #(16'hD77D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_522 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_523 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_524 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_525 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_526 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_527 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[13] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_528 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[15] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40102 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_529 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; lut40104 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_a3[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40105 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_clr ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40104 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40105 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_530 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; lut40106 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_0_a2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40107 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40106 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40107 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_531 ( input C1, B1, A1, C0, B0, A0, DI0, M1, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly; lut40108 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_int_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40109 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_3_0_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_d1 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40108 ( input A, B, C, D, output Z ); ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40109 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4141) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_532 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40110 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40110 ( input A, B, C, D, output Z ); ROM16X1A #(16'h00F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_533 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40111 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40112 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40111 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40112 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0045) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_534 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40113 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40113 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40113 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_535 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40114 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40113 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40114 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0301) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_536 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40111 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40113 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_537 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40115 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40116 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40115 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40116 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_538 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40117 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40118 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO[13] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40117 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40118 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA0CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_540 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40119 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_7_i_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40120 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40119 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40120 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_541 ( input D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40121 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1_7.m6_i_o2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_p1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40121 ( input A, B, C, D, output Z ); ROM16X1A #(16'h10F1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_542 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40122 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40120 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40122 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_543 ( input D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40123 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_9 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40123 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_544 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40030 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_0_0_a2_0_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40124 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_3_iv_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40124 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4445) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_545 ( input D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40091 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_551 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40125 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_RNIRIQV4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40126 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40125 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40126 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2310) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_562 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_563 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_564 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_565 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_566 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_lm_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_567 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40127 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40042 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40127 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_568 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_569 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_570 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_571 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_572 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40099 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr_lm_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cntr[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_573 ( input DI0, M1, LSR, CLK, output F0, Q0, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; lut40128 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/VCC\000/BUF1/BUF1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[2] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/sample_en_d ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40128 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_576 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly; lut40115 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40039 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_first_rd ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_578 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40130 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40129 ( input A, B, C, D, output Z ); ROM16X1A #(16'hBA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40130 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFE44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_579 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_580 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_581 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_582 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40129 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_lm_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_583 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40131 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40131 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40131 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_584 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40131 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40131 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_585 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40131 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40131 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_586 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40131 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40131 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_587 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40131 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40131 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_wr_addr_cntr[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_695 ( input B1, A1, D0, C0, B0, A0, DI0, M1, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, CE_dly, LSR_dly; lut40017 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40132 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/start_d ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40132 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3201) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_696 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40133 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/capture_6_f0_i_0_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40132 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_det_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40133 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5557) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_703 ( input B1, A1, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; lut40039 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNI0JLC ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40134 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_3_i_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_reclk[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40134 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5454) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_812 ( input C1, B1, A1, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; lut40135 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_0_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40136 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_8[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[2] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40135 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40136 ( input A, B, C, D, output Z ); ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_813 ( input C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40137 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40094 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read7 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40137 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tcnt_0_SLICE_817 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; lut40138 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40138 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40138 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF0E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_818 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; lut40115 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa_3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40139 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_reclk[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40139 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8CD8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_822 ( input D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, Q1 ); wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; lut40140 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[100] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/state_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40140 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_824 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40141 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF0D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_825 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_826 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_827 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_828 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_829 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_830 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[13] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[12] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_831 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40141 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_lm_0[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_840 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, LSR_dly; lut40142 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40143 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40142 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4140) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40143 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1110) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_841 ( input D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, Q1 ); wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; lut40107 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt_4_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[102] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_842 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; lut40038 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40144 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40144 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_844 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; lut40113 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40083 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_bit_cntr_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_845 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; lut40062 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4_0_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40145 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg_4_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[101] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_out_reg ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40145 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_SLICE_852 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, M1, M0, FXB, FXA, LSR, CLK, output OFX0, Q1, OFX1 ); wire \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE_H1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852_K0_H0 , VCCI, LSR_NOTIN, DI1_dly, CLK_dly, LSR_dly; lut40146 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE_H1 ) ); lut40147 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852_K0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852_K0_H0 ) ); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/tu_out ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); selmux2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852_K0K1MUX ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852_K0_H0 ) , .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_6/GATE_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/SLICE_852_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40146 ( input A, B, C, D, output Z ); ROM16X1A #(16'hD313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40147 ( input A, B, C, D, output Z ); ROM16X1A #(16'hBB06) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_853 ( input D1, C1, B1, A1, B0, A0, DI0, M1, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, M1_dly, LSR_dly; lut40148 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40030 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_0_sqmuxa ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[0] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trigger_reg ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40148 ( input A, B, C, D, output Z ); ROM16X1A #(16'h656A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_SLICE_854 ( input C0, B0, A0, DI0, CE, CLK, output F0, Q0 ); wire GNDI, VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; lut40144 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_en_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_en ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_855 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40149 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40149 ( input A, B, C, D, output Z ); ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_856 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40150 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40151 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40150 ( input A, B, C, D, output Z ); ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40151 ( input A, B, C, D, output Z ); ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_857 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); wire GNDI, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857_K1_H1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE_H0 , VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; lut40152 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40153 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE_H0 ) ); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); selmux2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857_K0K1MUX ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[3]/GATE_H0 ) , .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_857_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40152 ( input A, B, C, D, output Z ); ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40153 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAA30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_858 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); wire GNDI, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858_K1_H1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE_H0 , VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; lut40152 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40153 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE_H0 ) ); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); selmux2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858_K0K1MUX ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[4]/GATE_H0 ) , .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_858_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_859 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); wire GNDI, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859_K1_H1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE_H0 , VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; lut40152 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40153 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE_H0 ) ); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); selmux2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859_K0K1MUX ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[5]/GATE_H0 ) , .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_859_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_860 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40031 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[8] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40031 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_861 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40031 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40031 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_862 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, CLK_NOTIN, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; lut40031 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[12] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40031 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1[11] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_863 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); wire GNDI, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863_K1_H1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE_H0 , VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; lut40152 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40154 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE_H0 ) ); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); selmux2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863_K0K1MUX ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[13]/GATE_H0 ) , .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_863_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40154 ( input A, B, C, D, output Z ); ROM16X1A #(16'hC0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_SLICE_864 ( input C1, B1, A1, D0, C0, B0, A0, DI0, M0, CE, CLK, output OFX0, Q0 ); wire GNDI, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864_K1_H1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE_H0 , VCCI, CLK_NOTIN, DI0_dly, CLK_dly, CE_dly; lut40152 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40153 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE_H0 ) ); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[14] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); selmux2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864_K0K1MUX ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14[14]/GATE_H0 ) , .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/SLICE_864_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module BUS_Con_1_SLICE_866 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40155 \BUS_Con_1/state_ns_1_0_.m3_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40156 \BUS_Con_1/cmd_valid_out_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/cmd_valid_out ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40155 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3301) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40156 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_SLICE_867 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40122 \CPLD_Reg_1/state_RNI7UVD[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40157 \CPLD_Reg_1/regtable[1]_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40157 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0ACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_SLICE_868 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40025 \CPLD_Reg_1/err_flag8_1_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40137 \CPLD_Reg_1/rvalid_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/rvalid_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_869 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40158 \CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40159 \CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/err_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40158 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40159 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCF8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_878 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; lut40160 \CPLD_Con_1/PMU_OC_3d[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40160 \CPLD_Con_1/PMU_OC_3d[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Con_1/PMU_OC_3[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Con_1/PMU_OC_3[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40160 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0D08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_879 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; lut40160 \CPLD_Con_1/PMU_OC_3_RNO[21] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40160 \CPLD_Con_1/PMU_OC_3d[17] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Con_1/PMU_OC_3[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Con_1/PMU_OC_3[17] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_880 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40161 \CPLD_Con_1/RC_LOFS_6_1_0_.m16_0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40162 \CPLD_Con_1/RC_LOFS_6_1_0_.N_17_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/RC_ISel ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40161 ( input A, B, C, D, output Z ); ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40162 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0015) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_881 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40163 \CPLD_Con_1/RC_LOFS_6_1_0_.m9_0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40164 \CPLD_Con_1/RC_LOFS_6_1_0_.N_10_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/RC_LOFS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40163 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0ACE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40164 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0051) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_SLICE_883 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_883/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 , \CPLD_Reg_1/SLICE_883/CPLD_Reg_1/SLICE_883_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[0]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_883/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40166 \CPLD_Reg_1/SLICE_883_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_883/CPLD_Reg_1/SLICE_883_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_883_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_883/CPLD_Reg_1/SLICE_883_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_883/CPLD_Reg_1/rdata_reg_2_8[0]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_883_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40165 ( input A, B, C, D, output Z ); ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40166 ( input A, B, C, D, output Z ); ROM16X1A #(16'hACAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_SLICE_884 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_884/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 , \CPLD_Reg_1/SLICE_884/CPLD_Reg_1/SLICE_884_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[1]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_884/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_884_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_884/CPLD_Reg_1/SLICE_884_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_884_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_884/CPLD_Reg_1/SLICE_884_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_884/CPLD_Reg_1/rdata_reg_2_8[1]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_884_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40167 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_SLICE_885 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_885/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 , \CPLD_Reg_1/SLICE_885/CPLD_Reg_1/SLICE_885_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[2]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_885/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_885_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_885/CPLD_Reg_1/SLICE_885_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_885_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_885/CPLD_Reg_1/SLICE_885_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_885/CPLD_Reg_1/rdata_reg_2_8[2]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_885_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_886 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_886/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 , \CPLD_Reg_1/SLICE_886/CPLD_Reg_1/SLICE_886_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[3]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_886/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_886_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_886/CPLD_Reg_1/SLICE_886_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_886_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_886/CPLD_Reg_1/SLICE_886_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_886/CPLD_Reg_1/rdata_reg_2_8[3]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_886_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_887 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_887/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 , \CPLD_Reg_1/SLICE_887/CPLD_Reg_1/SLICE_887_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[4]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_887/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_887_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_887/CPLD_Reg_1/SLICE_887_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_887_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_887/CPLD_Reg_1/SLICE_887_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_887/CPLD_Reg_1/rdata_reg_2_8[4]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_887_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_888 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_888/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 , \CPLD_Reg_1/SLICE_888/CPLD_Reg_1/SLICE_888_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[5]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_888/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_888_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_888/CPLD_Reg_1/SLICE_888_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_888_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_888/CPLD_Reg_1/SLICE_888_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_888/CPLD_Reg_1/rdata_reg_2_8[5]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_888_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_889 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_889/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 , \CPLD_Reg_1/SLICE_889/CPLD_Reg_1/SLICE_889_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[6]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_889/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_889_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_889/CPLD_Reg_1/SLICE_889_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_889_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_889/CPLD_Reg_1/SLICE_889_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_889/CPLD_Reg_1/rdata_reg_2_8[6]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_889_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_890 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_890/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 , \CPLD_Reg_1/SLICE_890/CPLD_Reg_1/SLICE_890_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[7]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_890/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_890_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_890/CPLD_Reg_1/SLICE_890_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_890_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_890/CPLD_Reg_1/SLICE_890_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_890/CPLD_Reg_1/rdata_reg_2_8[7]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_890_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_891 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_891/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 , \CPLD_Reg_1/SLICE_891/CPLD_Reg_1/SLICE_891_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[8]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_891/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_891_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_891/CPLD_Reg_1/SLICE_891_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_891_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_891/CPLD_Reg_1/SLICE_891_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_891/CPLD_Reg_1/rdata_reg_2_8[8]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_891_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_892 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_892/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 , \CPLD_Reg_1/SLICE_892/CPLD_Reg_1/SLICE_892_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[9]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_892/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_892_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_892/CPLD_Reg_1/SLICE_892_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_892_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_892/CPLD_Reg_1/SLICE_892_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_892/CPLD_Reg_1/rdata_reg_2_8[9]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_892_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_893 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_893/CPLD_Reg_1/rdata_reg_2_8[10]/GATE_H1 , \CPLD_Reg_1/SLICE_893/CPLD_Reg_1/SLICE_893_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[10]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_893/CPLD_Reg_1/rdata_reg_2_8[10]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_893_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_893/CPLD_Reg_1/SLICE_893_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_893_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_893/CPLD_Reg_1/SLICE_893_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_893/CPLD_Reg_1/rdata_reg_2_8[10]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_893_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_894 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_894/CPLD_Reg_1/rdata_reg_2_8[11]/GATE_H1 , \CPLD_Reg_1/SLICE_894/CPLD_Reg_1/SLICE_894_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[11]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_894/CPLD_Reg_1/rdata_reg_2_8[11]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_894_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_894/CPLD_Reg_1/SLICE_894_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_894_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_894/CPLD_Reg_1/SLICE_894_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_894/CPLD_Reg_1/rdata_reg_2_8[11]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_894_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_895 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_895/CPLD_Reg_1/rdata_reg_2_8[12]/GATE_H1 , \CPLD_Reg_1/SLICE_895/CPLD_Reg_1/SLICE_895_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[12]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_895/CPLD_Reg_1/rdata_reg_2_8[12]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_895_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_895/CPLD_Reg_1/SLICE_895_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_895_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_895/CPLD_Reg_1/SLICE_895_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_895/CPLD_Reg_1/rdata_reg_2_8[12]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_895_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_896 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_896/CPLD_Reg_1/rdata_reg_2_8[13]/GATE_H1 , \CPLD_Reg_1/SLICE_896/CPLD_Reg_1/SLICE_896_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[13]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_896/CPLD_Reg_1/rdata_reg_2_8[13]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_896_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_896/CPLD_Reg_1/SLICE_896_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[13] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_896_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_896/CPLD_Reg_1/SLICE_896_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_896/CPLD_Reg_1/rdata_reg_2_8[13]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_896_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_897 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_897/CPLD_Reg_1/rdata_reg_2_8[14]/GATE_H1 , \CPLD_Reg_1/SLICE_897/CPLD_Reg_1/SLICE_897_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[14]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_897/CPLD_Reg_1/rdata_reg_2_8[14]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_897_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_897/CPLD_Reg_1/SLICE_897_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_897_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_897/CPLD_Reg_1/SLICE_897_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_897/CPLD_Reg_1/rdata_reg_2_8[14]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_897_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_898 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_898/CPLD_Reg_1/rdata_reg_2_8[15]/GATE_H1 , \CPLD_Reg_1/SLICE_898/CPLD_Reg_1/SLICE_898_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[15]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_898/CPLD_Reg_1/rdata_reg_2_8[15]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_898_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_898/CPLD_Reg_1/SLICE_898_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[15] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_898_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_898/CPLD_Reg_1/SLICE_898_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_898/CPLD_Reg_1/rdata_reg_2_8[15]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_898_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_899 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_899/CPLD_Reg_1/rdata_reg_2_8[16]/GATE_H1 , \CPLD_Reg_1/SLICE_899/CPLD_Reg_1/SLICE_899_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[16]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_899/CPLD_Reg_1/rdata_reg_2_8[16]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_899_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_899/CPLD_Reg_1/SLICE_899_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[16] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_899_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_899/CPLD_Reg_1/SLICE_899_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_899/CPLD_Reg_1/rdata_reg_2_8[16]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_899_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_900 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_900/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 , \CPLD_Reg_1/SLICE_900/CPLD_Reg_1/SLICE_900_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[17]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_900/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_900_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_900/CPLD_Reg_1/SLICE_900_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[17] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_900_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_900/CPLD_Reg_1/SLICE_900_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_900/CPLD_Reg_1/rdata_reg_2_8[17]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_900_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_901 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_901/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 , \CPLD_Reg_1/SLICE_901/CPLD_Reg_1/SLICE_901_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[18]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_901/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_901_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_901/CPLD_Reg_1/SLICE_901_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[18] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_901_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_901/CPLD_Reg_1/SLICE_901_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_901/CPLD_Reg_1/rdata_reg_2_8[18]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_901_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_902 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_902/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 , \CPLD_Reg_1/SLICE_902/CPLD_Reg_1/SLICE_902_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[19]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_902/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_902_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_902/CPLD_Reg_1/SLICE_902_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[19] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_902_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_902/CPLD_Reg_1/SLICE_902_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_902/CPLD_Reg_1/rdata_reg_2_8[19]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_902_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_903 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_903/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 , \CPLD_Reg_1/SLICE_903/CPLD_Reg_1/SLICE_903_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[20]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_903/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_903_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_903/CPLD_Reg_1/SLICE_903_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[20] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_903_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_903/CPLD_Reg_1/SLICE_903_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_903/CPLD_Reg_1/rdata_reg_2_8[20]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_903_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_904 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_904/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 , \CPLD_Reg_1/SLICE_904/CPLD_Reg_1/SLICE_904_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[21]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_904/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_904_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_904/CPLD_Reg_1/SLICE_904_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[21] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_904_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_904/CPLD_Reg_1/SLICE_904_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_904/CPLD_Reg_1/rdata_reg_2_8[21]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_904_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_905 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_905/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 , \CPLD_Reg_1/SLICE_905/CPLD_Reg_1/SLICE_905_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[22]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_905/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_905_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_905/CPLD_Reg_1/SLICE_905_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[22] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_905_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_905/CPLD_Reg_1/SLICE_905_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_905/CPLD_Reg_1/rdata_reg_2_8[22]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_905_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_906 ( input C1, B1, A1, C0, B0, A0, DI1, M1, M0, FXB, FXA, CE, CLK, output OFX0, Q1, OFX1 ); wire GNDI, \CPLD_Reg_1/SLICE_906/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 , \CPLD_Reg_1/SLICE_906/CPLD_Reg_1/SLICE_906_K0_H0 , VCCI, DI1_dly, CLK_dly, CE_dly; lut40165 \CPLD_Reg_1/rdata_reg_2_8[23]/GATE ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_906/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 )); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/SLICE_906_K0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/SLICE_906/CPLD_Reg_1/SLICE_906_K0_H0 )); vmuxregsre \CPLD_Reg_1/rdata_reg[23] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); selmux2 \CPLD_Reg_1/SLICE_906_K0K1MUX ( .D0(\CPLD_Reg_1/SLICE_906/CPLD_Reg_1/SLICE_906_K0_H0 ), .D1(\CPLD_Reg_1/SLICE_906/CPLD_Reg_1/rdata_reg_2_8[23]/GATE_H1 ), .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/SLICE_906_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_907 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40168 \BUS_Con_1/addr_out_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40168 \BUS_Con_1/addr_out_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \BUS_Con_1/addr_out[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40168 ( input A, B, C, D, output Z ); ROM16X1A #(16'h00D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_908 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40168 \BUS_Con_1/addr_out_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40168 \BUS_Con_1/addr_out_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \BUS_Con_1/addr_out[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_909 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40168 \BUS_Con_1/addr_out_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40168 \BUS_Con_1/addr_out_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \BUS_Con_1/addr_out[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_910 ( input D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40168 \BUS_Con_1/addr_out_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_911 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40168 \BUS_Con_1/addr_out_0_rep2_RNO ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40168 \BUS_Con_1/addr_out_0_rep1_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out_0_rep2 ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \BUS_Con_1/addr_out_0_rep1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_912 ( input D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0 ); wire VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40168 \BUS_Con_1/addr_out_1_rep1_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out_1_rep1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_913 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40168 \BUS_Con_1/addr_out_2_rep2_RNO ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40168 \BUS_Con_1/addr_out_2_rep1_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out_2_rep2 ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \BUS_Con_1/addr_out_2_rep1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_914 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40168 \BUS_Con_1/addr_out_3_rep2_RNO ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40168 \BUS_Con_1/addr_out_3_rep1_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out_3_rep2 ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \BUS_Con_1/addr_out_3_rep1 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_915 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40168 \BUS_Con_1/addr_out_fast_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40168 \BUS_Con_1/addr_out_fast_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out_fast[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \BUS_Con_1/addr_out_fast[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_916 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, LSR_NOTIN, DI1_dly, CLK_dly, DI0_dly, CE_dly, LSR_dly; lut40168 \BUS_Con_1/addr_out_fast_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40168 \BUS_Con_1/addr_out_fast_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/addr_out_fast[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \BUS_Con_1/addr_out_fast[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_917 ( input B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40119 \CPLD_Reg_1/busy_flag_1_i_a3_0_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40169 \CPLD_Reg_1/busy_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/busy_flag ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40169 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3DFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_930 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, DI0_dly, CLK_dly, CE_dly, LSR_dly; lut40137 \BUS_Con_1/wr_flag_RNIA5K7 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40161 \BUS_Con_1/wr_out_8_iv ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/wr_out ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module xo2chub_SLICE_947 ( input C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40170 \xo2chub/jtdo1_1_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \xo2chub/ip_enable[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/ip_enable[9] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40170 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1616) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module xo2chub_SLICE_948 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40039 \xo2chub/id_enable_0_sqmuxa ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40039 \xo2chub/er1_shift_reg8 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \xo2chub/ip_enable[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/ip_enable[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module SLICE_949 ( input B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40171 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40030 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/pre_trig_cap_reg_11_iv_0_0_a2[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \xo2chub/ip_enable[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/ip_enable[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40171 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_950 ( input D1, C1, B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; lut40041 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_RNIIDUQ1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40021 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/even_parity_RNI77DO ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \xo2chub/jce1_d1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module CPLD_Con_1_un1_i_DC_Con3_2lto8_d_SLICE_951 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); wire \CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951/CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951_K1_H1 , \CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951/CPLD_Con_1/un1_i_DC_Con3_2lto8_d/GATE_H0 ; lut40172 \CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951/CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951_K1_H1 ) ); lut40172 \CPLD_Con_1/un1_i_DC_Con3_2lto8_d/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951/CPLD_Con_1/un1_i_DC_Con3_2lto8_d/GATE_H0 ) ); selmux2 \CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951_K0K1MUX ( .D0(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951/CPLD_Con_1/un1_i_DC_Con3_2lto8_d/GATE_H0 ) , .D1(\CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951/CPLD_Con_1/un1_i_DC_Con3_2lto8_d/SLICE_951_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40172 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEAEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_rdata_reg_2_11_20__SLICE_952 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[20]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[20]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952/CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[20]/SLICE_952_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module lut40173 ( input A, B, C, D, output Z ); ROM16X1A #(16'hD8D8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_rdata_reg_2_10_20__SLICE_953 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[20]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953/CPLD_Reg_1/rdata_reg_2_10[20]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953/CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[20]/SLICE_953_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_20__SLICE_954 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[20]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954/CPLD_Reg_1/rdata_reg_2_9[20]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954/CPLD_Reg_1/rdata_reg_2_9[20]/SLICE_954_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40174 ( input A, B, C, D, output Z ); ROM16X1A #(16'hE4E4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_rdata_reg_2_9_0__SLICE_955 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ; lut40167 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40175 \CPLD_Reg_1/rdata_reg_2_9[0]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955/CPLD_Reg_1/rdata_reg_2_9[0]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955/CPLD_Reg_1/rdata_reg_2_9[0]/SLICE_955_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40175 ( input A, B, C, D, output Z ); ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_rdata_reg_2_10_0__SLICE_956 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40166 \CPLD_Reg_1/rdata_reg_2_10[0]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956/CPLD_Reg_1/rdata_reg_2_10[0]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956/CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[0]/SLICE_956_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_0__SLICE_957 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[0]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957/CPLD_Reg_1/rdata_reg_2_11[0]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957/CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[0]/SLICE_957_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_1__SLICE_958 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ; lut40167 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[1]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958/CPLD_Reg_1/rdata_reg_2_9[1]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958/CPLD_Reg_1/rdata_reg_2_9[1]/SLICE_958_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_1__SLICE_959 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[1]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959/CPLD_Reg_1/rdata_reg_2_10[1]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959/CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[1]/SLICE_959_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_1__SLICE_960 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[1]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960/CPLD_Reg_1/rdata_reg_2_11[1]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960/CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[1]/SLICE_960_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_2__SLICE_961 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ; lut40167 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[2]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961/CPLD_Reg_1/rdata_reg_2_9[2]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961/CPLD_Reg_1/rdata_reg_2_9[2]/SLICE_961_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_2__SLICE_962 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[2]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962/CPLD_Reg_1/rdata_reg_2_10[2]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962/CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[2]/SLICE_962_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_2__SLICE_963 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[2]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963/CPLD_Reg_1/rdata_reg_2_11[2]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963/CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[2]/SLICE_963_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_3__SLICE_964 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ; lut40167 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[3]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964/CPLD_Reg_1/rdata_reg_2_9[3]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964/CPLD_Reg_1/rdata_reg_2_9[3]/SLICE_964_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_3__SLICE_965 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[3]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965/CPLD_Reg_1/rdata_reg_2_10[3]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965/CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[3]/SLICE_965_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_3__SLICE_966 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[3]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966/CPLD_Reg_1/rdata_reg_2_11[3]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966/CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[3]/SLICE_966_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_4__SLICE_967 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ; lut40167 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[4]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967/CPLD_Reg_1/rdata_reg_2_9[4]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967/CPLD_Reg_1/rdata_reg_2_9[4]/SLICE_967_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_4__SLICE_968 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[4]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968/CPLD_Reg_1/rdata_reg_2_10[4]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968/CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[4]/SLICE_968_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_4__SLICE_969 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[4]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969/CPLD_Reg_1/rdata_reg_2_11[4]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969/CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[4]/SLICE_969_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_5__SLICE_970 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ; lut40167 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970/CPLD_Reg_1/rdata_reg_2_9[5]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970/CPLD_Reg_1/rdata_reg_2_9[5]/SLICE_970_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_5__SLICE_971 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971/CPLD_Reg_1/rdata_reg_2_10[5]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971/CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[5]/SLICE_971_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_5__SLICE_972 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[5]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972/CPLD_Reg_1/rdata_reg_2_11[5]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972/CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[5]/SLICE_972_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_6__SLICE_973 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ; lut40167 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[6]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973/CPLD_Reg_1/rdata_reg_2_9[6]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973/CPLD_Reg_1/rdata_reg_2_9[6]/SLICE_973_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_6__SLICE_974 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[6]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974/CPLD_Reg_1/rdata_reg_2_10[6]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974/CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[6]/SLICE_974_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_6__SLICE_975 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[6]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975/CPLD_Reg_1/rdata_reg_2_11[6]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975/CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[6]/SLICE_975_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_7__SLICE_976 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ; lut40167 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[7]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976/CPLD_Reg_1/rdata_reg_2_9[7]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976/CPLD_Reg_1/rdata_reg_2_9[7]/SLICE_976_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_7__SLICE_977 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[7]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977/CPLD_Reg_1/rdata_reg_2_10[7]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977/CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[7]/SLICE_977_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_7__SLICE_978 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[7]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978/CPLD_Reg_1/rdata_reg_2_11[7]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978/CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[7]/SLICE_978_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_8__SLICE_979 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[8]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979/CPLD_Reg_1/rdata_reg_2_9[8]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979/CPLD_Reg_1/rdata_reg_2_9[8]/SLICE_979_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_8__SLICE_980 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[8]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980/CPLD_Reg_1/rdata_reg_2_10[8]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980/CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[8]/SLICE_980_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_8__SLICE_981 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[8]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981/CPLD_Reg_1/rdata_reg_2_11[8]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981/CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[8]/SLICE_981_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_9__SLICE_982 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[9]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982/CPLD_Reg_1/rdata_reg_2_9[9]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982/CPLD_Reg_1/rdata_reg_2_9[9]/SLICE_982_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_9__SLICE_983 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[9]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983/CPLD_Reg_1/rdata_reg_2_10[9]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983/CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[9]/SLICE_983_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_9__SLICE_984 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[9]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984/CPLD_Reg_1/rdata_reg_2_11[9]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984/CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[9]/SLICE_984_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_10__SLICE_985 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985/CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985/CPLD_Reg_1/rdata_reg_2_9[10]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985/CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[10]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985/CPLD_Reg_1/rdata_reg_2_9[10]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985/CPLD_Reg_1/rdata_reg_2_9[10]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985/CPLD_Reg_1/rdata_reg_2_9[10]/SLICE_985_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_10__SLICE_986 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986/CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986/CPLD_Reg_1/rdata_reg_2_10[10]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986/CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[10]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986/CPLD_Reg_1/rdata_reg_2_10[10]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986/CPLD_Reg_1/rdata_reg_2_10[10]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986/CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[10]/SLICE_986_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_10__SLICE_987 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987/CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987/CPLD_Reg_1/rdata_reg_2_11[10]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987/CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[10]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987/CPLD_Reg_1/rdata_reg_2_11[10]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987/CPLD_Reg_1/rdata_reg_2_11[10]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987/CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[10]/SLICE_987_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_11__SLICE_988 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[11]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988/CPLD_Reg_1/rdata_reg_2_9[11]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988/CPLD_Reg_1/rdata_reg_2_9[11]/SLICE_988_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_11__SLICE_989 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989/CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989/CPLD_Reg_1/rdata_reg_2_10[11]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989/CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[11]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989/CPLD_Reg_1/rdata_reg_2_10[11]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989/CPLD_Reg_1/rdata_reg_2_10[11]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989/CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[11]/SLICE_989_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_11__SLICE_990 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[11]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990/CPLD_Reg_1/rdata_reg_2_11[11]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990/CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[11]/SLICE_990_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_12__SLICE_991 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[12]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991/CPLD_Reg_1/rdata_reg_2_9[12]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991/CPLD_Reg_1/rdata_reg_2_9[12]/SLICE_991_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_12__SLICE_992 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992/CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992/CPLD_Reg_1/rdata_reg_2_10[12]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992/CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[12]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992/CPLD_Reg_1/rdata_reg_2_10[12]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992/CPLD_Reg_1/rdata_reg_2_10[12]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992/CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[12]/SLICE_992_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_12__SLICE_993 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[12]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993/CPLD_Reg_1/rdata_reg_2_11[12]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993/CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[12]/SLICE_993_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_13__SLICE_994 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994/CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994/CPLD_Reg_1/rdata_reg_2_9[13]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994/CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[13]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994/CPLD_Reg_1/rdata_reg_2_9[13]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994/CPLD_Reg_1/rdata_reg_2_9[13]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994/CPLD_Reg_1/rdata_reg_2_9[13]/SLICE_994_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_13__SLICE_995 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995/CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995/CPLD_Reg_1/rdata_reg_2_10[13]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995/CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[13]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995/CPLD_Reg_1/rdata_reg_2_10[13]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995/CPLD_Reg_1/rdata_reg_2_10[13]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995/CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[13]/SLICE_995_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_13__SLICE_996 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996/CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996/CPLD_Reg_1/rdata_reg_2_11[13]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996/CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[13]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996/CPLD_Reg_1/rdata_reg_2_11[13]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996/CPLD_Reg_1/rdata_reg_2_11[13]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996/CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[13]/SLICE_996_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_14__SLICE_997 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[14]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997/CPLD_Reg_1/rdata_reg_2_9[14]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997/CPLD_Reg_1/rdata_reg_2_9[14]/SLICE_997_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_14__SLICE_998 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998/CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998/CPLD_Reg_1/rdata_reg_2_10[14]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998/CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[14]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998/CPLD_Reg_1/rdata_reg_2_10[14]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998/CPLD_Reg_1/rdata_reg_2_10[14]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998/CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[14]/SLICE_998_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_14__SLICE_999 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[14]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999/CPLD_Reg_1/rdata_reg_2_11[14]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999/CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[14]/SLICE_999_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_15__SLICE_1000 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[15]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000/CPLD_Reg_1/rdata_reg_2_9[15]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000/CPLD_Reg_1/rdata_reg_2_9[15]/SLICE_1000_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_15__SLICE_1001 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001/CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001/CPLD_Reg_1/rdata_reg_2_10[15]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001/CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[15]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001/CPLD_Reg_1/rdata_reg_2_10[15]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001/CPLD_Reg_1/rdata_reg_2_10[15]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001/CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[15]/SLICE_1001_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_15__SLICE_1002 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[15]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002/CPLD_Reg_1/rdata_reg_2_11[15]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002/CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[15]/SLICE_1002_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_16__SLICE_1003 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[16]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003/CPLD_Reg_1/rdata_reg_2_9[16]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003/CPLD_Reg_1/rdata_reg_2_9[16]/SLICE_1003_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_16__SLICE_1004 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004/CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004/CPLD_Reg_1/rdata_reg_2_10[16]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004/CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[16]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004/CPLD_Reg_1/rdata_reg_2_10[16]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004/CPLD_Reg_1/rdata_reg_2_10[16]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004/CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[16]/SLICE_1004_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_16__SLICE_1005 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[16]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005/CPLD_Reg_1/rdata_reg_2_11[16]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005/CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[16]/SLICE_1005_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_17__SLICE_1006 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[17]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006/CPLD_Reg_1/rdata_reg_2_9[17]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006/CPLD_Reg_1/rdata_reg_2_9[17]/SLICE_1006_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_17__SLICE_1007 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[17]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007/CPLD_Reg_1/rdata_reg_2_10[17]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007/CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[17]/SLICE_1007_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_17__SLICE_1008 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[17]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008/CPLD_Reg_1/rdata_reg_2_11[17]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008/CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[17]/SLICE_1008_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_18__SLICE_1009 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[18]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009/CPLD_Reg_1/rdata_reg_2_9[18]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009/CPLD_Reg_1/rdata_reg_2_9[18]/SLICE_1009_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_18__SLICE_1010 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[18]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010/CPLD_Reg_1/rdata_reg_2_10[18]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010/CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[18]/SLICE_1010_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_18__SLICE_1011 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[18]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011/CPLD_Reg_1/rdata_reg_2_11[18]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011/CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[18]/SLICE_1011_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_19__SLICE_1012 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[19]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012/CPLD_Reg_1/rdata_reg_2_9[19]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012/CPLD_Reg_1/rdata_reg_2_9[19]/SLICE_1012_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_19__SLICE_1013 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[19]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013/CPLD_Reg_1/rdata_reg_2_10[19]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013/CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[19]/SLICE_1013_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_19__SLICE_1014 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[19]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014/CPLD_Reg_1/rdata_reg_2_11[19]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014/CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[19]/SLICE_1014_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_21__SLICE_1015 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[21]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015/CPLD_Reg_1/rdata_reg_2_9[21]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015/CPLD_Reg_1/rdata_reg_2_9[21]/SLICE_1015_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_21__SLICE_1016 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[21]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016/CPLD_Reg_1/rdata_reg_2_10[21]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016/CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[21]/SLICE_1016_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_21__SLICE_1017 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[21]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017/CPLD_Reg_1/rdata_reg_2_11[21]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017/CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[21]/SLICE_1017_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_22__SLICE_1018 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[22]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018/CPLD_Reg_1/rdata_reg_2_9[22]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018/CPLD_Reg_1/rdata_reg_2_9[22]/SLICE_1018_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_22__SLICE_1019 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[22]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019/CPLD_Reg_1/rdata_reg_2_10[22]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019/CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[22]/SLICE_1019_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_22__SLICE_1020 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[22]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020/CPLD_Reg_1/rdata_reg_2_11[22]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020/CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[22]/SLICE_1020_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_9_23__SLICE_1021 ( input C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021_K1_H1 , \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ; lut40174 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_9[23]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021/CPLD_Reg_1/rdata_reg_2_9[23]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021/CPLD_Reg_1/rdata_reg_2_9[23]/SLICE_1021_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_10_23__SLICE_1022 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022_K1_H1 , \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ; lut40165 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40167 \CPLD_Reg_1/rdata_reg_2_10[23]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022/CPLD_Reg_1/rdata_reg_2_10[23]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022/CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_10[23]/SLICE_1022_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_rdata_reg_2_11_23__SLICE_1023 ( input C1, B1, A1, C0, B0, A0, M1, M0, FXB, FXA, output OFX0, OFX1 ); wire GNDI, \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023_K1_H1 , \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ; lut40173 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40165 \CPLD_Reg_1/rdata_reg_2_11[23]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ) ); selmux2 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023_K0K1MUX ( .D0(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023/CPLD_Reg_1/rdata_reg_2_11[23]/GATE_H0 ) , .D1(\CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023/CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023_K1_H1 ) , .SD(M0), .Z(OFX0)); selmux2 \CPLD_Reg_1/rdata_reg_2_11[23]/SLICE_1023_FXMUX ( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module BUS_Con_1_miso_shift_1_sqmuxa_i_0_SLICE_1024 ( input C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); wire GNDI, \BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024/BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024_K1_H1 , \BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024/BUS_Con_1/miso_shift_1_sqmuxa_i_0/GATE_H0 ; lut40176 \BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024/BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40059 \BUS_Con_1/miso_shift_1_sqmuxa_i_0/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024/BUS_Con_1/miso_shift_1_sqmuxa_i_0/GATE_H0 ) ); selmux2 \BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024_K0K1MUX ( .D0(\BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024/BUS_Con_1/miso_shift_1_sqmuxa_i_0/GATE_H0 ) , .D1(\BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024/BUS_Con_1/miso_shift_1_sqmuxa_i_0/SLICE_1024_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40176 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_tu_0_c_3_SLICE_1025 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); wire \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025_K1_H1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE_H0 ; lut40177 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025_K1_H1 ) ); lut40178 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE_H0 ) ); selmux2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025_K0K1MUX ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/GATE_H0 ) , .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_3/SLICE_1025_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40177 ( input A, B, C, D, output Z ); ROM16X1A #(16'hC404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40178 ( input A, B, C, D, output Z ); ROM16X1A #(16'h02F9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_addr_RNICFU83_0__SLICE_1026 ( input C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); wire GNDI, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026_K1_H1 , \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/GATE_H0 ; lut40179 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026_K1_H1 ) ); gnd DRIVEGND( .PWR0(GNDI)); lut40180 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/GATE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/GATE_H0 ) ); selmux2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026_K0K1MUX ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/GATE_H0 ) , .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_RNICFU83[0]/SLICE_1026_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40179 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40180 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5554) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_jtag_int_u_shift_reg_11_0__SLICE_1027 ( input D1, C1, B1, A1, C0, B0, A0, M0, output OFX0 ); wire \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027_K1_H1 , GNDI, \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/GATE_H0 ; lut40181 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027_K1_H1 ) ); lut40173 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/GATE_H0 ) ); gnd DRIVEGND( .PWR0(GNDI)); selmux2 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027_K0K1MUX ( .D0(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/GATE_H0 ) , .D1(\RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027/RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11[0]/SLICE_1027_K1_H1 ) , .SD(M0), .Z(OFX0)); specify (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40181 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module xo2chub_SLICE_1028 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, output OFX0 ); wire \xo2chub/SLICE_1028/xo2chub/SLICE_1028_K1_H1 , \xo2chub/SLICE_1028/xo2chub/genblk1.jtaghub_rom_0_0_0_H0 ; lut40057 \xo2chub/SLICE_1028_K1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(\xo2chub/SLICE_1028/xo2chub/SLICE_1028_K1_H1 )); lut40182 \xo2chub/genblk1.jtaghub_rom_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(\xo2chub/SLICE_1028/xo2chub/genblk1.jtaghub_rom_0_0_0_H0 )); selmux2 \xo2chub/SLICE_1028_K0K1MUX ( .D0(\xo2chub/SLICE_1028/xo2chub/genblk1.jtaghub_rom_0_0_0_H0 ), .D1(\xo2chub/SLICE_1028/xo2chub/SLICE_1028_K1_H1 ), .SD(M0), .Z(OFX0)); specify (D1 => OFX0) = (0:0:0,0:0:0); (C1 => OFX0) = (0:0:0,0:0:0); (B1 => OFX0) = (0:0:0,0:0:0); (A1 => OFX0) = (0:0:0,0:0:0); (D0 => OFX0) = (0:0:0,0:0:0); (C0 => OFX0) = (0:0:0,0:0:0); (B0 => OFX0) = (0:0:0,0:0:0); (A0 => OFX0) = (0:0:0,0:0:0); (M0 => OFX0) = (0:0:0,0:0:0); endspecify endmodule module lut40182 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0143) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1029 ( input D1, C1, B1, A1, M1, FXB, FXA, output OFX0, F1, OFX1 ); wire GNDI, \SLICE_1029/xo2chub/genblk1.jtaghub_rom_0_0_1_H0 ; lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40171 \xo2chub/genblk1.jtaghub_rom_0_0_1 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(\SLICE_1029/xo2chub/genblk1.jtaghub_rom_0_0_1_H0 )); gnd DRIVEGND( .PWR0(GNDI)); selmux20183 SLICE_1029_K0K1MUX( .D0(\SLICE_1029/xo2chub/genblk1.jtaghub_rom_0_0_1_H0 ), .Z(OFX0)); selmux2 SLICE_1029_FXMUX( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module selmux20183 ( input D0, output Z ); BUFBA INST1( .A(D0), .Z(Z)); endmodule module SLICE_1030 ( input B1, A1, M1, FXB, FXA, output OFX0, F1, OFX1 ); wire GNDI, \SLICE_1030/xo2chub/genblk1.jtaghub_rom_0_1_0_H0 ; lut40039 \BUS_Con_1/miso_shift9_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40171 \xo2chub/genblk1.jtaghub_rom_0_1_0 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(\SLICE_1030/xo2chub/genblk1.jtaghub_rom_0_1_0_H0 )); selmux20183 SLICE_1030_K0K1MUX( .D0(\SLICE_1030/xo2chub/genblk1.jtaghub_rom_0_1_0_H0 ), .Z(OFX0)); selmux2 SLICE_1030_FXMUX( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1031 ( input B1, A1, FXA, output F1, OFX1 ); wire GNDI; lut40027 \CPLD_Reg_1/o_err ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); selmux20183 \CPLD_Reg_1/SLICE_1031_FXMUX ( .D0(FXA), .Z(OFX1)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1032 ( input B1, A1, M1, FXB, FXA, output OFX0, F1, OFX1 ); wire GNDI, \SLICE_1032/xo2chub/genblk1.jtaghub_rom_1_0_0_H0 ; lut40119 \CPLD_Con_1/err_flag53lto4_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40171 \xo2chub/genblk1.jtaghub_rom_1_0_0 ( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(\SLICE_1032/xo2chub/genblk1.jtaghub_rom_1_0_0_H0 )); selmux20183 SLICE_1032_K0K1MUX( .D0(\SLICE_1032/xo2chub/genblk1.jtaghub_rom_1_0_0_H0 ), .Z(OFX0)); selmux2 SLICE_1032_FXMUX( .D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (M1 => OFX1) = (0:0:0,0:0:0); (FXB => OFX1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_1033 ( input B1, A1, M0, FXA, CE, LSR, CLK, output Q0, F1, OFX1 ); wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut40122 \CPLD_Con_1/dc_t_RNI5PFA[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_2_rep1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); selmux20183 \CPLD_Con_1/SLICE_1033_FXMUX ( .D0(FXA), .Z(OFX1)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_1034 ( input C1, B1, A1, FXA, output F1, OFX1 ); wire GNDI; lut40137 \CPLD_Con_1/un90_RC_RLSel.un90_RC_RLSel_c5_a0_2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); selmux20183 \CPLD_Con_1/SLICE_1034_FXMUX ( .D0(FXA), .Z(OFX1)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (FXA => OFX1) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1035 ( input D1, C1, B1, A1, M1, M0, LSR, CLK, output Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40184 \CPLD_Con_1/un1_en_t_c2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[188] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[187] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40184 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEC80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1036 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40185 \CPLD_Con_1/RC_RLSel_1_sqmuxa_3_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40186 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_axbxc3_RNIT3Q01 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[169] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40185 ( input A, B, C, D, output Z ); ROM16X1A #(16'h220A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40186 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1037 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40117 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40187 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/recv_reg[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40187 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1038 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40188 \CPLD_Con_1/io_RC9_RNIP70G4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40189 \CPLD_Con_1/exec_flag_rep1_RNI110M ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[142] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[141] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40188 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0E0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40189 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1039 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40190 \CPLD_Con_1/g0_48 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40191 \CPLD_Con_1/g0_48_sx ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[162] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[161] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40190 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5554) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40191 ( input A, B, C, D, output Z ); ROM16X1A #(16'h01FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_1040 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40192 \BUS_Con_1/un1_addr_out_0_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40193 \BUS_Con_1/state_RNIS4Q6[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_out[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/data_out[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40192 ( input A, B, C, D, output Z ); ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40193 ( input A, B, C, D, output Z ); ROM16X1A #(16'hDDD5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1041 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40194 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40195 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[7][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[7][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40194 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40195 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1042 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40196 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNI0T3K1[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40197 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_2[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40196 ( input A, B, C, D, output Z ); ROM16X1A #(16'hABAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40197 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1043 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40198 \CPLD_Con_1/DMM_en_cnst_0_a2[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40199 \CPLD_Con_1/un1_i_DC_Con1_1lto8_0_a2_0_RNIELNP ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[205] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[204] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40198 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40199 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0233) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1044 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40200 \CPLD_Con_1/un1_i_DC_Con3_1lto8_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40201 \CPLD_Con_1/DMM_en_26_0_RNO[11] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/recv_reg[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40200 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40201 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2220) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1045 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40202 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_c3_d_RNIE9DB_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40083 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_c3_d_RNIOTRB_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[62] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[61] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40202 ( input A, B, C, D, output Z ); ROM16X1A #(16'h02A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1046 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40203 \CPLD_Con_1/un45_RC_RLSel_m_0_a2_0[16] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40194 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[16] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/ip_enable[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/ip_enable[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40203 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0606) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1047 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut40204 \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40086 \CPLD_Con_1/RC_RLSel_13_0_iv_i_RNO_2[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40204 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1818) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1048 ( input C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; lut40205 \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40086 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/sclk_sync[1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40205 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8181) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1049 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40204 \CPLD_Con_1/un45_RC_RLSel_m_0_a2_0[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40194 \CPLD_Con_1/RC_RLSel_13_0_iv_i_RNO_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[2] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1050 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40206 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_axbxc3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40040 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_axbxc3_RNIKHQQ ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[59] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[58] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40206 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFE01) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1051 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40207 \CPLD_Con_1/un45_RC_RLSel_m_0_a2_0[12] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40127 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/er1_shift_reg[17] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/er1_shift_reg[16] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40207 ( input A, B, C, D, output Z ); ROM16X1A #(16'h6060) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1052 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; lut40207 \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[12] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40208 \CPLD_Con_1/RC_RLSel_13_iv_1[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40208 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1053 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40203 \CPLD_Con_1/un95_RC_RLSel_m_0_a2_0[16] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40209 \CPLD_Con_1/RC_RLSel_13_iv_1[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/er1_shift_reg[11] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/er1_shift_reg[10] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40209 ( input A, B, C, D, output Z ); ROM16X1A #(16'hBAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1054 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40194 \CPLD_Con_1/un1_exec_flag_5_i_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40210 \CPLD_Con_1/un1_exec_flag_5_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[203] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[202] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40210 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFF08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1055 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut40207 \CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[12] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40208 \CPLD_Con_1/RC_RLSel_13_iv_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1056 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; lut40203 \CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[16] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40209 \CPLD_Con_1/RC_RLSel_13_iv_0[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1057 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut40205 \CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40209 \CPLD_Con_1/RC_RLSel_13_iv_0[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1058 ( input C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut40204 \CPLD_Con_1/un70_RC_RLSel_m_0_a2_0[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40208 \CPLD_Con_1/RC_RLSel_13_iv_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0044 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1059 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40211 \CPLD_Con_1/PMU_OC_312lto8_0_a2_0_RNIVIPB2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40201 \CPLD_Con_1/PMU_OC_313_RNIC3P93 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[88] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[87] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40211 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1060 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40212 \CPLD_Con_1/DPS_m4_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40120 \CPLD_Con_1/DPS_FS_1_9_i_a2[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[42] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[41] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40212 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFD02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1061 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); lut40213 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVGIL1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40206 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40213 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFD57) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1062 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40031 \CPLD_Con_1/un1_i_DC_Con1_iv[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40095 \CPLD_Con_1/DMM_en_26_0_a2_0[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/recv_reg[25] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/recv_reg[24] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1063 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40214 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c9_a0_2_RNIEKJ11 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40200 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c9_a0_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[57] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[56] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40214 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1064 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut40215 \CPLD_Con_1/err_flag_en_0_a2_3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40216 \CPLD_Con_1/err_flag_en_0_a2_3_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \CPLD_Con_1/done_flag ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40215 ( input A, B, C, D, output Z ); ROM16X1A #(16'hC8CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40216 ( input A, B, C, D, output Z ); ROM16X1A #(16'h00A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1065 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40217 \CPLD_Con_1/g0_41 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40218 \CPLD_Con_1/g0_41_1_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[160] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40217 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40218 ( input A, B, C, D, output Z ); ROM16X1A #(16'h001F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_1066 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40117 \BUS_Con_1/data_ready17 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40219 \BUS_Con_1/un1_err_flag8 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_out[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/data_out[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40219 ( input A, B, C, D, output Z ); ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1067 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40026 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_RNI24Q31[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40220 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[10][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[10][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40220 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1068 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40221 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40222 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[10][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[10][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40221 ( input A, B, C, D, output Z ); ROM16X1A #(16'h09F9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40222 ( input A, B, C, D, output Z ); ROM16X1A #(16'h23AF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1069 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40055 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/ip_enable_bit_RNIBK203 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40223 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un4_jupdate_early_i_o2_RNI453R[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[8][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[8][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40223 ( input A, B, C, D, output Z ); ROM16X1A #(16'hC444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1070 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40085 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_RNI5CHP ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40224 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/full_reg_6_u_i_0_o2_RNIP85G1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[8][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[8][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40224 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1071 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40194 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_10[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40042 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[9][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[9][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1072 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_5[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40225 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40225 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1073 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40226 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40227 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40226 ( input A, B, C, D, output Z ); ROM16X1A #(16'h020A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40227 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1074 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40228 \CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40229 \CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0_N_3L3_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/recv_reg[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/recv_reg[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40228 ( input A, B, C, D, output Z ); ROM16X1A #(16'h777F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40229 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8A8A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1075 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40230 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_RNI1TUB1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40137 \CPLD_Con_1/g0_2_0_N_2L1 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[159] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[158] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40230 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1076 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40231 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40131 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/recv_reg[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40231 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAAA8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1077 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40232 \CPLD_Con_1/RC_VSel41_0_a2_RNI824V5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40131 \CPLD_Con_1/RC_VSel41_0_a2_RNI3HP41 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[117] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[116] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40232 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4CC4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1078 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40233 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i_RNO ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40086 \CPLD_Con_1/freq_t_fast_RNIL9BN2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[155] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[154] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40233 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1079 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40234 \CPLD_Con_1/freq_slot_flag_RNIBB605[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40025 \CPLD_Con_1/freq_slot_flag_RNIVIKB1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[146] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[145] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40234 ( input A, B, C, D, output Z ); ROM16X1A #(16'hC8C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1080 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40235 \CPLD_Con_1/dc_slot_flag_3_rep1_RNIHJ2H3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40236 \CPLD_Con_1/freq_t_fast_RNI015E4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/freq_t_fast[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \CPLD_Con_1/freq_t_fast[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40235 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7272) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40236 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1081 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40237 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c6_a0_1_RNIF4MU ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40238 \CPLD_Con_1/DPS_FS_3_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[59] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[58] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40237 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF708) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40238 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0041) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1082 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40191 \CPLD_Con_1/DMM_en_26_i_o2_0_o3[15] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40239 \CPLD_Con_1/DMM_en_26_i_o2_0_o3_RNIO4LA3[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[201] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[200] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40239 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1083 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40115 \CPLD_Con_1/freq_slot_flag_RNI6S8Q1_0[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40040 \CPLD_Con_1/freq_t_fast_RNIJMOK2[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[153] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[152] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_1084 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); lut40079 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c6_a0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40240 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c6_a0_1_RNI3PNV ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40240 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAAA6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1085 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40079 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c6_a0_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40240 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c6_a0_2_RNIUHVQ ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[86] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[85] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1086 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40040 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIEMT02_2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40240 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c6_a0_3_RNIOSA01 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[55] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[54] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1087 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40241 \CPLD_Con_1/DMM_en_cnst_0_a2_i_0[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40242 \CPLD_Con_1/DMM_en_cnst_0_a2_i_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[24] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[23] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40241 ( input A, B, C, D, output Z ); ROM16X1A #(16'hC3C7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40242 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1088 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40208 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNIH99G8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40236 \CPLD_Con_1/freq_t_fast_RNII6QS1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[151] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[150] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1089 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut40242 \CPLD_Con_1/err_flag89_2_RNISG5C2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40243 \CPLD_Con_1/DMM_en_26_0_am_RNO[13] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0028 \BUS_Con_1/wr_flag ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40243 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5551) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1090 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40119 \CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40244 \CPLD_Con_1/un1_i_DC_Con2lto8_1_0_a2_0_0_RNIH1JT ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[209] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[208] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40244 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1091 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40114 \CPLD_Con_1/un1_i_DC_Con1_1lto8_0_a2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40245 \CPLD_Con_1/DMM_en_26_0_a3_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/recv_reg[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40245 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0009) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1092 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40246 \CPLD_Con_1/RC_RLSel_1_sqmuxa_1_0_a2_0_RNITGOR_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40200 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/er1_shift_reg[19] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/er1_shift_reg[18] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40246 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1093 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40247 \CPLD_Con_1/RC_RLSel_1_sqmuxa_1_0_a2_0_RNITGOR_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40106 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO_0[17] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep2 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_rep1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40247 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1094 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40248 \CPLD_Con_1/RC_RLSel_13_0_iv_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40025 \CPLD_Con_1/RC_RLSel_13_0_iv_1_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40248 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1095 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40248 \CPLD_Con_1/RC_RLSel_13_iv_1[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40194 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/er1_shift_reg[15] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/er1_shift_reg[14] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module SLICE_1096 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40209 \CPLD_Con_1/RC_RLSel_13_0_iv_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40249 \CPLD_Con_1/RC_RLSel_13_0_iv_0_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40249 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1097 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40076 \CPLD_Con_1/RC_RLSel_13_0_iv_i_1[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40194 \CPLD_Con_1/RC_RLSel_13_0_iv_i_1_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1098 ( input C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; lut40250 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNI87G93 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40251 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNI1C7N4_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d2[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40250 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8282) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40251 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0028) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1099 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40233 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40252 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNI1C7N4 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[91] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[90] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40252 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1100 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40200 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40253 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNI1C7N4 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/input_a_d1[0] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[9] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40253 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1101 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40086 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_axbxc3_RNIH7QQ2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40252 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNI1C7N4_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[93] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[92] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1102 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40237 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40086 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIG0U22 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[40] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[3] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1103 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40204 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIHNDP_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40086 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIG0U22_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[42] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[41] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1104 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40203 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIHNDP_2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40086 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIG0U22_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[44] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[43] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1105 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40200 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_c5_a0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40254 \CPLD_Con_1/PMU_OC_4_4_38_i_RNISAJ31 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40254 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0220) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1106 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40203 \CPLD_Con_1/PMU_OC_4_4_35_0_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40255 \CPLD_Con_1/PMU_OC_4_4_35_0_a2_RNII6821 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[97] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[96] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40255 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1107 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; lut40233 \CPLD_Con_1/g0_50 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40256 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc7_RNIQUHT2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40256 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1108 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); lut40038 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc7_RNI1MA91 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40254 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc7_RNIQUHT2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1109 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40038 \CPLD_Con_1/PMU_OC_4_4_101_0_a4_RNI8SMN ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40256 \CPLD_Con_1/PMU_OC_4_4_101_0_a4_RNI15UB2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[93] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[92] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1110 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40257 \CPLD_Con_1/DMM_en_cnst_0_a2_i[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40258 \CPLD_Con_1/DMM_en_cnst_0_a2_i_RNI6AJU[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[22] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[21] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40257 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEAEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40258 ( input A, B, C, D, output Z ); ROM16X1A #(16'hB3B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1111 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40040 \CPLD_Con_1/io_RC10_i_0_o2_RNI8E281 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40259 \CPLD_Con_1/DMM_en_cnst_0_a2_RNINNEM3[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[209] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[208] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40259 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3A0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1112 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40094 \CPLD_Con_1/PMU_OC_1_0_sqmuxa_0_a2_0_a2_RNIISG01 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40260 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNINOLJ4 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[33] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[32] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40260 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7430) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1113 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; lut40021 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc5 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40261 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc5_RNI5N9R3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40261 ( input A, B, C, D, output Z ); ROM16X1A #(16'h20FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1114 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40119 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc3_RNI7MBE ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40208 \CPLD_Con_1/DMM_en_cnst_0_a2_RNIREHT2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[212] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[211] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1115 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40262 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNIP4ND1_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40263 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_RNI90D03[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[53] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[52] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40262 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2828) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40263 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1116 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40206 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_axbxc3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40263 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_RNI90D03_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[55] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[54] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1117 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40038 \CPLD_Con_1/PMU_OC_312lto8_0_a2_0_RNIVIPB2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40264 \CPLD_Con_1/PMU_OC_312lto8_0_a2_0_RNI4P9I7 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[84] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[83] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40264 ( input A, B, C, D, output Z ); ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1118 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40265 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_RNIEL8O5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40266 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[37] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[36] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40265 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40266 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1119 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40267 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5_RNIACKF1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40040 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNITD2B2_2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[51] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[50] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40267 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEBEB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1120 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40207 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIHNDP_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40040 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNITD2B2_1 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[4] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[49] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1121 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40205 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIHNDP ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40040 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNITD2B2_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[48] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[47] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1122 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40268 \CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40266 \CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[79] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[78] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40268 ( input A, B, C, D, output Z ); ROM16X1A #(16'hD000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1123 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; lut40116 \CPLD_Con_1/RC_Tx_1_sqmuxa_1_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40086 \CPLD_Con_1/PMU_OC_4_4_38_i_RNI3L2R ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[9] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module CPLD_Con_1_SLICE_1124 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; lut40269 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc6 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40194 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc5_RNISTJE ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40269 ( input A, B, C, D, output Z ); ROM16X1A #(16'hD2D2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1125 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40237 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc7 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40209 \CPLD_Con_1/DMM_en_cnst_0_a2_RNIPCHT2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[210] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1126 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40270 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40086 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_6 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[73] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[72] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40270 ( input A, B, C, D, output Z ); ROM16X1A #(16'h9999) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1127 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40206 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40106 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_8 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[77] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[76] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1128 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40271 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c3_0_1_RNIO6O52_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40025 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_10 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[6] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[69] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40271 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1E00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1129 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40272 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c3_0_1_RNIO6O52 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40038 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[66] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[65] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40272 ( input A, B, C, D, output Z ); ROM16X1A #(16'hE100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1130 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40233 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40254 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5_RNIR3292_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[53] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[52] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1131 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40120 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c5_RNIR3292 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40039 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNITD2B2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[46] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[45] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_1132 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); lut40025 \CPLD_Con_1/dc_t_RNICCDJ[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40086 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNI25RS4_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1133 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40104 \CPLD_Con_1/dc_slot_flag_fast_RNIUKT31[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40038 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNI56EI4 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[95] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[94] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_1134 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); lut40254 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNIBEMI2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40038 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNI25RS4 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1135 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40273 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c6_a0_1_RNII6O81 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40038 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNI56EI4_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[97] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[96] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40273 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1136 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut40206 \CPLD_Con_1/un90_RC_RLSel.un90_RC_RLSel_axbxc3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40209 \CPLD_Con_1/RC_RLSel_13_iv_1[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1137 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40038 \CPLD_Con_1/io_RC9_RNI05TL2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40162 \CPLD_Con_1/PMU_OC_3_0_sqmuxa_2_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[8] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[89] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1138 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40274 \CPLD_Con_1/err_flag_en_0_a2_6_mb_mb ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40275 \CPLD_Con_1/err_flag_en_0_o2_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[128] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[127] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40274 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEEE2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40275 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1139 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40039 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_axbxc3_RNI9478 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40200 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/ip_enable[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/ip_enable[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module SLICE_1140 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40078 \CPLD_Con_1/RC_RLSel_13_iv_i_1[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40038 \CPLD_Con_1/RC_RLSel_13_iv_i_1_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/er1_shift_reg[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/er1_shift_reg[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module SLICE_1141 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40212 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc7 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40117 \CPLD_Con_1/PMU_OC_4_4_101_a4_RNI8SMN_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[95] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[94] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1142 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40263 \CPLD_Con_1/DMM_en_cnst_0_a2_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40249 \CPLD_Con_1/DMM_en_cnst_0_a2[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[205] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[204] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1143 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40253 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c3_0_1_RNIQS951 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40025 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc7_RNIP2S03_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[82] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[81] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1144 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40276 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c3_0_1_RNIN1BF1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40117 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc7_RNIP2S03 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[80] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[7] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40276 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5401) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1145 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40277 \CPLD_Con_1/un1_RC_VSel41_1_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40248 \CPLD_Con_1/RC_RLSel_13_iv_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40277 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFEE9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1146 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; lut40251 \CPLD_Con_1/un90_RC_RLSel.un90_RC_RLSel_axbxc3_RNIEPJ01 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40209 \CPLD_Con_1/RC_RLSel_13_iv_1[13] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1147 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut40208 \CPLD_Con_1/RC_RLSel_13_iv_0[8] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40208 \CPLD_Con_1/RC_RLSel_13_iv_1[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1148 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; lut40278 \CPLD_Con_1/RC_RLSel_13_iv_0[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40208 \CPLD_Con_1/RC_RLSel_13_iv_1[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40278 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1149 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; lut40209 \CPLD_Con_1/RC_RLSel_13_iv_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40209 \CPLD_Con_1/RC_RLSel_13_iv_1[11] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1150 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40119 \CPLD_Con_1/DMM_en_26_i_a4_1_0[15] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40279 \CPLD_Con_1/DMM_en_26_i_1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[199] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[198] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40279 ( input A, B, C, D, output Z ); ROM16X1A #(16'h000E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1151 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40280 \CPLD_Con_1/err_flag75lto4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40281 \CPLD_Con_1/un1_exec_flag_1_0_o2_0_0_RNIDM3K1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[197] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[196] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40280 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40281 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1152 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); wire GNDI; lut40194 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc5_RNISTJE_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40030 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc7_RNICRT3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1153 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40282 \CPLD_Con_1/io_RC10_i_0_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40210 \CPLD_Con_1/un1_exec_flag_4_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40282 ( input A, B, C, D, output Z ); ROM16X1A #(16'hDDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1154 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40144 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_RNIGRLI1[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40202 \CPLD_Con_1/DPS_FS_3_9_i_a2_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[51] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[50] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1155 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40283 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_c3_d_RNIE9DB ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40106 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[17] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/ip_enable[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/ip_enable[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40283 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA802) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1156 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40284 \CPLD_Con_1/exec_flag_rep1_RNIRJ6J ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40285 \CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_c_d_RNINB1C1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[180] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40284 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4F4F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40285 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFCFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1157 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40233 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40286 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIJ1ER_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[31] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[30] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40286 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0014) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1158 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; lut40287 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO_0[16] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40288 \CPLD_Con_1/RC_RLSel_13_iv_1[16] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40287 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40288 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1159 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut40289 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO[17] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40278 \CPLD_Con_1/RC_RLSel_13_iv_1[17] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40289 ( input A, B, C, D, output Z ); ROM16X1A #(16'h6000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1160 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut40290 \CPLD_Con_1/RC_RLSel_1_sqmuxa_1_0_a2_0_RNITGOR ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40209 \CPLD_Con_1/RC_RLSel_13_iv_0[13] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_reg[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40290 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1161 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40040 \CPLD_Con_1/PMU_OC_1_0_sqmuxa_0_a2_0_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40094 \CPLD_Con_1/DMM_en_26_0_a3[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[29] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/recv_reg[28] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1162 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40291 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_o2_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40292 \CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_0_m2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[77] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[76] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40291 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFF78) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40292 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFDA8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1163 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut4 \CPLD_Con_1/RC_VSel39_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40040 \CPLD_Con_1/err_flag_en_0_a2_2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[3] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1164 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40117 \CPLD_Con_1/PMU_OC_4_4_101_a4_RNI8SMN_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40293 \CPLD_Con_1/PMU_OC_4_4_101_0_a4 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[91] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[90] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40293 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0909) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1165 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40083 \CPLD_Con_1/exec_flag_rep1_RNID4BO ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40210 \CPLD_Con_1/RC_Tx_0_sqmuxa_1_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[108] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[107] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1166 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40249 \CPLD_Con_1/un1_exec_flag_10_i_a2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40210 \CPLD_Con_1/un1_exec_flag_10_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[191] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[190] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1167 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40294 \CPLD_Con_1/err_flag45_i_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40038 \CPLD_Con_1/un1_exec_flag_4_i_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[201] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[200] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40294 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCCC4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1168 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40295 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc8 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40296 \CPLD_Con_1/err_flag_en_0_m2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[126] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[125] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40295 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7878) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40296 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5CFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1169 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40117 \CPLD_Con_1/PMU_OC_212lto8_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40039 \CPLD_Con_1/DMM_en_cnst_0_a2[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[203] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[202] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1170 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40191 \CPLD_Con_1/un1_i_DC_Con2lto8_1_0_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40297 \CPLD_Con_1/un1_i_DC_Con2_1lto7_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[207] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[206] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40297 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1171 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M0_dly, CLK_dly, LSR_dly; lut40025 \CPLD_Con_1/DMM_en_cnst_0_a2_i_o2_RNI8HNR2_0[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40192 \CPLD_Con_1/exec_flag_RNILEAP3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[135] ( .D0(GNDI), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); gnd DRIVEGND( .PWR0(GNDI)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[134] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1172 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40025 \CPLD_Con_1/DMM_en_cnst_0_a2_i_o2_RNI8HNR2[14] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40192 \CPLD_Con_1/exec_flag_RNIPIAP3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[140] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1173 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40025 \CPLD_Con_1/PMU_OC_412lto8_i_o2_0_o3_RNI8KJU2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40192 \CPLD_Con_1/exec_flag_RNIOK6S3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[139] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[138] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1174 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40079 \CPLD_Con_1/DPS_m3_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40298 \CPLD_Con_1/DPS_FS_2_9_i_a2_1[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[46] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[45] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40298 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1175 ( input D1, C1, B1, A1, D0, C0, B0, A0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, LSR_dly, CLK_dly; lut40127 \CPLD_Con_1/PMU_OC_412lto8_i_o2_0_o3_RNI8HNR2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40192 \CPLD_Con_1/exec_flag_RNIMFAP3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[137] ( .D0(GNDI), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); gnd DRIVEGND( .PWR0(GNDI)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[136] ( .D0(GNDI), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1176 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40200 \CPLD_Con_1/PMU_OC_412lto8_i_o2_0_o3_RNI8HNR2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40192 \CPLD_Con_1/exec_flag_RNIKDAP3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[133] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[132] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1177 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40115 \CPLD_Con_1/un1_err_flag107_i_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40027 \CPLD_Con_1/un1_err_flag107_i_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[189] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1178 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40115 \CPLD_Con_1/dc_slot_flag_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40017 \CPLD_Con_1/RC_Tx_0_sqmuxa_1_i_o2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[109] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1179 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40041 \CPLD_Con_1/un90_RC_RLSel.un90_RC_RLSel_c3_0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40293 \CPLD_Con_1/RC_RLSel_1_sqmuxa_2_i_RNIMT801 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d5 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d4 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1180 ( input D1, C1, B1, A1, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; lut40299 \CPLD_Con_1/RC_RLSel_1_sqmuxa_2_i ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40203 \CPLD_Con_1/RC_RLSel_1_sqmuxa_2_i_RNIMT801_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d6 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40299 ( input A, B, C, D, output Z ); ROM16X1A #(16'h555D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1181 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40085 \CPLD_Con_1/un1_i_DC_Con4_11_6_0_o2_i_a3_RNITGF53 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40192 \CPLD_Con_1/exec_flag_RNICG234 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[129] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_1182 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; lut40295 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc8 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40083 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc8_RNIU10M2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1183 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40122 \CPLD_Con_1/err_flag_en_0_a2_5_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40300 \CPLD_Con_1/err_flag_en_0_a2_5_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[122] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[121] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40300 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1184 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40301 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_axbxc8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut4 \CPLD_Con_1/DPS_FS_3_9_i_a2_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[57] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[56] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40301 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7F80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1185 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40298 \CPLD_Con_1/DPS_FS_4_9_i_a2_4[8] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40302 \CPLD_Con_1/DPS_FS_4_9_i_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[60] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[5] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40302 ( input A, B, C, D, output Z ); ROM16X1A #(16'h9090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1186 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; lut40135 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_axbxc8_RNI5B6H2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40109 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNIDPOE1 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1187 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40116 \CPLD_Con_1/DPS_FS_1_9_i_a2_2_3[12] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40254 \CPLD_Con_1/DPS_FS_1_9_i_a2[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[44] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[43] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1188 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40200 \CPLD_Con_1/dc_slot_flag_3_rep1_RNI2FEN ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40303 \CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[177] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[176] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40303 ( input A, B, C, D, output Z ); ROM16X1A #(16'h00FE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1189 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40030 \CPLD_Con_1/err_flag_en_0_a2_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40280 \CPLD_Con_1/un1_dc_slot_flag_0_sqmuxa_1_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[182] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[181] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1190 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40304 \CPLD_Con_1/err_flag53lto4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40161 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_o2_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/recv_reg[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40304 ( input A, B, C, D, output Z ); ROM16X1A #(16'hD500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1191 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); lut40117 \CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2_0_o2_RNIGLVL ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40065 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c9 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1192 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40280 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40305 \CPLD_Con_1/un1_exec_flag_1_0_o2_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[195] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[194] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40305 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFF8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1193 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40306 \CPLD_Con_1/un1_exec_flag_3_i_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40249 \CPLD_Con_1/un1_exec_flag_3_i_a2_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[199] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[198] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40306 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF1F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1194 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40307 \CPLD_Con_1/un1_exec_flag_10_i_a2_0_1_RNO ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut4 \CPLD_Con_1/un1_exec_flag_10_i_a2_0_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[193] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[192] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40307 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0016) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1195 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40027 \CPLD_Con_1/err_flag22_2_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40308 \CPLD_Con_1/DMM_en_cnst_0_a2_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[207] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[206] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40308 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1196 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40309 \CPLD_Con_1/un1_i_DC_Con1_iv_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40040 \CPLD_Con_1/DMM_en_26_0_a2_0[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/recv_reg[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40309 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1197 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40309 \CPLD_Con_1/dc_slot_flag_RNII9SK1[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40200 \CPLD_Con_1/DMM_en_26_0_a3_2[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/recv_reg[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1198 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40060 \CPLD_Con_1/DPS_FSMMCe_1[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40310 \CPLD_Con_1/DPS_FSMMC_17_5_4_.N_13_mux_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[39] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[38] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40310 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFD7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1199 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40119 \CPLD_Con_1/un16lto5_4_i_a2_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40311 \CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2_0_o2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[31] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[30] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40311 ( input A, B, C, D, output Z ); ROM16X1A #(16'h08FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1200 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40017 \CPLD_Con_1/DMM_en_cnst_0_a2_i_o2[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40249 \CPLD_Con_1/DMM_en_cnst_0_a2_i_o2_RNIURUD1[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[28] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[27] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module CPLD_Con_1_SLICE_1201 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40217 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_1_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40312 \CPLD_Con_1/err_flag45_i_o2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[2] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40312 ( input A, B, C, D, output Z ); ROM16X1A #(16'h02FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1202 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40233 \CPLD_Con_1/un17lto4_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40280 \CPLD_Con_1/un17lto5 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[175] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[174] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1203 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40027 \CPLD_Con_1/PMU_OC_412lto8_i_o2_0_o3 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40313 \CPLD_Con_1/un1_i_DC_Con4_11_6_0_o2_i_a3_RNIVHKK1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[24] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[23] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40313 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0E02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1204 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40137 \CPLD_Con_1/RC_m1_e_2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40314 \CPLD_Con_1/RC_VSel39_0_a2_RNIBFT6 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[111] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[110] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40314 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAAA2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1205 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40079 \CPLD_Con_1/un65_RC_RLSel.un65_RC_RLSel_c4_a0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40315 \CPLD_Con_1/RC_RLSel_1_sqmuxa_1_0_a2_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jupdate_d3 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d2 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40315 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA2A2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1206 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40316 \CPLD_Con_1/err_flag_en_0_a2_1_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40317 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_3_tz ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[35] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[34] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40316 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0959) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40317 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFF07) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1207 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40122 \CPLD_Con_1/io_RC9 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40249 \CPLD_Con_1/dc_t_RNI8TNV[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_fast[0] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_3_rep1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1208 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40318 \CPLD_Con_1/RC_Tx_0_0_iv_0_i_i_a2_2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40086 \CPLD_Con_1/DMM_en_cnst_0_a2_i_o2_RNI04R22[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[26] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[25] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40318 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1414) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1209 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40119 \CPLD_Con_1/DMM_en_26_i_a4_0_0[15] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40319 \CPLD_Con_1/DMM_en_26_i_a4_0_2[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40319 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0A02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1210 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40226 \CPLD_Con_1/DMM_en_26_0_a3_0_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40083 \CPLD_Con_1/DMM_en_26_0_a3_0_3[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/recv_reg[30] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/recv_reg[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1211 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40079 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_c4_a0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40021 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_axbxc4 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[171] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[170] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1212 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40135 \CPLD_Con_1/RC_LOFS_6_1_0_.m16_0_a2_0_2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40085 \CPLD_Con_1/RC_LOFS_6_1_0_.m16_0_a2_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1213 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40095 \CPLD_Con_1/DPS_FS_2_9_i_a2_2[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40025 \CPLD_Con_1/DPS_FS_2_9_i_a2_4_3[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[4] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[49] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1214 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40083 \CPLD_Con_1/PMU_OC_313 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40320 \CPLD_Con_1/PMU_OC_313_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[86] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[85] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40320 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1215 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40095 \CPLD_Con_1/err_flag_en_0_a2_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40115 \CPLD_Con_1/RC_VSel41_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[115] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[114] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_1216 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); lut40301 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_N_2L1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c8_a0_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1217 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40321 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_0_1_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[33] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[32] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40321 ( input A, B, C, D, output Z ); ROM16X1A #(16'hD0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1218 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40307 \CPLD_Con_1/freq_slot_flag_RNI6S8Q1_1[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40322 \CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_i_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[80] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[7] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40322 ( input A, B, C, D, output Z ); ROM16X1A #(16'hC800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1219 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40249 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIFE47E ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40064 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc7_RNIAO2A1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[39] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[38] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1220 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40295 \CPLD_Con_1/g0_32 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40079 \CPLD_Con_1/g1_4 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[166] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[165] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1221 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40291 \CPLD_Con_1/g2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \CPLD_Con_1/g1_5 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[168] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[167] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1222 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40086 \CPLD_Con_1/io_RC9_RNI13RC3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \CPLD_Con_1/freq_t_fast_RNIDG6HD[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[148] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[147] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1223 ( input B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40039 \CPLD_Con_1/g0_35 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40280 \CPLD_Con_1/g0_29 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[157] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[156] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1224 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40323 \CPLD_Con_1/un1_i_DC_Con3_2lto8_d_RNI71P79 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_a2_2_RNI86UQ4 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/recv_reg[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40323 ( input A, B, C, D, output Z ); ROM16X1A #(16'h80A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1225 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40170 \CPLD_Con_1/dc_slot_flag_0_rep1_RNIT85J ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40106 \CPLD_Con_1/dc_slot_flag_RNIFAF41[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_1_rep1 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \CPLD_Con_1/dc_slot_flag_0_rep1 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1226 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40116 \CPLD_Con_1/g0_45 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40324 \CPLD_Con_1/g1_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[164] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[163] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40324 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFFBE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1227 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); lut40325 \CPLD_Con_1/io_RC9_RNI4D7V2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40026 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVCCUA ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40325 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1228 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; lut40041 \CPLD_Con_1/g0_49 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40326 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIVGIL1_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40326 ( input A, B, C, D, output Z ); ROM16X1A #(16'hDEDE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1229 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40085 \CPLD_Con_1/freq_slot_flag_RNI8FRS1[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40170 \CPLD_Con_1/freq_slot_flag_RNIJJMB1[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1230 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40327 \CPLD_Con_1/PMU_OC_312lto8_1_0_o2_0_mb ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40119 \CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf0_1 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[210] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40327 ( input A, B, C, D, output Z ); ROM16X1A #(16'h444E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1231 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40328 \CPLD_Con_1/DMM_en_0_sqmuxa_5_i_1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut4 \CPLD_Con_1/DMM_en_0_sqmuxa_5_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/recv_reg[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40328 ( input A, B, C, D, output Z ); ROM16X1A #(16'h002A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1232 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40068 \CPLD_Con_1/io_RC9_RNI05TL2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40135 \CPLD_Con_1/freq_slot_flag_RNIJJMB1_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[144] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[143] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1233 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40122 \CPLD_Reg_1/regtable[4]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40086 \CPLD_Reg_1/regtable[4]_1_sqmuxa_0_a2_RNI9Q361 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0044 \CPLD_Reg_1/regtable[0][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[0][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1234 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40030 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40086 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a2_RNIDM9F1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[0][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0044 \CPLD_Reg_1/regtable[0][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1235 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40039 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40086 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2_0_0_RNIM9FH1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[0][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[0][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1236 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40194 \CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40116 \CPLD_Reg_1/regtable[4]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[0][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[0][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1237 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40119 \CPLD_Reg_1/un34_regtable_1_0_1_a2_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40116 \CPLD_Reg_1/regtable[0]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[0][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[0][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1238 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40027 \CPLD_Reg_1/state_ns_0_o4[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40263 \CPLD_Reg_1/state_ns_0_a4_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[0][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0044 \CPLD_Reg_1/regtable[0][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1239 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40030 \CPLD_Reg_1/state_ns_0_a4_0_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40329 \CPLD_Reg_1/un9_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[10][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[10][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40329 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_SLICE_1240 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; lut40122 \CPLD_Reg_1/state_s1_0_a2_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40116 \CPLD_Reg_1/rdata_reg_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1241 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40194 \CPLD_Reg_1/un10_i_0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40137 \CPLD_Reg_1/regtable[0]_1_sqmuxa_8_0_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/regtable[0][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[0][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_1242 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40017 \BUS_Con_1/cs_sync_RNI4H6C_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40330 \BUS_Con_1/miso_shift_rst[31] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_out[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/data_out[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40330 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0B08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_1243 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40122 \BUS_Con_1/sclk_rise ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40038 \BUS_Con_1/un1_bit_cnt_7_ac0_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_out[23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/data_out[22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_1244 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40039 \BUS_Con_1/addr_out_8_i_a2[6] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40331 \BUS_Con_1/un1_state_2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_out[5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/data_out[4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40331 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA0EC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1245 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40127 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40117 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/wen_tu[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[120] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1246 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40115 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40332 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/wen_te[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[119] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[118] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40332 ( input A, B, C, D, output Z ); ROM16X1A #(16'hE000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1247 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40085 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg2_0_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40085 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/wen_tcnt ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[117] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[116] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1248 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40048 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40122 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/rd_te ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[113] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[112] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1249 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40048 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40119 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/rd_tu ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[115] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[114] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1250 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/_decfrac0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40094 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[171] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[170] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1251 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40333 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40149 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/rd_dout_tu_2[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[175] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[174] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40333 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF1E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1252 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40039 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40264 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[162] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[161] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1253 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40117 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40208 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[168] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[167] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1254 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40122 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/rd_dout_te_1_u_i_a2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40086 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/cnt_contig_reg_wen_1_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[137] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[136] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1255 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40334 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40025 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/addr_cnt_init_1_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[135] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[134] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40334 ( input A, B, C, D, output Z ); ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1256 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40335 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1_RNI9GOH1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40336 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active_RNIJP0U ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[164] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[163] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40335 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40336 ( input A, B, C, D, output Z ); ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1257 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_det ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40338 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/trig_cnt_7_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[133] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[132] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40337 ( input A, B, C, D, output Z ); ROM16X1A #(16'hE2E2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40338 ( input A, B, C, D, output Z ); ROM16X1A #(16'h9C9C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1258 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40136 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/rd_dout_tcnt_1_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/rd_dout_tcnt_1[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[124] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[123] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1259 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40122 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_clk ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40339 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_5[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[128] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[127] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40339 ( input A, B, C, D, output Z ); ROM16X1A #(16'h54FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1260 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40340 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40341 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/rd_dout_trig[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[122] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[121] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40340 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0105) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40341 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1261 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40342 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40194 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_RNO_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[10][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[10][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40342 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1262 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40096 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_o3_0[12] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40343 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[11][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[11][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40343 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFDFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1263 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40344 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0_rd_dout_tcnt_RNIFJ5V[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40345 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[12][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[12][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40344 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40345 ( input A, B, C, D, output Z ); ROM16X1A #(16'h082A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1264 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40263 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40346 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[11][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[11][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40346 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1265 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40127 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_a3[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40346 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[11][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[11][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1266 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40026 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_a3[12] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40347 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/regtable[12][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[12][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40347 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1267 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40348 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jce2_RNI4BD81 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40349 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc_en_RNII3DP1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[7][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[7][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40348 ( input A, B, C, D, output Z ); ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40349 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1268 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40071 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg36_i_o2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40115 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_a2_3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[12][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[12][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1269 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40039 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_first_bit ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut4 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_a2[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[12][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[12][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1270 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40116 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40093 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[210] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[14][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[14][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1271 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40350 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_calc_5_iv_1_m2_0_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40217 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un15_jtdo_first_bit ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[7][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[7][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40350 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4C4C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1272 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40351 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jupdate_early_i_o2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40352 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[12][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[12][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40351 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40352 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFD20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1273 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40351 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un4_jupdate_early_i_o2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40353 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_regce[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[6][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[6][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40353 ( input A, B, C, D, output Z ); ROM16X1A #(16'hC044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1274 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40194 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_0_sqmuxa ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40135 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_first_bit_1_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/regtable[10][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[10][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1275 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40119 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40263 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_1_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[10][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[10][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1276 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40194 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40108 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un27_jtdo_first_bit_0_o3 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/regtable[7][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[7][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1277 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40354 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0_RNIL7MV ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40040 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/ren_0_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/regtable[11][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[11][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40354 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0070) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1278 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40230 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un22_jtdo ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un20_jtdo_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[7][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[7][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1279 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40309 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_4_x ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40094 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/rd_dout_tm_RNIKM151[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[11][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[11][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1280 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40355 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40351 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_0_1 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/regtable[10][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[10][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40355 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1281 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40122 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/mem_full_cntr_6_i_0_a2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40356 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[8][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[8][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40356 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFEF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1282 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40106 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40325 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[32] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[31] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1283 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40095 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_16_RNIS33R[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40325 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1284 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40357 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_3[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40045 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[30] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[29] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40357 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3B0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1285 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40200 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_3[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40041 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[28] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[27] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1286 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40116 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_7_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40358 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[9][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[9][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40358 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1287 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40094 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr19 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40041 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa_RNI97J51 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/last_addr_written[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1288 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40041 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_stretch_RNIUBR51 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40359 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/armed_RNIB8A02 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[8][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[8][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40359 ( input A, B, C, D, output Z ); ROM16X1A #(16'hEC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1289 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40117 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40039 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_post_trig_frm_0_sqmuxa_0_a2_0_a2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/regtable[8][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[8][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1290 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40095 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_15[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40038 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_enbl_0_sqmuxa_0_a2_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[102] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[101] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1291 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40038 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40360 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_a2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/r_w ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/addr_15 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40360 ( input A, B, C, D, output Z ); ROM16X1A #(16'h10B0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1292 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40083 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_6_1[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40361 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_6[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40361 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1293 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40137 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_13[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40194 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/force_trig_2_sqmuxa_i_0_0_a2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[8][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[8][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1294 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40108 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_i_0_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40362 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg_0_sqmuxa_i_0_0_RNI5CV21 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[104] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[103] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40362 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3332) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1295 ( input D1, C1, B1, A1, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); wire GNDI, VCCI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; lut40200 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_16[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40122 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_16_RNIM62E[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1296 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40095 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIT2371[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40193 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_rd_dout_tm51_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[108] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[107] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1297 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40122 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIHV1Q[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40363 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[24] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[23] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40363 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAAAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1298 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40200 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNIUQ3K1[8] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40364 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[26] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[25] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40364 ( input A, B, C, D, output Z ); ROM16X1A #(16'hD800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1299 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40024 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40351 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[100] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1300 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40115 \xo2chub/jtdo1_1_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40365 \xo2chub/jtdo1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[180] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40365 ( input A, B, C, D, output Z ); ROM16X1A #(16'h4080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1301 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40117 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40086 \CPLD_Con_1/RC_RLSel_13_0_iv_i_RNO_1[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1302 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40117 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40038 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[68] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[67] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1303 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40263 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40025 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_9 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[79] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[78] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1304 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40117 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40106 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_7 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[75] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[74] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1305 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40117 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40116 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[11] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/er1_shift_reg[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/er1_shift_reg[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module SLICE_1306 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40249 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40086 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/er1_shift_reg[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/er1_shift_reg[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module SLICE_1307 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; lut40025 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[8] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40194 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[13] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/id_enable ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1308 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; lut40116 \CPLD_Con_1/RC_RLSel_13_0_iv_i_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40200 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_prog_din[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1309 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, LSR, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M0_dly, CLK_dly, CE_dly, LSR_dly; lut40117 \CPLD_Con_1/RC_RLSel_13_0_iv_i_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40086 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/ip_enable[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module SLICE_1310 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly; lut40249 \CPLD_Con_1/RC_RLSel_13_0_iv_1_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40194 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_start_d1 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/jshift_d2 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); endspecify endmodule module CPLD_Con_1_SLICE_1311 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); lut40115 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut4 \CPLD_Con_1/un95_RC_RLSel_m_0_a2_1[17] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1312 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40249 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40200 \CPLD_Con_1/RC_RLSel_13_0_iv_i_1_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trig_ptr_reg[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1313 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40248 \CPLD_Con_1/un11_RC_RLSellto3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40104 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO_0[17] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/er1_shift_reg[20] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/er1_shift_reg[1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module SLICE_1314 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40366 \CPLD_Con_1/un15_RC_RLSel.un15_RC_RLSel_axbxc3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40115 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO[16] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/er1_shift_reg[13] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/er1_shift_reg[12] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module lut40366 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAAA9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1315 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40041 \CPLD_Con_1/io_RC_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40038 \CPLD_Con_1/CO1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_out[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/data_out[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1316 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40115 \CPLD_Con_1/DPS_FSMC_RNO_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40367 \CPLD_Con_1/PMU_OC_2_0_sqmuxa_2_o2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[82] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[81] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40367 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0112) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1317 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut4 \CPLD_Con_1/PMU_OC_119_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40368 \CPLD_Con_1/freq_slot_flag_RNI6S8Q1[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \CPLD_Con_1/freq_slot_flag[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40368 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0106) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1318 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40079 \CPLD_Con_1/DMM_en_0_sqmuxa_5_0_o2_2_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c8_a0_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[8] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[89] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1319 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40249 \CPLD_Con_1/exec_flag_RNIK38E1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40117 \CPLD_Con_1/exec_flag_RNIK38E1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[131] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[130] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1320 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40038 \CPLD_Reg_1/regtable[7]_1_sqmuxa_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40086 \CPLD_Reg_1/regtable[6]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[0][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[0][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1321 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40038 \CPLD_Reg_1/regtable[11]_1_sqmuxa_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40116 \CPLD_Reg_1/regtable[8]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[0][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[0][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1322 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40038 \CPLD_Reg_1/regtable[3]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40194 \CPLD_Reg_1/regtable[2]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0044 \CPLD_Reg_1/regtable[0][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[0][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1323 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40086 \CPLD_Reg_1/regtable[14]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40038 \CPLD_Reg_1/regtable[15]_1_sqmuxa_0_a2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[0][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[0][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1324 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40263 \CPLD_Reg_1/un10_i_0_1_RNI75F41 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40087 \CPLD_Reg_1/un10_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[10][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[10][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1325 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40233 \CPLD_Con_1/un65_RC_RLSel.un65_RC_RLSel_c3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40116 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO_0[16] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_rep1 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jshift_d1_fast_fast ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1326 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40086 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40263 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc4_RNI3T2O2_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[71] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[70] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1327 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40207 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNIS51O ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40251 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c3_RNIQQUR1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[99] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[98] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1328 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40025 \CPLD_Con_1/RC_RLSel_13_0_iv_i_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40038 \CPLD_Con_1/RC_RLSel_13_iv_i_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \xo2chub/ip_enable[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/ip_enable[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module CPLD_Con_1_SLICE_1329 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; lut40109 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNIP4ND1_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40318 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNIP4ND1_2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1330 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40094 \CPLD_Con_1/un9_DPS_FS_3_74_0_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40137 \CPLD_Con_1/N_72_0_i_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[71] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[70] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1331 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40040 \CPLD_Con_1/un9_DPS_FS_3_72_0_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40135 \CPLD_Con_1/N_68_0_i_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[68] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[67] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1332 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40095 \CPLD_Con_1/DPS_FS_3_9_i_a2_0_0[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40369 \CPLD_Con_1/N_66_0_i_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[66] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[65] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40369 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1333 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40083 \CPLD_Con_1/un9_DPS_FS_3_70_0_a2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40085 \CPLD_Con_1/N_70_0_i_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[6] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[69] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1334 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40135 \CPLD_Con_1/RC_RLSel_13_0_iv_0_RNO_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40085 \CPLD_Con_1/RC_RLSel_13_iv_1_RNO_0[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \xo2chub/er1_shift_reg[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \xo2chub/er1_shift_reg[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (negedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); endspecify endmodule module SLICE_1335 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40094 \CPLD_Con_1/DMM_en_26_0_a2_0_0[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40083 \CPLD_Con_1/DMM_en_26_0_a2_0_0[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[27] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/recv_reg[26] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1336 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40233 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_c3_d ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40205 \CPLD_Con_1/un45_RC_RLSel_m_0_a2_1[15] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[64] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[63] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1337 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40137 \CPLD_Con_1/un1_i_DC_Con1_1lto8_0_a2_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40206 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[37] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[36] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1338 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40137 \CPLD_Con_1/err_flag45_i_a2_0_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40041 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c3_0_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[84] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[83] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1339 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40137 \CPLD_Con_1/g0_45_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40204 \CPLD_Con_1/RC_Tx_0_0_iv_144_i_i_o2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[104] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[103] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_1340 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; lut40079 \CPLD_Con_1/g1_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40370 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40370 ( input A, B, C, D, output Z ); ROM16X1A #(16'hE1E1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1341 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40085 \CPLD_Con_1/RC_Tx_0_0_iv_1_i_i_a4_1_1_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40371 \CPLD_Con_1/RC_Tx_0_0_iv_4_74_i_i_a4_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[106] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[105] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40371 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1342 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40079 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc8_RNO ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \CPLD_Con_1/DPS_FS_4_9_i_a2_4_2[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[64] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[63] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1343 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40040 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIEMT02_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40095 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIEMT02_1 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[26] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[25] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_1344 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); wire GNDI; lut40137 \CPLD_Con_1/PMU_OC_4_0_sqmuxa_2_i ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut4 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_axbxc3_RNIC1U9B ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1345 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40372 \CPLD_Con_1/err_flag_en_0_a2_6_mb_sn ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40373 \CPLD_Con_1/err_flag_en_0_a2_6_mb_rn ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[124] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[123] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40372 ( input A, B, C, D, output Z ); ROM16X1A #(16'h080A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40373 ( input A, B, C, D, output Z ); ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_SLICE_1346 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40116 \CPLD_Reg_1/regtable[12]_1_sqmuxa_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40086 \CPLD_Reg_1/regtable[10]_1_sqmuxa_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[0][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[0][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_1347 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40102 \BUS_Con_1/un2_sclk_rise ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40025 \BUS_Con_1/wr_flag_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_out[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/data_out[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_1348 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40374 \BUS_Con_1/cmd_valid_out_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40025 \BUS_Con_1/data_out_0_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_out[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre0020 \BUS_Con_1/data_out[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40374 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0C3E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1349 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_4[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut4 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.wen_te12_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[111] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[110] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1350 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40200 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/decode_u/_l0.un1_addr_5 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[109] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1351 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut4 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40375 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/rd_dout_te_1_u_i_a3[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[140] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40375 ( input A, B, C, D, output Z ); ROM16X1A #(16'h00F6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1352 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40127 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40104 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/un1_tt_end_1_0_a3_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[169] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1353 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40376 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40376 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[11] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[11][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[11][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40376 ( input A, B, C, D, output Z ); ROM16X1A #(16'hD850) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1354 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40377 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40377 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[12][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[12][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40377 ( input A, B, C, D, output Z ); ROM16X1A #(16'h058D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1355 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40376 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[8] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40376 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[11][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[11][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1356 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40378 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40117 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[20] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40378 ( input A, B, C, D, output Z ); ROM16X1A #(16'hA080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1357 ( input D1, C1, B1, A1, D0, C0, B0, A0, M0, CE, CLK, output F0, Q0, F1 ); wire VCCI, GNDI, CLK_NOTIN, M0_dly, CLK_dly, CE_dly; lut40379 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[8] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40379 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40379 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8B88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1358 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40086 \CPLD_Con_1/exec_flag_RNILIC61 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40086 \CPLD_Con_1/freq_t_fast_RNIDHVB1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[149] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1359 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40135 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_axbxc3_RNIKHQQ_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40094 \CPLD_Con_1/un40_RC_RLSel.un40_RC_RLSel_c3_d_RNIOTRB ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[60] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[5] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1360 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, M1_dly, CLK_dly, M0_dly, CE_dly; lut40208 \CPLD_Con_1/RC_RLSel_13_iv_1[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40209 \CPLD_Con_1/RC_RLSel_13_iv_1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1361 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40079 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_c6_a0_3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40251 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIJ1ER ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[2] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[29] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1362 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40079 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40207 \CPLD_Con_1/DPS_FS_4_9_i_a2_2[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[62] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[61] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1363 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40249 \CPLD_Con_1/un1_exec_flag_4_i_a2_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40025 \CPLD_Con_1/RC_VSel39_0_a2_RNIVMCH1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[113] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[112] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1364 ( input B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly; lut40039 \CPLD_Con_1/err_flag75lto1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40094 \CPLD_Con_1/RC_RLSel_13_iv_0_RNO[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/te_precnt_val[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1365 ( input C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40094 \CPLD_Con_1/DMM_en_26_0_a3_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40122 \CPLD_Con_1/un1_dc_slot_flag_1_2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[184] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[183] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1366 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40027 \CPLD_Con_1/err_flag89_2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut4 \CPLD_Con_1/DMM_en_26_0_a4_1_1_0[13] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/recv_reg[8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1367 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40119 \CPLD_Con_1/g0_25 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40370 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_axbxc2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[35] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[34] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1368 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40119 \CPLD_Con_1/DPS_FS_1_9_i_a2_2_0[12] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40115 \CPLD_Con_1/PMU_OC_1_1_sqmuxa_1_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[75] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[74] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module CPLD_Con_1_SLICE_1369 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40380 \CPLD_Con_1/dc_slot_flag_3_rep1_RNI4FET ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40161 \CPLD_Con_1/dc_slot_flag_2_rep1_RNI2PA51 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40380 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFEEB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1370 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40381 \CPLD_Con_1/freq_t_RNIV9T5[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40104 \CPLD_Con_1/PMU_OC_1_0_sqmuxa_0_a2_0_a2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[73] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[72] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40381 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1371 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40137 \CPLD_Con_1/err_flag45_i_a3_0_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40079 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_c8_a0_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[88] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[87] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1372 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40134 \CPLD_Con_1/freq_slot_flag_RNI6U811[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40115 \CPLD_Con_1/DPSFS_RC1_1_sqmuxa_2_0_a2_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[2] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[29] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1373 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40371 \CPLD_Con_1/DPS_FSMMCe_N_2L1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40030 \CPLD_Con_1/DPS_FSMMC_17_5_4_.m4_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[40] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[3] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1374 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40040 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIEMT02 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40095 \CPLD_Con_1/un3_DPS_FS_1.un3_DPS_FS_1_ac0_3_0_RNIEMT02_3 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[28] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[27] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1375 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40117 \CPLD_Con_1/freq_slot_flag_RNIDF632[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40067 \CPLD_Con_1/RC_VSel41_0_a2_RNIRDIJ5 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[119] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[118] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1376 ( input C1, B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40369 \CPLD_Con_1/PMU_OC_312lto8_1_0_o2_0_sn ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40382 \CPLD_Con_1/un1_i_DC_Con3_2lto8_dcf1_1 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[212] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[211] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40382 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0707) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Reg_1_SLICE_1377 ( input B1, A1, B0, A0, output F0, F1 ); wire GNDI; lut40021 \CPLD_Reg_1/rvalid_flag_RNO_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40017 \CPLD_Reg_1/busy_flag_RNO_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module BUS_Con_1_SLICE_1378 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40017 \BUS_Con_1/cs_sync_RNI4H6C[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40383 \BUS_Con_1/miso_shift_en[31] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_out[16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/data_out[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40383 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFBFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_1379 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40039 \BUS_Con_1/err_flag8_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40233 \BUS_Con_1/miso_shift17lto2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_out[14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/data_out[13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module BUS_Con_1_SLICE_1380 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40119 \BUS_Con_1/data_ready17_3_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40194 \BUS_Con_1/err_flag8_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_out[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/data_out[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1381 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40135 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/op_code7 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40094 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/mask_reg[0]_0_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[173] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[172] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1382 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40030 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/num_then_wen_1_0_a3 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40039 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/next_then_reg_wen_1_0_a3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[139] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[138] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1383 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40226 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40091 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/rd_dout_tcnt_1[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[126] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[125] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1384 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40040 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_13_RNIMNP71[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40040 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_0_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[129] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1385 ( input D1, C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40378 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40040 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg1_RNIV2O21[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[131] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[130] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1386 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40384 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[14] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40346 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[9] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[12][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[12][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40384 ( input A, B, C, D, output Z ); ROM16X1A #(16'hCACA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1387 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40346 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_a2_1[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40346 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[12][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[12][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1388 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40376 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40376 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_0[12] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[11][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[11][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1389 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40149 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40117 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_1[13] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[11][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[11][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1390 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40385 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_0_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40386 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_0_tz ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[7][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[7][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40385 ( input A, B, C, D, output Z ); ROM16X1A #(16'h1B5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40386 ( input A, B, C, D, output Z ); ROM16X1A #(16'h3777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1391 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_jtck_0_a2_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[8][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[8][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1392 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40083 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_addr_2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40104 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[6][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[6][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1393 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40027 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/reset_rvl_n ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40039 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[10][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[10][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1394 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40387 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tcnt_0/reg0_read11 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40122 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/wen_0_a2_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/regtable[8][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[8][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40387 ( input A, B, C, D, output Z ); ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1395 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40085 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_a2_1[11] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40135 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_i_a2_2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[12][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[12][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1396 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40161 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40161 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_1[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[34] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[33] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1397 ( input B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40119 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_12[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40163 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[9][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[9][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1398 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40025 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/num_pre_trig_frm_0_sqmuxa_0_a2_0_a2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40119 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_15_0_iv_0_a2_14[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d5 ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/capture_dr_d4 ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1399 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40137 \CPLD_Con_1/g0_6_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40388 \CPLD_Con_1/PMU_OC_4_4_38_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[99] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[98] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40388 ( input A, B, C, D, output Z ); ROM16X1A #(16'h7E7E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1400 ( input B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; lut40119 \CPLD_Con_1/PMU_OC_312lto8_0_a2_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40250 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_RNIP4ND1 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module CPLD_Con_1_SLICE_1401 ( input B1, A1, C0, B0, A0, output F0, F1 ); wire GNDI; lut40119 \CPLD_Con_1/DPS_FS_4_9_i_a2_4_0[8] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40389 \CPLD_Con_1/un4_DPS_FS_4.un4_DPS_FS_4_c5_a0_RNIM8DT ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module lut40389 ( input A, B, C, D, output Z ); ROM16X1A #(16'h2424) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1402 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40083 \CPLD_Con_1/un1_exec_flag_3_i_0_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40079 \CPLD_Con_1/un1_PMU_OC_1_1_sqmuxa_0_c_d ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[179] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[178] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1403 ( input D1, C1, B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40161 \CPLD_Con_1/un1_i_DC_Con1_iv_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40122 \CPLD_Con_1/un1_dc_slot_flag_1_6 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[186] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[185] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1404 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40039 \CPLD_Con_1/un1_i_DC_Con1_iv_RNO[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40040 \CPLD_Con_1/DMM_en_26_0_a3_1_0[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/recv_reg[3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/recv_reg[31] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1405 ( input B1, A1, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40119 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_2_a0_3_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40137 \CPLD_Con_1/un1_i_DC_Con4_11_6_0_o2_i_a3 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[22] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[21] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1406 ( input B1, A1, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40119 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c5_a0_0_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40119 \CPLD_Con_1/un16lto5_4_i_a2_0_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[173] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[172] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1407 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, LSR_dly; lut40390 \CPLD_Con_1/DPS_FSMC_0_sqmuxa_0_o2_3_tz_RNI9M8I3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40391 \CPLD_Con_1/err_flag_en_0_a2_4 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[120] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_din_d[11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40390 ( input A, B, C, D, output Z ); ROM16X1A #(16'h5575) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module lut40391 ( input A, B, C, D, output Z ); ROM16X1A #(16'h0F08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module BUS_Con_1_SLICE_1408 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40119 \BUS_Con_1/state_s0_0_a2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40336 \BUS_Con_1/state_ns_1_0_.m6_i_a2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \BUS_Con_1/data_out[21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); vmuxregsre0020 \BUS_Con_1/data_out[20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1409 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40030 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/rd_dout_tu_2[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40030 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/rd_dout_tu_2[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[177] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[176] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1410 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40119 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/c_5_1 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40119 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/tu_0/un1_rising_edge_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[179] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[178] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1411 ( input C1, B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40094 \xo2chub/jtdo2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40039 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa_i_a3_0_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[166] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[165] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1412 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40384 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40346 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_14_1_2[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[11][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[11][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1413 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40392 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un4_jupdate_early_i_o2_RNIQKF31[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40093 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[209] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[14][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[14][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40392 ( input A, B, C, D, output Z ); ROM16X1A #(16'h8B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1414 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40384 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40384 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0_i_m3[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[11][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[11][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1415 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[208] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[14][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[14][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1416 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[207] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[15][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[15][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1417 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[206] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[3] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][11] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[1][10] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1418 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[205] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[2][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[2][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1419 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[204] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[5] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[2][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[2][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1420 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[203] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[3][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[3][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1421 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[202] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[4][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[4][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1422 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[201] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[8] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[5][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[5][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1423 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[200] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[9] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[6][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[6][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1424 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[199] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[10] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[13][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[13][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1425 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[198] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[11] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[13][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[13][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1426 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[197] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[12] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[13][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[13][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1427 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[196] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[13] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[13][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[13][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1428 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[195] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[14] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[13][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[13][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1429 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[194] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[15] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[13][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[13][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1430 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[193] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[16] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[13][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[13][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1431 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[192] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[17] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[13][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[13][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1432 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[191] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[18] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[13][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[13][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1433 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[190] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[19] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[13][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[13][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1434 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[189] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[20] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[14][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[14][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1435 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[188] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[21] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[14][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[14][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1436 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[187] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[22] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[14][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[14][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1437 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[186] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[23] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[14][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[14][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1438 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[185] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[12][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[12][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1439 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[184] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[24] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[14][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[14][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1440 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[183] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[25] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[14][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[14][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1441 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[182] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[26] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[14][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[14][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1442 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[181] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[27] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[14][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[14][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1443 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[180] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[28] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[14][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[14][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1444 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[179] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[29] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[15][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[15][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1445 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[178] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[30] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[15][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[15][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1446 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[177] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[31] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[15][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[15][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1447 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[176] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[32] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[15][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[15][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1448 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[175] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[33] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[15][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[15][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1449 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[174] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[34] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[15][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[15][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1450 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[173] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[35] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[15][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[15][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1451 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[172] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[36] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[15][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[15][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1452 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[171] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[37] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[15][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[15][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1453 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[170] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[38] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[15][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[15][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1454 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[169] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[39] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[15][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[15][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1455 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[168] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[40] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][13] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[1][12] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1456 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[167] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[41] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][15] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[1][14] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1457 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[166] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[42] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][17] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[1][16] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1458 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[165] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[43] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][19] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[1][18] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1459 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[164] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[44] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][20] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[1][1] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1460 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[163] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[45] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][22] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[1][21] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1461 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[162] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[46] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[1][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1462 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[161] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[47] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[1][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1463 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[160] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[48] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[1][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1464 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[159] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[49] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[1][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[1][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1465 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[158] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[50] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[2][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[2][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1466 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[157] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[51] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[2][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[2][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1467 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[156] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[52] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[2][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[2][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1468 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[155] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[53] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[2][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[2][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1469 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[154] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[54] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[2][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[2][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1470 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[153] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[55] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[2][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[2][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1471 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[152] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[56] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[2][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[2][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1472 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[151] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[57] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[2][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[2][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1473 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[150] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[58] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[2][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[2][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1474 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[149] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[59] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[2][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[2][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1475 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[148] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[60] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[3][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[3][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1476 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[147] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[61] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[3][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[3][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1477 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[146] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[62] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[3][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[3][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1478 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[145] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[63] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[3][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[3][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1479 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[144] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[64] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[3][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[3][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1480 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[143] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[65] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[3][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[3][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1481 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[142] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[66] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[3][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[3][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1482 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[141] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[67] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[3][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[3][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1483 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[140] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[68] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[3][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[3][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1484 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[139] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[69] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[3][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[3][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1485 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[138] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[70] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[3][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[3][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1486 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[137] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[71] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[4][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[4][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1487 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[136] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[72] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[4][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[4][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1488 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[135] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[73] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[4][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[4][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1489 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[134] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[74] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[4][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[4][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1490 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[133] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[75] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[4][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[4][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1491 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[132] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[76] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[4][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[4][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1492 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[131] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[77] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[4][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[4][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1493 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[130] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[78] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[4][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[4][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1494 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[129] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[79] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[4][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[4][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1495 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[128] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[80] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[4][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[4][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1496 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[127] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[81] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[4][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[4][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1497 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[126] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[82] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[5][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[5][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1498 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[125] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[83] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[5][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[5][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1499 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[124] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[84] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[5][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[5][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1500 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[123] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[85] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[5][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[5][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1501 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[122] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[86] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[5][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[5][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1502 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[121] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[87] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[5][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[5][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1503 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[120] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[88] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[5][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[5][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1504 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[119] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[89] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[5][23] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[5][22] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1505 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[118] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[90] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[5][5] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[5][4] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1506 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[117] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[91] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[5][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[5][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1507 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[116] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[92] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[5][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[5][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1508 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[115] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[93] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[6][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[6][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1509 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[114] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[94] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[6][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[6][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1510 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[113] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[95] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[6][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[6][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1511 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[112] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[96] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[6][16] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[6][15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1512 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[111] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[97] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[6][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[6][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1513 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[110] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[98] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[6][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[6][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1514 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[109] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[99] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[6][21] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[6][20] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1515 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[108] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[100] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[12][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[12][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1516 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[107] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[101] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[12][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[12][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1517 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[106] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[102] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[13][10] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[13][0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1518 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[105] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[103] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[13][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[13][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1519 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40085 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_1_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40094 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[10][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[10][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1520 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40030 \xo2chub/bit_count15 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40017 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tt_crc19_i_0 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[7][18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[7][17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1521 ( input B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40122 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_shift_en_RNIGKQS ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40030 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/un3_jtdo_first_bit ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[7][9] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[7][8] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1522 ( input C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40095 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/addr_RNILQ271[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40364 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[5] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[22] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[21] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1523 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40393 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40200 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/rd_dout_tm_1_RNO_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[18] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg[17] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module lut40393 ( input A, B, C, D, output Z ); ROM16X1A #(16'hAEBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module SLICE_1524 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40041 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_RNIJEUQ1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40027 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/post_trig_cntr_RNI2GFT[7] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/regtable[8][3] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[8][2] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_SLICE_1525 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/un1_pre_trig_cntr_10_6 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[106] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[105] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module SLICE_1526 ( input C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40337 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO_0[104] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40119 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tr_bit_0_3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[6][7] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[6][6] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1527 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_10 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_11 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[159] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[158] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module RelayConTop_reveal_coretop_instance_relaycontop_la0_inst_0_SLICE_1528 ( input D1, C1, B1, A1, D0, C0, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire VCCI, GNDI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40079 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/tt_prog_active20_9 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[160] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[15] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (D0 => F0) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module CPLD_Con_1_SLICE_1529 ( input B1, A1, B0, A0, output F0, F1 ); wire GNDI; lut40039 \CPLD_Con_1/RC_RLSel_1_sqmuxa_1_0_a2_0_RNIMH501 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40021 \CPLD_Con_1/un65_RC_RLSel.un65_RC_RLSel_axbxc4 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1530 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40394 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv_5_RNO ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40027 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/jtdo_iv ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/regtable[10][1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[10][19] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module lut40394 ( input A, B, C, D, output Z ); ROM16X1A #(16'hD0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); endmodule module CPLD_Con_1_SLICE_1531 ( input B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40119 \CPLD_Con_1/PMU_OC_313_0 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40170 \CPLD_Con_1/dc_slot_flag_0_rep1_RNIOJ3M ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[1] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre0020 \CPLD_Con_1/dc_slot_flag[0] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module CPLD_Reg_1_SLICE_1532 ( input D1, C1, B1, A1, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40038 \CPLD_Reg_1/state_ns_0_a4_0_3[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); lut40122 \CPLD_Reg_1/un34_regtable_1_0_2_a2_0_a2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); gnd DRIVEGND( .PWR0(GNDI)); vmuxregsre \CPLD_Reg_1/regtable[10][12] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[10][11] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (D1 => F1) = (0:0:0,0:0:0); (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module SLICE_1533 ( input B1, A1, B0, A0, M1, M0, CE, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, CLK_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly; lut40119 \CPLD_Con_1/un4_DPS_FS_2.un4_DPS_FS_2_axbxc7_RNO ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40119 \CPLD_Con_1/DPS_FS_2_9_i_a2_4_1[5] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[48] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); vmuxregsre \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/trace_dout[47] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_NOTIN), .LSR(GNDI), .Q(Q0)); specify (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); $setuphold (negedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (negedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); endspecify endmodule module CPLD_Con_1_SLICE_1534 ( input C1, B1, A1, B0, A0, output F0, F1 ); wire GNDI; lut40135 \CPLD_Con_1/RC_LOFS_6_1_0_.m9_0_a2_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40119 \CPLD_Con_1/un4_DPS_FS_3.un4_DPS_FS_3_c8_a0_2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); endspecify endmodule module SLICE_1535 ( input C1, B1, A1, C0, B0, A0, M1, M0, CE, LSR, CLK, output F0, Q0, F1, Q1 ); wire GNDI, VCCI, LSR_NOTIN, M1_dly, CLK_dly, M0_dly, CE_dly, LSR_dly; lut40036 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/tm_crc_2_1[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); gnd DRIVEGND( .PWR0(GNDI)); lut40384 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/jtag_int_u/shift_reg_11_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); vmuxregsre \CPLD_Reg_1/regtable[11][14] ( .D0(M1_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q1)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); vmuxregsre \CPLD_Reg_1/regtable[11][13] ( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(Q0)); specify (C1 => F1) = (0:0:0,0:0:0); (B1 => F1) = (0:0:0,0:0:0); (A1 => F1) = (0:0:0,0:0:0); (C0 => F0) = (0:0:0,0:0:0); (B0 => F0) = (0:0:0,0:0:0); (A0 => F0) = (0:0:0,0:0:0); (LSR => Q0) = (0:0:0,0:0:0); (LSR => Q1) = (0:0:0,0:0:0); (CLK => Q0) = (0:0:0,0:0:0); (CLK => Q1) = (0:0:0,0:0:0); $setuphold (posedge CLK, M1, 0:0:0, 0:0:0,,,, CLK_dly, M1_dly); $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge LSR, 0:0:0); $width (negedge LSR, 0:0:0); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_miso ( input IOLDO, PADDT, output o_miso ); xo2iobuf o_miso_pad( .I(IOLDO), .T(PADDT), .PAD(o_miso)); specify (IOLDO => o_miso) = (0:0:0,0:0:0); (PADDT => o_miso) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); endspecify endmodule module xo2iobuf ( input I, T, output PAD ); OBZ INST5( .I(I), .T(T), .O(PAD)); endmodule module o_miso_MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \BUS_Con_1_miso_shiftio[31] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module mfflsre ( input D0, SP, CK, LSR, output Q ); FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; endmodule module o_wready ( input PADDO, output o_wready ); xo2iobuf0395 o_wready_pad( .I(PADDO), .PAD(o_wready)); specify (PADDO => o_wready) = (0:0:0,0:0:0); endspecify endmodule module xo2iobuf0395 ( input I, output PAD ); OB INST5( .I(I), .O(PAD)); endmodule module i_sys_clk ( output PADDI, input i_sys_clk ); xo2iobuf0396 i_sys_clk_pad( .Z(PADDI), .PAD(i_sys_clk)); specify (i_sys_clk => PADDI) = (0:0:0,0:0:0); $width (posedge i_sys_clk, 0:0:0); $width (negedge i_sys_clk, 0:0:0); endspecify endmodule module xo2iobuf0396 ( output Z, input PAD ); IBPD INST1( .I(PAD), .O(Z)); endmodule module o_DPS_S_4_15_ ( input PADDO, output oDPSS415 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS415)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS415) = (0:0:0,0:0:0); endspecify endmodule module xo2iobuf0397 ( input I, T, output PAD ); OBZPU INST5( .I(I), .T(T), .O(PAD)); endmodule module o_DPS_S_4_14_ ( input PADDO, output oDPSS414 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS414)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS414) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_13_ ( input PADDO, output oDPSS413 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS413)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS413) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_12_ ( input PADDO, output oDPSS412 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS412)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS412) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_11_ ( input PADDO, output oDPSS411 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS411)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS411) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_10_ ( input PADDO, output oDPSS410 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS410)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS410) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_9_ ( input PADDO, output oDPSS49 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS49)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS49) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_8_ ( input PADDO, output oDPSS48 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS48)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS48) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_7_ ( input PADDO, output oDPSS47 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS47)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS47) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_6_ ( input PADDO, output oDPSS46 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS46)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS46) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_5_ ( input PADDO, output oDPSS45 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS45)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS45) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_4_ ( input PADDO, output oDPSS44 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS44)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS44) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_3_ ( input PADDO, output oDPSS43 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS43)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS43) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_2_ ( input PADDO, output oDPSS42 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS42)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS42) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_1_ ( input PADDO, output oDPSS41 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS41)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS41) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_4_0_ ( input PADDO, output oDPSS40 ); wire GNDI; xo2iobuf0397 \o_DPS_S_4_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS40)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS40) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_15_ ( input PADDO, output oDPSF415 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF415)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF415) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_14_ ( input PADDO, output oDPSF414 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF414)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF414) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_13_ ( input PADDO, output oDPSF413 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF413)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF413) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_12_ ( input PADDO, output oDPSF412 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF412)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF412) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_11_ ( input PADDO, output oDPSF411 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF411)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF411) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_10_ ( input PADDO, output oDPSF410 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF410)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF410) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_9_ ( input PADDO, output oDPSF49 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF49)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF49) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_8_ ( input PADDO, output oDPSF48 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF48)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF48) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_7_ ( input PADDO, output oDPSF47 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF47)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF47) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_6_ ( input PADDO, output oDPSF46 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF46)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF46) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_5_ ( input PADDO, output oDPSF45 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF45)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF45) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_4_ ( input PADDO, output oDPSF44 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF44)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF44) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_3_ ( input PADDO, output oDPSF43 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF43)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF43) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_2_ ( input PADDO, output oDPSF42 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF42)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF42) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_1_ ( input PADDO, output oDPSF41 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF41)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF41) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_4_0_ ( input PADDO, output oDPSF40 ); wire GNDI; xo2iobuf0397 \o_DPS_F_4_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF40)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF40) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_15_ ( input PADDO, output oDPSS315 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS315)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS315) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_14_ ( input PADDO, output oDPSS314 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS314)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS314) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_13_ ( input PADDO, output oDPSS313 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS313)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS313) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_12_ ( input PADDO, output oDPSS312 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS312)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS312) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_11_ ( input PADDO, output oDPSS311 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS311)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS311) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_10_ ( input PADDO, output oDPSS310 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS310)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS310) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_9_ ( input PADDO, output oDPSS39 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS39)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS39) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_8_ ( input PADDO, output oDPSS38 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS38)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS38) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_7_ ( input PADDO, output oDPSS37 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS37)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS37) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_6_ ( input PADDO, output oDPSS36 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS36)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS36) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_5_ ( input PADDO, output oDPSS35 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS35)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS35) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_4_ ( input PADDO, output oDPSS34 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS34)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS34) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_3_ ( input PADDO, output oDPSS33 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS33)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS33) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_2_ ( input PADDO, output oDPSS32 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS32)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS32) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_1_ ( input PADDO, output oDPSS31 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS31)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS31) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_3_0_ ( input PADDO, output oDPSS30 ); wire GNDI; xo2iobuf0397 \o_DPS_S_3_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS30)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS30) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_15_ ( input PADDO, output oDPSF315 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF315)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF315) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_14_ ( input PADDO, output oDPSF314 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF314)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF314) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_13_ ( input PADDO, output oDPSF313 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF313)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF313) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_12_ ( input PADDO, output oDPSF312 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF312)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF312) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_11_ ( input PADDO, output oDPSF311 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF311)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF311) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_10_ ( input PADDO, output oDPSF310 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF310)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF310) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_9_ ( input PADDO, output oDPSF39 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF39)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF39) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_8_ ( input PADDO, output oDPSF38 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF38)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF38) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_7_ ( input PADDO, output oDPSF37 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF37)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF37) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_6_ ( input PADDO, output oDPSF36 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF36)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF36) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_5_ ( input PADDO, output oDPSF35 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF35)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF35) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_4_ ( input PADDO, output oDPSF34 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF34)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF34) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_3_ ( input PADDO, output oDPSF33 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF33)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF33) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_2_ ( input PADDO, output oDPSF32 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF32)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF32) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_1_ ( input PADDO, output oDPSF31 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF31)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF31) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_3_0_ ( input PADDO, output oDPSF30 ); wire GNDI; xo2iobuf0397 \o_DPS_F_3_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF30)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF30) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_15_ ( input PADDO, output oDPSS215 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS215)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS215) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_14_ ( input PADDO, output oDPSS214 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS214)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS214) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_13_ ( input PADDO, output oDPSS213 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS213)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS213) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_12_ ( input PADDO, output oDPSS212 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS212)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS212) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_11_ ( input PADDO, output oDPSS211 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS211)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS211) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_10_ ( input PADDO, output oDPSS210 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS210)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS210) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_9_ ( input PADDO, output oDPSS29 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS29)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS29) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_8_ ( input PADDO, output oDPSS28 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS28)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS28) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_7_ ( input PADDO, output oDPSS27 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS27)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS27) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_6_ ( input PADDO, output oDPSS26 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS26)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS26) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_5_ ( input PADDO, output oDPSS25 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS25)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS25) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_4_ ( input PADDO, output oDPSS24 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS24)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS24) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_3_ ( input PADDO, output oDPSS23 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS23)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS23) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_2_ ( input PADDO, output oDPSS22 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS22)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS22) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_1_ ( input PADDO, output oDPSS21 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS21)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS21) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_2_0_ ( input PADDO, output oDPSS20 ); wire GNDI; xo2iobuf0397 \o_DPS_S_2_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS20)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS20) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_15_ ( input PADDO, output oDPSF215 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF215)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF215) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_14_ ( input PADDO, output oDPSF214 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF214)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF214) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_13_ ( input PADDO, output oDPSF213 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF213)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF213) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_12_ ( input PADDO, output oDPSF212 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF212)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF212) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_11_ ( input PADDO, output oDPSF211 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF211)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF211) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_10_ ( input PADDO, output oDPSF210 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF210)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF210) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_9_ ( input PADDO, output oDPSF29 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF29)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF29) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_8_ ( input PADDO, output oDPSF28 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF28)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF28) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_7_ ( input PADDO, output oDPSF27 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF27)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF27) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_6_ ( input PADDO, output oDPSF26 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF26)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF26) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_5_ ( input PADDO, output oDPSF25 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF25)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF25) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_4_ ( input PADDO, output oDPSF24 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF24)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF24) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_3_ ( input PADDO, output oDPSF23 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF23)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF23) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_2_ ( input PADDO, output oDPSF22 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF22)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF22) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_1_ ( input PADDO, output oDPSF21 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF21)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF21) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_2_0_ ( input PADDO, output oDPSF20 ); wire GNDI; xo2iobuf0397 \o_DPS_F_2_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF20)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF20) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_15_ ( input PADDO, output oDPSS115 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSS115)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS115) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_14_ ( input PADDO, output oDPSS114 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSS114)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS114) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_13_ ( input PADDO, output oDPSS113 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSS113)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS113) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_12_ ( input PADDO, output oDPSS112 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSS112)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS112) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_11_ ( input PADDO, output oDPSS111 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSS111)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS111) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_10_ ( input PADDO, output oDPSS110 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSS110)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS110) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_9_ ( input PADDO, output oDPSS19 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSS19)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS19) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_8_ ( input PADDO, output oDPSS18 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSS18)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS18) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_7_ ( input PADDO, output oDPSS17 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSS17)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS17) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_6_ ( input PADDO, output oDPSS16 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSS16)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS16) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_5_ ( input PADDO, output oDPSS15 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSS15)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS15) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_4_ ( input PADDO, output oDPSS14 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSS14)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS14) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_3_ ( input PADDO, output oDPSS13 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSS13)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS13) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_2_ ( input PADDO, output oDPSS12 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSS12)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS12) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_1_ ( input PADDO, output oDPSS11 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSS11)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS11) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_S_1_0_ ( input PADDO, output oDPSS10 ); wire GNDI; xo2iobuf0397 \o_DPS_S_1_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSS10)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSS10) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_15_ ( input PADDO, output oDPSF115 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDPSF115)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF115) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_14_ ( input PADDO, output oDPSF114 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDPSF114)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF114) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_13_ ( input PADDO, output oDPSF113 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDPSF113)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF113) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_12_ ( input PADDO, output oDPSF112 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDPSF112)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF112) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_11_ ( input PADDO, output oDPSF111 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDPSF111)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF111) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_10_ ( input PADDO, output oDPSF110 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDPSF110)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF110) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_9_ ( input PADDO, output oDPSF19 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDPSF19)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF19) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_8_ ( input PADDO, output oDPSF18 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDPSF18)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF18) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_7_ ( input PADDO, output oDPSF17 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDPSF17)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF17) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_6_ ( input PADDO, output oDPSF16 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDPSF16)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF16) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_5_ ( input PADDO, output oDPSF15 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDPSF15)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF15) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_4_ ( input PADDO, output oDPSF14 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDPSF14)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF14) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_3_ ( input PADDO, output oDPSF13 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDPSF13)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF13) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_2_ ( input PADDO, output oDPSF12 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDPSF12)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF12) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_1_ ( input PADDO, output oDPSF11 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDPSF11)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF11) = (0:0:0,0:0:0); endspecify endmodule module o_DPS_F_1_0_ ( input PADDO, output oDPSF10 ); wire GNDI; xo2iobuf0397 \o_DPS_F_1_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDPSF10)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDPSF10) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_15_ ( input IOLDO, output oPMUOC415 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC415)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC415) = (0:0:0,0:0:0); endspecify endmodule module xo2iobuf0398 ( input I, T, output PAD ); OBZPD INST5( .I(I), .T(T), .O(PAD)); endmodule module o_PMU_OC_4_15__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_4io[23] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_14_ ( input IOLDO, output oPMUOC414 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC414)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC414) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_4io[22] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module mfflsre0399 ( input D0, SP, CK, LSR, output Q ); FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; endmodule module o_PMU_OC_4_13_ ( input IOLDO, output oPMUOC413 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC413)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC413) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_4io[21] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_12_ ( input IOLDO, output oPMUOC412 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC412)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC412) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_12__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_4io[20] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_11_ ( input IOLDO, output oPMUOC411 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC411)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC411) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_11__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_4io[19] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_10_ ( input IOLDO, output oPMUOC410 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC410)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC410) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_4io[18] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_9_ ( input IOLDO, output oPMUOC49 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC49)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC49) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_4io[17] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_8_ ( input IOLDO, output oPMUOC48 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC48)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC48) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_8__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_4io[16] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_7_ ( input IOLDO, output oPMUOC47 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC47)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC47) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_4io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_6_ ( input IOLDO, output oPMUOC46 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC46)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC46) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_4io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_5_ ( input IOLDO, output oPMUOC45 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC45)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC45) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_5__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_4io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_4_ ( input IOLDO, output oPMUOC44 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC44)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC44) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_4io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_3_ ( input IOLDO, output oPMUOC43 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC43)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC43) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_4io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_2_ ( input IOLDO, output oPMUOC42 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC42)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC42) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_4io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_1_ ( input IOLDO, output oPMUOC41 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC41)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC41) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_4io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_4_0_ ( input IOLDO, output oPMUOC40 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_4_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC40)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC40) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_4_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_4io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_3_15_ ( input IOLDO, output oPMUOC315 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC315)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC315) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_15__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_3io[23] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_3_14_ ( input IOLDO, output oPMUOC314 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC314)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC314) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_14__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_3io[22] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_3_13_ ( input PADDO, output oPMUOC313 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC313)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC313) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_12_ ( input IOLDO, output oPMUOC312 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC312)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC312) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_12__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_3io[20] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_3_11_ ( input IOLDO, output oPMUOC311 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC311)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC311) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_11__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_3io[19] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_3_10_ ( input IOLDO, output oPMUOC310 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC310)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC310) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_10__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_3io[18] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_3_9_ ( input PADDO, output oPMUOC39 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC39)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC39) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_8_ ( input IOLDO, output oPMUOC38 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC38)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC38) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_8__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_3io[16] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_3_7_ ( input IOLDO, output oPMUOC37 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC37)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC37) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_3io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_3_6_ ( input IOLDO, output oPMUOC36 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC36)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC36) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_3io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_3_5_ ( input PADDO, output oPMUOC35 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC35)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC35) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_4_ ( input IOLDO, output oPMUOC34 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC34)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC34) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_3io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_3_3_ ( input IOLDO, output oPMUOC33 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC33)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC33) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_3io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_3_2_ ( input IOLDO, output oPMUOC32 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC32)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC32) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_3io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_3_1_ ( input PADDO, output oPMUOC31 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oPMUOC31)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oPMUOC31) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_0_ ( input IOLDO, output oPMUOC30 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_3_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC30)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC30) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_3_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_3io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_15_ ( input IOLDO, output oPMUOC215 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC215)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC215) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_15__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[23] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_14_ ( input IOLDO, output oPMUOC214 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC214)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC214) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_14__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[22] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_13_ ( input IOLDO, output oPMUOC213 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC213)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC213) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_13__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[21] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_12_ ( input IOLDO, output oPMUOC212 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC212)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC212) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_12__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[20] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_11_ ( input IOLDO, output oPMUOC211 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC211)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC211) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_11__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[19] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_10_ ( input IOLDO, output oPMUOC210 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC210)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC210) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_10__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[18] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_9_ ( input IOLDO, output oPMUOC29 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC29)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC29) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_9__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[17] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_8_ ( input IOLDO, output oPMUOC28 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC28)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC28) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_8__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[16] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_7_ ( input IOLDO, output oPMUOC27 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC27)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC27) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_6_ ( input IOLDO, output oPMUOC26 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC26)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC26) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_5_ ( input IOLDO, output oPMUOC25 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC25)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC25) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_4_ ( input IOLDO, output oPMUOC24 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC24)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC24) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_3_ ( input IOLDO, output oPMUOC23 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC23)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC23) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_2_ ( input IOLDO, output oPMUOC22 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC22)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC22) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_1_ ( input IOLDO, output oPMUOC21 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC21)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC21) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_2_0_ ( input IOLDO, output oPMUOC20 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_2_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC20)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC20) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_2_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_2io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_15_ ( input IOLDO, output oPMUOC115 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[15] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC115)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC115) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_15__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[23] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_14_ ( input IOLDO, output oPMUOC114 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[14] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC114)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC114) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_14__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[22] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_13_ ( input IOLDO, output oPMUOC113 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[13] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC113)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC113) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_13__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[21] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_12_ ( input IOLDO, output oPMUOC112 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[12] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC112)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC112) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_12__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[20] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_11_ ( input IOLDO, output oPMUOC111 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[11] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC111)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC111) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_11__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[19] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_10_ ( input IOLDO, output oPMUOC110 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[10] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC110)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC110) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_10__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[18] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_9_ ( input IOLDO, output oPMUOC19 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[9] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC19)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC19) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_9__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[17] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_8_ ( input IOLDO, output oPMUOC18 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[8] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC18)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC18) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_8__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_1io[16] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_7_ ( input IOLDO, output oPMUOC17 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[7] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC17)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC17) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_7__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_6_ ( input IOLDO, output oPMUOC16 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[6] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC16)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC16) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_6__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_5_ ( input IOLDO, output oPMUOC15 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[5] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC15)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC15) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_5__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_4_ ( input IOLDO, output oPMUOC14 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[4] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC14)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC14) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_4__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_3_ ( input IOLDO, output oPMUOC13 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[3] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC13)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC13) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_3__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_2_ ( input IOLDO, output oPMUOC12 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[2] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC12)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC12) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_2__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_1_ ( input IOLDO, output oPMUOC11 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[1] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC11)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC11) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; mfflsre0399 \CPLD_Con_1_PMU_OC_1io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(IOLDO)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_PMU_OC_1_0_ ( input IOLDO, output oPMUOC10 ); wire GNDI; xo2iobuf0398 \o_PMU_OC_1_pad[0] ( .I(IOLDO), .T(GNDI), .PAD(oPMUOC10)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => oPMUOC10) = (0:0:0,0:0:0); endspecify endmodule module o_PMU_OC_1_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_PMU_OC_1io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_DPSS_RC1 ( input PADDO, output o_DPSS_RC1 ); wire GNDI; xo2iobuf0397 o_DPSS_RC1_pad( .I(PADDO), .T(GNDI), .PAD(o_DPSS_RC1)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => o_DPSS_RC1) = (0:0:0,0:0:0); endspecify endmodule module o_DPSF_RC1 ( input PADDO, output o_DPSF_RC1 ); wire GNDI; xo2iobuf0397 o_DPSF_RC1_pad( .I(PADDO), .T(GNDI), .PAD(o_DPSF_RC1)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => o_DPSF_RC1) = (0:0:0,0:0:0); endspecify endmodule module o_SMMC_5_ ( input PADDO, output oSMMC5 ); xo2iobuf0395 \o_SMMC_pad[5] ( .I(PADDO), .PAD(oSMMC5)); specify (PADDO => oSMMC5) = (0:0:0,0:0:0); endspecify endmodule module o_SMMC_4_ ( input PADDO, output oSMMC4 ); xo2iobuf0395 \o_SMMC_pad[4] ( .I(PADDO), .PAD(oSMMC4)); specify (PADDO => oSMMC4) = (0:0:0,0:0:0); endspecify endmodule module o_SMMC_3_ ( input PADDO, output oSMMC3 ); xo2iobuf0395 \o_SMMC_pad[3] ( .I(PADDO), .PAD(oSMMC3)); specify (PADDO => oSMMC3) = (0:0:0,0:0:0); endspecify endmodule module o_SMMC_2_ ( input PADDO, output oSMMC2 ); xo2iobuf0395 \o_SMMC_pad[2] ( .I(PADDO), .PAD(oSMMC2)); specify (PADDO => oSMMC2) = (0:0:0,0:0:0); endspecify endmodule module o_SMMC_1_ ( input PADDO, output oSMMC1 ); xo2iobuf0395 \o_SMMC_pad[1] ( .I(PADDO), .PAD(oSMMC1)); specify (PADDO => oSMMC1) = (0:0:0,0:0:0); endspecify endmodule module o_SMMC_0_ ( input PADDO, output oSMMC0 ); xo2iobuf0395 \o_SMMC_pad[0] ( .I(PADDO), .PAD(oSMMC0)); specify (PADDO => oSMMC0) = (0:0:0,0:0:0); endspecify endmodule module o_FMMC_5_ ( input PADDO, output oFMMC5 ); wire GNDI; xo2iobuf0397 \o_FMMC_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oFMMC5)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oFMMC5) = (0:0:0,0:0:0); endspecify endmodule module o_FMMC_4_ ( input PADDO, output oFMMC4 ); wire GNDI; xo2iobuf0397 \o_FMMC_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oFMMC4)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oFMMC4) = (0:0:0,0:0:0); endspecify endmodule module o_FMMC_3_ ( input PADDO, output oFMMC3 ); wire GNDI; xo2iobuf0397 \o_FMMC_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oFMMC3)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oFMMC3) = (0:0:0,0:0:0); endspecify endmodule module o_FMMC_2_ ( input PADDO, output oFMMC2 ); wire GNDI; xo2iobuf0397 \o_FMMC_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oFMMC2)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oFMMC2) = (0:0:0,0:0:0); endspecify endmodule module o_FMMC_1_ ( input PADDO, output oFMMC1 ); wire GNDI; xo2iobuf0397 \o_FMMC_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oFMMC1)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oFMMC1) = (0:0:0,0:0:0); endspecify endmodule module o_FMMC_0_ ( input PADDO, output oFMMC0 ); wire GNDI; xo2iobuf0397 \o_FMMC_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oFMMC0)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oFMMC0) = (0:0:0,0:0:0); endspecify endmodule module o_SMC_3_ ( input PADDO, output oSMC3 ); xo2iobuf0395 \o_SMC_pad[3] ( .I(PADDO), .PAD(oSMC3)); specify (PADDO => oSMC3) = (0:0:0,0:0:0); endspecify endmodule module o_SMC_2_ ( input PADDO, output oSMC2 ); xo2iobuf0395 \o_SMC_pad[2] ( .I(PADDO), .PAD(oSMC2)); specify (PADDO => oSMC2) = (0:0:0,0:0:0); endspecify endmodule module o_SMC_1_ ( input PADDO, output oSMC1 ); xo2iobuf0395 \o_SMC_pad[1] ( .I(PADDO), .PAD(oSMC1)); specify (PADDO => oSMC1) = (0:0:0,0:0:0); endspecify endmodule module o_SMC_0_ ( input PADDO, output oSMC0 ); xo2iobuf0395 \o_SMC_pad[0] ( .I(PADDO), .PAD(oSMC0)); specify (PADDO => oSMC0) = (0:0:0,0:0:0); endspecify endmodule module o_FMC_3_ ( input PADDO, output oFMC3 ); wire GNDI; xo2iobuf0397 \o_FMC_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oFMC3)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oFMC3) = (0:0:0,0:0:0); endspecify endmodule module o_FMC_2_ ( input PADDO, output oFMC2 ); wire GNDI; xo2iobuf0397 \o_FMC_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oFMC2)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oFMC2) = (0:0:0,0:0:0); endspecify endmodule module o_FMC_1_ ( input PADDO, output oFMC1 ); wire GNDI; xo2iobuf0397 \o_FMC_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oFMC1)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oFMC1) = (0:0:0,0:0:0); endspecify endmodule module o_FMC_0_ ( input PADDO, output oFMC0 ); wire GNDI; xo2iobuf0397 \o_FMC_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oFMC0)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oFMC0) = (0:0:0,0:0:0); endspecify endmodule module o_RC_LOS_1_ ( input PADDO, output oRCLOS1 ); wire GNDI; xo2iobuf0398 \o_RC_LOS_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCLOS1)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCLOS1) = (0:0:0,0:0:0); endspecify endmodule module o_RC_LOS_0_ ( input PADDO, output oRCLOS0 ); wire GNDI; xo2iobuf0398 \o_RC_LOS_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCLOS0)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCLOS0) = (0:0:0,0:0:0); endspecify endmodule module o_RC_LOF_1_ ( input PADDO, output oRCLOF1 ); wire GNDI; xo2iobuf0398 \o_RC_LOF_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCLOF1)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCLOF1) = (0:0:0,0:0:0); endspecify endmodule module o_RC_LOF_0_ ( input PADDO, output oRCLOF0 ); wire GNDI; xo2iobuf0398 \o_RC_LOF_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCLOF0)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCLOF0) = (0:0:0,0:0:0); endspecify endmodule module o_RC_ISel ( input PADDO, output o_RC_ISel ); wire GNDI; xo2iobuf0398 o_RC_ISel_pad( .I(PADDO), .T(GNDI), .PAD(o_RC_ISel)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => o_RC_ISel) = (0:0:0,0:0:0); endspecify endmodule module o_RC_VSel ( input PADDO, output o_RC_VSel ); wire GNDI; xo2iobuf0398 o_RC_VSel_pad( .I(PADDO), .T(GNDI), .PAD(o_RC_VSel)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => o_RC_VSel) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_17_ ( input PADDO, output oRCRLSel17 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[17] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel17)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel17) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_16_ ( input PADDO, output oRCRLSel16 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[16] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel16)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel16) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_15_ ( input PADDO, output oRCRLSel15 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel15)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel15) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_14_ ( input PADDO, output oRCRLSel14 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel14)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel14) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_13_ ( input PADDO, output oRCRLSel13 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel13)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel13) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_12_ ( input PADDO, output oRCRLSel12 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel12)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel12) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_11_ ( input PADDO, output oRCRLSel11 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel11)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel11) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_10_ ( input PADDO, output oRCRLSel10 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel10)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel10) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_9_ ( input PADDO, output oRCRLSel9 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel9)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel9) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_8_ ( input PADDO, output oRCRLSel8 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel8)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel8) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_7_ ( input PADDO, output oRCRLSel7 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel7)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel7) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_6_ ( input PADDO, output oRCRLSel6 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel6)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel6) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_5_ ( input PADDO, output oRCRLSel5 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel5)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel5) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_4_ ( input PADDO, output oRCRLSel4 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel4)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel4) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_3_ ( input PADDO, output oRCRLSel3 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel3)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel3) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_2_ ( input PADDO, output oRCRLSel2 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel2)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel2) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_1_ ( input PADDO, output oRCRLSel1 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel1)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel1) = (0:0:0,0:0:0); endspecify endmodule module o_RC_RLSel_0_ ( input PADDO, output oRCRLSel0 ); wire GNDI; xo2iobuf0397 \o_RC_RLSel_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oRCRLSel0)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oRCRLSel0) = (0:0:0,0:0:0); endspecify endmodule module o_RC_T32 ( input IOLDO, output o_RC_T32 ); wire GNDI; xo2iobuf0398 o_RC_T32_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T32)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => o_RC_T32) = (0:0:0,0:0:0); endspecify endmodule module o_RC_T32_MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_RC_Txio[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_RC_T31 ( input IOLDO, output o_RC_T31 ); wire GNDI; xo2iobuf0398 o_RC_T31_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T31)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => o_RC_T31) = (0:0:0,0:0:0); endspecify endmodule module o_RC_T31_MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_RC_Txio[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_RC_T30 ( input IOLDO, output o_RC_T30 ); wire GNDI; xo2iobuf0398 o_RC_T30_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T30)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => o_RC_T30) = (0:0:0,0:0:0); endspecify endmodule module o_RC_T30_MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_RC_Txio[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_RC_T29 ( input IOLDO, output o_RC_T29 ); wire GNDI; xo2iobuf0398 o_RC_T29_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T29)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => o_RC_T29) = (0:0:0,0:0:0); endspecify endmodule module o_RC_T29_MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_RC_Txio[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_RC_T28 ( input IOLDO, output o_RC_T28 ); wire GNDI; xo2iobuf0398 o_RC_T28_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T28)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => o_RC_T28) = (0:0:0,0:0:0); endspecify endmodule module o_RC_T28_MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_RC_Txio[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_RC_T27 ( input IOLDO, output o_RC_T27 ); wire GNDI; xo2iobuf0398 o_RC_T27_pad( .I(IOLDO), .T(GNDI), .PAD(o_RC_T27)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => o_RC_T27) = (0:0:0,0:0:0); endspecify endmodule module o_RC_T27_MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre \CPLD_Con_1_RC_Txio[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_IO_RC1 ( input IOLDO, output o_IO_RC1 ); wire GNDI; xo2iobuf0398 o_IO_RC1_pad( .I(IOLDO), .T(GNDI), .PAD(o_IO_RC1)); gnd DRIVEGND( .PWR0(GNDI)); specify (IOLDO => o_IO_RC1) = (0:0:0,0:0:0); endspecify endmodule module o_IO_RC1_MGIOL ( output IOLDO, input OPOS, CE, CLK ); wire GNDI, OPOS_dly, CLK_dly, CE_dly; mfflsre CPLD_Con_1_io_RCio( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(IOLDO)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLK => IOLDO) = (0:0:0,0:0:0); $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module o_DMM_EN_18_ ( input PADDO, output oDMMEN18 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[18] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN18)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN18) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_17_ ( input PADDO, output oDMMEN17 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[17] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN17)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN17) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_16_ ( input PADDO, output oDMMEN16 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[16] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN16)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN16) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_15_ ( input PADDO, output oDMMEN15 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[15] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN15)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN15) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_14_ ( input PADDO, output oDMMEN14 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[14] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN14)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN14) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_13_ ( input PADDO, output oDMMEN13 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[13] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN13)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN13) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_12_ ( input PADDO, output oDMMEN12 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[12] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN12)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN12) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_11_ ( input PADDO, output oDMMEN11 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[11] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN11)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN11) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_10_ ( input PADDO, output oDMMEN10 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[10] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN10)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN10) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_9_ ( input PADDO, output oDMMEN9 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[9] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN9)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN9) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_8_ ( input PADDO, output oDMMEN8 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[8] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN8)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN8) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_7_ ( input PADDO, output oDMMEN7 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[7] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN7)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN7) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_6_ ( input PADDO, output oDMMEN6 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[6] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN6)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN6) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_5_ ( input PADDO, output oDMMEN5 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[5] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN5)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN5) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_4_ ( input PADDO, output oDMMEN4 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[4] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN4)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN4) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_3_ ( input PADDO, output oDMMEN3 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[3] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN3)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN3) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_2_ ( input PADDO, output oDMMEN2 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[2] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN2)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN2) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_1_ ( input PADDO, output oDMMEN1 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[1] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN1)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN1) = (0:0:0,0:0:0); endspecify endmodule module o_DMM_EN_0_ ( input PADDO, output oDMMEN0 ); wire GNDI; xo2iobuf0397 \o_DMM_EN_pad[0] ( .I(PADDO), .T(GNDI), .PAD(oDMMEN0)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => oDMMEN0) = (0:0:0,0:0:0); endspecify endmodule module o_con_done ( input PADDO, output o_con_done ); wire GNDI; xo2iobuf0398 o_con_done_pad( .I(PADDO), .T(GNDI), .PAD(o_con_done)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => o_con_done) = (0:0:0,0:0:0); endspecify endmodule module o_err ( input PADDO, output o_err ); wire GNDI; xo2iobuf0398 o_err_pad( .I(PADDO), .T(GNDI), .PAD(o_err)); gnd DRIVEGND( .PWR0(GNDI)); specify (PADDO => o_err) = (0:0:0,0:0:0); endspecify endmodule module i_cs ( output PADDI, input i_cs ); xo2iobuf0396 i_cs_pad( .Z(PADDI), .PAD(i_cs)); specify (i_cs => PADDI) = (0:0:0,0:0:0); $width (posedge i_cs, 0:0:0); $width (negedge i_cs, 0:0:0); endspecify endmodule module i_cs_MGIOL ( input DI, LSR, CLK, output IN ); wire VCCI, LSR_NOTIN, DI_dly, CLK_dly, LSR_dly; smuxlregsre \BUS_Con_1_cs_syncio[0] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IN)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (CLK => IN) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module smuxlregsre ( input D0, SP, CK, LSR, output Q ); IFS1P3JX INST01( .D(D0), .SP(SP), .SCLK(CK), .PD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; endmodule module i_mosi ( output PADDI, input i_mosi ); xo2iobuf0396 i_mosi_pad( .Z(PADDI), .PAD(i_mosi)); specify (i_mosi => PADDI) = (0:0:0,0:0:0); $width (posedge i_mosi, 0:0:0); $width (negedge i_mosi, 0:0:0); endspecify endmodule module i_mosi_MGIOL ( input DI, LSR, CLK, output IN ); wire VCCI, LSR_NOTIN, DI_dly, CLK_dly, LSR_dly; smuxlregsre0400 \BUS_Con_1_mosi_syncio[0] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IN)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (CLK => IN) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module smuxlregsre0400 ( input D0, SP, CK, LSR, output Q ); IFS1P3IX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); defparam INST01.GSR = "DISABLED"; endmodule module i_sclk ( output PADDI, input i_sclk ); xo2iobuf0396 i_sclk_pad( .Z(PADDI), .PAD(i_sclk)); specify (i_sclk => PADDI) = (0:0:0,0:0:0); $width (posedge i_sclk, 0:0:0); $width (negedge i_sclk, 0:0:0); endspecify endmodule module i_sclk_MGIOL ( input DI, LSR, CLK, output IN ); wire VCCI, LSR_NOTIN, DI_dly, CLK_dly, LSR_dly; smuxlregsre0400 \BUS_Con_1_sclk_syncio[0] ( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(LSR_NOTIN), .Q(IN)); vcc DRIVEVCC( .PWR1(VCCI)); inverter LSR_INVERTERIN( .I(LSR_dly), .Z(LSR_NOTIN)); specify (CLK => IN) = (0:0:0,0:0:0); $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); $width (posedge CLK, 0:0:0); $width (negedge CLK, 0:0:0); endspecify endmodule module i_rst_n ( output PADDI, input i_rst_n ); xo2iobuf0396 i_rst_n_pad( .Z(PADDI), .PAD(i_rst_n)); specify (i_rst_n => PADDI) = (0:0:0,0:0:0); $width (posedge i_rst_n, 0:0:0); $width (negedge i_rst_n, 0:0:0); endspecify endmodule module RelayConTop_reveal_coretop_instance_GSR_INST ( input GSRNET ); GSR5MODE \RelayConTop_reveal_coretop_instance/GSR_INST_GSRMODE ( .GSR(GSRNET)); specify endspecify endmodule module GSR5MODE ( input GSR ); wire GSRMODE; BUFBA INST10( .A(GSR), .Z(GSRMODE)); GSR INST20( .GSR(GSRMODE)); endmodule module lsblk0onTop_reveal_coretop_instance_relaycontop_la0_inst_0_trig_u_te_0_genblk1_te_tt_ebr_ram_pmi_ram_dpXbnonesadr112112p12e1aace_0_0_0 ( input DIA1, ADA0, WEA, CLKA, CLKB, output DOB0, input ADB0 ); wire VCCI, GNDI, DIA1_dly, CLKA_dly, ADA0_dly, WEA_dly, ADB0_dly, CLKB_dly; DP8KC_B \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/trig_u/te_0/genblk1.te_tt_ebr_ram/pmi_ram_dpXbnonesadr112112p12e1aace_0_0_0_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(GNDI), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_dly), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(GNDI), .DIA0(GNDI), .DIA1(DIA1_dly), .DIA2(GNDI), .DIA3(GNDI), .DIA4(GNDI), .DIA5(GNDI), .DIA6(GNDI), .DIA7(GNDI), .DIA8(GNDI), .ADA0(ADA0_dly), .ADA1(GNDI), .ADA2(GNDI), .ADA3(GNDI), .ADA4(GNDI), .ADA5(GNDI), .ADA6(GNDI), .ADA7(GNDI), .ADA8(GNDI), .ADA9(GNDI), .ADA10(GNDI), .ADA11(GNDI), .ADA12(GNDI), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(ADB0_dly), .ADB1(GNDI), .ADB2(GNDI), .ADB3(GNDI), .ADB4(GNDI), .ADB5(GNDI), .ADB6(GNDI), .ADB7(GNDI), .ADB8(GNDI), .ADB9(GNDI), .ADB10(GNDI), .ADB11(GNDI), .ADB12(GNDI), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(), .DOB2(), .DOB3(), .DOB4(), .DOB5(), .DOB6(), .DOB7(), .DOB8()); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); specify (CLKB => DOB0) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, ADA0, 0:0:0, 0:0:0,,,, CLKA_dly, ADA0_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKB, ADB0, 0:0:0, 0:0:0,,,, CLKB_dly, ADB0_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); endspecify endmodule module DP8KC_B ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 1; defparam INST10.DATA_WIDTH_B = 1; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk1ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_23_0 ( input DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA5_dly, CLKA_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0401 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_23_0_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(GNDI), .DIA7(GNDI), .DIA8(GNDI), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(), .DOB7(), .DOB8()); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0401 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk2ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_0_23 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0402 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_0_23_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0402 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk3ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_1_22 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0403 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_1_22_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0403 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk4ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_2_21 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0404 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_2_21_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0404 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk5ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_3_20 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0405 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_3_20_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0405 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk6ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_4_19 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0406 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_4_19_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0406 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk7ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_5_18 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0407 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_5_18_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0407 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk8ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_6_17 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0408 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_6_17_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0408 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk9ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_7_16 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0409 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_7_16_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0409 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk10ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_8_15 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0410 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_8_15_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0410 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk11ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_9_14 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0411 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_9_14_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0411 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk12onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_10_13 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0412 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_10_13_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0412 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk13onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_11_12 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0413 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_11_12_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0413 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk14onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_12_11 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0414 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_12_11_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0414 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk15onTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_13_10 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0415 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_13_10_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0415 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk16ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_14_9 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0416 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_14_9_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0416 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk17ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_15_8 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0417 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_15_8_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0417 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk18ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_16_7 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0418 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_16_7_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0418 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk19ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_17_6 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0419 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_17_6_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0419 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk20ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_18_5 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0420 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_18_5_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0420 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk21ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_19_4 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0421 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_19_4_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0421 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk22ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_20_3 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0422 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_20_3_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0422 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk23ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_21_2 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0423 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_21_2_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0423 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module lsblk24ConTop_reveal_coretop_instance_relaycontop_la0_inst_0_tm_u_genblk4_tr_mem_pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_22_1 ( input DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, WEA, RSTA, CLKA, CLKB, RSTB, output DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8, input ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12 ); wire VCCI, GNDI, RSTA_NOTIN, CLKB_NOTIN, RSTB_NOTIN, DIA8_dly, CLKA_dly, DIA7_dly, DIA6_dly, DIA5_dly, DIA4_dly, DIA3_dly, DIA2_dly, DIA1_dly, DIA0_dly, ADA12_dly, ADA11_dly, ADA10_dly, ADA9_dly, ADA8_dly, ADA7_dly, ADA6_dly, ADA5_dly, ADA4_dly, ADA3_dly, WEA_dly, RSTA_dly, RSTB_dly, CLKB_dly, ADB3_dly, ADB4_dly, ADB5_dly, ADB6_dly, ADB7_dly, ADB8_dly, ADB9_dly, ADB10_dly, ADB11_dly, ADB12_dly; DP8KC0424 \RelayConTop_reveal_coretop_instance/relaycontop_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr213101024213101024p13b96eed_0_22_1_DP8KC ( .CEA(VCCI), .OCEA(VCCI), .CLKA(CLKA_dly), .WEA(WEA_dly), .CSA0(GNDI), .CSA1(GNDI), .CSA2(GNDI), .RSTA(RSTA_NOTIN), .CEB(VCCI), .OCEB(VCCI), .CLKB(CLKB_NOTIN), .WEB(GNDI), .CSB0(GNDI), .CSB1(GNDI), .CSB2(GNDI), .RSTB(RSTB_NOTIN), .DIA0(DIA0_dly), .DIA1(DIA1_dly), .DIA2(DIA2_dly), .DIA3(DIA3_dly), .DIA4(DIA4_dly), .DIA5(DIA5_dly), .DIA6(DIA6_dly), .DIA7(DIA7_dly), .DIA8(DIA8_dly), .ADA0(VCCI), .ADA1(GNDI), .ADA2(GNDI), .ADA3(ADA3_dly), .ADA4(ADA4_dly), .ADA5(ADA5_dly), .ADA6(ADA6_dly), .ADA7(ADA7_dly), .ADA8(ADA8_dly), .ADA9(ADA9_dly), .ADA10(ADA10_dly), .ADA11(ADA11_dly), .ADA12(ADA12_dly), .DIB0(GNDI), .DIB1(GNDI), .DIB2(GNDI), .DIB3(GNDI), .DIB4(GNDI), .DIB5(GNDI), .DIB6(GNDI), .DIB7(GNDI), .DIB8(GNDI), .ADB0(GNDI), .ADB1(GNDI), .ADB2(GNDI), .ADB3(ADB3_dly), .ADB4(ADB4_dly), .ADB5(ADB5_dly), .ADB6(ADB6_dly), .ADB7(ADB7_dly), .ADB8(ADB8_dly), .ADB9(ADB9_dly), .ADB10(ADB10_dly), .ADB11(ADB11_dly), .ADB12(ADB12_dly), .DOA0(), .DOA1(), .DOA2(), .DOA3(), .DOA4(), .DOA5(), .DOA6(), .DOA7(), .DOA8(), .DOB0(DOB0), .DOB1(DOB1), .DOB2(DOB2), .DOB3(DOB3), .DOB4(DOB4), .DOB5(DOB5), .DOB6(DOB6), .DOB7(DOB7), .DOB8(DOB8)); vcc DRIVEVCC( .PWR1(VCCI)); gnd DRIVEGND( .PWR0(GNDI)); inverter RSTA_INVERTERIN( .I(RSTA_dly), .Z(RSTA_NOTIN)); inverter CLKB_INVERTERIN( .I(CLKB_dly), .Z(CLKB_NOTIN)); inverter RSTB_INVERTERIN( .I(RSTB_dly), .Z(RSTB_NOTIN)); specify (CLKB => DOB0) = (0:0:0,0:0:0); (CLKB => DOB1) = (0:0:0,0:0:0); (CLKB => DOB2) = (0:0:0,0:0:0); (CLKB => DOB3) = (0:0:0,0:0:0); (CLKB => DOB4) = (0:0:0,0:0:0); (CLKB => DOB5) = (0:0:0,0:0:0); (CLKB => DOB6) = (0:0:0,0:0:0); (CLKB => DOB7) = (0:0:0,0:0:0); (CLKB => DOB8) = (0:0:0,0:0:0); $setuphold (posedge CLKA, DIA8, 0:0:0, 0:0:0,,,, CLKA_dly, DIA8_dly); $setuphold (posedge CLKA, DIA7, 0:0:0, 0:0:0,,,, CLKA_dly, DIA7_dly); $setuphold (posedge CLKA, DIA6, 0:0:0, 0:0:0,,,, CLKA_dly, DIA6_dly); $setuphold (posedge CLKA, DIA5, 0:0:0, 0:0:0,,,, CLKA_dly, DIA5_dly); $setuphold (posedge CLKA, DIA4, 0:0:0, 0:0:0,,,, CLKA_dly, DIA4_dly); $setuphold (posedge CLKA, DIA3, 0:0:0, 0:0:0,,,, CLKA_dly, DIA3_dly); $setuphold (posedge CLKA, DIA2, 0:0:0, 0:0:0,,,, CLKA_dly, DIA2_dly); $setuphold (posedge CLKA, DIA1, 0:0:0, 0:0:0,,,, CLKA_dly, DIA1_dly); $setuphold (posedge CLKA, DIA0, 0:0:0, 0:0:0,,,, CLKA_dly, DIA0_dly); $setuphold (posedge CLKA, ADA12, 0:0:0, 0:0:0,,,, CLKA_dly, ADA12_dly); $setuphold (posedge CLKA, ADA11, 0:0:0, 0:0:0,,,, CLKA_dly, ADA11_dly); $setuphold (posedge CLKA, ADA10, 0:0:0, 0:0:0,,,, CLKA_dly, ADA10_dly); $setuphold (posedge CLKA, ADA9, 0:0:0, 0:0:0,,,, CLKA_dly, ADA9_dly); $setuphold (posedge CLKA, ADA8, 0:0:0, 0:0:0,,,, CLKA_dly, ADA8_dly); $setuphold (posedge CLKA, ADA7, 0:0:0, 0:0:0,,,, CLKA_dly, ADA7_dly); $setuphold (posedge CLKA, ADA6, 0:0:0, 0:0:0,,,, CLKA_dly, ADA6_dly); $setuphold (posedge CLKA, ADA5, 0:0:0, 0:0:0,,,, CLKA_dly, ADA5_dly); $setuphold (posedge CLKA, ADA4, 0:0:0, 0:0:0,,,, CLKA_dly, ADA4_dly); $setuphold (posedge CLKA, ADA3, 0:0:0, 0:0:0,,,, CLKA_dly, ADA3_dly); $setuphold (posedge CLKA, WEA, 0:0:0, 0:0:0,,,, CLKA_dly, WEA_dly); $setuphold (posedge CLKA, RSTA, 0:0:0, 0:0:0,,,, CLKA_dly, RSTA_dly); $width (posedge CLKA, 0:0:0); $width (negedge CLKA, 0:0:0); $width (posedge CLKB, 0:0:0); $width (negedge CLKB, 0:0:0); $setuphold (negedge CLKB, RSTB, 0:0:0, 0:0:0,,,, CLKB_dly, RSTB_dly); $setuphold (negedge CLKB, ADB3, 0:0:0, 0:0:0,,,, CLKB_dly, ADB3_dly); $setuphold (negedge CLKB, ADB4, 0:0:0, 0:0:0,,,, CLKB_dly, ADB4_dly); $setuphold (negedge CLKB, ADB5, 0:0:0, 0:0:0,,,, CLKB_dly, ADB5_dly); $setuphold (negedge CLKB, ADB6, 0:0:0, 0:0:0,,,, CLKB_dly, ADB6_dly); $setuphold (negedge CLKB, ADB7, 0:0:0, 0:0:0,,,, CLKB_dly, ADB7_dly); $setuphold (negedge CLKB, ADB8, 0:0:0, 0:0:0,,,, CLKB_dly, ADB8_dly); $setuphold (negedge CLKB, ADB9, 0:0:0, 0:0:0,,,, CLKB_dly, ADB9_dly); $setuphold (negedge CLKB, ADB10, 0:0:0, 0:0:0,,,, CLKB_dly, ADB10_dly); $setuphold (negedge CLKB, ADB11, 0:0:0, 0:0:0,,,, CLKB_dly, ADB11_dly); $setuphold (negedge CLKB, ADB12, 0:0:0, 0:0:0,,,, CLKB_dly, ADB12_dly); endspecify endmodule module DP8KC0424 ( input CEA, OCEA, CLKA, WEA, CSA0, CSA1, CSA2, RSTA, CEB, OCEB, CLKB, WEB, CSB0, CSB1, CSB2, RSTB, DIA0, DIA1, DIA2, DIA3, DIA4, DIA5, DIA6, DIA7, DIA8, ADA0, ADA1, ADA2, ADA3, ADA4, ADA5, ADA6, ADA7, ADA8, ADA9, ADA10, ADA11, ADA12, DIB0, DIB1, DIB2, DIB3, DIB4, DIB5, DIB6, DIB7, DIB8, ADB0, ADB1, ADB2, ADB3, ADB4, ADB5, ADB6, ADB7, ADB8, ADB9, ADB10, ADB11, ADB12, output DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7, DOA8, DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7, DOB8 ); DP8KC INST10( .DIA8(DIA8), .DIA7(DIA7), .DIA6(DIA6), .DIA5(DIA5), .DIA4(DIA4), .DIA3(DIA3), .DIA2(DIA2), .DIA1(DIA1), .DIA0(DIA0), .ADA12(ADA12), .ADA11(ADA11), .ADA10(ADA10), .ADA9(ADA9), .ADA8(ADA8), .ADA7(ADA7), .ADA6(ADA6), .ADA5(ADA5), .ADA4(ADA4), .ADA3(ADA3), .ADA2(ADA2), .ADA1(ADA1), .ADA0(ADA0), .CEA(CEA), .OCEA(OCEA), .CLKA(CLKA), .WEA(WEA), .CSA2(CSA2), .CSA1(CSA1), .CSA0(CSA0), .RSTA(RSTA), .DIB8(DIB8), .DIB7(DIB7), .DIB6(DIB6), .DIB5(DIB5), .DIB4(DIB4), .DIB3(DIB3), .DIB2(DIB2), .DIB1(DIB1), .DIB0(DIB0), .ADB12(ADB12), .ADB11(ADB11), .ADB10(ADB10), .ADB9(ADB9), .ADB8(ADB8), .ADB7(ADB7), .ADB6(ADB6), .ADB5(ADB5), .ADB4(ADB4), .ADB3(ADB3), .ADB2(ADB2), .ADB1(ADB1), .ADB0(ADB0), .CEB(CEB), .OCEB(OCEB), .CLKB(CLKB), .WEB(WEB), .CSB2(CSB2), .CSB1(CSB1), .CSB0(CSB0), .RSTB(RSTB), .DOA8(DOA8), .DOA7(DOA7), .DOA6(DOA6), .DOA5(DOA5), .DOA4(DOA4), .DOA3(DOA3), .DOA2(DOA2), .DOA1(DOA1), .DOA0(DOA0), .DOB8(DOB8), .DOB7(DOB7), .DOB6(DOB6), .DOB5(DOB5), .DOB4(DOB4), .DOB3(DOB3), .DOB2(DOB2), .DOB1(DOB1), .DOB0(DOB0)); defparam INST10.ASYNC_RESET_RELEASE = "ASYNC"; defparam INST10.CSDECODE_A = "0b000"; defparam INST10.CSDECODE_B = "0b000"; defparam INST10.DATA_WIDTH_A = 9; defparam INST10.DATA_WIDTH_B = 9; defparam INST10.GSR = "DISABLED"; defparam INST10.INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; defparam INST10.INIT_DATA = "STATIC"; defparam INST10.REGMODE_A = "OUTREG"; defparam INST10.REGMODE_B = "OUTREG"; defparam INST10.RESETMODE = "ASYNC"; defparam INST10.WRITEMODE_A = "NORMAL"; defparam INST10.WRITEMODE_B = "NORMAL"; endmodule module xo2chub_genblk7_jtagf_u ( input JTDO1, JTDO2, output JCE2, JCE1, JRSTN, JUPDATE, JSHIFT, JTCK, JTDI ); JTAGF_B \xo2chub/genblk7.jtagf_u_JTAGF ( .TCK(), .TMS(), .TDI(), .JTDO1(JTDO1), .JTDO2(JTDO2), .TDO(), .JTDI(JTDI), .JTCK(JTCK), .JRTI1(), .JRTI2(), .JSHIFT(JSHIFT), .JUPDATE(JUPDATE), .JRSTN(JRSTN), .JCE1(JCE1), .JCE2(JCE2)); specify endspecify endmodule module JTAGF_B ( input TCK, TMS, TDI, JTDO1, JTDO2, output TDO, JTDI, JTCK, JRTI1, JRTI2, JSHIFT, JUPDATE, JRSTN, JCE1, JCE2 ); JTAGF INST10( .TCK(TCK), .TMS(TMS), .TDI(TDI), .JTDO1(JTDO1), .JTDO2(JTDO2), .TDO(TDO), .JTCK(JTCK), .JTDI(JTDI), .JSHIFT(JSHIFT), .JUPDATE(JUPDATE), .JRSTN(JRSTN), .JCE1(JCE1), .JCE2(JCE2), .JRTI1(JRTI1), .JRTI2(JRTI2)); defparam INST10.ER1 = "ENABLED"; defparam INST10.ER2 = "ENABLED"; endmodule