module RelayConTop (
	input i_sys_clk,
	input i_rst_n,
	
	input i_sclk,
	input i_mosi,
	input i_cs,
	output o_miso,
	//output o_rvalid,
	input i_rready,
	input i_wvalid,
	output o_wready,
	output o_err,
	output o_con_done,
    output [18:0]o_DMM_EN,
    output o_IO_RC1,
	output o_RC_T27,
	output o_RC_T28,
	output o_RC_T29,
	output o_RC_T30,
	output o_RC_T31,
	output o_RC_T32,

	output [17:0]o_RC_RLSel,
	output o_RC_VSel,
	output o_RC_ISel,

	output [1:0]o_RC_LOF,					//Strange DMM_N port relay
	output [1:0]o_RC_LOS,

	output [3:0]o_FMC ,
	output [3:0]o_SMC ,
	output [5:0]o_FMMC ,
	output [5:0]o_SMMC ,

	output o_DPSF_RC1	,
	output o_DPSS_RC1	,

	output [15:0]o_PMU_OC_1,
	output [15:0]o_PMU_OC_2,
	output [15:0]o_PMU_OC_3,
	output [15:0]o_PMU_OC_4,

	output [15:0]o_DPS_F_1	,
	output [15:0]o_DPS_S_1	,
	output [15:0]o_DPS_F_2	,
	output [15:0]o_DPS_S_2	,
	output [15:0]o_DPS_F_3	,
	output [15:0]o_DPS_S_3	,
	output [15:0]o_DPS_F_4	,
	output [15:0]o_DPS_S_4	
	
);
	wire [3:0]OC_x01;
	wire [3:0]OC_x17;
	wire [5:0]RC_Tx;

	wire [18:0]DMM_EN;
	wire IO_RC1;


	wire [23:0]r_data ;
	wire [23:0]w_data ;
	wire [6:0]reg_addr ;

	wire cmd_valid;
	wire reg_busy;
	wire wr_flag;						//1=write,0=read
	wire bus_err_flag;
	wire reg_err_flag;
	wire cpld_err_flag;

	wire con_exec;
	wire [23:0]freq1_relay ;
	wire [23:0]freq2_relay ;
	wire [23:0]freq3_relay ;
	wire [23:0]freq4_relay ;

	//DC Control Reg output
	wire [23:0]DC_Con1 ;
	wire [23:0]DC_Con2 ;
	wire [23:0]DC_Con3 ;
	wire [23:0]DC_Con4 ;

	//PMU OC Control
	wire [31:0]PMU_OC_1 ;
	wire [31:0]PMU_OC_2 ;
	wire [31:0]PMU_OC_3 ;
	wire [31:0]PMU_OC_4 ;

	//DPS PerChannel Force/Sense Control
	wire [15:0]DPS_FS_1	;
	wire [15:0]DPS_FS_2	;
	wire [15:0]DPS_FS_3	;
	wire [15:0]DPS_FS_4	;

	//DPS Level Control
	wire [3:0]FSMC ;
	wire [5:0]FSMMC ;
	
	//DPS Output Control
	wire DPSFS_RC1 ;

	//RL Control
	wire [17:0]RC_RLSel ;

	//DMM V Select
	wire RC_VSel;
	//DMM I Select
	wire RC_ISel;

	//Force/Sense Control
	wire [1:0]RC_LOFS ;

	wire con_rvalid;

	wire con_done;

	BUS_Con BUS_Con_1(
		.i_sys_clk(i_sys_clk),
		.i_rst_n(i_rst_n),
		.i_sclk(i_sclk),
		.i_mosi(i_mosi),
		.i_cs(i_cs),
		.i_rvalid(con_rvalid),
		.i_wvalid(i_wvalid),
		.i_reg_busy(reg_busy),
		.i_rdata(r_data),
		.o_cmd_valid(cmd_valid),
		.o_wr(wr_flag),
 		.o_miso(o_miso),
		.o_rvalid(o_rvalid),
		.o_wready(o_wready),
		.o_data(w_data),
		.o_addr(reg_addr),
		.o_err(bus_err_flag)
	);

	Reg_file CPLD_Reg_1(
		.i_sys_clk(i_sys_clk),
		.i_rst_n(i_rst_n),
		.i_wr_req(cmd_valid),
		.i_wr(wr_flag),
		.i_addr(reg_addr),
		.i_wdata(w_data),
		.i_con_done(con_done),                               	//Controller Exec Done
		.o_freq1(freq1_relay),                            		//Freq_Slot1
		.o_freq2(freq2_relay),                            		//Freq_Slot2
		.o_freq3(freq3_relay),                            		//Freq_Slot3 
		.o_freq4(freq4_relay),									//Freq_Slot4
		.o_DC1(DC_Con1),
		.o_DC2(DC_Con2),
		.o_DC3(DC_Con3),
		.o_DC4(DC_Con4),
		.o_rvalid(con_rvalid),
		.o_rdata(r_data),
		.o_exec(con_exec),                                  	//Exec cmd
		.o_busy(reg_busy),
		.o_err(reg_err_flag)
	);
	
	CPLD_Con CPLD_Con_1(
		.i_sys_clk(i_sys_clk),
		.i_rst_n(i_rst_n),
		.i_con_exec(con_exec),
		.i_freq_relay1(freq1_relay),
		.i_freq_relay2(freq2_relay),
		.i_freq_relay3(freq3_relay),
		.i_freq_relay4(freq4_relay),
		.i_DC_Con1(DC_Con1),
		.i_DC_Con2(DC_Con2),
		.i_DC_Con3(DC_Con3),
		.i_DC_Con4(DC_Con4),
		.o_con_done(con_done),
		.o_RC_Tx(RC_Tx),
  		.o_DMM_EN(DMM_EN),
		.o_PMU_OC_1(PMU_OC_1),
		.o_PMU_OC_2(PMU_OC_2),
		.o_PMU_OC_3(PMU_OC_3),
		.o_PMU_OC_4(PMU_OC_4),
		.o_DPS_FS_1(DPS_FS_1),
		.o_DPS_FS_2(DPS_FS_2),
		.o_DPS_FS_3(DPS_FS_3),
		.o_DPS_FS_4(DPS_FS_4),
		.o_DPS_FSMC(FSMC),
		.o_DPS_FSMMC(FSMMC),
		.o_DPSFS_RC1(DPSFS_RC1),
    	.o_RC_VSel(RC_VSel),
    	.o_RC_ISel(RC_ISel),
		.o_RC_LOFS(RC_LOFS),
		.o_RC_RLSel(RC_RLSel),
  		.o_IO_RC1(IO_RC1),
  		.o_err(cpld_err_flag)
	);

	assign o_con_done = con_done;

	//Low on PIO resource, we need to only set pins this CPLD handles
	assign o_PMU_OC_1 = {PMU_OC_1[23:16],PMU_OC_1[7:0]};
	assign o_PMU_OC_2 = {PMU_OC_2[23:16],PMU_OC_2[7:0]};
	assign o_PMU_OC_3 = {PMU_OC_3[23:16],PMU_OC_3[7:0]};
	assign o_PMU_OC_4 = {PMU_OC_4[23:16],PMU_OC_4[7:0]};

	assign o_DMM_EN = DMM_EN;
	assign o_IO_RC1 = IO_RC1;

	assign o_RC_T27 = RC_Tx[0];
	assign o_RC_T28 = RC_Tx[1];
	assign o_RC_T29 = RC_Tx[2];
	assign o_RC_T30 = RC_Tx[3];
	assign o_RC_T31 = RC_Tx[4];
	assign o_RC_T32 = RC_Tx[5];

	assign o_RC_RLSel = RC_RLSel;
	assign o_RC_VSel = RC_VSel;
	assign o_RC_ISel = RC_ISel;
	
	assign o_RC_LOF = RC_LOFS;
	assign o_RC_LOS = RC_LOFS;

	assign o_DPS_F_1 = DPS_FS_1;
	assign o_DPS_S_1 = DPS_FS_1;
	assign o_DPS_F_2 = DPS_FS_2;
	assign o_DPS_S_2 = DPS_FS_2;
	assign o_DPS_F_3 = DPS_FS_3;
	assign o_DPS_S_3 = DPS_FS_3;
	assign o_DPS_F_4 = DPS_FS_4;
	assign o_DPS_S_4 = DPS_FS_4;
	
	assign o_FMC = FSMC	;
	assign o_SMC = FSMC	;
	assign o_FMMC = FSMMC	;
	assign o_SMMC = FSMMC	;
	assign o_DPSF_RC1	= DPSFS_RC1	;
	assign o_DPSS_RC1	= DPSFS_RC1	;

	assign o_err = bus_err_flag || reg_err_flag ||cpld_err_flag;
	
endmodule