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base: yuysh/NewInstrCalBoard_CPLD:1d92e2c53ee1a066fde7ec0a579ac195fbc4817f
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yuysh/NewInstrCalBoard_CPLD:master
yuysh/NewInstrCalBoard_CPLD:v1.1.2 yuysh/NewInstrCalBoard_CPLD:v1.1.0
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compare: yuysh/NewInstrCalBoard_CPLD:e19adb09f9ff8ce789d18009041808971fe9f15b
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yuysh/NewInstrCalBoard_CPLD:master
yuysh/NewInstrCalBoard_CPLD:v1.1.2 yuysh/NewInstrCalBoard_CPLD:v1.1.0
2 Commits
1d92e2c53e ... e19adb09f9
Author SHA1 Message Date
yuysh e19adb09f9 Fix bugs and Unify the PMU_OC logic 2026-06-09 11:41:21 +08:00
yuysh 092cad794c Remove unecessary code in CPLD1 
Unify PMU_OC_* logic in CPLD2
 2026-06-08 18:14:44 +08:00
5 changed files with 69 additions and 104 deletions
Expand all files Collapse all files
CPLD1/CPLD_Con.v
+4 -6
View File
@@ -74,16 +74,16 @@ module CPLD_Con (
//Reg Parsing
//Shift Counter
wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter1 = (i_DC_Con1[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter1 = i_DC_Con1[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter1 = i_DC_Con1[21:17] ; // RC_RL Shifter
wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter2 = (i_DC_Con2[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter2 = i_DC_Con2[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter2 = i_DC_Con2[21:17] ; // RC_RL Shifter
wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter3 = (i_DC_Con3[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter3 = i_DC_Con3[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter3 = i_DC_Con3[21:17] ; // RC_RL Shifter
wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter4 = (i_DC_Con4[8:1] - 1) >> 3; // Channel Number div 8
wire [2:0]DMM_Shifter4 = i_DC_Con4[8:7] ; // Channel Number div 64
wire [4:0]RC_RLShifter4 = i_DC_Con4[21:17] ; // RC_RL Shifter
@@ -367,7 +367,6 @@ module CPLD_Con (
if (i_DC_Con4[23] == 1'b0) begin //Select PMU
//Parsing Channel
//We need Speacial Handling for tthe "freq" channels
if (Channel_4[0] == 1'b0) begin
if (Channel_4 == 'd66 || Channel_4 == 'd68) begin
RC_Tx <= 'd1;
end
@@ -389,7 +388,6 @@ module CPLD_Con (
else begin
RC_Tx <= 'd0;
end
end
PMU_OC_4 <= (32'b0000_0000_0000_0000_0000_0000_0000_0001)<<(OC_Shifter4);
DMM_en <= (19'b000_0001_0000_0000_0000)<<(DMM_Shifter4);
end
CPLD1/RelayConTop.v
+6 -6
View File
@@ -169,12 +169,12 @@ module RelayConTop (
assign o_DMM_EN = DMM_EN;
assign o_IO_RC1 = IO_RC1;
assign o_RC_T27 = RC_Tx[5];
assign o_RC_T28 = RC_Tx[4];
assign o_RC_T29 = RC_Tx[3];
assign o_RC_T30 = RC_Tx[2];
assign o_RC_T31 = RC_Tx[1];
assign o_RC_T32 = RC_Tx[0];
assign o_RC_T27 = RC_Tx[0];
assign o_RC_T28 = RC_Tx[1];
assign o_RC_T29 = RC_Tx[2];
assign o_RC_T30 = RC_Tx[3];
assign o_RC_T31 = RC_Tx[4];
assign o_RC_T32 = RC_Tx[5];
assign o_RC_RLSel = RC_RLSel;
assign o_RC_VSel = RC_VSel;
CPLD2/CPLD_Con.v
+22 -32
View File
@@ -19,8 +19,6 @@ module CPLD_Con (
output [7:0]o_RC_F, //Ref: Schematic
output [15:0]o_RC_S,
output [31:0]o_RC_T,
output [3:0] o_OC_x09,
output [3:0] o_OC_x25,
output [31:0]o_PMU_OC_1 ,
output [31:0]o_PMU_OC_2 ,
@@ -32,10 +30,6 @@ module CPLD_Con (
output o_con_done
);
//Output Relay Reg
reg [3:0] OC_x09;
reg [3:0] OC_x25;
//Condition Tester
reg [3:0]en_t ;
reg [3:0]freq_t;
@@ -64,10 +58,10 @@ module CPLD_Con (
reg [15:0]delay_cnt;
//Shift Counter
wire [4:0]OC_Shifter1 = i_DC_Con1[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter2 = i_DC_Con2[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter3 = i_DC_Con3[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter4 = i_DC_Con4[8:4]; // Channel Number div 8
wire [4:0]OC_Shifter1 = (i_DC_Con1[8:1] - 1) >> 3;; // Channel Number div 8
wire [4:0]OC_Shifter2 = (i_DC_Con2[8:1] - 1) >> 3; // Channel Number div 8
wire [4:0]OC_Shifter3 = (i_DC_Con3[8:1] - 1) >> 3; // Channel Number div 8
wire [4:0]OC_Shifter4 = (i_DC_Con4[8:1] - 1) >> 3; // Channel Number div 8
//Channels
wire [8:0]Channel_1 = i_DC_Con1[9:1] ;
@@ -162,14 +156,13 @@ module CPLD_Con (
exec_done_flag <= 1'b1;
end
if ((freq_relay1 > 64) & (freq_relay1 < 73)) begin
OC_x09 <= 4'b0001;
PMU_OC_1 <= 32'b1 << 8;
end
else if ((freq_relay1 > 192) & (freq_relay1 < 201)) begin
OC_x25 <= 4'b0001;
PMU_OC_1 <= 32'b1 << 24;
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
PMU_OC_1 <= 'd0;
end
end
4'b0010: begin
@@ -185,14 +178,13 @@ module CPLD_Con (
exec_done_flag <= 1'b1;
end
if ((freq_relay2 > 64) & (freq_relay2 < 73)) begin
OC_x09 <= 4'b0010;
PMU_OC_2 <= 32'b1 << 8;
end
else if ((freq_relay2 > 192) & (freq_relay2 < 201)) begin
OC_x25 <= 4'b0010;
PMU_OC_2 <= 32'b1 << 24;
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
PMU_OC_2 <= 'd0;
end
end
4'b0100: begin
@@ -208,14 +200,13 @@ module CPLD_Con (
exec_done_flag <= 1'b1;
end
if ((freq_relay3 > 64) &(freq_relay3 <73)) begin
OC_x09 <= 4'b0100;
PMU_OC_3 <= 32'b1 << 8;
end
else if ((freq_relay3 > 192) & (freq_relay3 < 201)) begin
OC_x25 <= 4'b0100;
PMU_OC_3 <= 32'b1 << 24;
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
PMU_OC_3 <= 'd0;
end
end
4'b1000: begin
@@ -231,19 +222,20 @@ module CPLD_Con (
exec_done_flag <= 1'b1;
end
if ((freq_relay4 > 64) & (freq_relay4 < 73)) begin
OC_x09 <= 4'b1000;
PMU_OC_4 <= 32'b1 << 8;
end
else if ((freq_relay4 > 192) & (freq_relay4 < 201)) begin
OC_x25 <= 4'b1000;
PMU_OC_4 <= 32'b1 << 24;
end
else begin
OC_x09 <= 'd0;
OC_x25 <= 'd0;
PMU_OC_4 <= 'd0;
end
end
default: begin
OC_x09 <= 4'b0000;
OC_x25 <= 4'b0000;
PMU_OC_1 <= 'd0;
PMU_OC_2 <= 'd0;
PMU_OC_3 <= 'd0;
PMU_OC_4 <= 'd0;
end
endcase
end
@@ -1210,7 +1202,7 @@ module CPLD_Con (
'd68: begin
relay_l1 <= 8'b0000_0000;
if (delay_cnt == 'd500) begin
relay_l2 <= 16'b0000_0001_0000_0000;
relay_l2 <= 16'b0010_0000_0000_0000;
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= 32'b0000_0100_0000_0000_0000_0000_0000_0000;
@@ -1374,7 +1366,7 @@ module CPLD_Con (
'd200: begin
relay_l1 <= 8'b1000_0000;
if (delay_cnt == 'd500) begin
relay_l2 <= 16'b0000_0100_0000_0000;
relay_l2 <= 16'b1000_0000_0000_0000;
end
else if (delay_cnt == 'd1000) begin
relay_l3 <= 32'b1000_0000_0000_0000_0000_0000_0000_0000;
@@ -1421,8 +1413,6 @@ module CPLD_Con (
assign o_RC_S = relay_l2;
assign o_RC_T = relay_l3;
assign o_con_done = exec_done_flag;
assign o_OC_x09 = OC_x09;
assign o_OC_x25 = OC_x25;
assign o_PMU_OC_1 = PMU_OC_1;
assign o_PMU_OC_2 = PMU_OC_2;
CPLD2/RelayConTop.v
+4 -27
View File
@@ -124,8 +124,6 @@ BUS_Con BUS_Con_2(
.o_RC_F(RC_F),
.o_RC_S(RC_S),
.o_RC_T(RC_T),
.o_OC_x09(OC_x09),
.o_OC_x25(OC_x25),
.o_err(cpld_err_flag)
);
@@ -134,31 +132,10 @@ BUS_Con BUS_Con_2(
assign o_RC_S = RC_S;
assign o_RC_T = RC_T[25:0];
assign o_PMU_OC_1[8] = OC_x09[0];
assign o_PMU_OC_2[8] = OC_x09[1];
assign o_PMU_OC_3[8] = OC_x09[2];
assign o_PMU_OC_4[8] = OC_x09[3];
assign o_PMU_OC_1[24] = OC_x25[0];
assign o_PMU_OC_2[24] = OC_x25[1];
assign o_PMU_OC_3[24] = OC_x25[2];
assign o_PMU_OC_4[24] = OC_x25[3];
assign o_PMU_OC_1[7:0] = PMU_OC_1[7:0];
assign o_PMU_OC_1[23:9] = PMU_OC_1[23:8];
assign o_PMU_OC_1[31:25] = PMU_OC_1[31:25];
assign o_PMU_OC_2[7:0] = PMU_OC_2[7:0];
assign o_PMU_OC_2[23:9] = PMU_OC_2[23:9];
assign o_PMU_OC_2[31:25] = PMU_OC_2[31:25];
assign o_PMU_OC_3[7:0] = PMU_OC_3[7:0];
assign o_PMU_OC_3[23:9] = PMU_OC_3[23:9];
assign o_PMU_OC_3[31:25]= PMU_OC_3[31:25];
assign o_PMU_OC_4[7:0] = PMU_OC_4[7:0];
assign o_PMU_OC_4[23:9] = PMU_OC_4[23:9];
assign o_PMU_OC_4[31:25] = PMU_OC_4[31:25];
assign o_PMU_OC_1 = PMU_OC_1 ;
assign o_PMU_OC_2 = PMU_OC_2 ;
assign o_PMU_OC_3 = PMU_OC_3 ;
assign o_PMU_OC_4 = PMU_OC_4 ;
assign o_err = bus_err_flag || reg_err_flag || cpld_err_flag;
CPLD3/CPLD_Con.v
+5 -5
View File
@@ -117,19 +117,19 @@ module CPLD_Con (
else if (dc_t == 1'b1) begin
case (dc_slot_flag)
4'b0001: begin
PMU_RC <= 4'b0001;
PMU_RC <= 4'b1110;
end
4'b0010: begin
PMU_RC <= 4'b0010;
PMU_RC <= 4'b1101;
end
4'b0100: begin
PMU_RC <= 4'b0100;
PMU_RC <= 4'b1011;
end
4'b1000: begin
PMU_RC <= 4'b1000;
PMU_RC <= 4'b0111;
end
default:begin
PMU_RC <= 4'b0000;
PMU_RC <= 4'b1111;
end
endcase
end